[AMDGPU][MC][GFX11][NFC] Update tests for VOP3P.DPP instructions

[dp]

Summary

Note that tests for DOT opcodes have not been updated. DPP variants of DOT instructions seem to have an incorrect encoding.

[Joe_Nash]

llvm/test/MC/AMDGPU/gfx11_asm_vop3p_dpp16.s

8

I agree something is weird here with v_dot2_f32_f16 and v_dot2_f32_bf16, I will try to clarify the desired behavior.

20

I'm not sure where you're getting op_sel_hi=7 for v_fma_mix* instructions. From my reading of the spec and comparison with sp3, all values of op_sel and op_sel_hi are supported. The behavior is non-standard for mix opcodes, but the values should be accepted.
Does your observation have anything to do with dpp? Both dpp and non-dpp version should behave the same and allow all values of op_sel.

[dp]

llvm/test/MC/AMDGPU/gfx11_asm_vop3p_dpp16.s

20

I remember that SPG stated the following at some point:

When using DPP with VOP3/VOP3P, the OPSEL must be set such that the low result only uses low inputs, and the high result only uses high inputs.

I always thought that this was a suspicious statement, but see the original tests gfx11_asm_vop3p_dpp8.s below, they stated essentially the same:

// For test purpose only. OP_SEL has to be set to all 0 and OP_SEL_HI has to be set to all 1

llvm/test/MC/AMDGPU/gfx11_asm_vop3p_dpp8.s

13

Here is the original comment.

[dp]

Remove FIXME note regarding use of op_sel for fma_mix instructions. I assume op_sel is legal in this context.

[Joe_Nash]

llvm/test/MC/AMDGPU/gfx11_asm_vop3p_dpp16.s

20

Oh I see. In my previous reply I was just looking at the rules for vop3p by mistake. The existing comment was actually correct. There is a special case for vop3p with dpp.

When using DPP with VOP3P, OPSEL has to be set to all 0 and OPSEL_HI has to be set to all 1

And in GCNDPPCombine we actually check those rules. So Codegen is doing the right thing.

Sorry for the noise.

[dp]

When using DPP with VOP3P, OPSEL has to be set to all 0 and OPSEL_HI has to be set to all 1

Does it mean that DPP variants of fma_mix opcodes are encoded incorrectly? Both llvm and SP3 assemblers do not set op_sel_hi to all 1:

v_fma_mix_f32 v255, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xff,0x00,0x20,0xcc,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]

encoding: VOP3P.DPP8
  clamp             0
  encoding       0xcc
  fi8            0x01
  lane_sel_0     0x07
  lane_sel_1     0x06
  lane_sel_2     0x05
  lane_sel_3     0x04
  lane_sel_4     0x03
  lane_sel_5     0x02
  lane_sel_6     0x01
  lane_sel_7        0
  neg               0
  neg_hi            0
  op             0x20   v_fma_mix_f32_e64_dpp
  op_sel            0
  op_sel_hi         0
  op_sel_hi_2       0
  src0           0x01
  src1          0x102
  src2          0x103
  vdst           0xff

I'll file a ticket on this issue then. I think we should not update tests till the issue is fixed.

[Joe_Nash]

In D132957#3761978, @dp wrote:

When using DPP with VOP3P, OPSEL has to be set to all 0 and OPSEL_HI has to be set to all 1

Does it mean that DPP variants of fma_mix opcodes are encoded incorrectly? Both llvm and SP3 assemblers do not set op_sel_hi to all 1:

It is true that there is no check verifying that desired property in the assembler. Filing an issue makes sense, though adding a check for the property seems low priority.

[dp]

Added new issue.

[dp]

Tests will be updated after the encoding issue is fixed.

llvm/test/MC/AMDGPU/gfx11_asm_vop3p_dpp16.s

 // RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX11 %s
 // RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX11 %s
 
+//===----------------------------------------------------------------------===//
+// DOT INSTRUCTIONS.
+//===----------------------------------------------------------------------===//
+
+// FIXME: it looks like the encoding of DOT instructions is incorrect. SP3 sets op_sel_hi to 0x7.
+
 v_dot2_f32_f16 v0, v1, v2, v3 neg_lo:[0,0,0] neg_hi:[0,0,0] quad_perm:[2,2,3,1] bound_ctrl:0 fi:1
 // GFX11: v_dot2_f32_f16_e64_dpp v0, v1, v2, v3 quad_perm:[2,2,3,1] row_mask:0xf bank_mask:0xf bound_ctrl:1 fi:1 ; encoding: [0x00,0x00,0x13,0xcc,0xfa,0x04,0x0e,0x04,0x01,0x7a,0x0c,0xff]
 
 v_dot2_f32_f16 v0, v1, v2, v3 neg_lo:[1,1,0] neg_hi:[1,0,1] quad_perm:[3,2,1,0] bank_mask:0xe
 // GFX11: v_dot2_f32_f16_e64_dpp v0, v1, v2, v3 neg_lo:[1,1,0] neg_hi:[1,0,1] quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xe ; encoding: [0x00,0x05,0x13,0xcc,0xfa,0x04,0x0e,0x64,0x01,0x1b,0x00,0xfe]
 
-v_fma_mix_f32 v0, v1, v2, v3 op_sel:[0,0,0] row_ror:7 bank_mask:0x1 bound_ctrl:0
-// GFX11: v_fma_mix_f32_e64_dpp v0, v1, v2, v3 row_ror:7 row_mask:0xf bank_mask:0x1 bound_ctrl:1 ; encoding: [0x00,0x00,0x20,0xcc,0xfa,0x04,0x0e,0x04,0x01,0x27,0x09,0xf1]
+//===----------------------------------------------------------------------===//
+// FMA_MIX INSTRUCTIONS.
+//===----------------------------------------------------------------------===//
+
+v_fma_mix_f32_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0]
+// GFX11: encoding: [0x05,0x00,0x20,0xcc,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
+
+v_fma_mix_f32_e64_dpp v5, v1, v2, v255 quad_perm:[0,1,2,3]
+// GFX11: encoding: [0x05,0x00,0x20,0xcc,0xfa,0x04,0xfe,0x07,0x01,0xe4,0x00,0xff]
+
+v_fma_mix_f32_e64_dpp v5, v1, v2, s3 row_mirror
+// GFX11: encoding: [0x05,0x00,0x20,0xcc,0xfa,0x04,0x0e,0x00,0x01,0x40,0x01,0xff]
+
+v_fma_mix_f32_e64_dpp v5, v1, v2, s105 row_half_mirror
+// GFX11: encoding: [0x05,0x00,0x20,0xcc,0xfa,0x04,0xa6,0x01,0x01,0x41,0x01,0xff]
+
+v_fma_mix_f32_e64_dpp v5, v1, v2, ttmp15 row_shl:1
+// GFX11: encoding: [0x05,0x00,0x20,0xcc,0xfa,0x04,0xee,0x01,0x01,0x01,0x01,0xff]
+
+v_fma_mix_f32_e64_dpp v5, v1, v2, vcc_hi row_shl:15
+// GFX11: encoding: [0x05,0x00,0x20,0xcc,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
+
+v_fma_mix_f32_e64_dpp v5, v1, v2, vcc_lo row_shr:1
+// GFX11: encoding: [0x05,0x00,0x20,0xcc,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
+
+v_fma_mix_f32_e64_dpp v5, v1, v2, -|m0| row_shr:15
+// GFX11: encoding: [0x05,0x04,0x20,0xcc,0xfa,0x04,0xf6,0x81,0x01,0x1f,0x01,0xff]
+
+v_fma_mix_f32_e64_dpp v5, -|v1|, v2, -|exec_hi| row_ror:1
+// GFX11: encoding: [0x05,0x05,0x20,0xcc,0xfa,0x04,0xfe,0xa1,0x01,0x21,0x01,0xff]
+
+v_fma_mix_f32_e64_dpp v5, v1, -|v2|, -|exec_lo| op_sel:[1,1,1] op_sel_hi:[1,1,1] row_ror:15
+// GFX11: encoding: [0x05,0x7e,0x20,0xcc,0xfa,0x04,0xfa,0xd9,0x01,0x2f,0x01,0xff]
+
+v_fma_mix_f32_e64_dpp v5, |v1|, -v2, null op_sel:[0,0,0] op_sel_hi:[0,0,1] row_share:0 row_mask:0xf bank_mask:0xf
+// GFX11: encoding: [0x05,0x41,0x20,0xcc,0xfa,0x04,0xf2,0x41,0x01,0x50,0x01,0xff]
+
+v_fma_mix_f32_e64_dpp v5, -v1, |v2|, -1 op_sel:[1,0,0] op_sel_hi:[0,1,0] row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX11: encoding: [0x05,0x0a,0x20,0xcc,0xfa,0x04,0x06,0x33,0x01,0x5f,0x01,0x01]
+
+v_fma_mix_f32_e64_dpp v5, -|v1|, -|v2|, 0.5 op_sel:[0,1,0] op_sel_hi:[1,0,0] row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX11: encoding: [0x05,0x13,0x20,0xcc,0xfa,0x04,0xc2,0x6b,0x01,0x60,0x09,0x13]
+
+v_fma_mix_f32_e64_dpp v255, -|v255|, -|v255|, -|src_scc| op_sel:[0,0,1] op_sel_hi:[0,0,0] clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX11: encoding: [0xff,0xa7,0x20,0xcc,0xfa,0xfe,0xf7,0xe3,0xff,0x6f,0x0d,0x30]
+
+v_fma_mixhi_f16_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0]
+// GFX11: encoding: [0x05,0x00,0x22,0xcc,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
+
+v_fma_mixhi_f16_e64_dpp v5, v1, v2, v255 quad_perm:[0,1,2,3]
+// GFX11: encoding: [0x05,0x00,0x22,0xcc,0xfa,0x04,0xfe,0x07,0x01,0xe4,0x00,0xff]
+
+v_fma_mixhi_f16_e64_dpp v5, v1, v2, s3 row_mirror
+// GFX11: encoding: [0x05,0x00,0x22,0xcc,0xfa,0x04,0x0e,0x00,0x01,0x40,0x01,0xff]
+
+v_fma_mixhi_f16_e64_dpp v5, v1, v2, s105 row_half_mirror
+// GFX11: encoding: [0x05,0x00,0x22,0xcc,0xfa,0x04,0xa6,0x01,0x01,0x41,0x01,0xff]
+
+v_fma_mixhi_f16_e64_dpp v5, v1, v2, ttmp15 row_shl:1
+// GFX11: encoding: [0x05,0x00,0x22,0xcc,0xfa,0x04,0xee,0x01,0x01,0x01,0x01,0xff]
+
+v_fma_mixhi_f16_e64_dpp v5, v1, v2, vcc_hi row_shl:15
+// GFX11: encoding: [0x05,0x00,0x22,0xcc,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
+
+v_fma_mixhi_f16_e64_dpp v5, v1, v2, vcc_lo row_shr:1
+// GFX11: encoding: [0x05,0x00,0x22,0xcc,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
+
+v_fma_mixhi_f16_e64_dpp v5, v1, v2, -|m0| row_shr:15
+// GFX11: encoding: [0x05,0x04,0x22,0xcc,0xfa,0x04,0xf6,0x81,0x01,0x1f,0x01,0xff]
+
+v_fma_mixhi_f16_e64_dpp v5, -|v1|, v2, -|exec_hi| row_ror:1
+// GFX11: encoding: [0x05,0x05,0x22,0xcc,0xfa,0x04,0xfe,0xa1,0x01,0x21,0x01,0xff]
+
+v_fma_mixhi_f16_e64_dpp v5, v1, -|v2|, -|exec_lo| op_sel:[1,1,1] op_sel_hi:[1,1,1] row_ror:15
+// GFX11: encoding: [0x05,0x7e,0x22,0xcc,0xfa,0x04,0xfa,0xd9,0x01,0x2f,0x01,0xff]
+
+v_fma_mixhi_f16_e64_dpp v5, |v1|, -v2, null op_sel:[0,0,0] op_sel_hi:[0,0,1] row_share:0 row_mask:0xf bank_mask:0xf
+// GFX11: encoding: [0x05,0x41,0x22,0xcc,0xfa,0x04,0xf2,0x41,0x01,0x50,0x01,0xff]
+
+v_fma_mixhi_f16_e64_dpp v5, -v1, |v2|, -1 op_sel:[1,0,0] op_sel_hi:[0,1,0] row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX11: encoding: [0x05,0x0a,0x22,0xcc,0xfa,0x04,0x06,0x33,0x01,0x5f,0x01,0x01]
+
+v_fma_mixhi_f16_e64_dpp v5, -|v1|, -|v2|, 0.5 op_sel:[0,1,0] op_sel_hi:[1,0,0] row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX11: encoding: [0x05,0x13,0x22,0xcc,0xfa,0x04,0xc2,0x6b,0x01,0x60,0x09,0x13]
+
+v_fma_mixhi_f16_e64_dpp v255, -|v255|, -|v255|, -|src_scc| op_sel:[0,0,1] op_sel_hi:[0,0,0] clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX11: encoding: [0xff,0xa7,0x22,0xcc,0xfa,0xfe,0xf7,0xe3,0xff,0x6f,0x0d,0x30]
+
+v_fma_mixlo_f16_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0]
+// GFX11: encoding: [0x05,0x00,0x21,0xcc,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
+
+v_fma_mixlo_f16_e64_dpp v5, v1, v2, v255 quad_perm:[0,1,2,3]
+// GFX11: encoding: [0x05,0x00,0x21,0xcc,0xfa,0x04,0xfe,0x07,0x01,0xe4,0x00,0xff]
+
+v_fma_mixlo_f16_e64_dpp v5, v1, v2, s3 row_mirror
+// GFX11: encoding: [0x05,0x00,0x21,0xcc,0xfa,0x04,0x0e,0x00,0x01,0x40,0x01,0xff]
+
+v_fma_mixlo_f16_e64_dpp v5, v1, v2, s105 row_half_mirror
+// GFX11: encoding: [0x05,0x00,0x21,0xcc,0xfa,0x04,0xa6,0x01,0x01,0x41,0x01,0xff]
+
+v_fma_mixlo_f16_e64_dpp v5, v1, v2, ttmp15 row_shl:1
+// GFX11: encoding: [0x05,0x00,0x21,0xcc,0xfa,0x04,0xee,0x01,0x01,0x01,0x01,0xff]
+
+v_fma_mixlo_f16_e64_dpp v5, v1, v2, vcc_hi row_shl:15
+// GFX11: encoding: [0x05,0x00,0x21,0xcc,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
+
+v_fma_mixlo_f16_e64_dpp v5, v1, v2, vcc_lo row_shr:1
+// GFX11: encoding: [0x05,0x00,0x21,0xcc,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
+
+v_fma_mixlo_f16_e64_dpp v5, v1, v2, -|m0| row_shr:15
+// GFX11: encoding: [0x05,0x04,0x21,0xcc,0xfa,0x04,0xf6,0x81,0x01,0x1f,0x01,0xff]
+
+v_fma_mixlo_f16_e64_dpp v5, -|v1|, v2, -|exec_hi| row_ror:1
+// GFX11: encoding: [0x05,0x05,0x21,0xcc,0xfa,0x04,0xfe,0xa1,0x01,0x21,0x01,0xff]
+
+v_fma_mixlo_f16_e64_dpp v5, v1, -|v2|, -|exec_lo| op_sel:[1,1,1] op_sel_hi:[1,1,1] row_ror:15
+// GFX11: encoding: [0x05,0x7e,0x21,0xcc,0xfa,0x04,0xfa,0xd9,0x01,0x2f,0x01,0xff]
+
+v_fma_mixlo_f16_e64_dpp v5, |v1|, -v2, null op_sel:[0,0,0] op_sel_hi:[0,0,1] row_share:0 row_mask:0xf bank_mask:0xf
+// GFX11: encoding: [0x05,0x41,0x21,0xcc,0xfa,0x04,0xf2,0x41,0x01,0x50,0x01,0xff]
+
+v_fma_mixlo_f16_e64_dpp v5, -v1, |v2|, -1 op_sel:[1,0,0] op_sel_hi:[0,1,0] row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX11: encoding: [0x05,0x0a,0x21,0xcc,0xfa,0x04,0x06,0x33,0x01,0x5f,0x01,0x01]
+
+v_fma_mixlo_f16_e64_dpp v5, -|v1|, -|v2|, 0.5 op_sel:[0,1,0] op_sel_hi:[1,0,0] row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX11: encoding: [0x05,0x13,0x21,0xcc,0xfa,0x04,0xc2,0x6b,0x01,0x60,0x09,0x13]
 
-v_fma_mixhi_f16 v0, v1, v2, v3 op_sel_hi:[1,1,1] clamp quad_perm:[0,2,3,1] row_mask:0x0
-// GFX11: v_fma_mixhi_f16_e64_dpp v0, v1, v2, v3 op_sel_hi:[1,1,1] clamp quad_perm:[0,2,3,1] row_mask:0x0 bank_mask:0xf ; encoding: [0x00,0xc0,0x22,0xcc,0xfa,0x04,0x0e,0x1c,0x01,0x78,0x00,0x0f]
+v_fma_mixlo_f16_e64_dpp v255, -|v255|, -|v255|, -|src_scc| op_sel:[0,0,1] op_sel_hi:[0,0,0] clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX11: encoding: [0xff,0xa7,0x21,0xcc,0xfa,0xfe,0xf7,0xe3,0xff,0x6f,0x0d,0x30]

llvm/test/MC/AMDGPU/gfx11_asm_vop3p_dpp8.s

 // RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX11 %s
 // RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX11 %s
 
-v_fma_mix_f32 v0, v1, v2, v3 dpp8:[2,2,2,2,4,4,4,4]
-// GFX11: encoding: [0x00,0x00,0x20,0xcc,0xe9,0x04,0x0e,0x04,0x01,0x92,0x44,0x92]
+//===----------------------------------------------------------------------===//
+// DOT INSTRUCTIONS.
+//===----------------------------------------------------------------------===//
 
-v_fma_mix_f32 v0, v1, v2, v3 clamp dpp8:[2,2,2,2,4,4,4,4] fi:1
-// GFX11: encoding: [0x00,0x80,0x20,0xcc,0xea,0x04,0x0e,0x04,0x01,0x92,0x44,0x92]
-
-v_fma_mixlo_f16 v0, abs(v1), -v2, abs(v3) dpp8:[2,2,2,2,4,4,4,4]
-// GFX11: encoding: [0x00,0x05,0x21,0xcc,0xe9,0x04,0x0e,0x44,0x01,0x92,0x44,0x92]
-
-// For test purpose only. OP_SEL has to be set to all 0 and OP_SEL_HI has to be set to all 1
-v_fma_mixlo_f16 v0, abs(v1), -v2, abs(v3) op_sel:[1,0,0] op_sel_hi:[1,0,0] dpp8:[2,2,2,2,4,4,4,4]
-// GFX11: encoding: [0x00,0x0d,0x21,0xcc,0xe9,0x04,0x0e,0x4c,0x01,0x92,0x44,0x92]
+// FIXME: it looks like the encoding of DOT instructions is incorrect. SP3 sets op_sel_hi to 0x7.
 
 v_dot2_f32_f16_e64_dpp v0, v1, v2, v3 neg_lo:[0,1,1] neg_hi:[1,0,1] dpp8:[7,6,5,4,3,2,1,0]
 // GFX11: encoding: [0x00,0x05,0x13,0xcc,0xe9,0x04,0x0e,0xc4,0x01,0x77,0x39,0x05]
+
+//===----------------------------------------------------------------------===//
+// FMA_MIX INSTRUCTIONS.
+//===----------------------------------------------------------------------===//
+
+v_fma_mix_f32_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0]
+// GFX11: encoding: [0x05,0x00,0x20,0xcc,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
+
+v_fma_mix_f32_e64_dpp v5, v1, v2, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX11: encoding: [0x05,0x00,0x20,0xcc,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05]
+
+v_fma_mix_f32_e64_dpp v5, v1, v2, s3 dpp8:[7,6,5,4,3,2,1,0]
+// GFX11: encoding: [0x05,0x00,0x20,0xcc,0xe9,0x04,0x0e,0x00,0x01,0x77,0x39,0x05]
+
+v_fma_mix_f32_e64_dpp v5, v1, v2, s105 dpp8:[7,6,5,4,3,2,1,0]
+// GFX11: encoding: [0x05,0x00,0x20,0xcc,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05]
+
+v_fma_mix_f32_e64_dpp v5, v1, v2, ttmp15 dpp8:[7,6,5,4,3,2,1,0]
+// GFX11: encoding: [0x05,0x00,0x20,0xcc,0xe9,0x04,0xee,0x01,0x01,0x77,0x39,0x05]
+
+v_fma_mix_f32_e64_dpp v5, v1, v2, vcc_hi dpp8:[7,6,5,4,3,2,1,0]
+// GFX11: encoding: [0x05,0x00,0x20,0xcc,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05]
+
+v_fma_mix_f32_e64_dpp v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0]
+// GFX11: encoding: [0x05,0x00,0x20,0xcc,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05]
+
+v_fma_mix_f32_e64_dpp v5, v1, v2, -|m0| dpp8:[7,6,5,4,3,2,1,0]
+// GFX11: encoding: [0x05,0x04,0x20,0xcc,0xe9,0x04,0xf6,0x81,0x01,0x77,0x39,0x05]
+
+v_fma_mix_f32_e64_dpp v5, -|v1|, v2, -|exec_hi| dpp8:[7,6,5,4,3,2,1,0]
+// GFX11: encoding: [0x05,0x05,0x20,0xcc,0xe9,0x04,0xfe,0xa1,0x01,0x77,0x39,0x05]
+
+v_fma_mix_f32_e64_dpp v5, v1, -|v2|, -|exec_lo| op_sel:[1,1,1] op_sel_hi:[1,1,1] dpp8:[7,6,5,4,3,2,1,0]
+// GFX11: encoding: [0x05,0x7e,0x20,0xcc,0xe9,0x04,0xfa,0xd9,0x01,0x77,0x39,0x05]
+
+v_fma_mix_f32_e64_dpp v5, |v1|, -v2, null op_sel:[0,0,0] op_sel_hi:[0,0,1] dpp8:[7,6,5,4,3,2,1,0]
+// GFX11: encoding: [0x05,0x41,0x20,0xcc,0xe9,0x04,0xf2,0x41,0x01,0x77,0x39,0x05]
+
+v_fma_mix_f32_e64_dpp v5, -v1, |v2|, -1 op_sel:[1,0,0] op_sel_hi:[0,1,0] dpp8:[7,6,5,4,3,2,1,0]
+// GFX11: encoding: [0x05,0x0a,0x20,0xcc,0xe9,0x04,0x06,0x33,0x01,0x77,0x39,0x05]
+
+v_fma_mix_f32_e64_dpp v5, -|v1|, -|v2|, 0.5 op_sel:[0,1,0] op_sel_hi:[1,0,0] dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX11: encoding: [0x05,0x13,0x20,0xcc,0xea,0x04,0xc2,0x6b,0x01,0x77,0x39,0x05]
+
+v_fma_mix_f32_e64_dpp v255, -|v255|, -|v255|, -|src_scc| op_sel:[0,0,1] op_sel_hi:[0,0,0] clamp dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX11: encoding: [0xff,0xa7,0x20,0xcc,0xe9,0xfe,0xf7,0xe3,0xff,0x00,0x00,0x00]
+
+v_fma_mixhi_f16_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0]
+// GFX11: encoding: [0x05,0x00,0x22,0xcc,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
+
+v_fma_mixhi_f16_e64_dpp v5, v1, v2, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX11: encoding: [0x05,0x00,0x22,0xcc,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05]
+
+v_fma_mixhi_f16_e64_dpp v5, v1, v2, s3 dpp8:[7,6,5,4,3,2,1,0]
+// GFX11: encoding: [0x05,0x00,0x22,0xcc,0xe9,0x04,0x0e,0x00,0x01,0x77,0x39,0x05]
+
+v_fma_mixhi_f16_e64_dpp v5, v1, v2, s105 dpp8:[7,6,5,4,3,2,1,0]
+// GFX11: encoding: [0x05,0x00,0x22,0xcc,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05]
+
+v_fma_mixhi_f16_e64_dpp v5, v1, v2, ttmp15 dpp8:[7,6,5,4,3,2,1,0]
+// GFX11: encoding: [0x05,0x00,0x22,0xcc,0xe9,0x04,0xee,0x01,0x01,0x77,0x39,0x05]
+
+v_fma_mixhi_f16_e64_dpp v5, v1, v2, vcc_hi dpp8:[7,6,5,4,3,2,1,0]
+// GFX11: encoding: [0x05,0x00,0x22,0xcc,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05]
+
+v_fma_mixhi_f16_e64_dpp v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0]
+// GFX11: encoding: [0x05,0x00,0x22,0xcc,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05]
+
+v_fma_mixhi_f16_e64_dpp v5, v1, v2, -|m0| dpp8:[7,6,5,4,3,2,1,0]
+// GFX11: encoding: [0x05,0x04,0x22,0xcc,0xe9,0x04,0xf6,0x81,0x01,0x77,0x39,0x05]
+
+v_fma_mixhi_f16_e64_dpp v5, -|v1|, v2, -|exec_hi| dpp8:[7,6,5,4,3,2,1,0]
+// GFX11: encoding: [0x05,0x05,0x22,0xcc,0xe9,0x04,0xfe,0xa1,0x01,0x77,0x39,0x05]
+
+v_fma_mixhi_f16_e64_dpp v5, v1, -|v2|, -|exec_lo| op_sel:[1,1,1] op_sel_hi:[1,1,1] dpp8:[7,6,5,4,3,2,1,0]
+// GFX11: encoding: [0x05,0x7e,0x22,0xcc,0xe9,0x04,0xfa,0xd9,0x01,0x77,0x39,0x05]
+
+v_fma_mixhi_f16_e64_dpp v5, |v1|, -v2, null op_sel:[0,0,0] op_sel_hi:[0,0,1] dpp8:[7,6,5,4,3,2,1,0]
+// GFX11: encoding: [0x05,0x41,0x22,0xcc,0xe9,0x04,0xf2,0x41,0x01,0x77,0x39,0x05]
+
+v_fma_mixhi_f16_e64_dpp v5, -v1, |v2|, -1 op_sel:[1,0,0] op_sel_hi:[0,1,0] dpp8:[7,6,5,4,3,2,1,0]
+// GFX11: encoding: [0x05,0x0a,0x22,0xcc,0xe9,0x04,0x06,0x33,0x01,0x77,0x39,0x05]
+
+v_fma_mixhi_f16_e64_dpp v5, -|v1|, -|v2|, 0.5 op_sel:[0,1,0] op_sel_hi:[1,0,0] dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX11: encoding: [0x05,0x13,0x22,0xcc,0xea,0x04,0xc2,0x6b,0x01,0x77,0x39,0x05]
+
+v_fma_mixhi_f16_e64_dpp v255, -|v255|, -|v255|, -|src_scc| op_sel:[0,0,1] op_sel_hi:[0,0,0] clamp dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX11: encoding: [0xff,0xa7,0x22,0xcc,0xe9,0xfe,0xf7,0xe3,0xff,0x00,0x00,0x00]
+
+v_fma_mixlo_f16_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0]
+// GFX11: encoding: [0x05,0x00,0x21,0xcc,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
+
+v_fma_mixlo_f16_e64_dpp v5, v1, v2, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX11: encoding: [0x05,0x00,0x21,0xcc,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05]
+
+v_fma_mixlo_f16_e64_dpp v5, v1, v2, s3 dpp8:[7,6,5,4,3,2,1,0]
+// GFX11: encoding: [0x05,0x00,0x21,0xcc,0xe9,0x04,0x0e,0x00,0x01,0x77,0x39,0x05]
+
+v_fma_mixlo_f16_e64_dpp v5, v1, v2, s105 dpp8:[7,6,5,4,3,2,1,0]
+// GFX11: encoding: [0x05,0x00,0x21,0xcc,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05]
+
+v_fma_mixlo_f16_e64_dpp v5, v1, v2, ttmp15 dpp8:[7,6,5,4,3,2,1,0]
+// GFX11: encoding: [0x05,0x00,0x21,0xcc,0xe9,0x04,0xee,0x01,0x01,0x77,0x39,0x05]
+
+v_fma_mixlo_f16_e64_dpp v5, v1, v2, vcc_hi dpp8:[7,6,5,4,3,2,1,0]
+// GFX11: encoding: [0x05,0x00,0x21,0xcc,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05]
+
+v_fma_mixlo_f16_e64_dpp v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0]
+// GFX11: encoding: [0x05,0x00,0x21,0xcc,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05]
+
+v_fma_mixlo_f16_e64_dpp v5, v1, v2, -|m0| dpp8:[7,6,5,4,3,2,1,0]
+// GFX11: encoding: [0x05,0x04,0x21,0xcc,0xe9,0x04,0xf6,0x81,0x01,0x77,0x39,0x05]
+
+v_fma_mixlo_f16_e64_dpp v5, -|v1|, v2, -|exec_hi| dpp8:[7,6,5,4,3,2,1,0]
+// GFX11: encoding: [0x05,0x05,0x21,0xcc,0xe9,0x04,0xfe,0xa1,0x01,0x77,0x39,0x05]
+
+v_fma_mixlo_f16_e64_dpp v5, v1, -|v2|, -|exec_lo| op_sel:[1,1,1] op_sel_hi:[1,1,1] dpp8:[7,6,5,4,3,2,1,0]
+// GFX11: encoding: [0x05,0x7e,0x21,0xcc,0xe9,0x04,0xfa,0xd9,0x01,0x77,0x39,0x05]
+
+v_fma_mixlo_f16_e64_dpp v5, |v1|, -v2, null op_sel:[0,0,0] op_sel_hi:[0,0,1] dpp8:[7,6,5,4,3,2,1,0]
+// GFX11: encoding: [0x05,0x41,0x21,0xcc,0xe9,0x04,0xf2,0x41,0x01,0x77,0x39,0x05]
+
+v_fma_mixlo_f16_e64_dpp v5, -v1, |v2|, -1 op_sel:[1,0,0] op_sel_hi:[0,1,0] dpp8:[7,6,5,4,3,2,1,0]
+// GFX11: encoding: [0x05,0x0a,0x21,0xcc,0xe9,0x04,0x06,0x33,0x01,0x77,0x39,0x05]
+
+v_fma_mixlo_f16_e64_dpp v5, -|v1|, -|v2|, 0.5 op_sel:[0,1,0] op_sel_hi:[1,0,0] dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX11: encoding: [0x05,0x13,0x21,0xcc,0xea,0x04,0xc2,0x6b,0x01,0x77,0x39,0x05]
+
+v_fma_mixlo_f16_e64_dpp v255, -|v255|, -|v255|, -|src_scc| op_sel:[0,0,1] op_sel_hi:[0,0,0] clamp dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX11: encoding: [0xff,0xa7,0x21,0xcc,0xe9,0xfe,0xf7,0xe3,0xff,0x00,0x00,0x00]