[mlir][spirv] Add vector.fma lowering to CL.fma

[raikonenfnu]

Linted changes

[antiagainst]

One nit about the commit message: it should be written as [mlir][spirv] to be consistent with other commits.

[raikonenfnu]

Editted commit message to be more consistent

[raikonenfnu]

In D132424#3741284, @antiagainst wrote:

One nit about the commit message: it should be written as [mlir][spirv] to be consistent with other commits.

done, thanks :)

mlir/lib/Conversion/VectorToSPIRV/VectorToSPIRV.cpp

matchAndRewrite(vector::ExtractStridedSliceOp extractOp, OpAdaptor adaptor,
     rewriter.replaceOpWithNewOp<spirv::VectorShuffleOp>(
         extractOp, dstType, srcVector, srcVector,
         rewriter.getI32ArrayAttr(indices));
 
     return success();
   }
 };
 
+template <class SPVFMAOp>
 struct VectorFmaOpConvert final : public OpConversionPattern<vector::FMAOp> {
   using OpConversionPattern::OpConversionPattern;
 
   LogicalResult
   matchAndRewrite(vector::FMAOp fmaOp, OpAdaptor adaptor,
                   ConversionPatternRewriter &rewriter) const override {
     Type dstType = getTypeConverter()->convertType(fmaOp.getType());
     if (!dstType)
       return failure();
-    rewriter.replaceOpWithNewOp<spirv::GLFmaOp>(
-        fmaOp, dstType, adaptor.getLhs(), adaptor.getRhs(), adaptor.getAcc());
+    rewriter.replaceOpWithNewOp<SPVFMAOp>(fmaOp, dstType, adaptor.getLhs(),
+                                          adaptor.getRhs(), adaptor.getAcc());
     return success();
   }
 };
 
 struct VectorInsertOpConvert final
     : public OpConversionPattern<vector::InsertOp> {
   using OpConversionPattern::OpConversionPattern;
 

 };
 
 } // namespace
 
 void mlir::populateVectorToSPIRVPatterns(SPIRVTypeConverter &typeConverter,
                                          RewritePatternSet &patterns) {
   patterns.add<VectorBitcastConvert, VectorBroadcastConvert,
                VectorExtractElementOpConvert, VectorExtractOpConvert,
-               VectorExtractStridedSliceOpConvert, VectorFmaOpConvert,
-               VectorInsertElementOpConvert, VectorInsertOpConvert,
-               VectorReductionPattern, VectorInsertStridedSliceOpConvert,
-               VectorShuffleOpConvert, VectorSplatPattern>(
-      typeConverter, patterns.getContext());
+               VectorExtractStridedSliceOpConvert,
+               VectorFmaOpConvert<spirv::GLFmaOp>,
+               VectorFmaOpConvert<spirv::CLFmaOp>, VectorInsertElementOpConvert,
+               VectorInsertOpConvert, VectorReductionPattern,
+               VectorInsertStridedSliceOpConvert, VectorShuffleOpConvert,
+               VectorSplatPattern>(typeConverter, patterns.getContext());
 }

mlir/test/Conversion/VectorToSPIRV/vector-to-spirv.mlir

func.func @bitcast(%arg0 : vector<2xf32>, %arg1: vector<2xf16>) -> (vector<4xf16>, vector<1xf32>) {
   %1 = vector.bitcast %arg1 : vector<2xf16> to vector<1xf32>
   return %0, %1: vector<4xf16>, vector<1xf32>
 }
 
 } // end module
 
 // -----
 
+module attributes { spv.target_env = #spv.target_env<#spv.vce<v1.0, [Kernel], []>, #spv.resource_limits<>> } {
+
+// CHECK-LABEL: @cl_fma
+//  CHECK-SAME: %[[A:.*]]: vector<4xf32>, %[[B:.*]]: vector<4xf32>, %[[C:.*]]: vector<4xf32>
+//       CHECK:   spv.CL.fma %[[A]], %[[B]], %[[C]] : vector<4xf32>
+func.func @cl_fma(%a: vector<4xf32>, %b: vector<4xf32>, %c: vector<4xf32>) -> vector<4xf32> {
+  %0 = vector.fma %a, %b, %c: vector<4xf32>
+  return %0 : vector<4xf32>
+}
+
+// CHECK-LABEL: @cl_fma_size1_vector
+//       CHECK:   spv.CL.fma %{{.+}} : f32
+func.func @cl_fma_size1_vector(%a: vector<1xf32>, %b: vector<1xf32>, %c: vector<1xf32>) -> vector<1xf32> {
+  %0 = vector.fma %a, %b, %c: vector<1xf32>
+  return %0 : vector<1xf32>
+}
+
+} // end module
+
+// -----
+
 // CHECK-LABEL: @broadcast
 //  CHECK-SAME: %[[A:.*]]: f32
 //       CHECK:   spv.CompositeConstruct %[[A]], %[[A]], %[[A]], %[[A]]
 //       CHECK:   spv.CompositeConstruct %[[A]], %[[A]]
 func.func @broadcast(%arg0 : f32) -> (vector<4xf32>, vector<2xf32>) {
   %0 = vector.broadcast %arg0 : f32 to vector<4xf32>
   %1 = vector.broadcast %arg0 : f32 to vector<2xf32>
   return %0, %1: vector<4xf32>, vector<2xf32>