[AMDGPU][MC][GFX11][NFC] Add missing tests for SOP instructions

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Summary

Add tests for s_pack_hl_b32_b16, s_setreg_imm32_b32 and s_wait_event.

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Thanks!

llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_sop2.txt

 # GFX11: s_xor_b64 s[104:105], s[2:3], s[100:101] ; encoding: [0x02,0x64,0xe8,0x8d]
 0x02,0x64,0xe8,0x8d
 
 # GFX11: s_xor_b64 s[104:105], s[2:3], s[4:5]    ; encoding: [0x02,0x04,0xe8,0x8d]
 0x02,0x04,0xe8,0x8d
 
 # GFX11: s_xor_b64 vcc, s[2:3], s[4:5]           ; encoding: [0x02,0x04,0xea,0x8d]
 0x02,0x04,0xea,0x8d
+
+# GFX11: s_pack_hl_b32_b16 s5, s1, s2 ; encoding: [0x01,0x02,0x85,0x9a]
+0x01,0x02,0x85,0x9a
+
+# GFX11: s_pack_hl_b32_b16 s5, s105, s105 ; encoding: [0x69,0x69,0x85,0x9a]
+0x69,0x69,0x85,0x9a
+
+# GFX11: s_pack_hl_b32_b16 s5, vcc_lo, ttmp15 ; encoding: [0x6a,0x7b,0x85,0x9a]
+0x6a,0x7b,0x85,0x9a
+
+# GFX11: s_pack_hl_b32_b16 s5, vcc_hi, 0xfe0b ; encoding: [0x6b,0xff,0x85,0x9a,0x0b,0xfe,0x00,0x00]
+0x6b,0xff,0x85,0x9a,0x0b,0xfe,0x00,0x00
+
+# GFX11: s_pack_hl_b32_b16 s5, ttmp15, src_scc ; encoding: [0x7b,0xfd,0x85,0x9a]
+0x7b,0xfd,0x85,0x9a
+
+# GFX11: s_pack_hl_b32_b16 s105, m0, 0.5 ; encoding: [0x7d,0xf0,0xe9,0x9a]
+0x7d,0xf0,0xe9,0x9a
+
+# GFX11: s_pack_hl_b32_b16 vcc_lo, exec_lo, -1 ; encoding: [0x7e,0xc1,0xea,0x9a]
+0x7e,0xc1,0xea,0x9a
+
+# GFX11: s_pack_hl_b32_b16 vcc_hi, exec_hi, null ; encoding: [0x7f,0x7c,0xeb,0x9a]
+0x7f,0x7c,0xeb,0x9a
+
+# GFX11: s_pack_hl_b32_b16 ttmp15, null, exec_lo ; encoding: [0x7c,0x7e,0xfb,0x9a]
+0x7c,0x7e,0xfb,0x9a
+
+# GFX11: s_pack_hl_b32_b16 m0, -1, exec_hi ; encoding: [0xc1,0x7f,0xfd,0x9a]
+0xc1,0x7f,0xfd,0x9a
+
+# GFX11: s_pack_hl_b32_b16 exec_lo, 0.5, m0 ; encoding: [0xf0,0x7d,0xfe,0x9a]
+0xf0,0x7d,0xfe,0x9a
+
+# GFX11: s_pack_hl_b32_b16 exec_hi, src_scc, vcc_lo ; encoding: [0xfd,0x6a,0xff,0x9a]
+0xfd,0x6a,0xff,0x9a
+
+# GFX11: s_pack_hl_b32_b16 null, 0xaf123456, vcc_hi ; encoding: [0xff,0x6b,0xfc,0x9a,0x56,0x34,0x12,0xaf]
+0xff,0x6b,0xfc,0x9a,0x56,0x34,0x12,0xaf

llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_sopk.txt

 # GFX11: s_waitcnt_vscnt s105, 0x1234            ; encoding: [0x34,0x12,0x69,0xbc]
 0x34,0x12,0x69,0xbc
 
 # GFX11: s_waitcnt_vscnt vcc_hi, 0x1234          ; encoding: [0x34,0x12,0x6b,0xbc]
 0x34,0x12,0x6b,0xbc
 
 # GFX11: s_waitcnt_vscnt vcc_lo, 0x1234          ; encoding: [0x34,0x12,0x6a,0xbc]
 0x34,0x12,0x6a,0xbc
+
+# GFX11: s_setreg_imm32_b32 hwreg(HW_REG_MODE), 0xaf123456 ; encoding: [0x01,0xf8,0x80,0xb9,0x56,0x34,0x12,0xaf]
+0x01,0xf8,0x80,0xb9,0x56,0x34,0x12,0xaf
+
+# GFX11: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 31, 1), 0xaf123456 ; encoding: [0xc1,0x07,0x80,0xb9,0x56,0x34,0x12,0xaf]
+0xc1,0x07,0x80,0xb9,0x56,0x34,0x12,0xaf
+
+# GFX11: s_setreg_imm32_b32 hwreg(HW_REG_STATUS), 0xaf123456 ; encoding: [0x02,0xf8,0x80,0xb9,0x56,0x34,0x12,0xaf]
+0x02,0xf8,0x80,0xb9,0x56,0x34,0x12,0xaf
+
+# GFX11: s_setreg_imm32_b32 hwreg(HW_REG_TRAPSTS), 0xaf123456 ; encoding: [0x03,0xf8,0x80,0xb9,0x56,0x34,0x12,0xaf]
+0x03,0xf8,0x80,0xb9,0x56,0x34,0x12,0xaf
+
+# GFX11: s_setreg_imm32_b32 hwreg(HW_REG_GPR_ALLOC), 0xaf123456 ; encoding: [0x05,0xf8,0x80,0xb9,0x56,0x34,0x12,0xaf]
+0x05,0xf8,0x80,0xb9,0x56,0x34,0x12,0xaf
+
+# GFX11: s_setreg_imm32_b32 hwreg(HW_REG_LDS_ALLOC), 0xaf123456 ; encoding: [0x06,0xf8,0x80,0xb9,0x56,0x34,0x12,0xaf]
+0x06,0xf8,0x80,0xb9,0x56,0x34,0x12,0xaf
+
+# GFX11: s_setreg_imm32_b32 hwreg(HW_REG_IB_STS), 0xaf123456 ; encoding: [0x07,0xf8,0x80,0xb9,0x56,0x34,0x12,0xaf]
+0x07,0xf8,0x80,0xb9,0x56,0x34,0x12,0xaf
+
+# GFX11: s_setreg_imm32_b32 hwreg(HW_REG_SH_MEM_BASES), 0xaf123456 ; encoding: [0x0f,0xf8,0x80,0xb9,0x56,0x34,0x12,0xaf]
+0x0f,0xf8,0x80,0xb9,0x56,0x34,0x12,0xaf
+
+# GFX11: s_setreg_imm32_b32 hwreg(HW_REG_FLAT_SCR_LO), 0xaf123456 ; encoding: [0x14,0xf8,0x80,0xb9,0x56,0x34,0x12,0xaf]
+0x14,0xf8,0x80,0xb9,0x56,0x34,0x12,0xaf
+
+# GFX11: s_setreg_imm32_b32 hwreg(HW_REG_FLAT_SCR_HI), 0xaf123456 ; encoding: [0x15,0xf8,0x80,0xb9,0x56,0x34,0x12,0xaf]
+0x15,0xf8,0x80,0xb9,0x56,0x34,0x12,0xaf
+
+# GFX11: s_setreg_imm32_b32 hwreg(HW_REG_HW_ID1), 0xaf123456 ; encoding: [0x17,0xf8,0x80,0xb9,0x56,0x34,0x12,0xaf]
+0x17,0xf8,0x80,0xb9,0x56,0x34,0x12,0xaf
+
+# GFX11: s_setreg_imm32_b32 hwreg(HW_REG_HW_ID2), 0xaf123456 ; encoding: [0x18,0xf8,0x80,0xb9,0x56,0x34,0x12,0xaf]
+0x18,0xf8,0x80,0xb9,0x56,0x34,0x12,0xaf

llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_sopp.txt

 # GFX11: s_waitcnt vmcnt(4) expcnt(3) lgkmcnt(2) ; encoding: [0x23,0x10,0x89,0xbf]
 0x23,0x10,0x89,0xbf
 
 # GFX11: s_wait_idle                             ; encoding: [0x00,0x00,0x8a,0xbf]
 0x00,0x00,0x8a,0xbf
 
 # GFX11: s_wakeup                                ; encoding: [0x00,0x00,0xb4,0xbf]
 0x00,0x00,0xb4,0xbf
+
+# GFX11: s_wait_event 0x3141 ; encoding: [0x41,0x31,0x8b,0xbf]
+0x41,0x31,0x8b,0xbf
+
+# GFX11: s_wait_event 0xc1d1 ; encoding: [0xd1,0xc1,0x8b,0xbf]
+0xd1,0xc1,0x8b,0xbf