Add an MCTargetMachine and use it to configure MCAsmInfo

[dsanders]

Summary

All targets require a registered MCTargetMachine, even if it's just
MCTargetMachine itself.

A small number of MCTargetMachine subclasses (namely PPCMCTargetMachine,
and X86MCTargetMachine) store the Triple in order to compare MacOSX
versions. Ideally, this would be possible without having to store a Triple.

A corresponding patch to clang will be committed along with this. The patch
is similar to the patches in the tools in ./tools/....

Mips currently obtains the ABI from the Triple architecture. This is wrong
since the architecture is the wrong source for this information, the value
is often misleading, and selecting the N32 ABI isn't possible. However,
it preserves the existing behaviour for the moment. A follow-up patch will
address these problems.

Follow up patches will expand the MCTargetMachine to other parts of the MC
layer.

[hfinkel]

As part of this change, you're creating classes whose primary function seems to be to cache results from calling member functions of Triple? Is there some performance benefit to doing so? Maintaining this pattern increases the maintenance burden on using Triple queries; why not just expose the Triple member for querying?

[dsanders]

It's really about disconnecting an ambiguous representation of the target (implied by the triple) from the need for an unambiguous representation of the desired target.

The Triple is a representation of the given string and provides some methods to help understand the usual meaning of that string. However, as discussed in 'The Trouble with Triples' thread there are some problems with using the triple as the representation of the target.

The first problem is that the same string can have multiple effective meanings, either as a result of a particular build being configured to use meanings that are not the usual meaning (such as the default CPU/ABI or perhaps specific details being overridden), or as a result of command line processing overriding the default meaning. For this problem we would like our target description to definitively inform the backend how it should behave.

The second is that multiple strings can have the same meaning, either for one of the same reasons, or because they really are synonyms. For this problem we would like to resolve the multiple representations to a single description of the desired behaviour.

MCTargetMachine is trying solve both of these problems. It currently looks like it's only caching values since nothing has begun using the ability to mutate the MCTargetMachine before it's used for the first time. Over the next few weeks, I intend to post patches that will make use of the temporary mutability of MCTargetMachine to resolve various issues with the Mips target particularly in clang-based toolchains that are intended to be drop-in replacements for gcc.

[echristo]

Traveling this week so responses are delayed.

[dsanders]

Traveling this week so responses are delayed.

No worries, thanks for letting me know.

[dsanders]

Fix a mistake in the arguments to createMCTargetMachine(). The Target should
not be an argument to the outermost function.

[dsanders]

Having written a couple follow-on patches and reached the point where MCSubtargetInfo can (almost) be migrated and used appropriately, there's an issue I need to bring up.

To avoid dereferencing null MCTargetMachine pointers held by partially initialized TargetMachines there's a need to pass a MCTargetMachine to createTargetMachine(). However, this makes it necessary to call createMCTargetMachine() from LLVMCreateTargetMachine(). We can't change the C-API so we have four options:

1. Allow a memory leak. Obviously this isn't a good choice.
2. Change TargetMachine to an is-a relationship with MCTargetMachine. This doesn't look possible because you end up with MipsTargetMachine is-a TargetMachine is-a MipsMCTargetMachine is-a MCTargetMachine and this can't happen for more than one target.
3. Have Target/TargetMachine own MCTargetMachines allocated by LLVMCreateTargetMachine()
4. Wrap TargetMachine pointers returned by the C-API in a new class that also owns the MCTargetMachine pointer for the existing C-API and have LLVMDisposeTargetMachine() delete the MCTargetMachine if it owns it.

I'm not keen on any of these but the fourth sounds most sensible since it keeps this problem in the C-API's domain without affecting C++. Thoughts?

[dsanders]

Ping.

[echristo]

Almost there :)

Back from vacation, digging out from under email.

[echristo]

Hi Daniel,

It looks like what you've done is take a wrapper around Triple and propagate it - basically redoing some of the TargetTuple work and just calling it MCTargetMachine. :)

It wasn't quite where I was going though, let me try and explain by taking a look at some of the normal TargetMachine class contents:

/// Low level target information such as relocation model. Non-const to
/// allow resetting optimization level per-function.
MCCodeGenInfo *CodeGenInfo;

/// Contains target specific asm information.
const MCAsmInfo *AsmInfo;

const MCRegisterInfo *MRI;
const MCInstrInfo *MII;
const MCSubtargetInfo *STI;

Where we've actually got a lot of the information you're passing your wrapped Triple into. The idea that I was trying to get across is that the MCTargetMachine should serve as the base holder class for a lot of this information and would be initialized similarly to the various TargetMachines, but with MC level equivalents where it matters, e.g. MCTargetOptions, etc.

If you look at MCTargetOptions, for example, it even has this:

/// getABIName - If this returns a non-empty string this represents the                      
/// textual name of the ABI that we want the backend to use, e.g. o32, or                    
/// aapcs-linux.                                                                             
StringRef getABIName() const;
std::string ABIName;

which will serve as a good way of solving your "I don't have the ABI" problem that you were mentioning before - as long as argument parsing will set it correctly when constructing MCTargetMachine.

Does this make sense? Seem like it's going the right direction to you?

-eric

[dsanders]

I think I've caught on to the difference between your mental model and mine. It's just been tricky to notice it because the things you've said here fit perfectly into my mental model. :-)

In my mental model, I have an object named MCTargetMachine describing the desired target. I configure this however I want (starting with the triple then mutating it according to command line options). I then give this MCTargetMachine to MCCodeGenInfo, MCAsmInfo, MCRegisterInfo, MCInstrInfo, MCSubtargetInfo, etc. when constructing them and they consult it whenever they want to know certain properties of the target. When you spoke about MCTargetMachine holding information from these classes, I read it as moving the decision-making values into MCTargetMachine and having them ask MCTargetMachine for it which is what I was already doing.

I suspect your mental model is that MCTargetMachine holds an owning pointer to MCCodeGenInfo, MCAsmInfo, MCRegisterInfo, MCInstrInfo, MCSubtargetInfo, etc. and is also responsible for constructing them. This model works pretty much the same way as mine to begin with. You construct a MCTargetMachine and configure it. The difference is that the users then ask MCTargetMachine to create the various objects on their behalf and MCTargetMachine passes itself into their respective constructors in order to configure them. Is that what you're going for?

If that understanding is correct then there are two major steps here.

• Encapsulate MC layer objects in MCTargetMachine and make it their owner. This is effectively moving user calls to createMC*() into MCTargetMachine.
• Update the constructors to take an MCTargetMachine or at least information originating from it.

With my existing plan being the latter of these two steps. As far as the end result is concerned, I don't think it matters too much which order we do the steps.
I suppose we have less user-visible churn if we do the encapsulation of the MC layer objects first though.

[echristo]

You've got my mental model fairly well established. I'll take a look at
this yesterday and make sure it's going to work the way I want.

Thanks for your patience!

-eric

[dsanders]

Great! I think it's best to abandon this patch and then I'll post a patch that just does the encapsulation step. After that, I'll post another version of this patch starting from that point. Does that sound good?

... is that MCTargetMachine holds an owning pointer to MCCodeGenInfo, MCAsmInfo ...

I've realised I made a mistake here. The pointers ought to be owned by the caller of MCTargetMachine::create*(). This is consistent with TargetMachine.

[dsanders]

Great! I think it's best to abandon this patch and then I'll post a patch that just does the
encapsulation step. After that, I'll post another version of this patch starting from that point. Does that sound good?

Do note that what you're talking about as "the TargetMachine is passed down" only happens for
very few objects underneath TargetMachine and that generally things are constructed with the bare
minimum of information.

I'm finding that some of these use more information than they first appear to but I agree that we should generally be passing information down rather than the whole object.

... is that MCTargetMachine holds an owning pointer to MCCodeGenInfo, MCAsmInfo ...

I've realised I made a mistake here. The pointers ought to be owned by the caller of MCTargetMachine::create*(). This is consistent with TargetMachine.

I don't agree with this part. I think the ownership hierarchy should be similar to TargetMachine in the way that TargetMachine owns TargetSubtargetInfo and it owns the things that depend upon it.

Sorry, I've been a bit unclear here. I mean that the create*() functions themselves give ownership to their caller. TargetMachine holds some ownership resulting from LLVMTargetMachine's calls to TargetMachine's create*() functions.

By the way, some of those members (e.g. MRI) look like they should be unique_ptr's. TargetMachine is manually deleting them in its destructor but nothing seems to set them aside from LLVMTargetMachine's calls to create*() in LLVMTargetMachine::initAsmInfo(). Do you agree?

---

From: Eric Christopher [[e-mail]]
Sent: 17 October 2015 12:17
To: [e-mail]; Daniel Sanders; [e-mail]
Cc: [e-mail]; [e-mail]; [e-mail]; [e-mail]; [e-mail]; [e-mail]; [e-mail]; [e-mail]
Subject: Re: [PATCH] D13193: Add an MCTargetMachine and use it to configure MCAsmInfo

[dsanders]

Abandoning in favour of a different patch series. I'll post the new one shortly.

include/llvm/MC/MCTargetMachine.h

+//===-- llvm/MC/MCTargetMachine.h - Target Information ----------*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file defines the MCTargetMachine classes.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_MC_MCTARGETMACHINE_H
+#define LLVM_MC_MCTARGETMACHINE_H
+
+namespace llvm {
+class Target;
+class Triple;
+
+//===----------------------------------------------------------------------===//
+///
+/// Primary interface to the complete machine description for the target
+/// machine.  All target-specific information should be accessible through this
+/// interface.
+///
+class MCTargetMachine {
+  MCTargetMachine(const MCTargetMachine &) = delete;
+  void operator=(const MCTargetMachine &) = delete;
+
+protected:
+  /// The Target that this machine was created for.
+  const Target &TheTarget;
+
+public:
+  MCTargetMachine(const Target &T, const Triple &);
+
+  const Target &getTarget() const { return TheTarget; }
+};
+
+} // End llvm namespace
+
+#endif

include/llvm/Support/TargetRegistry.h

 class MCInstPrinter;
 class MCInstrInfo;
 class MCRegisterInfo;
 class MCStreamer;
 class MCSubtargetInfo;
 class MCSymbolizer;
 class MCRelocationInfo;
 class MCTargetAsmParser;
+class MCTargetMachine;
 class MCTargetOptions;
 class MCTargetStreamer;
 class TargetMachine;
 class TargetOptions;
 class raw_ostream;
 class raw_pwrite_stream;
 class formatted_raw_ostream;
 

 /// part of their initialization.
 class Target {
 public:
   friend struct TargetRegistry;
 
   typedef bool (*ArchMatchFnTy)(Triple::ArchType Arch);
 
   typedef MCAsmInfo *(*MCAsmInfoCtorFnTy)(const MCRegisterInfo &MRI,
-                                          const Triple &TT);
+                                          const MCTargetMachine &MCTM);
   typedef MCCodeGenInfo *(*MCCodeGenInfoCtorFnTy)(const Triple &TT,
                                                   Reloc::Model RM,
                                                   CodeModel::Model CM,
                                                   CodeGenOpt::Level OL);
   typedef MCInstrInfo *(*MCInstrInfoCtorFnTy)(void);
   typedef MCInstrAnalysis *(*MCInstrAnalysisCtorFnTy)(const MCInstrInfo *Info);
   typedef MCRegisterInfo *(*MCRegInfoCtorFnTy)(const Triple &TT);
   typedef MCSubtargetInfo *(*MCSubtargetInfoCtorFnTy)(const Triple &TT,
                                                       StringRef CPU,
                                                       StringRef Features);
   typedef TargetMachine *(*TargetMachineCtorTy)(
       const Target &T, const Triple &TT, StringRef CPU, StringRef Features,
       const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM,
       CodeGenOpt::Level OL);
+  typedef MCTargetMachine *(*MCTargetMachineCtorTy)(const Target &T,
+                                                    const Triple &TT);
   // If it weren't for layering issues (this header is in llvm/Support, but
   // depends on MC?) this should take the Streamer by value rather than rvalue
   // reference.
   typedef AsmPrinter *(*AsmPrinterCtorTy)(
       TargetMachine &TM, std::unique_ptr<MCStreamer> &&Streamer);
   typedef MCAsmBackend *(*MCAsmBackendCtorTy)(const Target &T,
                                               const MCRegisterInfo &MRI,
                                               const Triple &TT, StringRef CPU);
private:
   /// MCSubtargetInfoCtorFn - Constructor function for this target's
   /// MCSubtargetInfo, if registered.
   MCSubtargetInfoCtorFnTy MCSubtargetInfoCtorFn;
 
   /// TargetMachineCtorFn - Construction function for this target's
   /// TargetMachine, if registered.
   TargetMachineCtorTy TargetMachineCtorFn;
 
+  /// MCTargetMachineCtorFn - Construction function for this target's
+  /// MCTargetMachine, if registered.
+  MCTargetMachineCtorTy MCTargetMachineCtorFn;
+
   /// MCAsmBackendCtorFn - Construction function for this target's
   /// MCAsmBackend, if registered.
   MCAsmBackendCtorTy MCAsmBackendCtorFn;
 
   /// MCAsmParserCtorFn - Construction function for this target's
   /// MCTargetAsmParser, if registered.
   MCAsmParserCtorTy MCAsmParserCtorFn;
 
public:
   /// @{
 
   /// hasJIT - Check if this targets supports the just-in-time compilation.
   bool hasJIT() const { return HasJIT; }
 
   /// hasTargetMachine - Check if this target supports code generation.
   bool hasTargetMachine() const { return TargetMachineCtorFn != nullptr; }
 
+  /// hasMCTargetMachine - Check if this target supports machine code.
+  bool hasMCTargetMachine() const { return MCTargetMachineCtorFn != nullptr; }
+
   /// hasMCAsmBackend - Check if this target supports .o generation.
   bool hasMCAsmBackend() const { return MCAsmBackendCtorFn != nullptr; }
 
   /// @}
   /// @name Feature Constructors
   /// @{
 
   /// createMCAsmInfo - Create a MCAsmInfo implementation for the specified
   /// target triple.
-  ///
-  /// \param TheTriple This argument is used to determine the target machine
-  /// feature set; it should always be provided. Generally this should be
-  /// either the target triple from the module, or the target triple of the
-  /// host if that does not exist.
   MCAsmInfo *createMCAsmInfo(const MCRegisterInfo &MRI,
-                             StringRef TheTriple) const {
+                             const MCTargetMachine &MCTM) const {
     if (!MCAsmInfoCtorFn)
       return nullptr;
-    return MCAsmInfoCtorFn(MRI, Triple(TheTriple));
+    return MCAsmInfoCtorFn(MRI, MCTM);
   }
 
   /// createMCCodeGenInfo - Create a MCCodeGenInfo implementation.
   ///
   MCCodeGenInfo *createMCCodeGenInfo(StringRef TT, Reloc::Model RM,
                                      CodeModel::Model CM,
                                      CodeGenOpt::Level OL) const {
     if (!MCCodeGenInfoCtorFn)
createTargetMachine(StringRef TT, StringRef CPU, StringRef Features,
                       CodeModel::Model CM = CodeModel::Default,
                       CodeGenOpt::Level OL = CodeGenOpt::Default) const {
     if (!TargetMachineCtorFn)
       return nullptr;
     return TargetMachineCtorFn(*this, Triple(TT), CPU, Features, Options, RM,
                                CM, OL);
   }
 
+  /// createMCTargetMachine - Create a target specific machine implementation
+  /// for the specified \p Triple.
+  ///
+  /// \param TT This argument is used to determine the target machine
+  /// feature set; it should always be provided. Generally this should be
+  /// either the target triple from the module, or the target triple of the
+  /// host if that does not exist.
+  MCTargetMachine *createMCTargetMachine(const Triple &TT) const {
+    if (!MCTargetMachineCtorFn)
+      return nullptr;
+    return MCTargetMachineCtorFn(*this, TT);
+  }
+
   /// createMCAsmBackend - Create a target specific assembly parser.
   ///
   /// \param TheTriple The target triple string.
   MCAsmBackend *createMCAsmBackend(const MCRegisterInfo &MRI,
                                    StringRef TheTriple, StringRef CPU) const {
     if (!MCAsmBackendCtorFn)
       return nullptr;
     return MCAsmBackendCtorFn(*this, MRI, Triple(TheTriple), CPU);
struct TargetRegistry {
   /// this is done by initializing all targets at program startup.
   ///
   /// @param T - The target being registered.
   /// @param Fn - A function to construct a TargetMachine for the target.
   static void RegisterTargetMachine(Target &T, Target::TargetMachineCtorTy Fn) {
     T.TargetMachineCtorFn = Fn;
   }
 
+  /// RegisterMCTargetMachine - Register a MCTargetMachine implementation for
+  /// the given target.
+  ///
+  /// Clients are responsible for ensuring that registration doesn't occur
+  /// while another thread is attempting to access the registry. Typically
+  /// this is done by initializing all targets at program startup.
+  ///
+  /// @param T - The target being registered.
+  /// @param Fn - A function to construct a MCTargetMachine for the target.
+  static void RegisterMCTargetMachine(Target &T,
+                                      Target::MCTargetMachineCtorTy Fn) {
+    T.MCTargetMachineCtorFn = Fn;
+  }
+
   /// RegisterMCAsmBackend - Register a MCAsmBackend implementation for the
   /// given target.
   ///
   /// Clients are responsible for ensuring that registration doesn't occur
   /// while another thread is attempting to access the registry. Typically
   /// this is done by initializing all targets at program startup.
   ///
   /// @param T - The target being registered.

 /// RegisterMCAsmInfo - Helper template for registering a target assembly info
 /// implementation.  This invokes the static "Create" method on the class to
 /// actually do the construction.  Usage:
 ///
 /// extern "C" void LLVMInitializeFooTarget() {
 ///   extern Target TheFooTarget;
 ///   RegisterMCAsmInfo<FooMCAsmInfo> X(TheFooTarget);
 /// }
-template <class MCAsmInfoImpl> struct RegisterMCAsmInfo {
+template <class MCAsmInfoImpl, class MCTargetMachineImpl = MCTargetMachine>
+struct RegisterMCAsmInfo {
   RegisterMCAsmInfo(Target &T) {
     TargetRegistry::RegisterMCAsmInfo(T, &Allocator);
   }
 
 private:
   static MCAsmInfo *Allocator(const MCRegisterInfo & /*MRI*/,
-                              const Triple &TT) {
-    return new MCAsmInfoImpl(TT);
+                              const MCTargetMachine &MCTM) {
+    return new MCAsmInfoImpl(static_cast<const MCTargetMachineImpl &>(MCTM));
   }
 };
 
 /// RegisterMCAsmInfoFn - Helper template for registering a target assembly info
 /// implementation.  This invokes the specified function to do the
 /// construction.  Usage:
 ///
 /// extern "C" void LLVMInitializeFooTarget() {
private:
   static TargetMachine *Allocator(const Target &T, const Triple &TT,
                                   StringRef CPU, StringRef FS,
                                   const TargetOptions &Options, Reloc::Model RM,
                                   CodeModel::Model CM, CodeGenOpt::Level OL) {
     return new TargetMachineImpl(T, TT, CPU, FS, Options, RM, CM, OL);
   }
 };
 
+/// RegisterMCTargetMachine - Helper template for registering a target machine
+/// implementation, for use in the target machine initialization
+/// function. Usage:
+///
+/// extern "C" void LLVMInitializeFooTarget() {
+///   extern Target TheFooTarget;
+///   RegisterMCTargetMachine<FooMCTargetMachine> X(TheFooTarget);
+/// }
+template <class MCTargetMachineImpl> struct RegisterMCTargetMachine {
+  RegisterMCTargetMachine(Target &T) {
+    TargetRegistry::RegisterMCTargetMachine(T, &Allocator);
+  }
+
+private:
+  static MCTargetMachine *Allocator(const Target &T, const Triple &TT) {
+    return new MCTargetMachineImpl(T, TT);
+  }
+};
+
 /// RegisterMCAsmBackend - Helper template for registering a target specific
 /// assembler backend. Usage:
 ///
 /// extern "C" void LLVMInitializeFooMCAsmBackend() {
 ///   extern Target TheFooTarget;
 ///   RegisterMCAsmBackend<FooAsmLexer> X(TheFooTarget);
 /// }
 template <class MCAsmBackendImpl> struct RegisterMCAsmBackend {

include/llvm/Target/TargetMachine.h

 class MachineFunctionInitializer;
 class MCAsmInfo;
 class MCCodeGenInfo;
 class MCContext;
 class MCInstrInfo;
 class MCRegisterInfo;
 class MCSubtargetInfo;
 class MCSymbol;
+class MCTargetMachine;
 class Target;
 class DataLayout;
 class TargetLibraryInfo;
 class TargetFrameLowering;
 class TargetIRAnalysis;
 class TargetIntrinsicInfo;
 class TargetLowering;
 class TargetPassConfig;
protected: // Can only create subclasses.
   const DataLayout DL;
 
   /// Triple string, CPU name, and target feature strings the TargetMachine
   /// instance is created with.
   Triple TargetTriple;
   std::string TargetCPU;
   std::string TargetFS;
 
+  /// Information about the target as it relates to the MC layer.
+  const MCTargetMachine *MCTM;
+
   /// Low level target information such as relocation model. Non-const to
   /// allow resetting optimization level per-function.
   MCCodeGenInfo *CodeGenInfo;
 
   /// Contains target specific asm information.
   const MCAsmInfo *AsmInfo;
 
   const MCRegisterInfo *MRI;

lib/CodeGen/LLVMTargetMachine.cpp

 // Enable or disable FastISel. Both options are needed, because
 // FastISel is enabled by default with -fast, and we wish to be
 // able to enable or disable fast-isel independently from -O0.
 static cl::opt<cl::boolOrDefault>
 EnableFastISelOption("fast-isel", cl::Hidden,
   cl::desc("Enable the \"fast\" instruction selector"));
 
 void LLVMTargetMachine::initAsmInfo() {
+  MCTM = TheTarget.createMCTargetMachine(getTargetTriple());
+  assert(MCTM && "MCTargetMachine not initialized");
   MRI = TheTarget.createMCRegInfo(getTargetTriple().str());
   MII = TheTarget.createMCInstrInfo();
   // FIXME: Having an MCSubtargetInfo on the target machine is a hack due
   // to some backends having subtarget feature dependent module level
   // code generation. This is similar to the hack in the AsmPrinter for
   // module level assembly etc.
   STI = TheTarget.createMCSubtargetInfo(getTargetTriple().str(), getTargetCPU(),
                                         getTargetFeatureString());
 
-  MCAsmInfo *TmpAsmInfo =
-      TheTarget.createMCAsmInfo(*MRI, getTargetTriple().str());
+  MCAsmInfo *TmpAsmInfo = TheTarget.createMCAsmInfo(*MRI, *MCTM);
   // TargetSelect.h moved to a different directory between LLVM 2.9 and 3.0,
   // and if the old one gets included then MCAsmInfo will be NULL and
   // we'll crash later.
   // Provide the user with a useful error message about what's wrong.
   assert(TmpAsmInfo && "MCAsmInfo not initialized. "
          "Make sure you include the correct TargetSelect.h"
          "and that InitializeAllTargetMCs() is being invoked!");
 

lib/MC/CMakeLists.txt

add_llvm_library(LLVMMC
   MCSectionCOFF.cpp
   MCSectionELF.cpp
   MCSectionMachO.cpp
   MCStreamer.cpp
   MCSubtargetInfo.cpp
   MCSymbol.cpp
   MCSymbolELF.cpp
   MCSymbolizer.cpp
+  MCTargetMachine.cpp
   MCTargetOptions.cpp
   MCValue.cpp
   MCWin64EH.cpp
   MCWinEH.cpp
   MachObjectWriter.cpp
   StringTableBuilder.cpp
   SubtargetFeature.cpp
   WinCOFFObjectWriter.cpp

lib/MC/MCDisassembler/Disassembler.cpp

LLVMCreateDisasmCPUFeatures(const char *TT, const char *CPU,
                             LLVMOpInfoCallback GetOpInfo,
                             LLVMSymbolLookupCallback SymbolLookUp) {
   // Get the target.
   std::string Error;
   const Target *TheTarget = TargetRegistry::lookupTarget(TT, Error);
   if (!TheTarget)
     return nullptr;
 
+  const MCTargetMachine *MCTM = TheTarget->createMCTargetMachine(Triple(TT));
+  if (!MCTM)
+    return nullptr;
+
   const MCRegisterInfo *MRI = TheTarget->createMCRegInfo(TT);
   if (!MRI)
     return nullptr;
 
   // Get the assembler info needed to setup the MCContext.
-  const MCAsmInfo *MAI = TheTarget->createMCAsmInfo(*MRI, TT);
+  const MCAsmInfo *MAI = TheTarget->createMCAsmInfo(*MRI, *MCTM);
   if (!MAI)
     return nullptr;
 
   const MCInstrInfo *MII = TheTarget->createMCInstrInfo();
   if (!MII)
     return nullptr;
 
   const MCSubtargetInfo *STI =

lib/MC/MCTargetMachine.cpp

+//===-- MCTargetMachine.cpp - General Target Information -------------------==//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file describes the general parts of a MC Target machine.
+//
+//===----------------------------------------------------------------------===//
+
+#include "llvm/MC/MCTargetMachine.h"
+#include "llvm/Support/TargetRegistry.h"
+using namespace llvm;
+
+MCTargetMachine::MCTargetMachine(const Target &T, const Triple &)
+    : TheTarget(T) {}

lib/Object/IRObjectFile.cpp

 #include "llvm/IR/Module.h"
 #include "llvm/MC/MCAsmInfo.h"
 #include "llvm/MC/MCContext.h"
 #include "llvm/MC/MCInstrInfo.h"
 #include "llvm/MC/MCObjectFileInfo.h"
 #include "llvm/MC/MCParser/MCAsmParser.h"
 #include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/MC/MCSubtargetInfo.h"
+#include "llvm/MC/MCTargetMachine.h"
 #include "llvm/MC/MCTargetAsmParser.h"
 #include "llvm/Object/ObjectFile.h"
 #include "llvm/Support/MemoryBuffer.h"
 #include "llvm/Support/SourceMgr.h"
 #include "llvm/Support/TargetRegistry.h"
 #include "llvm/Support/raw_ostream.h"
 using namespace llvm;
 using namespace object;
 
 IRObjectFile::IRObjectFile(MemoryBufferRef Object, std::unique_ptr<Module> Mod)
     : SymbolicFile(Binary::ID_IR, Object), M(std::move(Mod)) {
   Mang.reset(new Mangler());
 
   const std::string &InlineAsm = M->getModuleInlineAsm();
   if (InlineAsm.empty())
     return;
 
   Triple TT(M->getTargetTriple());
   std::string Err;
   const Target *T = TargetRegistry::lookupTarget(TT.str(), Err);
   if (!T)
     return;
 
+  std::unique_ptr<MCTargetMachine> MCTM(T->createMCTargetMachine(TT));
+  if (!MCTM)
+    return;
+
   std::unique_ptr<MCRegisterInfo> MRI(T->createMCRegInfo(TT.str()));
   if (!MRI)
     return;
 
-  std::unique_ptr<MCAsmInfo> MAI(T->createMCAsmInfo(*MRI, TT.str()));
+  std::unique_ptr<MCAsmInfo> MAI(T->createMCAsmInfo(*MRI, *MCTM));
   if (!MAI)
     return;
 
   std::unique_ptr<MCSubtargetInfo> STI(
       T->createMCSubtargetInfo(TT.str(), "", ""));
   if (!STI)
     return;
 

lib/Target/AArch64/MCTargetDesc/AArch64MCAsmInfo.h

 #define LLVM_LIB_TARGET_AARCH64_MCTARGETDESC_AARCH64MCASMINFO_H
 
 #include "llvm/MC/MCAsmInfoDarwin.h"
 #include "llvm/MC/MCAsmInfoELF.h"
 
 namespace llvm {
 class MCStreamer;
 class Target;
-class Triple;
+class AArch64MCTargetMachine;
 
 struct AArch64MCAsmInfoDarwin : public MCAsmInfoDarwin {
   explicit AArch64MCAsmInfoDarwin();
   const MCExpr *
   getExprForPersonalitySymbol(const MCSymbol *Sym, unsigned Encoding,
                               MCStreamer &Streamer) const override;
 };
 
 struct AArch64MCAsmInfoELF : public MCAsmInfoELF {
-  explicit AArch64MCAsmInfoELF(const Triple &T);
+  explicit AArch64MCAsmInfoELF(const AArch64MCTargetMachine &T);
 };
 
 } // namespace llvm
 
 #endif

lib/Target/AArch64/MCTargetDesc/AArch64MCAsmInfo.cpp

 //===-- AArch64MCAsmInfo.cpp - AArch64 asm properties ---------------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file contains the declarations of the AArch64MCAsmInfo properties.
 //
 //===----------------------------------------------------------------------===//
 
 #include "AArch64MCAsmInfo.h"
-#include "llvm/ADT/Triple.h"
+#include "AArch64MCTargetMachine.h"
 #include "llvm/MC/MCContext.h"
 #include "llvm/MC/MCExpr.h"
 #include "llvm/MC/MCStreamer.h"
 #include "llvm/Support/CommandLine.h"
 using namespace llvm;
 
 enum AsmWriterVariantTy {
   Default = -1,
const MCExpr *AArch64MCAsmInfoDarwin::getExprForPersonalitySymbol(
   const MCExpr *Res =
       MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_GOT, Context);
   MCSymbol *PCSym = Context.createTempSymbol();
   Streamer.EmitLabel(PCSym);
   const MCExpr *PC = MCSymbolRefExpr::create(PCSym, Context);
   return MCBinaryExpr::createSub(Res, PC, Context);
 }
 
-AArch64MCAsmInfoELF::AArch64MCAsmInfoELF(const Triple &T) {
-  if (T.getArch() == Triple::aarch64_be)
-    IsLittleEndian = false;
+AArch64MCAsmInfoELF::AArch64MCAsmInfoELF(const AArch64MCTargetMachine &MCTM) {
+  IsLittleEndian = MCTM.isLittleEndian();
 
   // We prefer NEON instructions to be printed in the short form.
   AssemblerDialect = AsmWriterVariant == Default ? 0 : AsmWriterVariant;
 
   PointerSize = 8;
 
   // ".comm align is in bytes but .align is pow-2."
   AlignmentIsInBytes = false;

lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp

 //===-- AArch64MCTargetDesc.cpp - AArch64 Target Descriptions ---*- C++ -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file provides AArch64 specific target descriptions.
 //
 //===----------------------------------------------------------------------===//
 
 #include "AArch64MCTargetDesc.h"
 #include "AArch64ELFStreamer.h"
 #include "AArch64MCAsmInfo.h"
+#include "AArch64MCTargetMachine.h"
 #include "InstPrinter/AArch64InstPrinter.h"
 #include "llvm/MC/MCCodeGenInfo.h"
 #include "llvm/MC/MCInstrInfo.h"
 #include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/MC/MCStreamer.h"
 #include "llvm/MC/MCSubtargetInfo.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/TargetRegistry.h"

 
 static MCRegisterInfo *createAArch64MCRegisterInfo(const Triple &Triple) {
   MCRegisterInfo *X = new MCRegisterInfo();
   InitAArch64MCRegisterInfo(X, AArch64::LR);
   return X;
 }
 
 static MCAsmInfo *createAArch64MCAsmInfo(const MCRegisterInfo &MRI,
-                                         const Triple &TheTriple) {
+                                         const MCTargetMachine &MCTM_) {
+  const AArch64MCTargetMachine &MCTM =
+      static_cast<const AArch64MCTargetMachine &>(MCTM_);
   MCAsmInfo *MAI;
-  if (TheTriple.isOSBinFormatMachO())
+  if (MCTM.isOSBinFormatMachO())
     MAI = new AArch64MCAsmInfoDarwin();
   else {
-    assert(TheTriple.isOSBinFormatELF() && "Only expect Darwin or ELF");
-    MAI = new AArch64MCAsmInfoELF(TheTriple);
+    assert(MCTM.isOSBinFormatELF() && "Only expect Darwin or ELF");
+    MAI = new AArch64MCAsmInfoELF(MCTM);
   }
 
   // Initial state of the frame pointer is SP.
   unsigned Reg = MRI.getDwarfRegNum(AArch64::SP, true);
   MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(nullptr, Reg, 0);
   MAI->addInitialFrameState(Inst);
 
   return MAI;
return createMachOStreamer(Ctx, TAB, OS, Emitter, RelaxAll,
                              DWARFMustBeAtTheEnd,
                              /*LabelSections*/ true);
 }
 
 // Force static initialization.
 extern "C" void LLVMInitializeAArch64TargetMC() {
   for (Target *T :
        {&TheAArch64leTarget, &TheAArch64beTarget, &TheARM64Target}) {
+    // Register the MC target machine
+    RegisterMCTargetMachine<AArch64MCTargetMachine> Y(*T);
+
     // Register the MC asm info.
     RegisterMCAsmInfoFn X(*T, createAArch64MCAsmInfo);
 
     // Register the MC codegen info.
     TargetRegistry::RegisterMCCodeGenInfo(*T, createAArch64MCCodeGenInfo);
 
     // Register the MC instruction info.
     TargetRegistry::RegisterMCInstrInfo(*T, createAArch64MCInstrInfo);

lib/Target/AArch64/MCTargetDesc/AArch64MCTargetMachine.h

+//===-- AArch64MCTargetMachine.h - AArch64 Target Information ---*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file defines the MCTargetMachine classes.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIB_TARGET_AARCH64_AARCH64MCTARGETMACHINE_H
+#define LLVM_LIB_TARGET_AARCH64_AARCH64MCTARGETMACHINE_H
+
+#include "llvm/ADT/Triple.h"
+#include "llvm/MC/MCTargetMachine.h"
+
+namespace llvm {
+class Target;
+
+class AArch64MCTargetMachine : public MCTargetMachine {
+  AArch64MCTargetMachine(const AArch64MCTargetMachine &) = delete;
+  void operator=(const AArch64MCTargetMachine &) = delete;
+
+  bool IsOSDarwin;
+  bool IsOSBinFormatMachO;
+  bool IsOSBinFormatELF;
+  bool IsLittleEndian;
+
+public:
+  AArch64MCTargetMachine(const Target &T, const Triple &TargetTriple)
+      : MCTargetMachine(T, TargetTriple), IsOSDarwin(TargetTriple.isOSDarwin()),
+        IsOSBinFormatMachO(TargetTriple.isOSBinFormatMachO()),
+        IsOSBinFormatELF(TargetTriple.isOSBinFormatELF()),
+        IsLittleEndian(TargetTriple.getArch() != Triple::aarch64_be) {}
+
+  bool isOSDarwin() const { return IsOSDarwin; }
+  bool isOSBinFormatMachO() const { return IsOSBinFormatMachO; };
+  bool isOSBinFormatELF() const { return IsOSBinFormatELF; };
+  bool isLittleEndian() const { return IsLittleEndian; }
+};
+
+} // End llvm namespace
+
+#endif

lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCAsmInfo.h

 //
 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_LIB_TARGET_R600_MCTARGETDESC_AMDGPUMCASMINFO_H
 #define LLVM_LIB_TARGET_R600_MCTARGETDESC_AMDGPUMCASMINFO_H
 
 #include "llvm/MC/MCAsmInfoELF.h"
 namespace llvm {
-
-class Triple;
+class MCTargetMachine;
 
 // If you need to create another MCAsmInfo class, which inherits from MCAsmInfo,
 // you will need to make sure your new class sets PrivateGlobalPrefix to
 // a prefix that won't appear in a function name.  The default value
 // for PrivateGlobalPrefix is 'L', so it will consider any function starting
 // with 'L' as a local symbol.
 class AMDGPUMCAsmInfo : public MCAsmInfoELF {
 public:
-  explicit AMDGPUMCAsmInfo(const Triple &TT);
+  explicit AMDGPUMCAsmInfo(const MCTargetMachine &TM);
 };
 } // namespace llvm
 #endif

lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCAsmInfo.cpp

 //===-- MCTargetDesc/AMDGPUMCAsmInfo.cpp - Assembly Info ------------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 /// \file
 //===----------------------------------------------------------------------===//
 
 #include "AMDGPUMCAsmInfo.h"
 
 using namespace llvm;
-AMDGPUMCAsmInfo::AMDGPUMCAsmInfo(const Triple &TT) : MCAsmInfoELF() {
+AMDGPUMCAsmInfo::AMDGPUMCAsmInfo(const MCTargetMachine &MCTM) : MCAsmInfoELF() {
   HasSingleParameterDotFile = false;
   //===------------------------------------------------------------------===//
   MaxInstLength = 16;
   SeparatorString = "\n";
   CommentString = ";";
   PrivateLabelPrefix = "";
   InlineAsmStart = ";#ASMSTART";
   InlineAsmEnd = ";#ASMEND";

lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.cpp

 #include "InstPrinter/AMDGPUInstPrinter.h"
 #include "SIDefines.h"
 #include "llvm/MC/MCCodeGenInfo.h"
 #include "llvm/MC/MCContext.h"
 #include "llvm/MC/MCInstrInfo.h"
 #include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/MC/MCStreamer.h"
 #include "llvm/MC/MCSubtargetInfo.h"
+#include "llvm/MC/MCTargetMachine.h"
 #include "llvm/MC/MachineLocation.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/TargetRegistry.h"
 
 using namespace llvm;
 
 #define GET_INSTRINFO_MC_DESC
 #include "AMDGPUGenInstrInfo.inc"

 static MCTargetStreamer * createAMDGPUObjectTargetStreamer(
                                                    MCStreamer &S,
                                                    const MCSubtargetInfo &STI) {
   return new AMDGPUTargetELFStreamer(S);
 }
 
 extern "C" void LLVMInitializeAMDGPUTargetMC() {
   for (Target *T : {&TheAMDGPUTarget, &TheGCNTarget}) {
+    RegisterMCTargetMachine<MCTargetMachine> Y(*T);
     RegisterMCAsmInfo<AMDGPUMCAsmInfo> X(*T);
 
     TargetRegistry::RegisterMCCodeGenInfo(*T, createAMDGPUMCCodeGenInfo);
     TargetRegistry::RegisterMCInstrInfo(*T, createAMDGPUMCInstrInfo);
     TargetRegistry::RegisterMCRegInfo(*T, createAMDGPUMCRegisterInfo);
     TargetRegistry::RegisterMCSubtargetInfo(*T, createAMDGPUMCSubtargetInfo);
     TargetRegistry::RegisterMCInstPrinter(*T, createAMDGPUMCInstPrinter);
     TargetRegistry::RegisterMCAsmBackend(*T, createAMDGPUAsmBackend);

lib/Target/ARM/MCTargetDesc/ARMMCAsmInfo.h

 #ifndef LLVM_LIB_TARGET_ARM_MCTARGETDESC_ARMMCASMINFO_H
 #define LLVM_LIB_TARGET_ARM_MCTARGETDESC_ARMMCASMINFO_H
 
 #include "llvm/MC/MCAsmInfoCOFF.h"
 #include "llvm/MC/MCAsmInfoDarwin.h"
 #include "llvm/MC/MCAsmInfoELF.h"
 
 namespace llvm {
-class Triple;
+class ARMMCTargetMachine;
 
 class ARMMCAsmInfoDarwin : public MCAsmInfoDarwin {
   virtual void anchor();
 
 public:
-  explicit ARMMCAsmInfoDarwin(const Triple &TheTriple);
+  explicit ARMMCAsmInfoDarwin(const ARMMCTargetMachine &MCTM);
 };
 
 class ARMELFMCAsmInfo : public MCAsmInfoELF {
   void anchor() override;
 
 public:
-  explicit ARMELFMCAsmInfo(const Triple &TT);
+  explicit ARMELFMCAsmInfo(const ARMMCTargetMachine &MCTM);
 
   void setUseIntegratedAssembler(bool Value) override;
 };
 
 class ARMCOFFMCAsmInfoMicrosoft : public MCAsmInfoMicrosoft {
   void anchor() override;
 
 public:

lib/Target/ARM/MCTargetDesc/ARMMCAsmInfo.cpp

 //===-- ARMMCAsmInfo.cpp - ARM asm properties -----------------------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file contains the declarations of the ARMMCAsmInfo properties.
 //
 //===----------------------------------------------------------------------===//
 
 #include "ARMMCAsmInfo.h"
-#include "llvm/ADT/Triple.h"
+#include "ARMMCTargetMachine.h"
 #include "llvm/Support/CommandLine.h"
 
 using namespace llvm;
 
 void ARMMCAsmInfoDarwin::anchor() { }
 
-ARMMCAsmInfoDarwin::ARMMCAsmInfoDarwin(const Triple &TheTriple) {
-  if ((TheTriple.getArch() == Triple::armeb) ||
-      (TheTriple.getArch() == Triple::thumbeb))
-    IsLittleEndian = false;
+ARMMCAsmInfoDarwin::ARMMCAsmInfoDarwin(const ARMMCTargetMachine &MCTM) {
+  IsLittleEndian = MCTM.isLittleEndian();
 
   Data64bitsDirective = nullptr;
   CommentString = "@";
   Code16Directive = ".code\t16";
   Code32Directive = ".code\t32";
   UseDataRegionDirectives = true;
 
   SupportsDebugInformation = true;
 
   // Exceptions handling
   ExceptionsType = ExceptionHandling::SjLj;
 
   UseIntegratedAssembler = true;
 }
 
 void ARMELFMCAsmInfo::anchor() { }
 
-ARMELFMCAsmInfo::ARMELFMCAsmInfo(const Triple &TheTriple) {
-  if ((TheTriple.getArch() == Triple::armeb) ||
-      (TheTriple.getArch() == Triple::thumbeb))
-    IsLittleEndian = false;
+ARMELFMCAsmInfo::ARMELFMCAsmInfo(const ARMMCTargetMachine &MCTM) {
+  IsLittleEndian = MCTM.isLittleEndian();
 
   // ".comm align is in bytes but .align is pow-2."
   AlignmentIsInBytes = false;
 
   Data64bitsDirective = nullptr;
   CommentString = "@";
   Code16Directive = ".code\t16";
   Code32Directive = ".code\t32";
 
   SupportsDebugInformation = true;
 
   // Exceptions handling
-  switch (TheTriple.getOS()) {
+  switch (MCTM.getOS()) {
   case Triple::Bitrig:
   case Triple::NetBSD:
     ExceptionsType = ExceptionHandling::DwarfCFI;
     break;
   default:
     ExceptionsType = ExceptionHandling::ARM;
     break;
   }

lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp

 //===-- ARMMCTargetDesc.cpp - ARM Target Descriptions ---------------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file provides ARM specific target descriptions.
 //
 //===----------------------------------------------------------------------===//
 
 #include "ARMBaseInfo.h"
 #include "ARMMCAsmInfo.h"
 #include "ARMMCTargetDesc.h"
+#include "ARMMCTargetMachine.h"
 #include "InstPrinter/ARMInstPrinter.h"
 #include "llvm/ADT/Triple.h"
 #include "llvm/MC/MCCodeGenInfo.h"
 #include "llvm/MC/MCELFStreamer.h"
 #include "llvm/MC/MCInstrAnalysis.h"
 #include "llvm/MC/MCInstrInfo.h"
 #include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/MC/MCStreamer.h"

 
 static MCRegisterInfo *createARMMCRegisterInfo(const Triple &Triple) {
   MCRegisterInfo *X = new MCRegisterInfo();
   InitARMMCRegisterInfo(X, ARM::LR, 0, 0, ARM::PC);
   return X;
 }
 
 static MCAsmInfo *createARMMCAsmInfo(const MCRegisterInfo &MRI,
-                                     const Triple &TheTriple) {
+                                     const MCTargetMachine &MCTM_) {
+  const ARMMCTargetMachine &MCTM =
+      static_cast<const ARMMCTargetMachine &>(MCTM_);
   MCAsmInfo *MAI;
-  if (TheTriple.isOSDarwin() || TheTriple.isOSBinFormatMachO())
-    MAI = new ARMMCAsmInfoDarwin(TheTriple);
-  else if (TheTriple.isWindowsMSVCEnvironment())
+  if (MCTM.isOSDarwin() || MCTM.isOSBinFormatMachO())
+    MAI = new ARMMCAsmInfoDarwin(MCTM);
+  else if (MCTM.isWindowsMSVCEnvironment())
     MAI = new ARMCOFFMCAsmInfoMicrosoft();
-  else if (TheTriple.isOSWindows())
+  else if (MCTM.isOSWindows())
     MAI = new ARMCOFFMCAsmInfoGNU();
   else
-    MAI = new ARMELFMCAsmInfo(TheTriple);
+    MAI = new ARMELFMCAsmInfo(MCTM);
 
   unsigned Reg = MRI.getDwarfRegNum(ARM::SP, true);
   MAI->addInitialFrameState(MCCFIInstruction::createDefCfa(nullptr, Reg, 0));
 
   return MAI;
 }
 
 static MCCodeGenInfo *createARMMCCodeGenInfo(const Triple &TT, Reloc::Model RM,

 static MCInstrAnalysis *createARMMCInstrAnalysis(const MCInstrInfo *Info) {
   return new ARMMCInstrAnalysis(Info);
 }
 
 // Force static initialization.
 extern "C" void LLVMInitializeARMTargetMC() {
   for (Target *T : {&TheARMLETarget, &TheARMBETarget, &TheThumbLETarget,
                     &TheThumbBETarget}) {
+    // Register the MC target machine
+    RegisterMCTargetMachine<ARMMCTargetMachine> Y(*T);
+
     // Register the MC asm info.
     RegisterMCAsmInfoFn X(*T, createARMMCAsmInfo);
 
     // Register the MC codegen info.
     TargetRegistry::RegisterMCCodeGenInfo(*T, createARMMCCodeGenInfo);
 
     // Register the MC instruction info.
     TargetRegistry::RegisterMCInstrInfo(*T, createARMMCInstrInfo);

lib/Target/ARM/MCTargetDesc/ARMMCTargetMachine.h

+//===-- ARMMCTargetMachine.h - ARM Target Information -----------*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file defines the MCTargetMachine classes.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIB_TARGET_ARM_ARMMCTARGETMACHINE_H
+#define LLVM_LIB_TARGET_ARM_ARMMCTARGETMACHINE_H
+
+#include "llvm/ADT/Triple.h"
+#include "llvm/MC/MCTargetMachine.h"
+
+namespace llvm {
+class Target;
+
+class ARMMCTargetMachine : public MCTargetMachine {
+  ARMMCTargetMachine(const ARMMCTargetMachine &) = delete;
+  void operator=(const ARMMCTargetMachine &) = delete;
+
+  bool IsOSDarwin;
+  bool IsOSWindows;
+  bool IsWindowsMSVCEnvironment;
+  bool IsOSBinFormatMachO;
+  bool IsLittleEndian;
+  Triple::OSType OS;
+
+public:
+  ARMMCTargetMachine(const Target &T, const Triple &TargetTriple)
+      : MCTargetMachine(T, TargetTriple), IsOSDarwin(TargetTriple.isOSDarwin()),
+        IsOSWindows(TargetTriple.isOSWindows()),
+        IsWindowsMSVCEnvironment(TargetTriple.isWindowsMSVCEnvironment()),
+        IsOSBinFormatMachO(TargetTriple.isOSBinFormatMachO()),
+        IsLittleEndian(TargetTriple.getArch() != Triple::armeb &&
+                       TargetTriple.getArch() != Triple::thumbeb),
+        OS(TargetTriple.getOS()) {}
+
+  bool isOSDarwin() const { return IsOSDarwin; }
+  bool isOSBinFormatMachO() const { return IsOSBinFormatMachO; };
+  bool isOSWindows() const { return IsOSWindows; }
+  bool isWindowsMSVCEnvironment() const { return IsWindowsMSVCEnvironment; }
+  Triple::OSType getOS() const { return OS; }
+  bool isLittleEndian() const { return IsLittleEndian; }
+};
+
+} // End llvm namespace
+
+#endif

lib/Target/BPF/MCTargetDesc/BPFMCAsmInfo.h

 //===-- BPFMCAsmInfo.h - BPF asm properties -------------------*- C++ -*--====//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file contains the declaration of the BPFMCAsmInfo class.
 //
 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_LIB_TARGET_BPF_MCTARGETDESC_BPFMCASMINFO_H
 #define LLVM_LIB_TARGET_BPF_MCTARGETDESC_BPFMCASMINFO_H
 
+#include "BPFMCTargetMachine.h"
 #include "llvm/ADT/StringRef.h"
-#include "llvm/MC/MCAsmInfo.h"
 #include "llvm/ADT/Triple.h"
+#include "llvm/MC/MCAsmInfo.h"
 
 namespace llvm {
 class Target;
-class Triple;
+class BPFMCTargetMachine;
 
 class BPFMCAsmInfo : public MCAsmInfo {
 public:
-  explicit BPFMCAsmInfo(const Triple &TT) {
-    if (TT.getArch() == Triple::bpfeb)
-      IsLittleEndian = false;
+  explicit BPFMCAsmInfo(const MCTargetMachine &MCTM_) {
+    const BPFMCTargetMachine &MCTM =
+        static_cast<const BPFMCTargetMachine &>(MCTM_);
+    IsLittleEndian = MCTM.isLittleEndian();
 
     PrivateGlobalPrefix = ".L";
     WeakRefDirective = "\t.weak\t";
 
     UsesELFSectionDirectiveForBSS = true;
     HasSingleParameterDotFile = false;
     HasDotTypeDotSizeDirective = false;
 
     SupportsDebugInformation = true;
   }
 };
 }
 
 #endif

lib/Target/BPF/MCTargetDesc/BPFMCTargetDesc.cpp

 //===-- BPFMCTargetDesc.cpp - BPF Target Descriptions ---------------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file provides BPF specific target descriptions.
 //
 //===----------------------------------------------------------------------===//
 
 #include "BPF.h"
-#include "BPFMCTargetDesc.h"
 #include "BPFMCAsmInfo.h"
+#include "BPFMCTargetDesc.h"
+#include "BPFMCTargetMachine.h"
 #include "InstPrinter/BPFInstPrinter.h"
 #include "llvm/MC/MCCodeGenInfo.h"
 #include "llvm/MC/MCInstrInfo.h"
 #include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/MC/MCStreamer.h"
 #include "llvm/MC/MCSubtargetInfo.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/TargetRegistry.h"
static MCInstPrinter *createBPFMCInstPrinter(const Triple &T,
                                              const MCRegisterInfo &MRI) {
   if (SyntaxVariant == 0)
     return new BPFInstPrinter(MAI, MII, MRI);
   return 0;
 }
 
 extern "C" void LLVMInitializeBPFTargetMC() {
   for (Target *T : {&TheBPFleTarget, &TheBPFbeTarget, &TheBPFTarget}) {
+    // Register the MC target machine
+    RegisterMCTargetMachine<BPFMCTargetMachine> Y(*T);
+
     // Register the MC asm info.
-    RegisterMCAsmInfo<BPFMCAsmInfo> X(*T);
+    RegisterMCAsmInfo<BPFMCAsmInfo, BPFMCTargetMachine> X(*T);
 
     // Register the MC codegen info.
     TargetRegistry::RegisterMCCodeGenInfo(*T, createBPFMCCodeGenInfo);
 
     // Register the MC instruction info.
     TargetRegistry::RegisterMCInstrInfo(*T, createBPFMCInstrInfo);
 
     // Register the MC register info.

lib/Target/BPF/MCTargetDesc/BPFMCTargetMachine.h

+//===-- BPFMCTargetMachine.h - BPF Target Information -----------*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file defines the MCTargetMachine classes.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIB_TARGET_BPF_BPFMCTARGETMACHINE_H
+#define LLVM_LIB_TARGET_BPF_BPFMCTARGETMACHINE_H
+
+#include "llvm/ADT/Triple.h"
+#include "llvm/MC/MCTargetMachine.h"
+
+namespace llvm {
+class Target;
+
+class BPFMCTargetMachine : public MCTargetMachine {
+  BPFMCTargetMachine(const BPFMCTargetMachine &) = delete;
+  void operator=(const BPFMCTargetMachine &) = delete;
+
+  bool IsLittleEndian;
+
+public:
+  BPFMCTargetMachine(const Target &T, const Triple &TargetTriple)
+      : MCTargetMachine(T, TargetTriple),
+        IsLittleEndian(TargetTriple.getArch() != Triple::bpfeb) {}
+
+  bool isLittleEndian() const { return IsLittleEndian; }
+};
+
+} // End llvm namespace
+
+#endif

lib/Target/Hexagon/MCTargetDesc/HexagonMCAsmInfo.h

 
 #ifndef LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONMCASMINFO_H
 #define LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONMCASMINFO_H
 
 #include "llvm/ADT/StringRef.h"
 #include "llvm/MC/MCAsmInfoELF.h"
 
 namespace llvm {
-class Triple;
+class MCTargetMachine;
 
 class HexagonMCAsmInfo : public MCAsmInfoELF {
   void anchor() override;
 
 public:
-  explicit HexagonMCAsmInfo(const Triple &TT);
+  explicit HexagonMCAsmInfo(const MCTargetMachine &MCTM);
 };
 
 } // namespace llvm
 
 #endif

lib/Target/Hexagon/MCTargetDesc/HexagonMCAsmInfo.cpp

 
 #include "HexagonMCAsmInfo.h"
 
 using namespace llvm;
 
 // Pin the vtable to this file.
 void HexagonMCAsmInfo::anchor() {}
 
-HexagonMCAsmInfo::HexagonMCAsmInfo(const Triple &TT) {
+HexagonMCAsmInfo::HexagonMCAsmInfo(const MCTargetMachine &MCTM) {
   Data16bitsDirective = "\t.half\t";
   Data32bitsDirective = "\t.word\t";
   Data64bitsDirective = nullptr;  // .xword is only supported by V9.
   ZeroDirective = "\t.skip\t";
   CommentString = "//";
 
   LCOMMDirectiveAlignmentType = LCOMM::ByteAlignment;
   InlineAsmStart = "# InlineAsm Start";
   InlineAsmEnd = "# InlineAsm End";
   ZeroDirective = "\t.space\t";
   AscizDirective = "\t.string\t";
 
   SupportsDebugInformation = true;
   UsesELFSectionDirectiveForBSS  = true;
   ExceptionsType = ExceptionHandling::DwarfCFI;
 }

lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp

 #include "llvm/MC/MCCodeGenInfo.h"
 #include "llvm/MC/MCContext.h"
 #include "llvm/MC/MCELFStreamer.h"
 #include "llvm/MC/MCInstrInfo.h"
 #include "llvm/MC/MCObjectStreamer.h"
 #include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/MC/MCStreamer.h"
 #include "llvm/MC/MCSubtargetInfo.h"
+#include "llvm/MC/MCTargetMachine.h"
 #include "llvm/MC/MachineLocation.h"
 #include "llvm/Support/ELF.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/TargetRegistry.h"
 
 using namespace llvm;
 
 #define GET_INSTRINFO_MC_DESC
HexagonMCELFStreamer &HexagonELFStreamer =
         static_cast<HexagonMCELFStreamer &>(getStreamer());
     HexagonELFStreamer.HexagonMCEmitLocalCommonSymbol(
         Symbol, Size, ByteAlignment, AccessSize);
   }
 };
 }
 
 static MCAsmInfo *createHexagonMCAsmInfo(const MCRegisterInfo &MRI,
-                                         const Triple &TT) {
-  MCAsmInfo *MAI = new HexagonMCAsmInfo(TT);
+                                         const MCTargetMachine &MCTM) {
+  MCAsmInfo *MAI = new HexagonMCAsmInfo(MCTM);
 
   // VirtualFP = (R30 + #0).
   MCCFIInstruction Inst =
       MCCFIInstruction::createDefCfa(nullptr, Hexagon::R30, 0);
   MAI->addInitialFrameState(Inst);
 
   return MAI;
 }

 
 static MCTargetStreamer *
 createHexagonObjectTargetStreamer(MCStreamer &S, MCSubtargetInfo const &STI) {
   return new HexagonTargetELFStreamer(S, STI);
 }
 
 // Force static initialization.
 extern "C" void LLVMInitializeHexagonTargetMC() {
+  // Register the MC target machine
+  RegisterMCTargetMachine<MCTargetMachine> Y(TheHexagonTarget);
+
   // Register the MC asm info.
   RegisterMCAsmInfoFn X(TheHexagonTarget, createHexagonMCAsmInfo);
 
   // Register the MC codegen info.
   TargetRegistry::RegisterMCCodeGenInfo(TheHexagonTarget,
                                         createHexagonMCCodeGenInfo);
 
   // Register the MC instruction info.

lib/Target/MSP430/MCTargetDesc/MSP430MCAsmInfo.h

 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_LIB_TARGET_MSP430_MCTARGETDESC_MSP430MCASMINFO_H
 #define LLVM_LIB_TARGET_MSP430_MCTARGETDESC_MSP430MCASMINFO_H
 
 #include "llvm/MC/MCAsmInfoELF.h"
 
 namespace llvm {
-class Triple;
+class MCTargetMachine;
 
 class MSP430MCAsmInfo : public MCAsmInfoELF {
   void anchor() override;
 
 public:
-  explicit MSP430MCAsmInfo(const Triple &TT);
+  explicit MSP430MCAsmInfo(const MCTargetMachine &MCTM);
 };
 
 } // namespace llvm
 
 #endif

lib/Target/MSP430/MCTargetDesc/MSP430MCAsmInfo.cpp

 //
 //===----------------------------------------------------------------------===//
 
 #include "MSP430MCAsmInfo.h"
 using namespace llvm;
 
 void MSP430MCAsmInfo::anchor() { }
 
-MSP430MCAsmInfo::MSP430MCAsmInfo(const Triple &TT) {
+MSP430MCAsmInfo::MSP430MCAsmInfo(const MCTargetMachine &MCTM) {
   PointerSize = CalleeSaveStackSlotSize = 2;
 
   CommentString = ";";
 
   AlignmentIsInBytes = false;
   UsesELFSectionDirectiveForBSS = true;
 }

lib/Target/MSP430/MCTargetDesc/MSP430MCTargetDesc.cpp

 
 #include "MSP430MCTargetDesc.h"
 #include "InstPrinter/MSP430InstPrinter.h"
 #include "MSP430MCAsmInfo.h"
 #include "llvm/MC/MCCodeGenInfo.h"
 #include "llvm/MC/MCInstrInfo.h"
 #include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/MC/MCSubtargetInfo.h"
+#include "llvm/MC/MCTargetMachine.h"
 #include "llvm/Support/TargetRegistry.h"
 
 using namespace llvm;
 
 #define GET_INSTRINFO_MC_DESC
 #include "MSP430GenInstrInfo.inc"
 
 #define GET_SUBTARGETINFO_MC_DESC
static MCInstPrinter *createMSP430MCInstPrinter(const Triple &T,
                                                 const MCInstrInfo &MII,
                                                 const MCRegisterInfo &MRI) {
   if (SyntaxVariant == 0)
     return new MSP430InstPrinter(MAI, MII, MRI);
   return nullptr;
 }
 
 extern "C" void LLVMInitializeMSP430TargetMC() {
+  // Register the MC target machine
+  RegisterMCTargetMachine<MCTargetMachine> Y(TheMSP430Target);
+
   // Register the MC asm info.
   RegisterMCAsmInfo<MSP430MCAsmInfo> X(TheMSP430Target);
 
   // Register the MC codegen info.
   TargetRegistry::RegisterMCCodeGenInfo(TheMSP430Target,
                                         createMSP430MCCodeGenInfo);
 
   // Register the MC instruction info.

lib/Target/Mips/MCTargetDesc/MipsABIInfo.h

public:
   unsigned GetFramePtr() const;
   unsigned GetBasePtr() const;
   unsigned GetNullPtr() const;
   unsigned GetZeroReg() const;
   unsigned GetPtrAdduOp() const;
   unsigned GetPtrAddiuOp() const;
   unsigned GetGPRMoveOp() const;
   inline bool ArePtrs64bit() const { return IsN64(); }
+  inline unsigned GetPtrSizeInBytes() const { return ArePtrs64bit() ? 8 : 4; }
+  inline unsigned GetStackSlotSizeInBytes() const {
+    return AreGprs64bit() ? 8 : 4;
+  }
   inline bool AreGprs64bit() const { return IsN32() || IsN64(); }
 
   unsigned GetEhDataReg(unsigned I) const;
 };
 }
 
 #endif

lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.h

 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSMCASMINFO_H
 #define LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSMCASMINFO_H
 
 #include "llvm/MC/MCAsmInfoELF.h"
 
 namespace llvm {
-class Triple;
+class MipsMCTargetMachine;
 
 class MipsMCAsmInfo : public MCAsmInfoELF {
   void anchor() override;
 
 public:
-  explicit MipsMCAsmInfo(const Triple &TheTriple);
+  explicit MipsMCAsmInfo(const MipsMCTargetMachine &MCTM);
 };
 
 } // namespace llvm
 
 #endif

lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.cpp

 //===-- MipsMCAsmInfo.cpp - Mips Asm Properties ---------------------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file contains the declarations of the MipsMCAsmInfo properties.
 //
 //===----------------------------------------------------------------------===//
 
 #include "MipsMCAsmInfo.h"
-#include "llvm/ADT/Triple.h"
+#include "MipsMCTargetMachine.h"
 
 using namespace llvm;
 
 void MipsMCAsmInfo::anchor() { }
 
-MipsMCAsmInfo::MipsMCAsmInfo(const Triple &TheTriple) {
-  if ((TheTriple.getArch() == Triple::mips) ||
-      (TheTriple.getArch() == Triple::mips64))
-    IsLittleEndian = false;
-
-  if ((TheTriple.getArch() == Triple::mips64el) ||
-      (TheTriple.getArch() == Triple::mips64)) {
-    PointerSize = CalleeSaveStackSlotSize = 8;
-  }
+MipsMCAsmInfo::MipsMCAsmInfo(const MipsMCTargetMachine &MCTM) {
+  IsLittleEndian = MCTM.isLittleEndian();
+  PointerSize = MCTM.getABI().GetPtrSizeInBytes();
+  CalleeSaveStackSlotSize = MCTM.getABI().GetStackSlotSizeInBytes();
 
   AlignmentIsInBytes          = false;
   Data16bitsDirective         = "\t.2byte\t";
   Data32bitsDirective         = "\t.4byte\t";
   Data64bitsDirective         = "\t.8byte\t";
   PrivateGlobalPrefix         = "$";
   PrivateLabelPrefix          = "$";
   CommentString               = "#";
   ZeroDirective               = "\t.space\t";
   GPRel32Directive            = "\t.gpword\t";
   GPRel64Directive            = "\t.gpdword\t";
   UseAssignmentForEHBegin = true;
   SupportsDebugInformation = true;
   ExceptionsType = ExceptionHandling::DwarfCFI;
   DwarfRegNumForCFI = true;
 }

lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp

 //
 //===----------------------------------------------------------------------===//
 
 #include "InstPrinter/MipsInstPrinter.h"
 #include "MipsELFStreamer.h"
 #include "MipsMCAsmInfo.h"
 #include "MipsMCNaCl.h"
 #include "MipsMCTargetDesc.h"
+#include "MipsMCTargetMachine.h"
 #include "MipsTargetStreamer.h"
 #include "llvm/ADT/Triple.h"
 #include "llvm/MC/MCCodeGenInfo.h"
 #include "llvm/MC/MCELFStreamer.h"
 #include "llvm/MC/MCInstrInfo.h"
 #include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/MC/MCSubtargetInfo.h"
 #include "llvm/MC/MCSymbol.h"

 
 static MCSubtargetInfo *createMipsMCSubtargetInfo(const Triple &TT,
                                                   StringRef CPU, StringRef FS) {
   CPU = MIPS_MC::selectMipsCPU(TT, CPU);
   return createMipsMCSubtargetInfoImpl(TT, CPU, FS);
 }
 
 static MCAsmInfo *createMipsMCAsmInfo(const MCRegisterInfo &MRI,
-                                      const Triple &TT) {
-  MCAsmInfo *MAI = new MipsMCAsmInfo(TT);
+                                      const MCTargetMachine &MCTM_) {
+  const MipsMCTargetMachine &MCTM =
+      static_cast<const MipsMCTargetMachine &>(MCTM_);
+  MCAsmInfo *MAI = new MipsMCAsmInfo(MCTM);
 
   unsigned SP = MRI.getDwarfRegNum(Mips::SP, true);
   MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(nullptr, SP, 0);
   MAI->addInitialFrameState(Inst);
 
   return MAI;
 }
 

 static MCTargetStreamer *
 createMipsObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI) {
   return new MipsTargetELFStreamer(S, STI);
 }
 
 extern "C" void LLVMInitializeMipsTargetMC() {
   for (Target *T : {&TheMipsTarget, &TheMipselTarget, &TheMips64Target,
                     &TheMips64elTarget}) {
+    // Register the MC target machine
+    RegisterMCTargetMachine<MipsMCTargetMachine> Y(*T);
+
     // Register the MC asm info.
     RegisterMCAsmInfoFn X(*T, createMipsMCAsmInfo);
 
     // Register the MC codegen info.
     TargetRegistry::RegisterMCCodeGenInfo(*T, createMipsMCCodeGenInfo);
 
     // Register the MC instruction info.
     TargetRegistry::RegisterMCInstrInfo(*T, createMipsMCInstrInfo);

lib/Target/Mips/MCTargetDesc/MipsMCTargetMachine.h

+//===-- MipsMCTargetMachine.h - Mips Target Information ---------*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file defines the MCTargetMachine classes.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIB_TARGET_MIPS_MIPSMCTARGETMACHINE_H
+#define LLVM_LIB_TARGET_MIPS_MIPSMCTARGETMACHINE_H
+
+#include "MipsABIInfo.h"
+#include "llvm/ADT/Triple.h"
+#include "llvm/MC/MCTargetMachine.h"
+
+namespace llvm {
+class Target;
+
+class MipsMCTargetMachine : public MCTargetMachine {
+  MipsMCTargetMachine(const MipsMCTargetMachine &) = delete;
+  void operator=(const MipsMCTargetMachine &) = delete;
+
+  bool IsLittleEndian;
+  MipsABIInfo ABI;
+
+public:
+  MipsMCTargetMachine(const Target &T, const Triple &TargetTriple)
+      : MCTargetMachine(T, TargetTriple),
+        IsLittleEndian(!(TargetTriple.getArch() == Triple::mips ||
+                         TargetTriple.getArch() == Triple::mips64)),
+        ABI(
+            // FIXME: This is wrong but it preserves current behaviour until
+            // we receive the correct ABI.
+            (TargetTriple.getArch() == Triple::mips64el ||
+             TargetTriple.getArch() == Triple::mips64)
+                ? MipsABIInfo::N64()
+                : MipsABIInfo::O32()) {}
+
+  bool isLittleEndian() const { return IsLittleEndian; }
+  const MipsABIInfo getABI() const { return ABI; };
+};
+
+} // End llvm namespace
+
+#endif

lib/Target/NVPTX/MCTargetDesc/NVPTXMCAsmInfo.h

 
 #ifndef LLVM_LIB_TARGET_NVPTX_MCTARGETDESC_NVPTXMCASMINFO_H
 #define LLVM_LIB_TARGET_NVPTX_MCTARGETDESC_NVPTXMCASMINFO_H
 
 #include "llvm/MC/MCAsmInfo.h"
 
 namespace llvm {
 class Target;
-class Triple;
+class NVPTXMCTargetMachine;
 
 class NVPTXMCAsmInfo : public MCAsmInfo {
   virtual void anchor();
 
 public:
-  explicit NVPTXMCAsmInfo(const Triple &TheTriple);
+  explicit NVPTXMCAsmInfo(const NVPTXMCTargetMachine &MCTM);
 };
 } // namespace llvm
 
 #endif

lib/Target/NVPTX/MCTargetDesc/NVPTXMCAsmInfo.cpp

 //===-- NVPTXMCAsmInfo.cpp - NVPTX asm properties -------------------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file contains the declarations of the NVPTXMCAsmInfo properties.
 //
 //===----------------------------------------------------------------------===//
 
 #include "NVPTXMCAsmInfo.h"
-#include "llvm/ADT/Triple.h"
+#include "NVPTXMCTargetMachine.h"
 #include "llvm/Support/CommandLine.h"
 
 using namespace llvm;
 
 // -debug-compile - Command line option to inform opt and llc passes to
 // compile for debugging
 static cl::opt<bool> CompileForDebugging("debug-compile",
                                          cl::desc("Compile for debugging"),
                                          cl::Hidden, cl::init(false));
 
 void NVPTXMCAsmInfo::anchor() {}
 
-NVPTXMCAsmInfo::NVPTXMCAsmInfo(const Triple &TheTriple) {
-  if (TheTriple.getArch() == Triple::nvptx64) {
+NVPTXMCAsmInfo::NVPTXMCAsmInfo(const NVPTXMCTargetMachine &MCTM) {
+  if (MCTM.isArch64Bit())
     PointerSize = CalleeSaveStackSlotSize = 8;
-  }
 
   CommentString = "//";
 
   HasSingleParameterDotFile = false;
 
   InlineAsmStart = " inline asm";
   InlineAsmEnd = " inline asm";
 

lib/Target/NVPTX/MCTargetDesc/NVPTXMCTargetDesc.cpp

 //===-- NVPTXMCTargetDesc.cpp - NVPTX Target Descriptions -------*- C++ -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file provides NVPTX specific target descriptions.
 //
 //===----------------------------------------------------------------------===//
 
 #include "NVPTXMCTargetDesc.h"
 #include "InstPrinter/NVPTXInstPrinter.h"
 #include "NVPTXMCAsmInfo.h"
+#include "NVPTXMCTargetMachine.h"
 #include "llvm/MC/MCCodeGenInfo.h"
 #include "llvm/MC/MCInstrInfo.h"
 #include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/MC/MCSubtargetInfo.h"
 #include "llvm/Support/TargetRegistry.h"
 
 using namespace llvm;
 
static MCInstPrinter *createNVPTXMCInstPrinter(const Triple &T,
   if (SyntaxVariant == 0)
     return new NVPTXInstPrinter(MAI, MII, MRI);
   return nullptr;
 }
 
 // Force static initialization.
 extern "C" void LLVMInitializeNVPTXTargetMC() {
   for (Target *T : {&TheNVPTXTarget32, &TheNVPTXTarget64}) {
+    // Register the MC target machine
+    RegisterMCTargetMachine<NVPTXMCTargetMachine> Y(*T);
+
     // Register the MC asm info.
-    RegisterMCAsmInfo<NVPTXMCAsmInfo> X(*T);
+    RegisterMCAsmInfo<NVPTXMCAsmInfo, NVPTXMCTargetMachine> X(*T);
 
     // Register the MC codegen info.
     TargetRegistry::RegisterMCCodeGenInfo(*T, createNVPTXMCCodeGenInfo);
 
     // Register the MC instruction info.
     TargetRegistry::RegisterMCInstrInfo(*T, createNVPTXMCInstrInfo);
 
     // Register the MC register info.

lib/Target/NVPTX/MCTargetDesc/NVPTXMCTargetMachine.h

+//===-- NVPTXMCTargetMachine.h - NVPTX Target Information -------*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file defines the MCTargetMachine classes.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIB_TARGET_AARCH64_AARCH64MCTARGETMACHINE_H
+#define LLVM_LIB_TARGET_AARCH64_AARCH64MCTARGETMACHINE_H
+
+#include "llvm/ADT/Triple.h"
+#include "llvm/MC/MCTargetMachine.h"
+
+namespace llvm {
+class Target;
+
+class NVPTXMCTargetMachine : public MCTargetMachine {
+  NVPTXMCTargetMachine(const NVPTXMCTargetMachine &) = delete;
+  void operator=(const NVPTXMCTargetMachine &) = delete;
+
+  bool IsArch64Bit;
+
+public:
+  NVPTXMCTargetMachine(const Target &T, const Triple &TargetTriple)
+      : MCTargetMachine(T, TargetTriple),
+        IsArch64Bit(TargetTriple.getArch() == Triple::nvptx64) {}
+
+  bool isArch64Bit() const { return IsArch64Bit; }
+};
+
+} // End llvm namespace
+
+#endif

lib/Target/PowerPC/MCTargetDesc/PPCMCAsmInfo.h

 
 #ifndef LLVM_LIB_TARGET_POWERPC_MCTARGETDESC_PPCMCASMINFO_H
 #define LLVM_LIB_TARGET_POWERPC_MCTARGETDESC_PPCMCASMINFO_H
 
 #include "llvm/MC/MCAsmInfoDarwin.h"
 #include "llvm/MC/MCAsmInfoELF.h"
 
 namespace llvm {
-class Triple;
+class PPCMCTargetMachine;
 
 class PPCMCAsmInfoDarwin : public MCAsmInfoDarwin {
   virtual void anchor();
 
 public:
-  explicit PPCMCAsmInfoDarwin(bool is64Bit, const Triple &);
+  explicit PPCMCAsmInfoDarwin(bool is64Bit, const PPCMCTargetMachine &);
 };
 
 class PPCELFMCAsmInfo : public MCAsmInfoELF {
   void anchor() override;
 
 public:
-  explicit PPCELFMCAsmInfo(bool is64Bit, const Triple &);
+  explicit PPCELFMCAsmInfo(bool is64Bit, const PPCMCTargetMachine &);
 };
 
 } // namespace llvm
 
 #endif

lib/Target/PowerPC/MCTargetDesc/PPCMCAsmInfo.cpp

 //===-- PPCMCAsmInfo.cpp - PPC asm properties -----------------------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file contains the declarations of the MCAsmInfoDarwin properties.
 //
 //===----------------------------------------------------------------------===//
 
 #include "PPCMCAsmInfo.h"
-#include "llvm/ADT/Triple.h"
+#include "PPCMCTargetMachine.h"
 
 using namespace llvm;
 
 void PPCMCAsmInfoDarwin::anchor() { }
 
-PPCMCAsmInfoDarwin::PPCMCAsmInfoDarwin(bool is64Bit, const Triple& T) {
+PPCMCAsmInfoDarwin::PPCMCAsmInfoDarwin(bool is64Bit,
+                                       const PPCMCTargetMachine &MCTM) {
   if (is64Bit) {
     PointerSize = CalleeSaveStackSlotSize = 8;
   }
   IsLittleEndian = false;
 
   CommentString = ";";
   ExceptionsType = ExceptionHandling::DwarfCFI;
 
   if (!is64Bit)
     Data64bitsDirective = nullptr; // We can't emit a 64-bit unit in PPC32 mode.
 
   AssemblerDialect = 1;           // New-Style mnemonics.
   SupportsDebugInformation= true; // Debug information.
 
   // The installed assembler for OSX < 10.6 lacks some directives.
   // FIXME: this should really be a check on the assembler characteristics
   // rather than OS version
-  if (T.isMacOSX() && T.isMacOSXVersionLT(10, 6))
+  if (MCTM.isMacOSX() && MCTM.isMacOSXVersionLT(10, 6))
     HasWeakDefCanBeHiddenDirective = false;
 
   UseIntegratedAssembler = true;
 }
 
 void PPCELFMCAsmInfo::anchor() { }
 
-PPCELFMCAsmInfo::PPCELFMCAsmInfo(bool is64Bit, const Triple& T) {
+PPCELFMCAsmInfo::PPCELFMCAsmInfo(bool is64Bit, const PPCMCTargetMachine &MCTM) {
   // FIXME: This is not always needed. For example, it is not needed in the
   // v2 abi.
   NeedsLocalForSize = true;
 
   if (is64Bit) {
     PointerSize = CalleeSaveStackSlotSize = 8;
   }
-  IsLittleEndian = T.getArch() == Triple::ppc64le;
+  IsLittleEndian = MCTM.isLittleEndian();
 
   // ".comm align is in bytes but .align is pow-2."
   AlignmentIsInBytes = false;
 
   CommentString = "#";
 
   // Uses '.section' before '.bss' directive
   UsesELFSectionDirectiveForBSS = true;  

lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp

 //===-- PPCMCTargetDesc.cpp - PowerPC Target Descriptions -----------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file provides PowerPC specific target descriptions.
 //
 //===----------------------------------------------------------------------===//
 
 #include "PPCMCTargetDesc.h"
 #include "InstPrinter/PPCInstPrinter.h"
 #include "PPCMCAsmInfo.h"
+#include "PPCMCTargetMachine.h"
 #include "PPCTargetStreamer.h"
 #include "llvm/MC/MCCodeGenInfo.h"
 #include "llvm/MC/MCContext.h"
 #include "llvm/MC/MCELFStreamer.h"
 #include "llvm/MC/MCExpr.h"
 #include "llvm/MC/MCInstrInfo.h"
 #include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/MC/MCStreamer.h"

 }
 
 static MCSubtargetInfo *createPPCMCSubtargetInfo(const Triple &TT,
                                                  StringRef CPU, StringRef FS) {
   return createPPCMCSubtargetInfoImpl(TT, CPU, FS);
 }
 
 static MCAsmInfo *createPPCMCAsmInfo(const MCRegisterInfo &MRI,
-                                     const Triple &TheTriple) {
-  bool isPPC64 = (TheTriple.getArch() == Triple::ppc64 ||
-                  TheTriple.getArch() == Triple::ppc64le);
+                                     const MCTargetMachine &MCTM_) {
+  const PPCMCTargetMachine &MCTM =
+      static_cast<const PPCMCTargetMachine &>(MCTM_);
+  bool isPPC64 = MCTM.isArch64Bit();
 
   MCAsmInfo *MAI;
-  if (TheTriple.isOSDarwin())
-    MAI = new PPCMCAsmInfoDarwin(isPPC64, TheTriple);
+  if (MCTM.isOSDarwin())
+    MAI = new PPCMCAsmInfoDarwin(isPPC64, MCTM);
   else
-    MAI = new PPCELFMCAsmInfo(isPPC64, TheTriple);
+    MAI = new PPCELFMCAsmInfo(isPPC64, MCTM);
 
   // Initial state of the frame pointer is R1.
   unsigned Reg = isPPC64 ? PPC::X1 : PPC::R1;
   MCCFIInstruction Inst =
       MCCFIInstruction::createDefCfa(nullptr, MRI.getDwarfRegNum(Reg, true), 0);
   MAI->addInitialFrameState(Inst);
 
   return MAI;
static MCInstPrinter *createPPCMCInstPrinter(const Triple &T,
                                              const MCAsmInfo &MAI,
                                              const MCInstrInfo &MII,
                                              const MCRegisterInfo &MRI) {
   return new PPCInstPrinter(MAI, MII, MRI, T.isOSDarwin());
 }
 
 extern "C" void LLVMInitializePowerPCTargetMC() {
   for (Target *T : {&ThePPC32Target, &ThePPC64Target, &ThePPC64LETarget}) {
+    // Register the MC target machine
+    RegisterMCTargetMachine<PPCMCTargetMachine> Y(*T);
+
     // Register the MC asm info.
     RegisterMCAsmInfoFn C(*T, createPPCMCAsmInfo);
 
     // Register the MC codegen info.
     TargetRegistry::RegisterMCCodeGenInfo(*T, createPPCMCCodeGenInfo);
 
     // Register the MC instruction info.
     TargetRegistry::RegisterMCInstrInfo(*T, createPPCMCInstrInfo);

lib/Target/PowerPC/MCTargetDesc/PPCMCTargetMachine.h

+//===-- PPCMCTargetMachine.h - PPC Target Information -----------*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file defines the MCTargetMachine classes.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIB_TARGET_PPC_PPCMCTARGETMACHINE_H
+#define LLVM_LIB_TARGET_PPC_PPCMCTARGETMACHINE_H
+
+#include "llvm/ADT/Triple.h"
+#include "llvm/MC/MCTargetMachine.h"
+
+namespace llvm {
+class Target;
+
+class PPCMCTargetMachine : public MCTargetMachine {
+  PPCMCTargetMachine(const PPCMCTargetMachine &) = delete;
+  void operator=(const PPCMCTargetMachine &) = delete;
+
+  // FIXME: We have this to be able to use the MacOSX version comparison.
+  //        It should not be used as a description of the target.
+  Triple TheTargetTriple;
+
+  bool IsOSDarwin;
+  bool IsMacOSX;
+  bool IsLittleEndian;
+  bool IsArch64Bit;
+
+public:
+  PPCMCTargetMachine(const Target &T, const Triple &TargetTriple)
+      : MCTargetMachine(T, TargetTriple), TheTargetTriple(TargetTriple),
+        IsOSDarwin(TargetTriple.isOSDarwin()),
+        IsMacOSX(TargetTriple.isMacOSX()),
+        IsLittleEndian(TargetTriple.getArch() == Triple::ppc64le),
+        IsArch64Bit(TargetTriple.getArch() == Triple::ppc64 ||
+                    TargetTriple.getArch() == Triple::ppc64le) {}
+
+  bool isOSDarwin() const { return IsOSDarwin; }
+  bool isMacOSX() const { return IsMacOSX; }
+  unsigned isMacOSXVersionLT(unsigned Major, unsigned Minor = 0,
+                             unsigned Micro = 0) const {
+    return TheTargetTriple.isMacOSXVersionLT(Major, Minor, Micro);
+  }
+  bool isLittleEndian() const { return IsLittleEndian; }
+  bool isArch64Bit() const { return IsArch64Bit; }
+};
+
+} // End llvm namespace
+
+#endif

lib/Target/Sparc/MCTargetDesc/SparcMCAsmInfo.h

 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_LIB_TARGET_SPARC_MCTARGETDESC_SPARCMCASMINFO_H
 #define LLVM_LIB_TARGET_SPARC_MCTARGETDESC_SPARCMCASMINFO_H
 
 #include "llvm/MC/MCAsmInfoELF.h"
 
 namespace llvm {
-class Triple;
+class SparcMCTargetMachine;
 
 class SparcELFMCAsmInfo : public MCAsmInfoELF {
   void anchor() override;
 
 public:
-  explicit SparcELFMCAsmInfo(const Triple &TheTriple);
+  explicit SparcELFMCAsmInfo(const SparcMCTargetMachine &MCTM);
   const MCExpr*
   getExprForPersonalitySymbol(const MCSymbol *Sym, unsigned Encoding,
                               MCStreamer &Streamer) const override;
   const MCExpr* getExprForFDESymbol(const MCSymbol *Sym,
                                     unsigned Encoding,
                                     MCStreamer &Streamer) const override;
 
 };
 
 } // namespace llvm
 
 #endif

lib/Target/Sparc/MCTargetDesc/SparcMCAsmInfo.cpp

 //===-- SparcMCAsmInfo.cpp - Sparc asm properties -------------------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file contains the declarations of the SparcMCAsmInfo properties.
 //
 //===----------------------------------------------------------------------===//
 
 #include "SparcMCAsmInfo.h"
 #include "SparcMCExpr.h"
-#include "llvm/ADT/Triple.h"
+#include "SparcMCTargetMachine.h"
 #include "llvm/MC/MCStreamer.h"
 
 using namespace llvm;
 
 void SparcELFMCAsmInfo::anchor() {}
 
-SparcELFMCAsmInfo::SparcELFMCAsmInfo(const Triple &TheTriple) {
-  bool isV9 = (TheTriple.getArch() == Triple::sparcv9);
-  IsLittleEndian = (TheTriple.getArch() == Triple::sparcel);
+SparcELFMCAsmInfo::SparcELFMCAsmInfo(const SparcMCTargetMachine &MCTM) {
+  bool isV9 = MCTM.isV9();
+  IsLittleEndian = MCTM.isLittleEndian();
 
   if (isV9) {
     PointerSize = CalleeSaveStackSlotSize = 8;
   }
 
   Data16bitsDirective = "\t.half\t";
   Data32bitsDirective = "\t.word\t";
   // .xword is only supported by V9.

lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp

 //===-- SparcMCTargetDesc.cpp - Sparc Target Descriptions -----------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file provides Sparc specific target descriptions.
 //
 //===----------------------------------------------------------------------===//
 
 #include "SparcMCTargetDesc.h"
 #include "InstPrinter/SparcInstPrinter.h"
 #include "SparcMCAsmInfo.h"
+#include "SparcMCTargetMachine.h"
 #include "SparcTargetStreamer.h"
 #include "llvm/MC/MCCodeGenInfo.h"
 #include "llvm/MC/MCInstrInfo.h"
 #include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/MC/MCSubtargetInfo.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/TargetRegistry.h"
 
 using namespace llvm;
 
 #define GET_INSTRINFO_MC_DESC
 #include "SparcGenInstrInfo.inc"
 
 #define GET_SUBTARGETINFO_MC_DESC
 #include "SparcGenSubtargetInfo.inc"
 
 #define GET_REGINFO_MC_DESC
 #include "SparcGenRegisterInfo.inc"
 
 static MCAsmInfo *createSparcMCAsmInfo(const MCRegisterInfo &MRI,
-                                       const Triple &TT) {
-  MCAsmInfo *MAI = new SparcELFMCAsmInfo(TT);
+                                       const MCTargetMachine &MCTM_) {
+  const SparcMCTargetMachine &MCTM =
+      static_cast<const SparcMCTargetMachine &>(MCTM_);
+  MCAsmInfo *MAI = new SparcELFMCAsmInfo(MCTM);
   unsigned Reg = MRI.getDwarfRegNum(SP::O6, true);
   MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(nullptr, Reg, 0);
   MAI->addInitialFrameState(Inst);
   return MAI;
 }
 
 static MCAsmInfo *createSparcV9MCAsmInfo(const MCRegisterInfo &MRI,
-                                         const Triple &TT) {
-  MCAsmInfo *MAI = new SparcELFMCAsmInfo(TT);
+                                         const MCTargetMachine &MCTM_) {
+  const SparcMCTargetMachine &MCTM =
+      static_cast<const SparcMCTargetMachine &>(MCTM_);
+  MCAsmInfo *MAI = new SparcELFMCAsmInfo(MCTM);
   unsigned Reg = MRI.getDwarfRegNum(SP::O6, true);
   MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(nullptr, Reg, 2047);
   MAI->addInitialFrameState(Inst);
   return MAI;
 }
 
 static MCInstrInfo *createSparcMCInstrInfo() {
   MCInstrInfo *X = new MCInstrInfo();

 
 extern "C" void LLVMInitializeSparcTargetMC() {
   // Register the MC asm info.
   RegisterMCAsmInfoFn X(TheSparcTarget, createSparcMCAsmInfo);
   RegisterMCAsmInfoFn Y(TheSparcV9Target, createSparcV9MCAsmInfo);
   RegisterMCAsmInfoFn Z(TheSparcelTarget, createSparcMCAsmInfo);
 
   for (Target *T : {&TheSparcTarget, &TheSparcV9Target, &TheSparcelTarget}) {
+    // Register the MC target machine
+    RegisterMCTargetMachine<SparcMCTargetMachine> Y(*T);
+
     // Register the MC instruction info.
     TargetRegistry::RegisterMCInstrInfo(*T, createSparcMCInstrInfo);
 
     // Register the MC register info.
     TargetRegistry::RegisterMCRegInfo(*T, createSparcMCRegisterInfo);
 
     // Register the MC subtarget info.
     TargetRegistry::RegisterMCSubtargetInfo(*T, createSparcMCSubtargetInfo);

lib/Target/Sparc/MCTargetDesc/SparcMCTargetMachine.h

+//===-- SparcMCTargetMachine.h - Sparc Target Information -------*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file defines the MCTargetMachine classes.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIB_TARGET_SPARC_SPARCMCTARGETMACHINE_H
+#define LLVM_LIB_TARGET_SPARC_SPARCMCTARGETMACHINE_H
+
+#include "llvm/ADT/Triple.h"
+#include "llvm/MC/MCTargetMachine.h"
+
+namespace llvm {
+class Target;
+
+class SparcMCTargetMachine : public MCTargetMachine {
+  SparcMCTargetMachine(const SparcMCTargetMachine &) = delete;
+  void operator=(const SparcMCTargetMachine &) = delete;
+
+  bool IsV9;
+  bool IsLittleEndian;
+
+public:
+  SparcMCTargetMachine(const Target &T, const Triple &TargetTriple)
+      : MCTargetMachine(T, TargetTriple),
+        IsV9(TargetTriple.getArch() == Triple::sparcv9),
+        IsLittleEndian(TargetTriple.getArch() == Triple::sparcel) {}
+
+  bool isV9() const { return IsV9; }
+  bool isLittleEndian() const { return IsLittleEndian; }
+};
+
+} // End llvm namespace
+
+#endif

lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmInfo.h

 //====-- SystemZMCAsmInfo.h - SystemZ asm properties -----------*- C++ -*--===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_LIB_TARGET_SYSTEMZ_MCTARGETDESC_SYSTEMZMCASMINFO_H
 #define LLVM_LIB_TARGET_SYSTEMZ_MCTARGETDESC_SYSTEMZMCASMINFO_H
 
 #include "llvm/MC/MCAsmInfoELF.h"
 #include "llvm/Support/Compiler.h"
 
 namespace llvm {
-class Triple;
+class MCTargetMachine;
 
 class SystemZMCAsmInfo : public MCAsmInfoELF {
 public:
-  explicit SystemZMCAsmInfo(const Triple &TT);
+  explicit SystemZMCAsmInfo(const MCTargetMachine &MCTM);
 };
 
 } // end namespace llvm
 
 #endif

lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmInfo.cpp

 //===-- SystemZMCAsmInfo.cpp - SystemZ asm properties ---------------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 
 #include "SystemZMCAsmInfo.h"
 #include "llvm/MC/MCContext.h"
 #include "llvm/MC/MCSectionELF.h"
 
 using namespace llvm;
 
-SystemZMCAsmInfo::SystemZMCAsmInfo(const Triple &TT) {
+SystemZMCAsmInfo::SystemZMCAsmInfo(const MCTargetMachine &MCTM) {
   PointerSize = 8;
   CalleeSaveStackSlotSize = 8;
   IsLittleEndian = false;
 
   CommentString = "#";
   ZeroDirective = "\t.space\t";
   Data64bitsDirective = "\t.quad\t";
   UsesELFSectionDirectiveForBSS = true;
   SupportsDebugInformation = true;
   ExceptionsType = ExceptionHandling::DwarfCFI;
 
   UseIntegratedAssembler = true;
 }

lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp

 #include "SystemZMCTargetDesc.h"
 #include "InstPrinter/SystemZInstPrinter.h"
 #include "SystemZMCAsmInfo.h"
 #include "llvm/MC/MCCodeGenInfo.h"
 #include "llvm/MC/MCInstrInfo.h"
 #include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/MC/MCStreamer.h"
 #include "llvm/MC/MCSubtargetInfo.h"
+#include "llvm/MC/MCTargetMachine.h"
 #include "llvm/Support/TargetRegistry.h"
 
 using namespace llvm;
 
 #define GET_INSTRINFO_MC_DESC
 #include "SystemZGenInstrInfo.inc"
 
 #define GET_SUBTARGETINFO_MC_DESC
for (unsigned I = 0; I < 32; ++I) {
       Map[VR128Regs[I]] = I;
     }
   }
   assert(Reg < SystemZ::NUM_TARGET_REGS);
   return Map[Reg];
 }
 
 static MCAsmInfo *createSystemZMCAsmInfo(const MCRegisterInfo &MRI,
-                                         const Triple &TT) {
-  MCAsmInfo *MAI = new SystemZMCAsmInfo(TT);
+                                         const MCTargetMachine &MCTM) {
+  MCAsmInfo *MAI = new SystemZMCAsmInfo(MCTM);
   MCCFIInstruction Inst =
       MCCFIInstruction::createDefCfa(nullptr,
                                      MRI.getDwarfRegNum(SystemZ::R15D, true),
                                      SystemZMC::CFAOffsetFromInitialSP);
   MAI->addInitialFrameState(Inst);
   return MAI;
 }
 
static MCInstPrinter *createSystemZMCInstPrinter(const Triple &T,
                                                  unsigned SyntaxVariant,
                                                  const MCAsmInfo &MAI,
                                                  const MCInstrInfo &MII,
                                                  const MCRegisterInfo &MRI) {
   return new SystemZInstPrinter(MAI, MII, MRI);
 }
 
 extern "C" void LLVMInitializeSystemZTargetMC() {
+  // Register the MC target machine
+  RegisterMCTargetMachine<MCTargetMachine> Y(TheSystemZTarget);
+
   // Register the MCAsmInfo.
   TargetRegistry::RegisterMCAsmInfo(TheSystemZTarget,
                                     createSystemZMCAsmInfo);
 
   // Register the MCCodeGenInfo.
   TargetRegistry::RegisterMCCodeGenInfo(TheSystemZTarget,
                                         createSystemZMCCodeGenInfo);
 

lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCAsmInfo.h

 
 #ifndef LLVM_LIB_TARGET_WEBASSEMBLY_MCTARGETDESC_WEBASSEMBLYMCASMINFO_H
 #define LLVM_LIB_TARGET_WEBASSEMBLY_MCTARGETDESC_WEBASSEMBLYMCASMINFO_H
 
 #include "llvm/MC/MCAsmInfo.h"
 
 namespace llvm {
 
-class Triple;
+class WebAssemblyMCTargetMachine;
 
 class WebAssemblyMCAsmInfo final : public MCAsmInfo {
 public:
-  explicit WebAssemblyMCAsmInfo(const Triple &T);
+  explicit WebAssemblyMCAsmInfo(const WebAssemblyMCTargetMachine &MCTM);
   ~WebAssemblyMCAsmInfo() override;
 };
 
 } // end namespace llvm
 
 #endif

lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCAsmInfo.cpp

 //===-- WebAssemblyMCAsmInfo.cpp - WebAssembly asm properties -------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
 /// \brief This file contains the declarations of the WebAssemblyMCAsmInfo
 /// properties.
 ///
 //===----------------------------------------------------------------------===//
 
 #include "WebAssemblyMCAsmInfo.h"
-#include "llvm/ADT/Triple.h"
+#include "WebAssemblyMCTargetMachine.h"
 #include "llvm/Support/CommandLine.h"
 using namespace llvm;
 
 #define DEBUG_TYPE "wasm-mc-asm-info"
 
 WebAssemblyMCAsmInfo::~WebAssemblyMCAsmInfo() {}
 
-WebAssemblyMCAsmInfo::WebAssemblyMCAsmInfo(const Triple &T) {
-  PointerSize = CalleeSaveStackSlotSize = T.isArch64Bit() ? 8 : 4;
+WebAssemblyMCAsmInfo::WebAssemblyMCAsmInfo(
+    const WebAssemblyMCTargetMachine &MCTM) {
+  PointerSize = CalleeSaveStackSlotSize = MCTM.isArch64Bit() ? 8 : 4;
 
   // TODO: What should MaxInstLength be?
 
   // The s-expression format of WebAssembly uses LISP-style comments.
   CommentString = ";;";
 
   PrivateGlobalPrefix = "";
   PrivateLabelPrefix = "";

lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.cpp

 /// \file
 /// \brief This file provides WebAssembly-specific target descriptions.
 ///
 //===----------------------------------------------------------------------===//
 
 #include "WebAssemblyMCTargetDesc.h"
 #include "InstPrinter/WebAssemblyInstPrinter.h"
 #include "WebAssemblyMCAsmInfo.h"
+#include "WebAssemblyMCTargetMachine.h"
 #include "llvm/MC/MCCodeGenInfo.h"
 #include "llvm/MC/MCInstrInfo.h"
 #include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/MC/MCStreamer.h"
 #include "llvm/MC/MCSubtargetInfo.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/TargetRegistry.h"
 using namespace llvm;
 
 #define DEBUG_TYPE "wasm-mc-target-desc"
 
 #define GET_INSTRINFO_MC_DESC
 #include "WebAssemblyGenInstrInfo.inc"
 
 #define GET_SUBTARGETINFO_MC_DESC
 #include "WebAssemblyGenSubtargetInfo.inc"
 
 #define GET_REGINFO_MC_DESC
 #include "WebAssemblyGenRegisterInfo.inc"
 
-static MCAsmInfo *createWebAssemblyMCAsmInfo(const MCRegisterInfo &MRI,
-                                             const Triple &TT) {
-  return new WebAssemblyMCAsmInfo(TT);
-}
-
 static MCInstPrinter *
 createWebAssemblyMCInstPrinter(const Triple &T, unsigned SyntaxVariant,
                                const MCAsmInfo &MAI, const MCInstrInfo &MII,
                                const MCRegisterInfo &MRI) {
   assert(SyntaxVariant == 0);
   return new WebAssemblyInstPrinter(MAI, MII, MRI);
 }
 
 // Force static initialization.
 extern "C" void LLVMInitializeWebAssemblyTargetMC() {
   for (Target *T : {&TheWebAssemblyTarget32, &TheWebAssemblyTarget64}) {
+    // Register the MC target machine
+    RegisterMCTargetMachine<WebAssemblyMCTargetMachine> Y(*T);
+
     // Register the MC asm info.
-    RegisterMCAsmInfoFn X(*T, createWebAssemblyMCAsmInfo);
+    RegisterMCAsmInfo<WebAssemblyMCAsmInfo, WebAssemblyMCTargetMachine> X(*T);
 
     // Register the MCInstPrinter.
     TargetRegistry::RegisterMCInstPrinter(*T, createWebAssemblyMCInstPrinter);
   }
 }

lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetMachine.h

+//===-- WebAssemblyMCTargetMachine.h - Target Information -------*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file defines the MCTargetMachine classes.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIB_TARGET_WEBASSEMBLY_WEBASSEMBLYMCTARGETMACHINE_H
+#define LLVM_LIB_TARGET_WEBASSEMBLY_WEBASSEMBLYMCTARGETMACHINE_H
+
+#include "llvm/ADT/Triple.h"
+#include "llvm/MC/MCTargetMachine.h"
+
+namespace llvm {
+class Target;
+
+class WebAssemblyMCTargetMachine : public MCTargetMachine {
+  WebAssemblyMCTargetMachine(const WebAssemblyMCTargetMachine &) = delete;
+  void operator=(const WebAssemblyMCTargetMachine &) = delete;
+
+  bool IsArch64Bit;
+
+public:
+  WebAssemblyMCTargetMachine(const Target &T, const Triple &TargetTriple)
+      : MCTargetMachine(T, TargetTriple),
+        IsArch64Bit(TargetTriple.isArch64Bit()) {}
+
+  bool isArch64Bit() const { return IsArch64Bit; }
+};
+
+} // End llvm namespace
+
+#endif

lib/Target/X86/MCTargetDesc/X86MCAsmInfo.h

 #define LLVM_LIB_TARGET_X86_MCTARGETDESC_X86MCASMINFO_H
 
 #include "llvm/MC/MCAsmInfo.h"
 #include "llvm/MC/MCAsmInfoCOFF.h"
 #include "llvm/MC/MCAsmInfoDarwin.h"
 #include "llvm/MC/MCAsmInfoELF.h"
 
 namespace llvm {
-class Triple;
+class X86MCTargetMachine;
 
 class X86MCAsmInfoDarwin : public MCAsmInfoDarwin {
   virtual void anchor();
 
 public:
-  explicit X86MCAsmInfoDarwin(const Triple &Triple);
+  explicit X86MCAsmInfoDarwin(const X86MCTargetMachine &MCTM);
 };
 
 struct X86_64MCAsmInfoDarwin : public X86MCAsmInfoDarwin {
-  explicit X86_64MCAsmInfoDarwin(const Triple &Triple);
+  explicit X86_64MCAsmInfoDarwin(const X86MCTargetMachine &MCTM);
   const MCExpr *
   getExprForPersonalitySymbol(const MCSymbol *Sym, unsigned Encoding,
                               MCStreamer &Streamer) const override;
 };
 
 class X86ELFMCAsmInfo : public MCAsmInfoELF {
   void anchor() override;
 
 public:
-  explicit X86ELFMCAsmInfo(const Triple &Triple);
+  explicit X86ELFMCAsmInfo(const X86MCTargetMachine &MCTM);
 };
 
 class X86MCAsmInfoMicrosoft : public MCAsmInfoMicrosoft {
   void anchor() override;
 
 public:
-  explicit X86MCAsmInfoMicrosoft(const Triple &Triple);
+  explicit X86MCAsmInfoMicrosoft(const X86MCTargetMachine &MCTM);
 };
 
 class X86MCAsmInfoGNUCOFF : public MCAsmInfoGNUCOFF {
   void anchor() override;
 
 public:
-  explicit X86MCAsmInfoGNUCOFF(const Triple &Triple);
+  explicit X86MCAsmInfoGNUCOFF(const X86MCTargetMachine &MCTM);
 };
 } // namespace llvm
 
 #endif

lib/Target/X86/MCTargetDesc/X86MCAsmInfo.cpp

 //===-- X86MCAsmInfo.cpp - X86 asm properties -----------------------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file contains the declarations of the X86MCAsmInfo properties.
 //
 //===----------------------------------------------------------------------===//
 
 #include "X86MCAsmInfo.h"
-#include "llvm/ADT/Triple.h"
+#include "X86MCTargetMachine.h"
 #include "llvm/MC/MCContext.h"
 #include "llvm/MC/MCExpr.h"
 #include "llvm/MC/MCSectionELF.h"
 #include "llvm/MC/MCStreamer.h"
 #include "llvm/Support/CommandLine.h"
 #include "llvm/Support/ELF.h"
 using namespace llvm;
 

 
 static cl::opt<bool>
 MarkedJTDataRegions("mark-data-regions", cl::init(false),
   cl::desc("Mark code section jump table data regions."),
   cl::Hidden);
 
 void X86MCAsmInfoDarwin::anchor() { }
 
-X86MCAsmInfoDarwin::X86MCAsmInfoDarwin(const Triple &T) {
-  bool is64Bit = T.getArch() == Triple::x86_64;
+X86MCAsmInfoDarwin::X86MCAsmInfoDarwin(const X86MCTargetMachine &MCTM) {
+  bool is64Bit = MCTM.isArch64Bit();
   if (is64Bit)
     PointerSize = CalleeSaveStackSlotSize = 8;
 
   AssemblerDialect = AsmWriterFlavor;
 
   TextAlignFillValue = 0x90;
 
   if (!is64Bit)
X86MCAsmInfoDarwin::X86MCAsmInfoDarwin(const X86MCTargetMachine &MCTM) {
   UseDataRegionDirectives = MarkedJTDataRegions;
 
   // Exceptions handling
   ExceptionsType = ExceptionHandling::DwarfCFI;
 
   // old assembler lacks some directives
   // FIXME: this should really be a check on the assembler characteristics
   // rather than OS version
-  if (T.isMacOSX() && T.isMacOSXVersionLT(10, 6))
+  if (MCTM.isMacOSX() && MCTM.isMacOSXVersionLT(10, 6))
     HasWeakDefCanBeHiddenDirective = false;
 
   // Assume ld64 is new enough that the abs-ified FDE relocs may be used
   // (actually, must, since otherwise the non-extern relocations we produce
   // overwhelm ld64's tiny little mind and it fails).
   DwarfFDESymbolsUseAbsDiff = true;
 
   UseIntegratedAssembler = true;
 }
 
-X86_64MCAsmInfoDarwin::X86_64MCAsmInfoDarwin(const Triple &Triple)
-  : X86MCAsmInfoDarwin(Triple) {
-}
+X86_64MCAsmInfoDarwin::X86_64MCAsmInfoDarwin(const X86MCTargetMachine &MCTM)
+    : X86MCAsmInfoDarwin(MCTM) {}
 
 void X86ELFMCAsmInfo::anchor() { }
 
-X86ELFMCAsmInfo::X86ELFMCAsmInfo(const Triple &T) {
-  bool is64Bit = T.getArch() == Triple::x86_64;
-  bool isX32 = T.getEnvironment() == Triple::GNUX32;
+X86ELFMCAsmInfo::X86ELFMCAsmInfo(const X86MCTargetMachine &MCTM) {
+  bool is64Bit = MCTM.isArch64Bit();
+  bool isX32 = MCTM.isGnuX32Environment();
 
   // For ELF, x86-64 pointer size depends on the ABI.
   // For x86-64 without the x32 ABI, pointer size is 8. For x86 and for x86-64
   // with the x32 ABI, pointer size remains the default 4.
   PointerSize = (is64Bit && !isX32) ? 8 : 4;
 
   // OTOH, stack slot size is always 8 for x86-64, even with the x32 ABI.
   CalleeSaveStackSlotSize = is64Bit ? 8 : 4;
X86_64MCAsmInfoDarwin::getExprForPersonalitySymbol(const MCSymbol *Sym,
   const MCExpr *Res =
     MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_GOTPCREL, Context);
   const MCExpr *Four = MCConstantExpr::create(4, Context);
   return MCBinaryExpr::createAdd(Res, Four, Context);
 }
 
 void X86MCAsmInfoMicrosoft::anchor() { }
 
-X86MCAsmInfoMicrosoft::X86MCAsmInfoMicrosoft(const Triple &Triple) {
-  if (Triple.getArch() == Triple::x86_64) {
+X86MCAsmInfoMicrosoft::X86MCAsmInfoMicrosoft(const X86MCTargetMachine &MCTM) {
+  if (MCTM.isArch64Bit()) {
     PrivateGlobalPrefix = ".L";
     PrivateLabelPrefix = ".L";
     PointerSize = 8;
     WinEHEncodingType = WinEH::EncodingType::Itanium;
   } else {
     // 32-bit X86 doesn't use CFI, so this isn't a real encoding type. It's just
     // a place holder that the Windows EHStreamer looks for to suppress CFI
     // output. In particular, usesWindowsCFI() returns false.
     WinEHEncodingType = WinEH::EncodingType::X86;
   }
 
   ExceptionsType = ExceptionHandling::WinEH;
 
   AssemblerDialect = AsmWriterFlavor;
 
   TextAlignFillValue = 0x90;
 
   AllowAtInName = true;
 
   UseIntegratedAssembler = true;
 }
 
 void X86MCAsmInfoGNUCOFF::anchor() { }
 
-X86MCAsmInfoGNUCOFF::X86MCAsmInfoGNUCOFF(const Triple &Triple) {
-  assert(Triple.isOSWindows() && "Windows is the only supported COFF target");
-  if (Triple.getArch() == Triple::x86_64) {
+X86MCAsmInfoGNUCOFF::X86MCAsmInfoGNUCOFF(const X86MCTargetMachine &MCTM) {
+  assert(MCTM.isOSWindows() && "Windows is the only supported COFF target");
+  if (MCTM.isArch64Bit()) {
     PrivateGlobalPrefix = ".L";
     PrivateLabelPrefix = ".L";
     PointerSize = 8;
     WinEHEncodingType = WinEH::EncodingType::Itanium;
     ExceptionsType = ExceptionHandling::WinEH;
   } else {
     ExceptionsType = ExceptionHandling::DwarfCFI;
   }
 
   AssemblerDialect = AsmWriterFlavor;
 
   TextAlignFillValue = 0x90;
 
   UseIntegratedAssembler = true;
 }

lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp

 // This file provides X86 specific target descriptions.
 //
 //===----------------------------------------------------------------------===//
 
 #include "X86MCTargetDesc.h"
 #include "InstPrinter/X86ATTInstPrinter.h"
 #include "InstPrinter/X86IntelInstPrinter.h"
 #include "X86MCAsmInfo.h"
+#include "X86MCTargetMachine.h"
 #include "llvm/ADT/Triple.h"
 #include "llvm/MC/MCCodeGenInfo.h"
 #include "llvm/MC/MCInstrAnalysis.h"
 #include "llvm/MC/MCInstrInfo.h"
 #include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/MC/MCStreamer.h"
 #include "llvm/MC/MCSubtargetInfo.h"
 #include "llvm/MC/MachineLocation.h"
static MCRegisterInfo *createX86MCRegisterInfo(const Triple &TT) {
   MCRegisterInfo *X = new MCRegisterInfo();
   InitX86MCRegisterInfo(X, RA, X86_MC::getDwarfRegFlavour(TT, false),
                         X86_MC::getDwarfRegFlavour(TT, true), RA);
   X86_MC::InitLLVM2SEHRegisterMapping(X);
   return X;
 }
 
 static MCAsmInfo *createX86MCAsmInfo(const MCRegisterInfo &MRI,
-                                     const Triple &TheTriple) {
-  bool is64Bit = TheTriple.getArch() == Triple::x86_64;
+                                     const MCTargetMachine &MCTM_) {
+  const X86MCTargetMachine &MCTM =
+      static_cast<const X86MCTargetMachine &>(MCTM_);
+  bool is64Bit = MCTM.isArch64Bit();
 
   MCAsmInfo *MAI;
-  if (TheTriple.isOSBinFormatMachO()) {
+  if (MCTM.isOSBinFormatMachO()) {
     if (is64Bit)
-      MAI = new X86_64MCAsmInfoDarwin(TheTriple);
+      MAI = new X86_64MCAsmInfoDarwin(MCTM);
     else
-      MAI = new X86MCAsmInfoDarwin(TheTriple);
-  } else if (TheTriple.isOSBinFormatELF()) {
+      MAI = new X86MCAsmInfoDarwin(MCTM);
+  } else if (MCTM.isOSBinFormatELF()) {
     // Force the use of an ELF container.
-    MAI = new X86ELFMCAsmInfo(TheTriple);
-  } else if (TheTriple.isWindowsMSVCEnvironment() ||
-             TheTriple.isWindowsCoreCLREnvironment()) {
-    MAI = new X86MCAsmInfoMicrosoft(TheTriple);
-  } else if (TheTriple.isOSCygMing() ||
-             TheTriple.isWindowsItaniumEnvironment()) {
-    MAI = new X86MCAsmInfoGNUCOFF(TheTriple);
+    MAI = new X86ELFMCAsmInfo(MCTM);
+  } else if (MCTM.isWindowsMSVCEnvironment() ||
+             MCTM.isWindowsCoreCLREnvironment()) {
+    MAI = new X86MCAsmInfoMicrosoft(MCTM);
+  } else if (MCTM.isOSCygMing() || MCTM.isWindowsItaniumEnvironment()) {
+    MAI = new X86MCAsmInfoGNUCOFF(MCTM);
   } else {
     // The default is ELF.
-    MAI = new X86ELFMCAsmInfo(TheTriple);
+    MAI = new X86ELFMCAsmInfo(MCTM);
   }
 
   // Initialize initial frame state.
   // Calculate amount of bytes used for return address storing
   int stackGrowth = is64Bit ? -8 : -4;
 
   // Initial state of the frame pointer is esp+stackGrowth.
   unsigned StackPtr = is64Bit ? X86::RSP : X86::ESP;

 
 static MCInstrAnalysis *createX86MCInstrAnalysis(const MCInstrInfo *Info) {
   return new MCInstrAnalysis(Info);
 }
 
 // Force static initialization.
 extern "C" void LLVMInitializeX86TargetMC() {
   for (Target *T : {&TheX86_32Target, &TheX86_64Target}) {
+    // Register the MC target machine
+    RegisterMCTargetMachine<X86MCTargetMachine> Z(*T);
+
     // Register the MC asm info.
     RegisterMCAsmInfoFn X(*T, createX86MCAsmInfo);
 
     // Register the MC codegen info.
     RegisterMCCodeGenInfoFn Y(*T, createX86MCCodeGenInfo);
 
     // Register the MC instruction info.
     TargetRegistry::RegisterMCInstrInfo(*T, createX86MCInstrInfo);

lib/Target/X86/MCTargetDesc/X86MCTargetMachine.h

+//===-- X86MCTargetMachine.h - X86 Target Information -----------*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file defines the MCTargetMachine classes.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIB_TARGET_X86_X86MCTARGETMACHINE_H
+#define LLVM_LIB_TARGET_X86_X86MCTARGETMACHINE_H
+
+#include "llvm/MC/MCTargetMachine.h"
+#include "llvm/ADT/Triple.h"
+
+namespace llvm {
+class Target;
+
+class X86MCTargetMachine : public MCTargetMachine {
+  X86MCTargetMachine(const X86MCTargetMachine &) = delete;
+  void operator=(const X86MCTargetMachine &) = delete;
+
+  // FIXME: We have this to be able to use the MacOSX version comparison.
+  //        It should not be used as a description of the target.
+  Triple TheTargetTriple;
+
+  bool IsMachO;
+  bool IsELF;
+  bool IsMacOSX;
+  bool IsOSCygMing;
+  bool IsWindows;
+  bool IsWindowsMSVCEnvironment;
+  bool IsWindowsCoreCLREnvironment;
+  bool IsWindowsItaniumEnvironment;
+  bool IsGnuX32Environment;
+  bool IsArch64Bit;
+
+public:
+  X86MCTargetMachine(const Target &T, const Triple &TargetTriple)
+      : MCTargetMachine(T, TargetTriple), TheTargetTriple(TargetTriple),
+        IsMachO(TargetTriple.isOSBinFormatMachO()),
+        IsELF(TargetTriple.isOSBinFormatELF()),
+        IsMacOSX(TargetTriple.isMacOSX()),
+        IsOSCygMing(TargetTriple.isOSCygMing()),
+        IsWindows(TargetTriple.isOSWindows()),
+        IsWindowsMSVCEnvironment(TargetTriple.isWindowsMSVCEnvironment()),
+        IsWindowsCoreCLREnvironment(TargetTriple.isWindowsCoreCLREnvironment()),
+        IsWindowsItaniumEnvironment(TargetTriple.isWindowsItaniumEnvironment()),
+        IsGnuX32Environment(TargetTriple.getEnvironment() == Triple::GNUX32),
+        IsArch64Bit(TargetTriple.getArch() == Triple::x86_64) {}
+
+  bool isOSBinFormatELF() const { return IsELF; };
+  bool isOSBinFormatMachO() const { return IsMachO; };
+  bool isMacOSX() const { return IsMacOSX; }
+  unsigned isMacOSXVersionLT(unsigned Major, unsigned Minor = 0,
+                             unsigned Micro = 0) const {
+    return TheTargetTriple.isMacOSXVersionLT(Major, Minor, Micro);
+  }
+  bool isOSWindows() const { return IsWindows; }
+  bool isOSCygMing() const { return IsOSCygMing; }
+  bool isWindowsItaniumEnvironment() const {
+    return IsWindowsItaniumEnvironment;
+  }
+  bool isWindowsCoreCLREnvironment() const {
+    return IsWindowsCoreCLREnvironment;
+  }
+  bool isWindowsMSVCEnvironment() const { return IsWindowsMSVCEnvironment; }
+  bool isGnuX32Environment() const { return IsGnuX32Environment; }
+  bool isArch64Bit() const { return IsArch64Bit; }
+};
+
+} // End llvm namespace
+
+#endif

lib/Target/XCore/MCTargetDesc/XCoreMCAsmInfo.h

 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_LIB_TARGET_XCORE_MCTARGETDESC_XCOREMCASMINFO_H
 #define LLVM_LIB_TARGET_XCORE_MCTARGETDESC_XCOREMCASMINFO_H
 
 #include "llvm/MC/MCAsmInfoELF.h"
 
 namespace llvm {
-class Triple;
+class MCTargetMachine;
 
 class XCoreMCAsmInfo : public MCAsmInfoELF {
   void anchor() override;
 
 public:
-  explicit XCoreMCAsmInfo(const Triple &TT);
+  explicit XCoreMCAsmInfo(const MCTargetMachine &MCTM);
 };
 
 } // namespace llvm
 
 #endif

lib/Target/XCore/MCTargetDesc/XCoreMCAsmInfo.cpp

 //===-- XCoreMCAsmInfo.cpp - XCore asm properties -------------------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 
 #include "XCoreMCAsmInfo.h"
 using namespace llvm;
 
 void XCoreMCAsmInfo::anchor() { }
 
-XCoreMCAsmInfo::XCoreMCAsmInfo(const Triple &TT) {
+XCoreMCAsmInfo::XCoreMCAsmInfo(const MCTargetMachine &MCTM) {
   SupportsDebugInformation = true;
   Data16bitsDirective = "\t.short\t";
   Data32bitsDirective = "\t.long\t";
   Data64bitsDirective = nullptr;
   ZeroDirective = "\t.space\t";
   CommentString = "#";
 
   AscizDirective = ".asciiz";

lib/Target/XCore/MCTargetDesc/XCoreMCTargetDesc.cpp

 #include "XCoreMCTargetDesc.h"
 #include "InstPrinter/XCoreInstPrinter.h"
 #include "XCoreMCAsmInfo.h"
 #include "XCoreTargetStreamer.h"
 #include "llvm/MC/MCCodeGenInfo.h"
 #include "llvm/MC/MCInstrInfo.h"
 #include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/MC/MCSubtargetInfo.h"
+#include "llvm/MC/MCTargetMachine.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/FormattedStream.h"
 #include "llvm/Support/TargetRegistry.h"
 
 using namespace llvm;
 
 #define GET_INSTRINFO_MC_DESC
 #include "XCoreGenInstrInfo.inc"

 }
 
 static MCSubtargetInfo *
 createXCoreMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
   return createXCoreMCSubtargetInfoImpl(TT, CPU, FS);
 }
 
 static MCAsmInfo *createXCoreMCAsmInfo(const MCRegisterInfo &MRI,
-                                       const Triple &TT) {
-  MCAsmInfo *MAI = new XCoreMCAsmInfo(TT);
+                                       const MCTargetMachine &MCTM) {
+  MCAsmInfo *MAI = new XCoreMCAsmInfo(MCTM);
 
   // Initial state of the frame pointer is SP.
   MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(nullptr, XCore::SP, 0);
   MAI->addInitialFrameState(Inst);
 
   return MAI;
 }
 
static MCTargetStreamer *createTargetAsmStreamer(MCStreamer &S,
                                                  formatted_raw_ostream &OS,
                                                  MCInstPrinter *InstPrint,
                                                  bool isVerboseAsm) {
   return new XCoreTargetAsmStreamer(S, OS);
 }
 
 // Force static initialization.
 extern "C" void LLVMInitializeXCoreTargetMC() {
+  // Register the MC target machine
+  RegisterMCTargetMachine<MCTargetMachine> Y(TheXCoreTarget);
+
   // Register the MC asm info.
   RegisterMCAsmInfoFn X(TheXCoreTarget, createXCoreMCAsmInfo);
 
   // Register the MC codegen info.
   TargetRegistry::RegisterMCCodeGenInfo(TheXCoreTarget,
                                         createXCoreMCCodeGenInfo);
 
   // Register the MC instruction info.

tools/dsymutil/DwarfLinker.cpp

 #include "llvm/MC/MCContext.h"
 #include "llvm/MC/MCCodeEmitter.h"
 #include "llvm/MC/MCDwarf.h"
 #include "llvm/MC/MCInstrInfo.h"
 #include "llvm/MC/MCObjectFileInfo.h"
 #include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/MC/MCStreamer.h"
 #include "llvm/MC/MCSubtargetInfo.h"
+#include "llvm/MC/MCTargetMachine.h"
 #include "llvm/Object/MachO.h"
 #include "llvm/Support/Dwarf.h"
 #include "llvm/Support/LEB128.h"
 #include "llvm/Support/TargetRegistry.h"
 #include "llvm/Target/TargetMachine.h"
 #include "llvm/Target/TargetOptions.h"
 #include <string>
 #include <tuple>

 
 /// \brief The Dwarf streaming logic
 ///
 /// All interactions with the MC layer that is used to build the debug
 /// information binary representation are handled in this class.
 class DwarfStreamer {
   /// \defgroup MCObjects MC layer objects constructed by the streamer
   /// @{
+  std::unique_ptr<MCTargetMachine> MCTM;
   std::unique_ptr<MCRegisterInfo> MRI;
   std::unique_ptr<MCAsmInfo> MAI;
   std::unique_ptr<MCObjectFileInfo> MOFI;
   std::unique_ptr<MCContext> MC;
   MCAsmBackend *MAB; // Owned by MCStreamer
   std::unique_ptr<MCInstrInfo> MII;
   std::unique_ptr<MCSubtargetInfo> MSTI;
   MCCodeEmitter *MCE; // Owned by MCStreamer
bool DwarfStreamer::init(Triple TheTriple, StringRef OutputFilename) {
   // Get the target.
   const Target *TheTarget =
       TargetRegistry::lookupTarget(TripleName, TheTriple, ErrorStr);
   if (!TheTarget)
     return error(ErrorStr, Context);
   TripleName = TheTriple.getTriple();
 
   // Create all the MC Objects.
+  MCTM.reset(TheTarget->createMCTargetMachine(TheTriple));
+  if (!MCTM)
+    return error(Twine("no MC target machine for target ") + TripleName,
+                 Context);
+
   MRI.reset(TheTarget->createMCRegInfo(TripleName));
   if (!MRI)
     return error(Twine("no register info for target ") + TripleName, Context);
 
-  MAI.reset(TheTarget->createMCAsmInfo(*MRI, TripleName));
+  MAI.reset(TheTarget->createMCAsmInfo(*MRI, *MCTM));
   if (!MAI)
     return error("no asm info for target " + TripleName, Context);
 
   MOFI.reset(new MCObjectFileInfo);
   MC.reset(new MCContext(MAI.get(), MRI.get(), MOFI.get()));
   MOFI->InitMCObjectFileInfo(TheTriple, Reloc::Default, CodeModel::Default,
                              *MC);
 

tools/llvm-mc/Disassembler.cpp

 #include "llvm/ADT/Triple.h"
 #include "llvm/MC/MCAsmInfo.h"
 #include "llvm/MC/MCContext.h"
 #include "llvm/MC/MCDisassembler.h"
 #include "llvm/MC/MCInst.h"
 #include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/MC/MCStreamer.h"
 #include "llvm/MC/MCSubtargetInfo.h"
+#include "llvm/MC/MCTargetMachine.h"
 #include "llvm/Support/MemoryBuffer.h"
 #include "llvm/Support/SourceMgr.h"
 #include "llvm/Support/TargetRegistry.h"
 #include "llvm/Support/raw_ostream.h"
 
 using namespace llvm;
 
 typedef std::pair<std::vector<unsigned char>, std::vector<const char *>>
while (SkipToToken(Str)) {
     ByteArray.first.push_back(ByteVal);
     ByteArray.second.push_back(Value.data());
     Str = Str.substr(Next);
   }
 
   return false;
 }
 
-int Disassembler::disassemble(const Target &T,
-                              const std::string &Triple,
-                              MCSubtargetInfo &STI,
-                              MCStreamer &Streamer,
-                              MemoryBuffer &Buffer,
-                              SourceMgr &SM,
+int Disassembler::disassemble(const Target &T, const std::string &TripleStr,
+                              MCSubtargetInfo &STI, MCStreamer &Streamer,
+                              MemoryBuffer &Buffer, SourceMgr &SM,
                               raw_ostream &Out) {
+  Triple TT(TripleStr);
 
-  std::unique_ptr<const MCRegisterInfo> MRI(T.createMCRegInfo(Triple));
+  std::unique_ptr<const MCTargetMachine> MCTM(T.createMCTargetMachine(TT));
+  if (!MCTM) {
+    errs() << "error: no MC target machine for target " << TripleStr << "\n";
+    return -1;
+  }
+
+  std::unique_ptr<const MCRegisterInfo> MRI(T.createMCRegInfo(TripleStr));
   if (!MRI) {
-    errs() << "error: no register info for target " << Triple << "\n";
+    errs() << "error: no register info for target " << TripleStr << "\n";
     return -1;
   }
 
-  std::unique_ptr<const MCAsmInfo> MAI(T.createMCAsmInfo(*MRI, Triple));
+  std::unique_ptr<const MCAsmInfo> MAI(T.createMCAsmInfo(*MRI, *MCTM));
   if (!MAI) {
-    errs() << "error: no assembly info for target " << Triple << "\n";
+    errs() << "error: no assembly info for target " << TripleStr << "\n";
     return -1;
   }
 
   // Set up the MCContext for creating symbols and MCExpr's.
   MCContext Ctx(MAI.get(), MRI.get(), nullptr);
 
   std::unique_ptr<const MCDisassembler> DisAsm(
     T.createMCDisassembler(STI, Ctx));
   if (!DisAsm) {
-    errs() << "error: no disassembler for target " << Triple << "\n";
+    errs() << "error: no disassembler for target " << TripleStr << "\n";
     return -1;
   }
 
   // Set up initial section manually here
   Streamer.InitSections(false);
 
   bool ErrorOccurred = false;
 

tools/llvm-mc/llvm-mc.cpp

 #include "llvm/MC/MCInstrInfo.h"
 #include "llvm/MC/MCObjectFileInfo.h"
 #include "llvm/MC/MCParser/AsmLexer.h"
 #include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/MC/MCSectionMachO.h"
 #include "llvm/MC/MCStreamer.h"
 #include "llvm/MC/MCSubtargetInfo.h"
 #include "llvm/MC/MCTargetAsmParser.h"
+#include "llvm/MC/MCTargetMachine.h"
 #include "llvm/MC/MCTargetOptionsCommandFlags.h"
 #include "llvm/Support/CommandLine.h"
 #include "llvm/Support/Compression.h"
 #include "llvm/Support/FileUtilities.h"
 #include "llvm/Support/FormattedStream.h"
 #include "llvm/Support/Host.h"
 #include "llvm/Support/ManagedStatic.h"
 #include "llvm/Support/MemoryBuffer.h"
int main(int argc, char **argv) {
 
   // Tell SrcMgr about this buffer, which is what the parser will pick up.
   SrcMgr.AddNewSourceBuffer(std::move(*BufferPtr), SMLoc());
 
   // Record the location of the include directories so that the lexer can find
   // it later.
   SrcMgr.setIncludeDirs(IncludeDirs);
 
+  std::unique_ptr<MCTargetMachine> MCTM(
+      TheTarget->createMCTargetMachine(TheTriple));
+  assert(MCTM && "Unable to create MC target machine info!");
+
   std::unique_ptr<MCRegisterInfo> MRI(TheTarget->createMCRegInfo(TripleName));
   assert(MRI && "Unable to create target register info!");
 
-  std::unique_ptr<MCAsmInfo> MAI(TheTarget->createMCAsmInfo(*MRI, TripleName));
+  std::unique_ptr<MCAsmInfo> MAI(TheTarget->createMCAsmInfo(*MRI, *MCTM));
   assert(MAI && "Unable to create target asm info!");
 
   if (CompressDebugSections) {
     if (!zlib::isAvailable()) {
       errs() << ProgName
              << ": build tools with zlib to enable -compress-debug-sections";
       return 1;
     }

tools/llvm-objdump/MachODump.cpp

 #include "llvm/MC/MCContext.h"
 #include "llvm/MC/MCDisassembler.h"
 #include "llvm/MC/MCInst.h"
 #include "llvm/MC/MCInstPrinter.h"
 #include "llvm/MC/MCInstrDesc.h"
 #include "llvm/MC/MCInstrInfo.h"
 #include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/MC/MCSubtargetInfo.h"
+#include "llvm/MC/MCTargetMachine.h"
 #include "llvm/Object/MachO.h"
 #include "llvm/Object/MachOUniversal.h"
 #include "llvm/Support/Casting.h"
 #include "llvm/Support/CommandLine.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/Endian.h"
 #include "llvm/Support/Format.h"
 #include "llvm/Support/FormattedStream.h"
static void DisassembleMachO(StringRef Filename, MachOObjectFile *MachOOF,
   if (MAttrs.size()) {
     SubtargetFeatures Features;
     for (unsigned i = 0; i != MAttrs.size(); ++i)
       Features.AddFeature(MAttrs[i]);
     FeaturesStr = Features.getString();
   }
 
   // Set up disassembler.
+  Triple TT(TripleName);
+  std::unique_ptr<const MCTargetMachine> MCTM(
+      TheTarget->createMCTargetMachine(TT));
   std::unique_ptr<const MCRegisterInfo> MRI(
       TheTarget->createMCRegInfo(TripleName));
   std::unique_ptr<const MCAsmInfo> AsmInfo(
-      TheTarget->createMCAsmInfo(*MRI, TripleName));
+      TheTarget->createMCAsmInfo(*MRI, *MCTM));
   std::unique_ptr<const MCSubtargetInfo> STI(
       TheTarget->createMCSubtargetInfo(TripleName, MCPU, FeaturesStr));
   MCContext Ctx(AsmInfo.get(), MRI.get(), nullptr);
   std::unique_ptr<MCDisassembler> DisAsm(
       TheTarget->createMCDisassembler(*STI, Ctx));
   std::unique_ptr<MCSymbolizer> Symbolizer;
   struct DisassembleInfo SymbolizerInfo;
   std::unique_ptr<MCRelocationInfo> RelInfo(
       TheTarget->createMCRelocationInfo(TripleName, Ctx));
   if (RelInfo) {
     Symbolizer.reset(TheTarget->createMCSymbolizer(
         TripleName, SymbolizerGetOpInfo, SymbolizerSymbolLookUp,
         &SymbolizerInfo, &Ctx, std::move(RelInfo)));
     DisAsm->setSymbolizer(std::move(Symbolizer));
   }
   int AsmPrinterVariant = AsmInfo->getAssemblerDialect();
   std::unique_ptr<MCInstPrinter> IP(TheTarget->createMCInstPrinter(
-      Triple(TripleName), AsmPrinterVariant, *AsmInfo, *InstrInfo, *MRI));
+      TT, AsmPrinterVariant, *AsmInfo, *InstrInfo, *MRI));
   // Set the display preference for hex vs. decimal immediates.
   IP->setPrintImmHex(PrintImmHex);
   // Comment stream and backing vector.
   SmallString<128> CommentsToEmit;
   raw_svector_ostream CommentStream(CommentsToEmit);
   // FIXME: Setting the CommentStream in the InstPrinter is problematic in that
   // if it is done then arm64 comments for string literals don't get printed
   // and some constant get printed instead and not setting it causes intel
   // (32-bit and 64-bit) comments printed with different spacing before the
   // comment causing different diffs with the 'C' disassembler library API.
   // IP->setCommentStream(CommentStream);
 
   if (!AsmInfo || !STI || !DisAsm || !IP) {
     errs() << "error: couldn't initialize disassembler for target "
            << TripleName << '\n';
     return;
   }
 
   // Set up thumb disassembler.
+  std::unique_ptr<const MCTargetMachine> ThumbMCTM;
   std::unique_ptr<const MCRegisterInfo> ThumbMRI;
   std::unique_ptr<const MCAsmInfo> ThumbAsmInfo;
   std::unique_ptr<const MCSubtargetInfo> ThumbSTI;
   std::unique_ptr<MCDisassembler> ThumbDisAsm;
   std::unique_ptr<MCInstPrinter> ThumbIP;
   std::unique_ptr<MCContext> ThumbCtx;
   std::unique_ptr<MCSymbolizer> ThumbSymbolizer;
   struct DisassembleInfo ThumbSymbolizerInfo;
   std::unique_ptr<MCRelocationInfo> ThumbRelInfo;
   if (ThumbTarget) {
+    Triple ThumbTT(ThumbTripleName);
+    ThumbMCTM.reset(ThumbTarget->createMCTargetMachine(ThumbTT));
     ThumbMRI.reset(ThumbTarget->createMCRegInfo(ThumbTripleName));
-    ThumbAsmInfo.reset(
-        ThumbTarget->createMCAsmInfo(*ThumbMRI, ThumbTripleName));
+    ThumbAsmInfo.reset(ThumbTarget->createMCAsmInfo(*ThumbMRI, *ThumbMCTM));
     ThumbSTI.reset(
         ThumbTarget->createMCSubtargetInfo(ThumbTripleName, MCPU, FeaturesStr));
     ThumbCtx.reset(new MCContext(ThumbAsmInfo.get(), ThumbMRI.get(), nullptr));
     ThumbDisAsm.reset(ThumbTarget->createMCDisassembler(*ThumbSTI, *ThumbCtx));
     MCContext *PtrThumbCtx = ThumbCtx.get();
     ThumbRelInfo.reset(
         ThumbTarget->createMCRelocationInfo(ThumbTripleName, *PtrThumbCtx));
     if (ThumbRelInfo) {
       ThumbSymbolizer.reset(ThumbTarget->createMCSymbolizer(
           ThumbTripleName, SymbolizerGetOpInfo, SymbolizerSymbolLookUp,
           &ThumbSymbolizerInfo, PtrThumbCtx, std::move(ThumbRelInfo)));
       ThumbDisAsm->setSymbolizer(std::move(ThumbSymbolizer));
     }
     int ThumbAsmPrinterVariant = ThumbAsmInfo->getAssemblerDialect();
     ThumbIP.reset(ThumbTarget->createMCInstPrinter(
-        Triple(ThumbTripleName), ThumbAsmPrinterVariant, *ThumbAsmInfo,
-        *ThumbInstrInfo, *ThumbMRI));
+        ThumbTT, ThumbAsmPrinterVariant, *ThumbAsmInfo, *ThumbInstrInfo,
+        *ThumbMRI));
     // Set the display preference for hex vs. decimal immediates.
     ThumbIP->setPrintImmHex(PrintImmHex);
   }
 
   if (ThumbTarget && (!ThumbAsmInfo || !ThumbSTI || !ThumbDisAsm || !ThumbIP)) {
     errs() << "error: couldn't initialize disassembler for target "
            << ThumbTripleName << '\n';
     return;

tools/llvm-objdump/llvm-objdump.cpp

 #include "llvm/MC/MCInst.h"
 #include "llvm/MC/MCInstPrinter.h"
 #include "llvm/MC/MCInstrAnalysis.h"
 #include "llvm/MC/MCInstrInfo.h"
 #include "llvm/MC/MCObjectFileInfo.h"
 #include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/MC/MCRelocationInfo.h"
 #include "llvm/MC/MCSubtargetInfo.h"
+#include "llvm/MC/MCTargetMachine.h"
 #include "llvm/Object/Archive.h"
 #include "llvm/Object/ELFObjectFile.h"
 #include "llvm/Object/COFF.h"
 #include "llvm/Object/MachO.h"
 #include "llvm/Object/ObjectFile.h"
 #include "llvm/Support/Casting.h"
 #include "llvm/Support/CommandLine.h"
 #include "llvm/Support/Debug.h"

 
 static void DisassembleObject(const ObjectFile *Obj, bool InlineRelocs) {
   const Target *TheTarget = getTarget(Obj);
   // getTarget() will have already issued a diagnostic if necessary, so
   // just bail here if it failed.
   if (!TheTarget)
     return;
 
+  Triple TT(TripleName);
+
   // Package up features to be passed to target/subtarget
   std::string FeaturesStr;
   if (MAttrs.size()) {
     SubtargetFeatures Features;
     for (unsigned i = 0; i != MAttrs.size(); ++i)
       Features.AddFeature(MAttrs[i]);
     FeaturesStr = Features.getString();
   }
 
+  std::unique_ptr<const MCTargetMachine> MCTM(
+      TheTarget->createMCTargetMachine(TT));
+  if (!MCTM) {
+    errs() << "error: no register info for target " << TripleName << "\n";
+    return;
+  }
+
   std::unique_ptr<const MCRegisterInfo> MRI(
       TheTarget->createMCRegInfo(TripleName));
   if (!MRI) {
     errs() << "error: no register info for target " << TripleName << "\n";
     return;
   }
 
   // Set up disassembler.
   std::unique_ptr<const MCAsmInfo> AsmInfo(
-      TheTarget->createMCAsmInfo(*MRI, TripleName));
+      TheTarget->createMCAsmInfo(*MRI, *MCTM));
   if (!AsmInfo) {
     errs() << "error: no assembly info for target " << TripleName << "\n";
     return;
   }
 
   std::unique_ptr<const MCSubtargetInfo> STI(
       TheTarget->createMCSubtargetInfo(TripleName, MCPU, FeaturesStr));
   if (!STI) {

tools/llvm-rtdyld/llvm-rtdyld.cpp

 #include "llvm/ExecutionEngine/RuntimeDyldChecker.h"
 #include "llvm/MC/MCAsmInfo.h"
 #include "llvm/MC/MCContext.h"
 #include "llvm/MC/MCDisassembler.h"
 #include "llvm/MC/MCInstPrinter.h"
 #include "llvm/MC/MCInstrInfo.h"
 #include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/MC/MCSubtargetInfo.h"
+#include "llvm/MC/MCTargetMachine.h"
 #include "llvm/Object/MachO.h"
 #include "llvm/Object/SymbolSize.h"
 #include "llvm/Support/CommandLine.h"
 #include "llvm/Support/DynamicLibrary.h"
 #include "llvm/Support/ManagedStatic.h"
 #include "llvm/Support/Memory.h"
 #include "llvm/Support/MemoryBuffer.h"
 #include "llvm/Support/PrettyStackTrace.h"
if (!TheTarget) {
     return 1;
   }
   TripleName = TheTriple.getTriple();
 
   std::unique_ptr<MCSubtargetInfo> STI(
     TheTarget->createMCSubtargetInfo(TripleName, MCPU, ""));
   assert(STI && "Unable to create subtarget info!");
 
+  std::unique_ptr<MCTargetMachine> MCTM(
+      TheTarget->createMCTargetMachine(TheTriple));
+  assert(MCTM && "Unable to create MC target machine info!");
+
   std::unique_ptr<MCRegisterInfo> MRI(TheTarget->createMCRegInfo(TripleName));
   assert(MRI && "Unable to create target register info!");
 
-  std::unique_ptr<MCAsmInfo> MAI(TheTarget->createMCAsmInfo(*MRI, TripleName));
+  std::unique_ptr<MCAsmInfo> MAI(TheTarget->createMCAsmInfo(*MRI, *MCTM));
   assert(MAI && "Unable to create target asm info!");
 
   MCContext Ctx(MAI.get(), MRI.get(), nullptr);
 
   std::unique_ptr<MCDisassembler> Disassembler(
     TheTarget->createMCDisassembler(*STI, Ctx));
   assert(Disassembler && "Unable to create disassembler!");