[AVR] Do not emit instructions invalid for attiny10

[aykevl]

Summary

The attiny4/attiny5/attiny9/attiny10 have a slightly modified instruction set that drops a number of useful instructions. This patch makes sure to not emit them on these "reduced tiny" cores.

The affected instructions are:

• lds and sts (load/store directly from data)
• ldd and std (load/store with displacement)
• adiw and sbiw (add/sub register pairs)
• various other instructions that were emitted without checking whether the chip actually supports them (movw, adiw, etc)

There is a variant on lds and sts on these chips, but it can only address a limited portion of the address space and is mainly useful to load/store I/O registers (as an extension to the in and out instructions). I have not implemented it here, implementing it can be done in a separate patch.

This patch is not optimal. I'm sure it can be improved a lot. For example, we could teach the instruction selector to not select lddw/stdw instructions so that the weird pointer adjustments are not necessary. But for now I've focused just on correctness, not on code quality.

[benshi001]

llvm/lib/Target/AVR/AVRRegisterInfo.cpp

238

It seems better to be

int MaxOffset = STI.hasTinyEncoding() ? 0 : 62;

And you can change to that when committing your patch.

[benshi001]

More suggestions

1. Change the title to [AVR] Avoid emitting instructions invalid on avrtiny devices

2. Simplify the commit message to

The attiny4/attiny5/attiny9/attiny10 have a slightly modified instruction set that drops a number of useful instructions. This patch makes sure to not emit them on these "reduced tiny" cores.

The affected instructions are:

lds and sts (load/store directly from data)
ldd and std (load/store with displacement)
adiw and sbiw (add/sub register pairs)

3. Append Updates https://github.com/llvm/llvm-project/issues/53459 at the end of your commit message.

4. When you committing, report the commit link to https://github.com/llvm/llvm-project/issues/53459 .

5. Mention TODOs in https://github.com/llvm/llvm-project/issues/53459 , as you pointed

There is a variant on lds and sts on these chips, but it can only address a limited portion of the address space and is mainly useful to load/store I/O registers (as an extension to the in and out instructions). I have not implemented it here, implementing it can be done in a separate patch.

This patch is not optimal. I'm sure it can be improved a lot. For example, we could teach the instruction selector to not select lddw/stdw instructions so that the weird pointer adjustments are not necessary. But for now I've focused just on correctness, not on code quality.

[aykevl]

In D131867#3722606, @benshi001 wrote:

2. Simplify the commit message to

The attiny4/attiny5/attiny9/attiny10 have a slightly modified instruction set that drops a number of useful instructions. This patch makes sure to not emit them on these "reduced tiny" cores.

The affected instructions are:

lds and sts (load/store directly from data)
ldd and std (load/store with displacement)
adiw and sbiw (add/sub register pairs)

Why? I think the extra information in the commit message is helpful.

I will apply the other suggestions when I commit.

[benshi001]

@aykevl , you are appreciated to commit it ASAP.

[aykevl]

Looks like this patch doesn't apply cleanly, I'll need to rebase it.

[benshi001]

Ayke, you are appreciated to commit your code ASAP.

[aykevl]

While rebasing I found a bug, see: https://reviews.llvm.org/D121672#3927385

[benshi001]

In D131867#3927386, @aykevl wrote:

While rebasing I found a bug, see: https://reviews.llvm.org/D121672#3927385

Thanks for your information. I have made a patch to fix that.

https://reviews.llvm.org/D138125

Beside changes in the clang side, some extra work is need on the backend, and I will do that later this week.

[benshi001]

In D131867#3927386, @aykevl wrote:

While rebasing I found a bug, see: https://reviews.llvm.org/D121672#3927385

This bug is fully fixed in https://reviews.llvm.org/D138201, you are appreciated to have a look.

[benshi001]

In D131867#3927386, @aykevl wrote:

While rebasing I found a bug, see: https://reviews.llvm.org/D121672#3927385

The bug you found is fixed. I think you can merge this patch.

[aykevl]

Working on rebasing this but there were a lot of changes.

[aykevl]

• rebased on top of the main branch (with lots of improvements and fixed as well)

[aykevl]

Please take another look! A lot of things have changed.

llvm/lib/Target/AVR/AVRExpandPseudoInsts.cpp

1141–1147

I've changed the behavior here slightly because that's what I did in the previous version of this patch and because it's more efficient. It's better to subtract and then add the pointer than to push, subtract, and pop the previous value.

llvm/lib/Target/AVR/AVRFrameLowering.cpp

466

I think this was a preexisting bug that simply never surfaced. It was necessary to fix to get parameter loads from the stack to work correctly.

llvm/lib/Target/AVR/AVRRegisterInfo.cpp

172–183

Instead of changing the instruction, the new code creates a new movw (or two new movs) and removes the FRMIDX instruction. This seems cleaner to me and also fixes a potential bug where the MOVRdRr instruction had an implicit SREG operand (which is weird).

238

Fixed.

llvm/test/CodeGen/AVR/calling-conv/c/tiny.ll

43–44

Fixed the ldd!

49–59

The code here is really terrible but it should be correct. I hope to optimize this in a later pass with a late pass that merges pointer adjustments.

[benshi001]

llvm/lib/Target/AVR/AVRExpandPseudoInsts.cpp

1141–1147

That's good!

llvm/lib/Target/AVR/AVRInstrInfo.td

1337

subiw is still a pseudo instruction, it would be better to give real instructions in this comment.

1418

subiw is still a pseudo instruction, it would be better to give real instructions in this comment.

1555

The same suggestion as above.

1667

The same suggestion as above.

[benshi001]

It would be better to mention Updates https://github.com/llvm/llvm-project/issues/53459 in your commit message.

[benshi001]

llvm/test/CodeGen/AVR/calling-conv/c/tiny.ll

49–59

Is such pattern common ? Is it necessary to introduce an extra pass just for this pattern?

Since AVRTiny is a known low performance device serial, I think such pattern is OK. An extra pass will lead to longer run time.

[benshi001]

LGTM. Thanks. You can apply my suggestion while commiting your patch.

[aykevl]

llvm/lib/Target/AVR/AVRInstrInfo.td

1337

How would you suggest to do this? Something like this?

//   ld   Rd,   P+
//   ld   Rd+1, P+
//   subi PL,    2
//   sbci PH,    0

I think the original is easier to read.

1418

Same here, but here it becomes even harder to write nice instructions. Closest I can think of is this:

//   subi PL,   lo8(-q)
//   sbci PH,   hi8(-q)
//   ld   Rd,   P+
//   ld   Rd+1, P+
//   subi PL,   lo8(q)
//   sbci PH,   hi8(q)

llvm/test/CodeGen/AVR/calling-conv/c/tiny.ll

49–59

Is such pattern common ? Is it necessary to introduce an extra pass just for this pattern?

I don't know. Maybe I'll try it, maybe not. But these chips are so small that every bit helps.

[benshi001]

llvm/lib/Target/AVR/AVRInstrInfo.td

1337

Indeed, I think this form is more obvious

1418

That is fine.

llvm/test/CodeGen/AVR/calling-conv/c/tiny.ll

49–59

That is another issue which we can decide later. Please commit this patch.

[benshi001]

llvm/lib/Target/AVR/AVRInstrInfo.td

327

Should it be any_of rather than all_of for HasNonTinyEncoding ?

[aykevl]

llvm/lib/Target/AVR/AVRInstrInfo.td

327

It seems like all_of is the more common form. Try:

git grep 'all_of' llvm/lib/Target/ | grep not

llvm/lib/Target/AVR/AVRExpandPseudoInsts.cpp

bool AVRExpandPseudo::expand<AVR::LDSWRdK>(Block &MBB, BlockIt MBBI) {
 
   MI.eraseFromParent();
   return true;
 }
 
 template <>
 bool AVRExpandPseudo::expand<AVR::LDWRdPtr>(Block &MBB, BlockIt MBBI) {
   MachineInstr &MI = *MBBI;
-  Register DstLoReg, DstHiReg;
   Register DstReg = MI.getOperand(0).getReg();
   Register SrcReg = MI.getOperand(1).getReg();
+  bool DstIsKill = MI.getOperand(0).isKill();
   bool SrcIsKill = MI.getOperand(1).isKill();
-  unsigned OpLo = AVR::LDRdPtr;
-  unsigned OpHi = AVR::LDDRdPtrQ;
-  TRI->splitReg(DstReg, DstLoReg, DstHiReg);
+  const AVRSubtarget &STI = MBB.getParent()->getSubtarget<AVRSubtarget>();
 
   // DstReg has an earlyclobber so the register allocator will allocate them in
   // separate registers.
   assert(DstReg != SrcReg && "Dst and Src registers are the same!");
 
+  if (STI.hasTinyEncoding()) {
+    // Handle this case in the expansion of LDDWRdPtrQ because it is very
+    // similar.
+    buildMI(MBB, MBBI, AVR::LDDWRdPtrQ)
+        .addDef(DstReg, getKillRegState(DstIsKill))
+        .addReg(SrcReg, getKillRegState(SrcIsKill))
+        .addImm(0)
+        .setMemRefs(MI.memoperands());
+
+  } else {
+    Register DstLoReg, DstHiReg;
+    TRI->splitReg(DstReg, DstLoReg, DstHiReg);
+
     // Load low byte.
-  buildMI(MBB, MBBI, OpLo)
+    buildMI(MBB, MBBI, AVR::LDRdPtr)
         .addReg(DstLoReg, RegState::Define)
         .addReg(SrcReg)
         .setMemRefs(MI.memoperands());
 
     // Load high byte.
-  buildMI(MBB, MBBI, OpHi)
+    buildMI(MBB, MBBI, AVR::LDDRdPtrQ)
         .addReg(DstHiReg, RegState::Define)
         .addReg(SrcReg, getKillRegState(SrcIsKill))
         .addImm(1)
         .setMemRefs(MI.memoperands());
+  }
 
   MI.eraseFromParent();
   return true;
 }
 
 template <>
 bool AVRExpandPseudo::expand<AVR::LDWRdPtrPi>(Block &MBB, BlockIt MBBI) {
   MachineInstr &MI = *MBBI;
bool AVRExpandPseudo::expand<AVR::LDWRdPtrPd>(Block &MBB, BlockIt MBBI) {
 
   MI.eraseFromParent();
   return true;
 }
 
 template <>
 bool AVRExpandPseudo::expand<AVR::LDDWRdPtrQ>(Block &MBB, BlockIt MBBI) {
   MachineInstr &MI = *MBBI;
-  Register DstLoReg, DstHiReg;
   Register DstReg = MI.getOperand(0).getReg();
   Register SrcReg = MI.getOperand(1).getReg();
   unsigned Imm = MI.getOperand(2).getImm();
+  bool DstIsKill = MI.getOperand(0).isKill();
   bool SrcIsKill = MI.getOperand(1).isKill();
-  unsigned OpLo = AVR::LDDRdPtrQ;
-  unsigned OpHi = AVR::LDDRdPtrQ;
-  TRI->splitReg(DstReg, DstLoReg, DstHiReg);
+  const AVRSubtarget &STI = MBB.getParent()->getSubtarget<AVRSubtarget>();
 
   // Since we add 1 to the Imm value for the high byte below, and 63 is the
   // highest Imm value allowed for the instruction, 62 is the limit here.
   assert(Imm <= 62 && "Offset is out of range");
 
   // DstReg has an earlyclobber so the register allocator will allocate them in
   // separate registers.
   assert(DstReg != SrcReg && "Dst and Src registers are the same!");
 
+  if (STI.hasTinyEncoding()) {
+    // Reduced tiny cores don't support load/store with displacement. However,
+    // they do support postincrement. So we'll simply adjust the pointer before
+    // and after and use postincrement to load multiple registers.
+
+    // Add offset. The offset can be 0 when expanding this instruction from the
+    // more specific LDWRdPtr instruction.
+    if (Imm != 0) {
+      buildMI(MBB, MBBI, AVR::SUBIWRdK, SrcReg)
+          .addReg(SrcReg)
+          .addImm(0x10000 - Imm);
+    }
+
+    // Do a word load with postincrement. This will be lowered to a two byte
+    // load.
+    buildMI(MBB, MBBI, AVR::LDWRdPtrPi)
+        .addDef(DstReg, getKillRegState(DstIsKill))
+        .addReg(SrcReg, getKillRegState(SrcIsKill))
+        .addImm(0)
+        .setMemRefs(MI.memoperands());
+
+    // If the pointer is used after the store instruction, subtract the new
+    // offset (with 2 added after the postincrement instructions) so it is the
+    // same as before.
+    if (!SrcIsKill) {
+      buildMI(MBB, MBBI, AVR::SUBIWRdK, SrcReg).addReg(SrcReg).addImm(Imm + 2);
+    }
+  } else {
+    Register DstLoReg, DstHiReg;
+    TRI->splitReg(DstReg, DstLoReg, DstHiReg);
+
     // Load low byte.
-  buildMI(MBB, MBBI, OpLo)
+    buildMI(MBB, MBBI, AVR::LDDRdPtrQ)
         .addReg(DstLoReg, RegState::Define)
         .addReg(SrcReg)
         .addImm(Imm)
         .setMemRefs(MI.memoperands());
 
     // Load high byte.
-  buildMI(MBB, MBBI, OpHi)
+    buildMI(MBB, MBBI, AVR::LDDRdPtrQ)
         .addReg(DstHiReg, RegState::Define)
         .addReg(SrcReg, getKillRegState(SrcIsKill))
         .addImm(Imm + 1)
         .setMemRefs(MI.memoperands());
+  }
 
   MI.eraseFromParent();
   return true;
 }
 
 bool AVRExpandPseudo::expandLPMWELPMW(Block &MBB, BlockIt MBBI, bool IsExt) {
   MachineInstr &MI = *MBBI;
   Register DstLoReg, DstHiReg;
bool AVRExpandPseudo::expand<AVR::STSWKRr>(Block &MBB, BlockIt MBBI) {
 
   MI.eraseFromParent();
   return true;
 }
 
 template <>
 bool AVRExpandPseudo::expand<AVR::STWPtrRr>(Block &MBB, BlockIt MBBI) {
   MachineInstr &MI = *MBBI;
-  Register SrcLoReg, SrcHiReg;
   Register DstReg = MI.getOperand(0).getReg();
   Register SrcReg = MI.getOperand(1).getReg();
+  bool DstIsKill = MI.getOperand(0).isKill();
   bool DstIsUndef = MI.getOperand(0).isUndef();
   bool SrcIsKill = MI.getOperand(1).isKill();
-  unsigned OpLo = AVR::STPtrRr;
-  unsigned OpHi = AVR::STDPtrQRr;
-  TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg);
+  const AVRSubtarget &STI = MBB.getParent()->getSubtarget<AVRSubtarget>();
 
   //: TODO: need to reverse this order like inw and stsw?
-  auto MIBLO = buildMI(MBB, MBBI, OpLo)
-                   .addReg(DstReg, getUndefRegState(DstIsUndef))
-                   .addReg(SrcLoReg, getKillRegState(SrcIsKill));
+
+  if (STI.hasTinyEncoding()) {
+    // Handle this case in the expansion of STDWPtrQRr because it is very
+    // similar.
+    buildMI(MBB, MBBI, AVR::STDWPtrQRr)
+        .addReg(DstReg,
+                getKillRegState(DstIsKill) | getUndefRegState(DstIsUndef))
+        .addImm(0)
+        .addReg(SrcReg, getKillRegState(SrcIsKill))
+        .setMemRefs(MI.memoperands());
+
+  } else {
+    Register SrcLoReg, SrcHiReg;
+    TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg);
+    buildMI(MBB, MBBI, AVR::STPtrRr)
+        .addReg(SrcLoReg, getKillRegState(SrcIsKill))
+        .setMemRefs(MI.memoperands());
 
-  auto MIBHI = buildMI(MBB, MBBI, OpHi)
-                   .addReg(DstReg, getUndefRegState(DstIsUndef))
-                   .addImm(1)
-                   .addReg(SrcHiReg, getKillRegState(SrcIsKill));
-
-  MIBLO.setMemRefs(MI.memoperands());
-  MIBHI.setMemRefs(MI.memoperands());
+    buildMI(MBB, MBBI, AVR::STDPtrQRr)
+        .addReg(SrcHiReg, getKillRegState(SrcIsKill))
+        .setMemRefs(MI.memoperands());
+  }
 
   MI.eraseFromParent();
   return true;
 }
 
 template <>
 bool AVRExpandPseudo::expand<AVR::STWPtrPiRr>(Block &MBB, BlockIt MBBI) {
   MachineInstr &MI = *MBBI;
bool AVRExpandPseudo::expand<AVR::STWPtrPdRr>(Block &MBB, BlockIt MBBI) {
 
   MI.eraseFromParent();
   return true;
 }
 
 template <>
 bool AVRExpandPseudo::expand<AVR::STDWPtrQRr>(Block &MBB, BlockIt MBBI) {
   MachineInstr &MI = *MBBI;
+  const AVRSubtarget &STI = MBB.getParent()->getSubtarget<AVRSubtarget>();
 
   Register DstReg = MI.getOperand(0).getReg();
   bool DstIsKill = MI.getOperand(0).isKill();
   unsigned Imm = MI.getOperand(1).getImm();
   Register SrcReg = MI.getOperand(2).getReg();
   bool SrcIsKill = MI.getOperand(2).isKill();
 
   // STD's maximum displacement is 63, so larger stores have to be split into a
-  // set of operations
-  if (Imm >= 63) {
-    if (!DstIsKill) {
-      buildMI(MBB, MBBI, AVR::PUSHWRr).addReg(DstReg);
-    }
-
-    buildMI(MBB, MBBI, AVR::SUBIWRdK)
-        .addReg(DstReg, RegState::Define)
+  // set of operations.
+  // For avrtiny chips, STD is not available at all so we always have to fall
+  // back to manual pointer adjustments.
+  if (Imm >= 63 || STI.hasTinyEncoding()) {
+    // Add offset. The offset can be 0 when expanding this instruction from the
+    // more specific STWPtrRr instruction.
+    if (Imm != 0) {
+      buildMI(MBB, MBBI, AVR::SUBIWRdK, DstReg)
           .addReg(DstReg, RegState::Kill)
-        .addImm(-Imm);
+          .addImm(0x10000 - Imm);
+    }
 
-    buildMI(MBB, MBBI, AVR::STWPtrRr)
-        .addReg(DstReg, RegState::Kill)
-        .addReg(SrcReg, getKillRegState(SrcIsKill));
+    // Do the store. This is a word store, that will be expanded further.
+    buildMI(MBB, MBBI, AVR::STWPtrPiRr, DstReg)
+        .addReg(DstReg, getKillRegState(DstIsKill))
+        .addReg(SrcReg, getKillRegState(SrcIsKill))
+        .addImm(0)
+        .setMemRefs(MI.memoperands());
 
+    // If the pointer is used after the store instruction, subtract the new
+    // offset (with 2 added after the postincrement instructions) so it is the
+    // same as before.
     if (!DstIsKill) {
-      buildMI(MBB, MBBI, AVR::POPWRd).addDef(DstReg, RegState::Define);
+      buildMI(MBB, MBBI, AVR::SUBIWRdK, DstReg)
+          .addReg(DstReg, RegState::Kill)
+          .addImm(Imm + 2);
     }
   } else {
     unsigned OpLo = AVR::STDPtrQRr;
     unsigned OpHi = AVR::STDPtrQRr;
     Register SrcLoReg, SrcHiReg;
     TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg);
 
     auto MIBLO = buildMI(MBB, MBBI, OpLo)

llvm/lib/Target/AVR/AVRFrameLowering.cpp

for (MachineBasicBlock &MBBJ : llvm::drop_begin(MF)) {
     MBBJ.addLiveIn(AVR::R29R28);
   }
 
   if (!FrameSize) {
     return;
   }
 
   // Reserve the necessary frame memory by doing FP -= <size>.
-  unsigned Opcode = (isUInt<6>(FrameSize)) ? AVR::SBIWRdK : AVR::SUBIWRdK;
+  unsigned Opcode = (isUInt<6>(FrameSize) && STI.hasADDSUBIW()) ? AVR::SBIWRdK
+                                                                : AVR::SUBIWRdK;
 
   MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(Opcode), AVR::R29R28)
                          .addReg(AVR::R29R28, RegState::Kill)
                          .addImm(FrameSize)
                          .setMIFlag(MachineInstr::FrameSetup);
   // The SREG implicit def is dead.
   MI->getOperand(3).setIsDead();
 
while (MBBI != MBB.begin()) {
 
     --MBBI;
   }
 
   if (FrameSize) {
     unsigned Opcode;
 
     // Select the optimal opcode depending on how big it is.
-    if (isUInt<6>(FrameSize)) {
+    if (isUInt<6>(FrameSize) && STI.hasADDSUBIW()) {
       Opcode = AVR::ADIWRdK;
     } else {
       Opcode = AVR::SUBIWRdK;
       FrameSize = -FrameSize;
     }
 
     // Restore the frame pointer by doing FP += <size>.
     MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(Opcode), AVR::R29R28)
if (Opcode == TII.getCallFrameSetupOpcode()) {
 
     // Note that small stack changes could be implemented more efficiently
     // with a few pop instructions instead of the 8-9 instructions now
     // required.
 
     // Select the best opcode to adjust SP based on the offset size.
     unsigned AddOpcode;
 
-    if (isUInt<6>(Amount)) {
+    if (isUInt<6>(Amount) && STI.hasADDSUBIW()) {
       AddOpcode = AVR::ADIWRdK;
     } else {
       AddOpcode = AVR::SUBIWRdK;
       Amount = -Amount;
     }
 
     // Build the instruction sequence.
     BuildMI(MBB, MI, DL, TII.get(AVR::SPREAD), AVR::R31R30).addReg(AVR::SP);
bool runOnMachineFunction(MachineFunction &MF) override {
 
     // Ok fixed frame indexes present, now scan the function to see if they
     // are really being used, otherwise we can ignore them.
     for (const MachineBasicBlock &BB : MF) {
       for (const MachineInstr &MI : BB) {
         int Opcode = MI.getOpcode();
 
         if ((Opcode != AVR::LDDRdPtrQ) && (Opcode != AVR::LDDWRdPtrQ) &&
-            (Opcode != AVR::STDPtrQRr) && (Opcode != AVR::STDWPtrQRr)) {
+            (Opcode != AVR::STDPtrQRr) && (Opcode != AVR::STDWPtrQRr) &&
+            (Opcode != AVR::FRMIDX)) {
           continue;
         }
 
         for (const MachineOperand &MO : MI.operands()) {
           if (!MO.isFI()) {
             continue;
           }
 

llvm/lib/Target/AVR/AVRInstrInfo.td

def SupportsMultiplication : Predicate<"Subtarget->supportsMultiplication()">,
                              AssemblerPredicate<(all_of FeatureMultiplication)>;
 
 def HasBREAK : Predicate<"Subtarget->hasBREAK()">,
                AssemblerPredicate<(all_of FeatureBREAK)>;
 
 def HasTinyEncoding : Predicate<"Subtarget->hasTinyEncoding()">,
                       AssemblerPredicate<(all_of FeatureTinyEncoding)>;
 
+def HasNonTinyEncoding : Predicate<"!Subtarget->hasTinyEncoding()">,
+                         AssemblerPredicate<(all_of (not FeatureTinyEncoding))>;
+
 // AVR specific condition code. These correspond to AVR_*_COND in
 // AVRInstrInfo.td. They must be kept in synch.
 def AVR_COND_EQ : PatLeaf<(i8 0)>;
 def AVR_COND_NE : PatLeaf<(i8 1)>;
 def AVR_COND_GE : PatLeaf<(i8 2)>;
 def AVR_COND_LT : PatLeaf<(i8 3)>;
 def AVR_COND_SH : PatLeaf<(i8 4)>;
 def AVR_COND_LO : PatLeaf<(i8 5)>;
let canFoldAsLoad = 1, isReMaterializable = 1 in {
   def LDSRdK : F32DM<0b0,
                      (outs GPR8
                       : $rd),
                      (ins imm16
                       : $k),
                      "lds\t$rd, $k", [(set i8
                                        : $rd, (load imm
                                                : $k))]>,
-               Requires<[HasSRAM]>;
+               Requires<[HasSRAM, HasNonTinyEncoding]>;
 
   // LDSW Rd+1:Rd, K+1:K
   //
   // Expands to:
   // lds Rd,  (K+1:K)
   // lds Rd+1 (K+1:K) + 1
   def LDSWRdK : Pseudo<(outs DREGS
                         : $dst),
                        (ins i16imm
                         : $src),
                        "ldsw\t$dst, $src", [(set i16
                                              : $dst, (load imm
                                                       : $src))]>,
-                Requires<[HasSRAM]>;
+                Requires<[HasSRAM, HasNonTinyEncoding]>;
 }
 
 // Indirect loads.
 let canFoldAsLoad = 1, isReMaterializable = 1 in {
   def LDRdPtr : FSTLD<0, 0b00,
                       (outs GPR8
                        : $reg),
                       (ins LDSTPtrReg
                        : $ptrreg),
                       "ld\t$reg, $ptrreg", [(set GPR8
                                              : $reg, (load i16
                                                       : $ptrreg))]>,
                 Requires<[HasSRAM]>;
 
   // LDW Rd+1:Rd, P
   //
   // Expands to:
-  // ld  Rd,   P
-  // ldd Rd+1, P+1
+  //   ld  Rd,   P
+  //   ldd Rd+1, P+1
+  // On reduced tiny cores, this instruction expands to:
+  //   ld    Rd,   P+
+  //   ld    Rd+1, P+
+  //   subiw P,    2
   let Constraints = "@earlyclobber $reg" in def LDWRdPtr
       : Pseudo<(outs DREGS
                 : $reg),
                (ins PTRDISPREGS
                 : $ptrreg),
                "ldw\t$reg, $ptrreg", [(set i16
                                        : $reg, (load i16
                                                 : $ptrreg))]>,
let Constraints = "@earlyclobber $reg" in def LDDRdPtrQ
       : FSTDLDD<0,
                 (outs GPR8
                  : $reg),
                 (ins memri
                  : $memri),
                 "ldd\t$reg, $memri", [(set i8
                                        : $reg, (load addr
                                                 : $memri))]>,
-      Requires<[HasSRAM]>;
+      Requires<[HasSRAM, HasNonTinyEncoding]>;
 
   // LDDW Rd+1:Rd, P+q
   //
   // Expands to:
-  // ldd Rd,   P+q
-  // ldd Rd+1, P+q+1
+  //   ldd Rd,   P+q
+  //   ldd Rd+1, P+q+1
+  // On reduced tiny cores, this instruction expands to:
+  //   subiw P,    -q
+  //   ld    Rd,   P+
+  //   ld    Rd+1, P+
+  //   subiw P,    q+2
   let Constraints = "@earlyclobber $dst" in def LDDWRdPtrQ
       : Pseudo<(outs DREGS
                 : $dst),
                (ins memri
                 : $memri),
                "lddw\t$dst, $memri", [(set i16
                                        : $dst, (load addr
                                                 : $memri))]>,

 // Indirect store from register to data space.
 def STSKRr : F32DM<0b1, (outs),
                    (ins imm16
                     : $k, GPR8
                     : $rd),
                    "sts\t$k, $rd", [(store i8
                                      : $rd, imm
                                      : $k)]>,
-             Requires<[HasSRAM]>;
+             Requires<[HasSRAM, HasNonTinyEncoding]>;
 
 // STSW K+1:K, Rr+1:Rr
 //
 // Expands to:
 // sts Rr+1, (K+1:K) + 1
 // sts Rr,   (K+1:K)
 def STSWKRr : Pseudo<(outs),
                      (ins i16imm
                       : $dst, DREGS
                       : $src),
                      "stsw\t$dst, $src", [(store i16
                                            : $src, imm
                                            : $dst)]>,
-              Requires<[HasSRAM]>;
+              Requires<[HasSRAM, HasNonTinyEncoding]>;
 
 // Indirect stores.
 // ST P, Rr
 // Stores the value of Rr into the location addressed by pointer P.
 def STPtrRr : FSTLD<1, 0b00, (outs),
                     (ins LDSTPtrReg
                      : $ptrreg, GPR8
                      : $reg),
                     "st\t$ptrreg, $reg", [(store GPR8
                                            : $reg, i16
                                            : $ptrreg)]>,
               Requires<[HasSRAM]>;
 
 // STW P, Rr+1:Rr
 // Stores the value of Rr into the location addressed by pointer P.
 //
 // Expands to:
-// st P, Rr
-// std P+1, Rr+1
+//   st P, Rr
+//   std P+1, Rr+1
+// On reduced tiny cores, this instruction expands to:
+//   st    P+, Rr
+//   st    P+, Rr+1
+//   subiw P,  q+2
 def STWPtrRr : Pseudo<(outs),
                       (ins PTRDISPREGS
                        : $ptrreg, DREGS
                        : $reg),
                       "stw\t$ptrreg, $reg", [(store i16
                                               : $reg, i16
                                               : $ptrreg)]>,
                Requires<[HasSRAM]>;

 // displacement of q. Does not modify P.
 def STDPtrQRr : FSTDLDD<1, (outs),
                         (ins memri
                          : $memri, GPR8
                          : $reg),
                         "std\t$memri, $reg", [(store i8
                                                : $reg, addr
                                                : $memri)]>,
-                Requires<[HasSRAM]>;
+                Requires<[HasSRAM, HasNonTinyEncoding]>;
 
 // STDW P+q, Rr+1:Rr
 // Stores the value of Rr into the location addressed by pointer P with a
 // displacement of q. Does not modify P.
 //
 // Expands to:
-// std P+q,   Rr
-// std P+q+1, Rr+1
+//   std P+q,   Rr
+//   std P+q+1, Rr+1
+// On reduced tiny cores, this instruction expands to:
+//   subiw P,  -q
+//   st    P+, Rr
+//   st    P+, Rr+1
+//   subiw P,  q+2
 def STDWPtrQRr : Pseudo<(outs),
                         (ins memri
                          : $memri, DREGS
                          : $src),
                         "stdw\t$memri, $src", [(store i16
                                                 : $src, addr
                                                 : $memri)]>,
                  Requires<[HasSRAM]>;

 
 // These patterns convert add (x, -imm) to sub (x, imm) since we dont have
 // any add with imm instructions. Also take care of the adiw/sbiw instructions.
 def : Pat<(add i16
            : $src1, imm0_63_neg
            : $src2),
           (SBIWRdK i16
            : $src1, (imm0_63_neg
-                     : $src2))>;
+                     : $src2))>,
+          Requires<[HasADDSUBIW]>;
 def : Pat<(add i16
            : $src1, imm
            : $src2),
           (SUBIWRdK i16
            : $src1, (imm16_neg_XFORM imm
                      : $src2))>;
 def : Pat<(addc i16
            : $src1, imm

 // GlobalAddress
 def : Pat<(i16(AVRWrapper tglobaladdr : $dst)), (LDIWRdK tglobaladdr : $dst)>;
 def : Pat<(add i16
            : $src, (AVRWrapper tglobaladdr
                     : $src2)),
           (SUBIWRdK i16
            : $src, tglobaladdr
            : $src2)>;
-def : Pat<(i8(load(AVRWrapper tglobaladdr
-                   : $dst))),
-          (LDSRdK tglobaladdr
-           : $dst)>;
-def : Pat<(i16(load(AVRWrapper tglobaladdr
-                    : $dst))),
-          (LDSWRdK tglobaladdr
-           : $dst)>;
-def : Pat<(store i8
-           : $src, (i16(AVRWrapper tglobaladdr
-                        : $dst))),
-          (STSKRr tglobaladdr
-           : $dst, i8
-           : $src)>;
-def : Pat<(store i16
-           : $src, (i16(AVRWrapper tglobaladdr
-                        : $dst))),
-          (STSWKRr tglobaladdr
-           : $dst, i16
-           : $src)>;
+def : Pat<(i8(load(AVRWrapper tglobaladdr:$dst))),
+          (LDSRdK tglobaladdr:$dst)>,
+          Requires<[HasSRAM, HasNonTinyEncoding]>;
+def : Pat<(i16(load(AVRWrapper tglobaladdr:$dst))),
+          (LDSWRdK tglobaladdr:$dst)>,
+          Requires<[HasSRAM, HasNonTinyEncoding]>;
+def : Pat<(store i8:$src, (i16(AVRWrapper tglobaladdr:$dst))),
+          (STSKRr tglobaladdr:$dst, i8:$src)>,
+          Requires<[HasSRAM, HasNonTinyEncoding]>;
+def : Pat<(store i16:$src, (i16(AVRWrapper tglobaladdr:$dst))),
+          (STSWKRr tglobaladdr:$dst, i16:$src)>,
+          Requires<[HasSRAM, HasNonTinyEncoding]>;
 
 // BlockAddress
 def : Pat<(i16(AVRWrapper tblockaddress
                : $dst)),
           (LDIWRdK tblockaddress
            : $dst)>;
 
 def : Pat<(i8(trunc(AVRlsrwn DLDREGS

llvm/lib/Target/AVR/AVRRegisterInfo.cpp

bool AVRRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
   Offset += MFI.getStackSize() - TFI->getOffsetOfLocalArea() + 1;
   // Fold incoming offset.
   Offset += MI.getOperand(FIOperandNum + 1).getImm();
 
   // This is actually "load effective address" of the stack slot
   // instruction. We have only two-address instructions, thus we need to
   // expand it into move + add.
   if (MI.getOpcode() == AVR::FRMIDX) {
-    MI.setDesc(TII.get(AVR::MOVWRdRr));
-    MI.getOperand(FIOperandNum).ChangeToRegister(AVR::R29R28, false);
-    MI.removeOperand(2);
+    Register DstReg = MI.getOperand(0).getReg();
+    assert(DstReg != AVR::R29R28 && "Dest reg cannot be the frame pointer");
+
+    // Copy the frame pointer.
+    if (STI.hasMOVW()) {
+      BuildMI(MBB, MI, dl, TII.get(AVR::MOVWRdRr), DstReg)
+          .addReg(AVR::R29R28);
+    } else {
+      Register DstLoReg, DstHiReg;
+      splitReg(DstReg, DstLoReg, DstHiReg);
+      BuildMI(MBB, MI, dl, TII.get(AVR::MOVRdRr), DstLoReg)
+          .addReg(AVR::R28);
+      BuildMI(MBB, MI, dl, TII.get(AVR::MOVRdRr), DstHiReg)
+          .addReg(AVR::R29);
+    }
 
     assert(Offset > 0 && "Invalid offset");
 
     // We need to materialize the offset via an add instruction.
     unsigned Opcode;
-    Register DstReg = MI.getOperand(0).getReg();
-    assert(DstReg != AVR::R29R28 && "Dest reg cannot be the frame pointer");
 
-    II++; // Skip over the FRMIDX (and now MOVW) instruction.
+    II++; // Skip over the FRMIDX instruction.
 
     // Generally, to load a frame address two add instructions are emitted that
     // could get folded into a single one:
     //  movw    r31:r30, r29:r28
     //  adiw    r31:r30, 29
     //  adiw    r31:r30, 16
     // to:
     //  movw    r31:r30, r29:r28
     //  adiw    r31:r30, 45
     if (II != MBB.end())
       foldFrameOffset(II, Offset, DstReg);
 
     // Select the best opcode based on DstReg and the offset size.
     switch (DstReg) {
     case AVR::R25R24:
     case AVR::R27R26:
     case AVR::R31R30: {
-      if (isUInt<6>(Offset)) {
+      if (isUInt<6>(Offset) && STI.hasADDSUBIW()) {
         Opcode = AVR::ADIWRdK;
         break;
       }
       [[fallthrough]];
     }
     default: {
       // This opcode will get expanded into a pair of subi/sbci.
       Opcode = AVR::SUBIWRdK;
       Offset = -Offset;
       break;
     }
     }
 
     MachineInstr *New = BuildMI(MBB, II, dl, TII.get(Opcode), DstReg)
                             .addReg(DstReg, RegState::Kill)
                             .addImm(Offset);
     New->getOperand(3).setIsDead();
 
+    MI.eraseFromParent(); // remove FRMIDX
+
     return false;
   }
 
+  // On most AVRs, we can use an offset up to 62 for load/store with
+  // displacement (63 for byte values, 62 for word values). However, the
+  // "reduced tiny" cores don't support load/store with displacement. So for
+  // them, we force an offset of 0 meaning that any positive offset will require
+  // adjusting the frame pointer.
+  int MaxOffset = STI.hasTinyEncoding() ? 0 : 62;
+
   // If the offset is too big we have to adjust and restore the frame pointer
   // to materialize a valid load/store with displacement.
   //: TODO: consider using only one adiw/sbiw chain for more than one frame
   //: index
-  if (Offset > 62) {
+  if (Offset > MaxOffset) {
     unsigned AddOpc = AVR::ADIWRdK, SubOpc = AVR::SBIWRdK;
-    int AddOffset = Offset - 63 + 1;
+    int AddOffset = Offset - MaxOffset;
 
     // For huge offsets where adiw/sbiw cannot be used use a pair of subi/sbci.
-    if ((Offset - 63 + 1) > 63) {
+    if ((Offset - MaxOffset) > 63 || !STI.hasADDSUBIW()) {
       AddOpc = AVR::SUBIWRdK;
       SubOpc = AVR::SUBIWRdK;
       AddOffset = -AddOffset;
     }
 
     // It is possible that the spiller places this frame instruction in between
     // a compare and branch, invalidating the contents of SREG set by the
     // compare instruction because of the add/sub pairs. Conservatively save and
if (Offset > MaxOffset) {
     BuildMI(MBB, std::next(II), dl, TII.get(AVR::OUTARr))
         .addImm(STI.getIORegSREG())
         .addReg(STI.getTmpRegister(), RegState::Kill);
 
     // No need to set SREG as dead here otherwise if the next instruction is a
     // cond branch it will be using a dead register.
     BuildMI(MBB, std::next(II), dl, TII.get(SubOpc), AVR::R29R28)
         .addReg(AVR::R29R28, RegState::Kill)
-        .addImm(Offset - 63 + 1);
+        .addImm(Offset - MaxOffset);
 
-    Offset = 62;
+    Offset = MaxOffset;
   }
 
   MI.getOperand(FIOperandNum).ChangeToRegister(AVR::R29R28, false);
   assert(isUInt<6>(Offset) && "Offset is out of range");
   MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
   return false;
 }
 

llvm/test/CodeGen/AVR/calling-conv/c/tiny.ll

 ; CHECK-NEXT:    ret
   %d = sub i16 %a, %b
   %e = sub i16 %c, %d
   ret i16 %e
 }
 
 ; NOTE:  %a(i16), %b(i16) and %c(i16) each costs two registers,
 ;        while %d(i16) is passed via the stack.
-; FIXME: The `ldd` instruction is invalid on avrtiny, this test just shows
-;        how arguments are passed.
 define i16 @foo3(i16 %a, i16 %b, i16 %c, i16 %d) {
 ; CHECK-LABEL: foo3:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    push r28
 ; CHECK-NEXT:    push r29
 ; CHECK-NEXT:    in r28, 61
 ; CHECK-NEXT:    in r29, 62
-; CHECK-NEXT:    ldd r30, Y+5
-; CHECK-NEXT:    ldd r31, Y+6
+; CHECK-NEXT:    in r16, 63
+; CHECK-NEXT:    subi r28, 251
+; CHECK-NEXT:    sbci r29, 255
+; CHECK-NEXT:    ld r30, Y+
+; CHECK-NEXT:    ld r31, Y+
+; CHECK-NEXT:    subi r28, 2
+; CHECK-NEXT:    sbci r29, 0
+; CHECK-NEXT:    subi r28, 5
+; CHECK-NEXT:    sbci r29, 0
+; CHECK-NEXT:    out 63, r16
 ; CHECK-NEXT:    sub r20, r30
 ; CHECK-NEXT:    sbc r21, r31
 ; CHECK-NEXT:    sub r24, r22
 ; CHECK-NEXT:    sbc r25, r23
 ; CHECK-NEXT:    add r24, r20
 ; CHECK-NEXT:    adc r25, r21
 ; CHECK-NEXT:    pop r29
 ; CHECK-NEXT:    pop r28
 ; CHECK-NEXT:    ret
   %e = sub i16 %a, %b
   %g = sub i16 %c, %d
   %h = add i16 %e, %g
   ret i16 %h
 }
 
 ; NOTE: %a(i32) costs four registers, while %b(i32) is passed via the stack.
-; FIXME: The `ldd` instruction is invalid on avrtiny, this test just shows
-;        how arguments are passed.
 define i32 @foo4(i32 %a, i32 %b) {
 ; CHECK-LABEL: foo4:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    push r28
 ; CHECK-NEXT:    push r29
 ; CHECK-NEXT:    in r28, 61
 ; CHECK-NEXT:    in r29, 62
-; CHECK-NEXT:    ldd r20, Y+5
-; CHECK-NEXT:    ldd r21, Y+6
-; CHECK-NEXT:    ldd r30, Y+7
-; CHECK-NEXT:    ldd r31, Y+8
+; CHECK-NEXT:    in r16, 63
+; CHECK-NEXT:    subi r28, 251
+; CHECK-NEXT:    sbci r29, 255
+; CHECK-NEXT:    ld r20, Y+
+; CHECK-NEXT:    ld r21, Y+
+; CHECK-NEXT:    subi r28, 2
+; CHECK-NEXT:    sbci r29, 0
+; CHECK-NEXT:    subi r28, 5
+; CHECK-NEXT:    sbci r29, 0
+; CHECK-NEXT:    out 63, r16
+; CHECK-NEXT:    in r16, 63
+; CHECK-NEXT:    subi r28, 249
+; CHECK-NEXT:    sbci r29, 255
+; CHECK-NEXT:    ld r30, Y+
+; CHECK-NEXT:    ld r31, Y+
+; CHECK-NEXT:    subi r28, 2
+; CHECK-NEXT:    sbci r29, 0
+; CHECK-NEXT:    subi r28, 7
+; CHECK-NEXT:    sbci r29, 0
+; CHECK-NEXT:    out 63, r16
 ; CHECK-NEXT:    sub r20, r22
 ; CHECK-NEXT:    sbc r21, r23
 ; CHECK-NEXT:    sbc r30, r24
 ; CHECK-NEXT:    sbc r31, r25
 ; CHECK-NEXT:    mov r22, r20
 ; CHECK-NEXT:    mov r23, r21
 ; CHECK-NEXT:    mov r24, r30
 ; CHECK-NEXT:    mov r25, r31
 ; CHECK-NEXT:    pop r29
 ; CHECK-NEXT:    pop r28
 ; CHECK-NEXT:    ret
   %c = sub i32 %b, %a
   ret i32 %c
 }
 
 ; NOTE: %0 costs six registers, while %1 is passed via the stack.
-; FIXME: The `ldd` instruction is invalid on avrtiny, this test just shows
-;        how arguments are passed.
 define i8 @foo5([5 x i8] %0, i8 %1) {
 ; CHECK-LABEL: foo5:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    push r28
 ; CHECK-NEXT:    push r29
 ; CHECK-NEXT:    in r28, 61
 ; CHECK-NEXT:    in r29, 62
-; CHECK-NEXT:    ldd r24, Y+5
+; CHECK-NEXT:    mov r26, r28
+; CHECK-NEXT:    mov r27, r29
+; CHECK-NEXT:    subi r26, 251
+; CHECK-NEXT:    sbci r27, 255
+; CHECK-NEXT:    ld r24, X
 ; CHECK-NEXT:    add r24, r20
 ; CHECK-NEXT:    pop r29
 ; CHECK-NEXT:    pop r28
 ; CHECK-NEXT:    ret
   %3 = extractvalue [5 x i8] %0, 0
   %4 = add i8 %3, %1
   ret i8 %4
 }
 
 ; NOTE: %0 costs two registers and %1 costs four registers.
 define i8 @foo6([2 x i8] %0, [4 x i8] %1) {
 ; CHECK-LABEL: foo6:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    add r24, r20
 ; CHECK-NEXT:    ret
   %3 = extractvalue [2 x i8] %0, 0
   %4 = extractvalue [4 x i8] %1, 0
   %5 = add i8 %3, %4
   ret i8 %5
 }
 
 ; NOTE: %0 cost four registers, while %1 is passed via the stack,
 ;       though there are two vacant registers.
-; FIXME: The `ldd` instruction is invalid on avrtiny, this test just shows
-;        how arguments are passed.
 define i8 @foo7([3 x i8] %0, [3 x i8] %1) {
 ; CHECK-LABEL: foo7:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    push r28
 ; CHECK-NEXT:    push r29
 ; CHECK-NEXT:    in r28, 61
 ; CHECK-NEXT:    in r29, 62
-; CHECK-NEXT:    ldd r24, Y+5
+; CHECK-NEXT:    mov r26, r28
+; CHECK-NEXT:    mov r27, r29
+; CHECK-NEXT:    subi r26, 251
+; CHECK-NEXT:    sbci r27, 255
+; CHECK-NEXT:    ld r24, X
 ; CHECK-NEXT:    add r24, r22
 ; CHECK-NEXT:    pop r29
 ; CHECK-NEXT:    pop r28
 ; CHECK-NEXT:    ret
   %3 = extractvalue [3 x i8] %0, 0
   %4 = extractvalue [3 x i8] %1, 0
   %5 = add i8 %3, %4
   ret i8 %5
 }
 
 ; NOTE: %0 costs four registers, and %1 costs two registers, while %2 is
 ;       passed via the stack, though there is one vacant register.
-; FIXME: The `ldd` instruction is invalid on avrtiny, this test just shows
-;        how arguments are passed.
 define i8 @foo8([3 x i8] %0, i8 %1, i8 %2) {
 ; CHECK-LABEL: foo8:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    push r28
 ; CHECK-NEXT:    push r29
 ; CHECK-NEXT:    in r28, 61
 ; CHECK-NEXT:    in r29, 62
 ; CHECK-NEXT:    add r22, r20
-; CHECK-NEXT:    ldd r24, Y+5
+; CHECK-NEXT:    mov r26, r28
+; CHECK-NEXT:    mov r27, r29
+; CHECK-NEXT:    subi r26, 251
+; CHECK-NEXT:    sbci r27, 255
+; CHECK-NEXT:    ld r24, X
 ; CHECK-NEXT:    sub r24, r22
 ; CHECK-NEXT:    pop r29
 ; CHECK-NEXT:    pop r28
 ; CHECK-NEXT:    ret
   %4 = extractvalue [3 x i8] %0, 0
   %5 = add i8 %4, %1
   %6 = sub i8 %2, %5
   ret i8 %6
 }
 
 ; NOTE: %0 is passed via registers, though there are 6 vacant registers.
-; FIXME: The `ldd` instruction is invalid on avrtiny, this test just shows
-;        how arguments are passed.
 define i8 @foo9([7 x i8] %0) {
 ; CHECK-LABEL: foo9:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    push r28
 ; CHECK-NEXT:    push r29
 ; CHECK-NEXT:    in r28, 61
 ; CHECK-NEXT:    in r29, 62
-; CHECK-NEXT:    ldd r25, Y+6
-; CHECK-NEXT:    ldd r24, Y+5
+; CHECK-NEXT:    mov r26, r28
+; CHECK-NEXT:    mov r27, r29
+; CHECK-NEXT:    subi r26, 250
+; CHECK-NEXT:    sbci r27, 255
+; CHECK-NEXT:    ld r25, X
+; CHECK-NEXT:    mov r26, r28
+; CHECK-NEXT:    mov r27, r29
+; CHECK-NEXT:    subi r26, 251
+; CHECK-NEXT:    sbci r27, 255
+; CHECK-NEXT:    ld r24, X
 ; CHECK-NEXT:    add r24, r25
 ; CHECK-NEXT:    pop r29
 ; CHECK-NEXT:    pop r28
 ; CHECK-NEXT:    ret
   %2 = extractvalue [7 x i8] %0, 0
   %3 = extractvalue [7 x i8] %0, 1
   %4 = add i8 %2, %3
   ret i8 %4
 }
 
 ; NOTE: %0 costs six registers, while %1 and %2 are passed via the stack.
-; FIXME: The `ldd` instruction is invalid on avrtiny, this test just shows
-;        how arguments are passed.
 define i8 @fooa([6 x i8] %0, i8 %1, i8 %2) {
 ; CHECK-LABEL: fooa:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    push r28
 ; CHECK-NEXT:    push r29
 ; CHECK-NEXT:    in r28, 61
 ; CHECK-NEXT:    in r29, 62
-; CHECK-NEXT:    ldd r25, Y+5
-; CHECK-NEXT:    ldd r24, Y+6
+; CHECK-NEXT:    mov r26, r28
+; CHECK-NEXT:    mov r27, r29
+; CHECK-NEXT:    subi r26, 251
+; CHECK-NEXT:    sbci r27, 255
+; CHECK-NEXT:    ld r25, X
+; CHECK-NEXT:    mov r26, r28
+; CHECK-NEXT:    mov r27, r29
+; CHECK-NEXT:    subi r26, 250
+; CHECK-NEXT:    sbci r27, 255
+; CHECK-NEXT:    ld r24, X
 ; CHECK-NEXT:    sub r24, r25
 ; CHECK-NEXT:    sub r24, r20
 ; CHECK-NEXT:    pop r29
 ; CHECK-NEXT:    pop r28
 ; CHECK-NEXT:    ret
   %4 = extractvalue [6 x i8] %0, 0
   %5 = sub i8 %2, %1
   %6 = sub i8 %5, %4
   ret i8 %6
 }

llvm/test/CodeGen/AVR/directmem.ll

 ; RUN: llc -mattr=sram,addsubiw < %s -march=avr | FileCheck %s
+; RUN: llc -mattr=sram,avrtiny < %s -march=avr | FileCheck %s --check-prefix=CHECK-TINY
 
 @char = common global i8 0
 @char.array = common global [3 x i8] zeroinitializer
 @char.static = internal global i8 0
 
 @int = common global i16 0
 @int.array = common global [3 x i16] zeroinitializer
 @int.static = internal global i16 0
 
 @long = common global i32 0
 @long.array = common global [3 x i32] zeroinitializer
 @long.static = internal global i32 0
 
 @longlong = common global i64 0
 @longlong.array = common global [3 x i64] zeroinitializer
 @longlong.static = internal global i64 0
 
 define void @global8_store() {
 ; CHECK-LABEL: global8_store:
 ; CHECK: ldi [[REG:r[0-9]+]], 6
 ; CHECK: sts char, [[REG]]
+; CHECK-TINY-LABEL: global8_store:
+; CHECK-TINY: ldi [[REG1:r[0-9]+]], 6
+; CHECK-TINY: ldi [[REG2:r[0-9]+]], lo8(char)
+; CHECK-TINY: ldi [[REG3:r[0-9]+]], hi8(char)
+; CHECK-TINY: st [[REG4:[X-Z]]], [[REG1]]
   store i8 6, i8* @char
   ret void
 }
 
 define i8 @global8_load() {
 ; CHECK-LABEL: global8_load:
 ; CHECK: lds r24, char
+; CHECK-TINY-LABEL: global8_load:
+; CHECK-TINY: ldi [[REG1:r[0-9]+]], lo8(char)
+; CHECK-TINY: ldi [[REG2:r[0-9]+]], hi8(char)
+; CHECK-TINY: ld [[REG3:r[0-9]+]], [[REG4:[X-Z]]]
   %result = load i8, i8* @char
   ret i8 %result
 }
 
 define void @array8_store() {
 ; CHECK-LABEL: array8_store:
 ; CHECK: ldi [[REG1:r[0-9]+]], 3
 ; CHECK: sts char.array+2, [[REG1]]

llvm/test/CodeGen/AVR/pseudo/LDDWRdPtrQ.mir

-# RUN: llc -O0  %s -o - -march=avr | FileCheck %s
+# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s
+# RUN: llc -O0 -run-pass=avr-expand-pseudo -mattr=avrtiny %s -o - | FileCheck %s --check-prefix=CHECK-TINY
 
 # This test checks the expansion of the 16-bit 'LDDWRdPtrQ' pseudo instruction.
 
 --- |
   target triple = "avr--"
   define void @test_lddwrdptrq() {
   entry:
     ret void
   }
 ...
 
 ---
 name:            test_lddwrdptrq
 tracksRegLiveness: true
 body: |
   bb.0.entry:
     liveins: $r31r30
 
     ; CHECK-LABEL: test_lddwrdptrq
 
-    ; CHECK:      ldd     r24, Z+10
-    ; CHECK-NEXT: ldd     r25, Z+11
+    ; CHECK:      $r24 = LDDRdPtrQ $r31r30, 10
+    ; CHECK-NEXT: $r25 = LDDRdPtrQ $r31r30, 11
+
+    ; CHECK-TINY:      $r30 = SUBIRdK $r30, 246, implicit-def $sreg
+    ; CHECK-TINY-NEXT: $r31 = SBCIRdK $r31, 255, implicit-def $sreg, implicit killed $sreg
+    ; CHECK-TINY-NEXT: $r24, $r31r30 = LDRdPtrPi killed $r31r30
+    ; CHECK-TINY-NEXT: $r25, $r31r30 = LDRdPtrPi killed $r31r30
+    ; CHECK-TINY-NEXT: $r30 = SUBIRdK $r30, 12, implicit-def $sreg
+    ; CHECK-TINY-NEXT: $r31 = SBCIRdK $r31, 0, implicit-def $sreg, implicit killed $sreg
 
     early-clobber $r25r24 = LDDWRdPtrQ undef $r31r30, 10
 ...

llvm/test/CodeGen/AVR/pseudo/LDWRdPtr.mir

 # RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s
+# RUN: llc -O0 -run-pass=avr-expand-pseudo -mattr=avrtiny %s -o - | FileCheck %s --check-prefix=CHECK-TINY
 
 # This test checks the expansion of the 16-bit LDWRdPtr pseudo instruction.
 
 --- |
   target triple = "avr--"
   define void @test_ldwrdptr() {
   entry:
     ret void
   }
 ...
 
 ---
 name:            test_ldwrdptr
 body: |
   bb.0.entry:
     liveins: $r31r30
 
     ; CHECK-LABEL: test_ldwrdptr
 
     ; CHECK:               $r0 = LDRdPtr $r31r30
     ; CHECK-NEXT:          $r1 = LDDRdPtrQ $r31r30, 1
 
+    ; CHECK-TINY:      $r0, $r31r30 = LDRdPtrPi killed $r31r30
+    ; CHECK-TINY-NEXT: $r1, $r31r30 = LDRdPtrPi killed $r31r30
+    ; CHECK-TINY-NEXT: $r30 = SUBIRdK $r30, 2, implicit-def $sreg
+    ; CHECK-TINY-NEXT: $r31 = SBCIRdK $r31, 0, implicit-def $sreg, implicit killed $sreg
+
     $r1r0 = LDWRdPtr $r31r30
 ...

llvm/test/CodeGen/AVR/pseudo/STDWPtrQRr.mir

 # RUN: llc -O0 -run-pass=avr-expand-pseudo -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -O0 -run-pass=avr-expand-pseudo -verify-machineinstrs -mattr=avrtiny %s -o - | FileCheck %s --check-prefix=CHECK-TINY
 
 --- |
   target triple = "avr--"
   define void @test() {
   entry:
     ret void
   }
 ...
 
 ---
 name:            test
 body: |
   bb.0.entry:
 
     ; CHECK-LABEL: test
 
     ; Small displacement (<63):
     ; CHECK:      STDPtrQRr $r29r28, 3, $r0
     ; CHECK-NEXT: STDPtrQRr $r29r28, 4, $r1
+    ; CHECK-TINY:      $r28 = SUBIRdK killed $r28, 253, implicit-def $sreg
+    ; CHECK-TINY-NEXT: $r29 = SBCIRdK killed $r29, 255, implicit-def $sreg, implicit killed $sreg
+    ; CHECK-TINY-NEXT: early-clobber $r29r28 = STPtrPiRr killed $r29r28, $r0, 0
+    ; CHECK-TINY-NEXT: early-clobber $r29r28 = STPtrPiRr killed $r29r28, $r1, 0
+    ; CHECK-TINY-NEXT: $r28 = SUBIRdK killed $r28, 5, implicit-def $sreg
+    ; CHECK-TINY-NEXT: $r29 = SBCIRdK killed $r29, 0, implicit-def $sreg, implicit killed $sreg
     STDWPtrQRr $r29r28, 3, $r1r0
 
     ; Small displacement where the destination register is killed:
     ; CHECK:      STDPtrQRr $r29r28, 3, $r0
     ; CHECK-NEXT: STDPtrQRr killed $r29r28, 4, $r1
     STDWPtrQRr killed $r29r28, 3, $r1r0
 
     ; Small displacement where the source register is killed:
     ; CHECK:      STDPtrQRr $r29r28, 3, killed $r0
     ; CHECK-NEXT: STDPtrQRr $r29r28, 4, killed $r1
     STDWPtrQRr $r29r28, 3, killed $r1r0
 
     ; Small displacement, near the limit (=62):
     ; CHECK:      STDPtrQRr $r29r28, 62, $r0
     ; CHECK-NEXT: STDPtrQRr $r29r28, 63, $r1
     STDWPtrQRr $r29r28, 62, $r1r0
 
     ; Large displacement (>=63):
-    ; CHECK: PUSHRr $r28, implicit-def $sp, implicit $sp
-    ; CHECK-NEXT: PUSHRr $r29, implicit-def $sp, implicit $sp
-    ; CHECK-NEXT: $r28 = SUBIRdK killed $r28, 193, implicit-def $sreg
+    ; CHECK:      $r28 = SUBIRdK killed $r28, 193, implicit-def $sreg
     ; CHECK-NEXT: $r29 = SBCIRdK killed $r29, 255, implicit-def $sreg, implicit killed $sreg
-    ; CHECK-NEXT: STPtrRr $r29r28, $r0
-    ; CHECK-NEXT: STDPtrQRr $r29r28, 1, $r1
-    ; CHECK-NEXT: $r29 = POPRd implicit-def $sp, implicit $sp
-    ; CHECK-NEXT: $r28 = POPRd implicit-def $sp, implicit $sp
+    ; CHECK-NEXT: $r29r28 = STPtrPiRr killed $r29r28, $r0, 0
+    ; CHECK-NEXT: $r29r28 = STPtrPiRr killed $r29r28, $r1, 0
+    ; CHECK-NEXT: $r28 = SUBIRdK killed $r28, 65, implicit-def $sreg
+    ; CHECK-NEXT: $r29 = SBCIRdK killed $r29, 0, implicit-def $sreg, implicit killed $sreg
+    ; CHECK-TINY:      $r28 = SUBIRdK killed $r28, 193, implicit-def $sreg
+    ; CHECK-TINY-NEXT: $r29 = SBCIRdK killed $r29, 255, implicit-def $sreg, implicit killed $sreg
+    ; CHECK-TINY-NEXT: $r29r28 = STPtrPiRr killed $r29r28, $r0, 0
+    ; CHECK-TINY-NEXT: $r29r28 = STPtrPiRr killed $r29r28, $r1, 0
+    ; CHECK-TINY-NEXT: $r28 = SUBIRdK killed $r28, 65, implicit-def $sreg
+    ; CHECK-TINY-NEXT: $r29 = SBCIRdK killed $r29, 0, implicit-def $sreg, implicit killed $sreg
     STDWPtrQRr $r29r28, 63, $r1r0
 
     ; Large displacement where the destination register is killed:
     ; CHECK: $r28 = SUBIRdK killed $r28, 193, implicit-def $sreg
     ; CHECK-NEXT: $r29 = SBCIRdK killed $r29, 255, implicit-def $sreg, implicit killed $sreg
-    ; CHECK-NEXT: STPtrRr $r29r28, $r0
-    ; CHECK-NEXT: STDPtrQRr $r29r28, 1, $r1
+    ; CHECK-NEXT: $r29r28 = STPtrPiRr killed $r29r28, $r0
+    ; CHECK-NEXT: $r29r28 = STPtrPiRr killed $r29r28, $r1
     STDWPtrQRr killed $r29r28, 63, $r1r0
 
     ; Large displacement where the source register is killed:
-    ; CHECK: PUSHRr $r28, implicit-def $sp, implicit $sp
-    ; CHECK-NEXT: PUSHRr $r29, implicit-def $sp, implicit $sp
-    ; CHECK-NEXT: $r28 = SUBIRdK killed $r28, 193, implicit-def $sreg
+    ; CHECK:      $r28 = SUBIRdK killed $r28, 193, implicit-def $sreg
     ; CHECK-NEXT: $r29 = SBCIRdK killed $r29, 255, implicit-def $sreg, implicit killed $sreg
-    ; CHECK-NEXT: STPtrRr $r29r28, killed $r0
-    ; CHECK-NEXT: STDPtrQRr $r29r28, 1, killed $r1
-    ; CHECK-NEXT: $r29 = POPRd implicit-def $sp, implicit $sp
-    ; CHECK-NEXT: $r28 = POPRd implicit-def $sp, implicit $sp
+    ; CHECK-NEXT: STPtrPiRr killed $r29r28, killed $r0, 0
+    ; CHECK-NEXT: STPtrPiRr killed $r29r28, killed $r1, 0
+    ; CHECK-NEXT: $r28 = SUBIRdK killed $r28, 65, implicit-def $sreg
+    ; CHECK-NEXT: $r29 = SBCIRdK killed $r29, 0, implicit-def $sreg, implicit killed $sreg
     STDWPtrQRr $r29r28, 63, killed $r1r0
 ...

llvm/test/CodeGen/AVR/pseudo/STWPtrRr.mir

 # RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s
+# RUN: llc -O0 -run-pass=avr-expand-pseudo -mattr=avrtiny %s -o - | FileCheck %s --check-prefix=CHECK-TINY
 
 # This test checks the expansion of the 16-bit STSWRdK pseudo instruction.
 
 --- |
   target triple = "avr--"
   define void @test_stwptrrr() {
   entry:
     ret void
   }
 ...
 
 ---
 name:            test_stwptrrr
 body: |
   bb.0.entry:
     liveins: $r31r30, $r17r16
 
     ; CHECK-LABEL: test_stwptrrr
 
     ; CHECK:      STPtrRr $r31r30, $r16
     ; CHECK-NEXT: STDPtrQRr $r31r30, 1, $r17
 
+    ; CHECK-TINY:      $r31r30 = STPtrPiRr killed $r31r30, $r16, 0
+    ; CHECK-TINY-NEXT: $r31r30 = STPtrPiRr killed $r31r30, $r17, 0
+    ; CHECK-TINY-NEXT: $r30 = SUBIRdK killed $r30, 2, implicit-def $sreg
+    ; CHECK-TINY-NEXT: $r31 = SBCIRdK killed $r31, 0, implicit-def $sreg, implicit killed $sreg
+
     STWPtrRr $r31r30, $r17r16
 ...

llvm/test/CodeGen/AVR/return.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mattr=avr6,sram -mtriple=avr < %s | FileCheck %s --check-prefix=AVR
-; RUN: llc -mattr=tinyencoding -mtriple=avr < %s | FileCheck %s --check-prefix=TINY
+; RUN: llc -mcpu=attiny10 -mtriple=avr < %s | FileCheck %s --check-prefix=TINY
 
 ;TODO: test returning byval structs
 ; TODO: test naked functions
 
 define void @return_void() {
 ; AVR-LABEL: return_void:
 ; AVR:       ; %bb.0:
 ; AVR-NEXT:    ret

 ; AVR-NEXT:    ret
 ;
 ; TINY-LABEL: return32_arg2:
 ; TINY:       ; %bb.0:
 ; TINY-NEXT:    push r28
 ; TINY-NEXT:    push r29
 ; TINY-NEXT:    in r28, 61
 ; TINY-NEXT:    in r29, 62
-; TINY-NEXT:    ldd r22, Y+9
-; TINY-NEXT:    ldd r23, Y+10
-; TINY-NEXT:    ldd r24, Y+11
-; TINY-NEXT:    ldd r25, Y+12
+; TINY-NEXT:    in r16, 63
+; TINY-NEXT:    subi r28, 247
+; TINY-NEXT:    sbci r29, 255
+; TINY-NEXT:    ld r22, Y+
+; TINY-NEXT:    ld r23, Y+
+; TINY-NEXT:    subi r28, 2
+; TINY-NEXT:    sbci r29, 0
+; TINY-NEXT:    subi r28, 9
+; TINY-NEXT:    sbci r29, 0
+; TINY-NEXT:    out 63, r16
+; TINY-NEXT:    in r16, 63
+; TINY-NEXT:    subi r28, 245
+; TINY-NEXT:    sbci r29, 255
+; TINY-NEXT:    ld r24, Y+
+; TINY-NEXT:    ld r25, Y+
+; TINY-NEXT:    subi r28, 2
+; TINY-NEXT:    sbci r29, 0
+; TINY-NEXT:    subi r28, 11
+; TINY-NEXT:    sbci r29, 0
+; TINY-NEXT:    out 63, r16
 ; TINY-NEXT:    pop r29
 ; TINY-NEXT:    pop r28
 ; TINY-NEXT:    ret
     ret i32 %z
 }
 
 define i64 @return64_imm() {
 ; AVR-LABEL: return64_imm:

 ; AVR-NEXT:    ret
 ;
 ; TINY-LABEL: return64_imm:
 ; TINY:       ; %bb.0:
 ; TINY-NEXT:    ldi r20, 236
 ; TINY-NEXT:    ldi r21, 190
 ; TINY-NEXT:    mov r30, r24
 ; TINY-NEXT:    mov r31, r25
-; TINY-NEXT:    std Z+6, r20
-; TINY-NEXT:    std Z+7, r21
+; TINY-NEXT:    subi r30, 250
+; TINY-NEXT:    sbci r31, 255
+; TINY-NEXT:    st Z+, r20
+; TINY-NEXT:    st Z+, r21
+; TINY-NEXT:    subi r30, 8
+; TINY-NEXT:    sbci r31, 0
 ; TINY-NEXT:    ldi r24, 25
 ; TINY-NEXT:    ldi r25, 22
-; TINY-NEXT:    std Z+4, r24
-; TINY-NEXT:    std Z+5, r25
+; TINY-NEXT:    subi r30, 252
+; TINY-NEXT:    sbci r31, 255
+; TINY-NEXT:    st Z+, r24
+; TINY-NEXT:    st Z+, r25
+; TINY-NEXT:    subi r30, 6
+; TINY-NEXT:    sbci r31, 0
 ; TINY-NEXT:    ldi r24, 104
 ; TINY-NEXT:    ldi r25, 37
-; TINY-NEXT:    std Z+2, r24
-; TINY-NEXT:    std Z+3, r25
+; TINY-NEXT:    subi r30, 254
+; TINY-NEXT:    sbci r31, 255
+; TINY-NEXT:    st Z+, r24
+; TINY-NEXT:    st Z+, r25
+; TINY-NEXT:    subi r30, 4
+; TINY-NEXT:    sbci r31, 0
 ; TINY-NEXT:    ldi r24, 204
 ; TINY-NEXT:    ldi r25, 204
-; TINY-NEXT:    st Z, r24
-; TINY-NEXT:    std Z+1, r25
+; TINY-NEXT:    st Z+, r24
+; TINY-NEXT:    st Z+, r25
 ; TINY-NEXT:    ret
     ret i64 13757395258967641292
 }
 
 define i64 @return64_arg(i64 %x) {
 ; AVR-LABEL: return64_arg:
 ; AVR:       ; %bb.0:
 ; AVR-NEXT:    ret
 ;
 ; TINY-LABEL: return64_arg:
 ; TINY:       ; %bb.0:
 ; TINY-NEXT:    push r28
 ; TINY-NEXT:    push r29
 ; TINY-NEXT:    in r28, 61
 ; TINY-NEXT:    in r29, 62
-; TINY-NEXT:    ldd r20, Y+11
-; TINY-NEXT:    ldd r21, Y+12
+; TINY-NEXT:    in r16, 63
+; TINY-NEXT:    subi r28, 245
+; TINY-NEXT:    sbci r29, 255
+; TINY-NEXT:    ld r20, Y+
+; TINY-NEXT:    ld r21, Y+
+; TINY-NEXT:    subi r28, 2
+; TINY-NEXT:    sbci r29, 0
+; TINY-NEXT:    subi r28, 11
+; TINY-NEXT:    sbci r29, 0
+; TINY-NEXT:    out 63, r16
 ; TINY-NEXT:    mov r30, r24
 ; TINY-NEXT:    mov r31, r25
-; TINY-NEXT:    std Z+6, r20
-; TINY-NEXT:    std Z+7, r21
-; TINY-NEXT:    ldd r24, Y+9
-; TINY-NEXT:    ldd r25, Y+10
-; TINY-NEXT:    std Z+4, r24
-; TINY-NEXT:    std Z+5, r25
-; TINY-NEXT:    ldd r24, Y+7
-; TINY-NEXT:    ldd r25, Y+8
-; TINY-NEXT:    std Z+2, r24
-; TINY-NEXT:    std Z+3, r25
-; TINY-NEXT:    ldd r24, Y+5
-; TINY-NEXT:    ldd r25, Y+6
-; TINY-NEXT:    st Z, r24
-; TINY-NEXT:    std Z+1, r25
+; TINY-NEXT:    subi r30, 250
+; TINY-NEXT:    sbci r31, 255
+; TINY-NEXT:    st Z+, r20
+; TINY-NEXT:    st Z+, r21
+; TINY-NEXT:    subi r30, 8
+; TINY-NEXT:    sbci r31, 0
+; TINY-NEXT:    in r16, 63
+; TINY-NEXT:    subi r28, 247
+; TINY-NEXT:    sbci r29, 255
+; TINY-NEXT:    ld r24, Y+
+; TINY-NEXT:    ld r25, Y+
+; TINY-NEXT:    subi r28, 2
+; TINY-NEXT:    sbci r29, 0
+; TINY-NEXT:    subi r28, 9
+; TINY-NEXT:    sbci r29, 0
+; TINY-NEXT:    out 63, r16
+; TINY-NEXT:    subi r30, 252
+; TINY-NEXT:    sbci r31, 255
+; TINY-NEXT:    st Z+, r24
+; TINY-NEXT:    st Z+, r25
+; TINY-NEXT:    subi r30, 6
+; TINY-NEXT:    sbci r31, 0
+; TINY-NEXT:    in r16, 63
+; TINY-NEXT:    subi r28, 249
+; TINY-NEXT:    sbci r29, 255
+; TINY-NEXT:    ld r24, Y+
+; TINY-NEXT:    ld r25, Y+
+; TINY-NEXT:    subi r28, 2
+; TINY-NEXT:    sbci r29, 0
+; TINY-NEXT:    subi r28, 7
+; TINY-NEXT:    sbci r29, 0
+; TINY-NEXT:    out 63, r16
+; TINY-NEXT:    subi r30, 254
+; TINY-NEXT:    sbci r31, 255
+; TINY-NEXT:    st Z+, r24
+; TINY-NEXT:    st Z+, r25
+; TINY-NEXT:    subi r30, 4
+; TINY-NEXT:    sbci r31, 0
+; TINY-NEXT:    in r16, 63
+; TINY-NEXT:    subi r28, 251
+; TINY-NEXT:    sbci r29, 255
+; TINY-NEXT:    ld r24, Y+
+; TINY-NEXT:    ld r25, Y+
+; TINY-NEXT:    subi r28, 2
+; TINY-NEXT:    sbci r29, 0
+; TINY-NEXT:    subi r28, 5
+; TINY-NEXT:    sbci r29, 0
+; TINY-NEXT:    out 63, r16
+; TINY-NEXT:    st Z+, r24
+; TINY-NEXT:    st Z+, r25
 ; TINY-NEXT:    pop r29
 ; TINY-NEXT:    pop r28
 ; TINY-NEXT:    ret
     ret i64 %x
 }
 
 define i64 @return64_arg2(i64 %x, i64 %y, i64 %z) {
 ; AVR-LABEL: return64_arg2:

 ; AVR-NEXT:    ret
 ;
 ; TINY-LABEL: return64_arg2:
 ; TINY:       ; %bb.0:
 ; TINY-NEXT:    push r28
 ; TINY-NEXT:    push r29
 ; TINY-NEXT:    in r28, 61
 ; TINY-NEXT:    in r29, 62
-; TINY-NEXT:    ldd r20, Y+27
-; TINY-NEXT:    ldd r21, Y+28
+; TINY-NEXT:    in r16, 63
+; TINY-NEXT:    subi r28, 229
+; TINY-NEXT:    sbci r29, 255
+; TINY-NEXT:    ld r20, Y+
+; TINY-NEXT:    ld r21, Y+
+; TINY-NEXT:    subi r28, 2
+; TINY-NEXT:    sbci r29, 0
+; TINY-NEXT:    subi r28, 27
+; TINY-NEXT:    sbci r29, 0
+; TINY-NEXT:    out 63, r16
 ; TINY-NEXT:    mov r30, r24
 ; TINY-NEXT:    mov r31, r25
-; TINY-NEXT:    std Z+6, r20
-; TINY-NEXT:    std Z+7, r21
-; TINY-NEXT:    ldd r24, Y+25
-; TINY-NEXT:    ldd r25, Y+26
-; TINY-NEXT:    std Z+4, r24
-; TINY-NEXT:    std Z+5, r25
-; TINY-NEXT:    ldd r24, Y+23
-; TINY-NEXT:    ldd r25, Y+24
-; TINY-NEXT:    std Z+2, r24
-; TINY-NEXT:    std Z+3, r25
-; TINY-NEXT:    ldd r24, Y+21
-; TINY-NEXT:    ldd r25, Y+22
-; TINY-NEXT:    st Z, r24
-; TINY-NEXT:    std Z+1, r25
+; TINY-NEXT:    subi r30, 250
+; TINY-NEXT:    sbci r31, 255
+; TINY-NEXT:    st Z+, r20
+; TINY-NEXT:    st Z+, r21
+; TINY-NEXT:    subi r30, 8
+; TINY-NEXT:    sbci r31, 0
+; TINY-NEXT:    in r16, 63
+; TINY-NEXT:    subi r28, 231
+; TINY-NEXT:    sbci r29, 255
+; TINY-NEXT:    ld r24, Y+
+; TINY-NEXT:    ld r25, Y+
+; TINY-NEXT:    subi r28, 2
+; TINY-NEXT:    sbci r29, 0
+; TINY-NEXT:    subi r28, 25
+; TINY-NEXT:    sbci r29, 0
+; TINY-NEXT:    out 63, r16
+; TINY-NEXT:    subi r30, 252
+; TINY-NEXT:    sbci r31, 255
+; TINY-NEXT:    st Z+, r24
+; TINY-NEXT:    st Z+, r25
+; TINY-NEXT:    subi r30, 6
+; TINY-NEXT:    sbci r31, 0
+; TINY-NEXT:    in r16, 63
+; TINY-NEXT:    subi r28, 233
+; TINY-NEXT:    sbci r29, 255
+; TINY-NEXT:    ld r24, Y+
+; TINY-NEXT:    ld r25, Y+
+; TINY-NEXT:    subi r28, 2
+; TINY-NEXT:    sbci r29, 0
+; TINY-NEXT:    subi r28, 23
+; TINY-NEXT:    sbci r29, 0
+; TINY-NEXT:    out 63, r16
+; TINY-NEXT:    subi r30, 254
+; TINY-NEXT:    sbci r31, 255
+; TINY-NEXT:    st Z+, r24
+; TINY-NEXT:    st Z+, r25
+; TINY-NEXT:    subi r30, 4
+; TINY-NEXT:    sbci r31, 0
+; TINY-NEXT:    in r16, 63
+; TINY-NEXT:    subi r28, 235
+; TINY-NEXT:    sbci r29, 255
+; TINY-NEXT:    ld r24, Y+
+; TINY-NEXT:    ld r25, Y+
+; TINY-NEXT:    subi r28, 2
+; TINY-NEXT:    sbci r29, 0
+; TINY-NEXT:    subi r28, 21
+; TINY-NEXT:    sbci r29, 0
+; TINY-NEXT:    out 63, r16
+; TINY-NEXT:    st Z+, r24
+; TINY-NEXT:    st Z+, r25
 ; TINY-NEXT:    pop r29
 ; TINY-NEXT:    pop r28
 ; TINY-NEXT:    ret
     ret i64 %z
 }
 
 define i32 @return64_trunc(i32 %a, i32 %b, i32 %c, i64 %d) {
 ; AVR-LABEL: return64_trunc:

 ; AVR-NEXT:    ret
 ;
 ; TINY-LABEL: return64_trunc:
 ; TINY:       ; %bb.0:
 ; TINY-NEXT:    push r28
 ; TINY-NEXT:    push r29
 ; TINY-NEXT:    in r28, 61
 ; TINY-NEXT:    in r29, 62
-; TINY-NEXT:    ldd r24, Y+15
-; TINY-NEXT:    ldd r25, Y+16
-; TINY-NEXT:    ldd r22, Y+13
-; TINY-NEXT:    ldd r23, Y+14
+; TINY-NEXT:    in r16, 63
+; TINY-NEXT:    subi r28, 241
+; TINY-NEXT:    sbci r29, 255
+; TINY-NEXT:    ld r24, Y+
+; TINY-NEXT:    ld r25, Y+
+; TINY-NEXT:    subi r28, 2
+; TINY-NEXT:    sbci r29, 0
+; TINY-NEXT:    subi r28, 15
+; TINY-NEXT:    sbci r29, 0
+; TINY-NEXT:    out 63, r16
+; TINY-NEXT:    in r16, 63
+; TINY-NEXT:    subi r28, 243
+; TINY-NEXT:    sbci r29, 255
+; TINY-NEXT:    ld r22, Y+
+; TINY-NEXT:    ld r23, Y+
+; TINY-NEXT:    subi r28, 2
+; TINY-NEXT:    sbci r29, 0
+; TINY-NEXT:    subi r28, 13
+; TINY-NEXT:    sbci r29, 0
+; TINY-NEXT:    out 63, r16
 ; TINY-NEXT:    pop r29
 ; TINY-NEXT:    pop r28
 ; TINY-NEXT:    ret
   %result = trunc i64 %d to i32
   ret i32 %result
 }
 
 define avr_intrcc void @interrupt_handler() {