[PowerPC] Converting to comparison against zero even when the optimization doesn't happened in peephole optimizer.

[Esme]

Summary

Converting a comparison against 1 or -1 into a comparison against 0 can exploit record-form instructions for comparison optimization. The conversion will happen only when a record-form instruction can be used to replace the comparison during the peephole optimizer (see function optimizeCompareInstr).

In post-RA, we also want to optimize the comparison by using the record form (see D131873) and it requires additional dataflow analysis to reliably find uses of the CR register set. It's reasonable to common the conversion for both peephole optimizer and post-RA optimizer.

Converting to comparison against zero even when the optimization doesn't happened in peephole optimizer may create additional opportunities for the post-RA optimization.

[nemanjai]

I don't really have an issue with the code in this patch. Converting to comparison against zero whenever possible (even when a record-form instruction cannot be used to replace the comparison) seems perfectly reasonable.
However, I don't want this to go in without a good explanation - and the explanation you provided is inadequate.

• There is no mention of why this conversion doesn't already happen (i.e. no opportunity exists to produce a record-form instruction)
• There isn't an adequate description of what you hope to do with these in post-RA optimizations
• The post-RA patch should be posted first and linked with this one so that it is clear what the relationship is between the optimizations
• The description makes it seem like the future post-RA optimization depends on this which is not OK - it is OK for this to create additional opportunities for the post-RA optimization

llvm/lib/Target/PowerPC/PPCInstrInfo.cpp

2541–2546

"Modify the condition code..." is too vague. You want to state what is actually being changed here:

// Convert the comparison and its user to a compare against zero with
// the appropriate predicate on the branch. Zero comparison might provide
// optimization opportunities post-RA (see optimization in 
// PPCPreEmitPeephole.cpp).

(assuming that is where the post-RA transformation you're referring to is).

[Esme]

Addressed @nemanjai 's comments. Thx!

1. updated the description.
2. updated the comment.
3. posted patch D131873 for comparison optimization in post-RA.

[nemanjai]

On the surface, this patch is fine. I don't think it should cause any issues. However, there are some important implications that you need to consider here.

1. There are paths out of this function where we can return false even though we have actually modified code. The convention for functions that perform and optimization and return a Boolean to state whether they successfully performed the optimization is to not modify code at all if they are returning false (indicating the optimization was not successful). You are fundamentally changing that for this function. Is that OK? Well, I don't know. It depends on what assumptions the caller (and recursively the conceptual call stack) makes wrt. to the return value - both now and in the future. Ultimately, optimization and canonicalization are distinct. This is a function that is expected to perform an optimization. But it performs a canonicalization in a superset of cases for which it performs an optimization. And the answer to the question "What should it return if it performs a canonicalization and not an optimization?" is not easy to formulate.
2. There is a lot of code with diverging paths in this function after the canonicalization you perform here. Have you verified that none of it depends on the def and use have not been modified? As a reviewer, I certainly don't have the time to track through the entire large function and confirm this. But it needs to be done.
3. Although this seems like a rather benign change, this is potentially rather pervasive. As such, this patch needs to be tested extremely thoroughly. Certainly execution tests using SPEC, LLVM bootstrap and perhaps some other software packages that we can use for testing.

As I am not opposed to this patch, I will approve it since further reviews will not reveal any new useful information. However, I trust that you will consider these comments and perform the testing and analysis of the surrounding code prior to committing this. If it turns out that the early returns after the canonicalization need to change from false to true and you would prefer another review, feel free to request another review. Also, please provide details as a comment here as to what testing you performed.

[Esme]

In D131374#3767476, @nemanjai wrote:

On the surface, this patch is fine. I don't think it should cause any issues. However, there are some important implications that you need to consider here.

1. There are paths out of this function where we can return false even though we have actually modified code. The convention for functions that perform and optimization and return a Boolean to state whether they successfully performed the optimization is to not modify code at all if they are returning false (indicating the optimization was not successful). You are fundamentally changing that for this function. Is that OK? Well, I don't know. It depends on what assumptions the caller (and recursively the conceptual call stack) makes wrt. to the return value - both now and in the future. Ultimately, optimization and canonicalization are distinct. This is a function that is expected to perform an optimization. But it performs a canonicalization in a superset of cases for which it performs an optimization. And the answer to the question "What should it return if it performs a canonicalization and not an optimization?" is not easy to formulate.

I had the concern too, and tried to put this conversion elsewhere, like in ISelLowering (as D98542), but found some case could therefore miss the optimization in PPCMIPeephole::eliminateRedundantCompare( ).
Performing a canonicalization in a function for optimization does change the instruction but doesn't perform any optimization behavior, so I think it doesn't changes the meaning of the return value (i.e. whether the optimization was performed successfully).
Although the patch seems not the most perfect approach, but this is a rather appropriate approach after a trade-off.

1. There is a lot of code with diverging paths in this function after the canonicalization you perform here. Have you verified that none of it depends on the def and use have not been modified? As a reviewer, I certainly don't have the time to track through the entire large function and confirm this. But it needs to be done.

Yes, this canonicalization will not affect following paths in this function.

1. Although this seems like a rather benign change, this is potentially rather pervasive. As such, this patch needs to be tested extremely thoroughly. Certainly execution tests using SPEC, LLVM bootstrap and perhaps some other software packages that we can use for testing.

Both SPEC and bootstrap are clean after applying this patch.

As I am not opposed to this patch, I will approve it since further reviews will not reveal any new useful information. However, I trust that you will consider these comments and perform the testing and analysis of the surrounding code prior to committing this. If it turns out that the early returns after the canonicalization need to change from false to true and you would prefer another review, feel free to request another review. Also, please provide details as a comment here as to what testing you performed.

Thanks for your approve. The return value of true for this function means the optimization of comparison is performed successfully (ie. the comparison is eliminated), therefore the canonicalization should not change the return value.

llvm/lib/Target/PowerPC/PPCInstrInfo.cpp

else if (Immed == 1 && PredCond == PPC::PRED_LT)
       // We convert "less than 1" into "less than or equal to 0".
       Pred = PPC::getPredicate(PPC::PRED_LE, PredHint);
     else if (Immed == 1 && PredCond == PPC::PRED_GE)
       // We convert "greater than or equal to 1" into "greater than 0".
       Pred = PPC::getPredicate(PPC::PRED_GT, PredHint);
     else
       return false;
 
-    PredsToUpdate.push_back(std::make_pair(&(UseMI->getOperand(0)), Pred));
+    // Convert the comparison and its user to a compare against zero with the
+    // appropriate predicate on the branch. Zero comparison might provide
+    // optimization opportunities post-RA (see optimization in
+    // PPCPreEmitPeephole.cpp).
+    UseMI->getOperand(0).setImm(Pred);
+    CmpInstr.getOperand(2).setImm(0);
   }
 
   // Search for Sub.
   --I;
 
   // Get ready to iterate backward from CmpInstr.
   MachineBasicBlock::iterator E = MI, B = CmpInstr.getParent()->begin();
 

llvm/test/CodeGen/PowerPC/common-chain.ll

 ;     sum += x1 * x2 * x3 * x4;
 ;   }
 ;   return sum;
 ; }
 ;
 define i64 @two_chain_same_offset_succ(i8* %p, i64 %offset, i64 %base1, i64 %n) {
 ; CHECK-LABEL: two_chain_same_offset_succ:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    cmpdi r6, 1
-; CHECK-NEXT:    blt cr0, .LBB0_4
+; CHECK-NEXT:    cmpdi r6, 0
+; CHECK-NEXT:    ble cr0, .LBB0_4
 ; CHECK-NEXT:  # %bb.1: # %for.body.preheader
 ; CHECK-NEXT:    sldi r7, r4, 1
 ; CHECK-NEXT:    mtctr r6
 ; CHECK-NEXT:    add r8, r4, r7
 ; CHECK-NEXT:    add r7, r5, r4
 ; CHECK-NEXT:    add r5, r5, r8
 ; CHECK-NEXT:    add r7, r3, r7
 ; CHECK-NEXT:    add r5, r3, r5

 ;     sum += x1 * x2 * x3 * x4 * x5;
 ;   }
 ;   return sum;
 ; }
 ;
 define i64 @not_perfect_chain_all_same_offset_fail(i8* %p, i64 %offset, i64 %base1, i64 %n) {
 ; CHECK-LABEL: not_perfect_chain_all_same_offset_fail:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    cmpdi r6, 1
+; CHECK-NEXT:    cmpdi r6, 0
 ; CHECK-NEXT:    std r30, -16(r1) # 8-byte Folded Spill
-; CHECK-NEXT:    blt cr0, .LBB1_4
+; CHECK-NEXT:    ble cr0, .LBB1_4
 ; CHECK-NEXT:  # %bb.1: # %for.body.preheader
 ; CHECK-NEXT:    sldi r7, r4, 1
 ; CHECK-NEXT:    sldi r9, r4, 2
 ; CHECK-NEXT:    add r5, r3, r5
 ; CHECK-NEXT:    li r3, 0
 ; CHECK-NEXT:    add r8, r4, r7
 ; CHECK-NEXT:    mtctr r6
 ; CHECK-NEXT:    add r10, r4, r9

 ;     sum += x1 * x2 * x3;
 ;   }
 ;   return sum;
 ; }
 ;
 define i64 @no_enough_elements_fail(i8* %p, i64 %offset, i64 %base1, i64 %n) {
 ; CHECK-LABEL: no_enough_elements_fail:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    cmpdi r6, 1
-; CHECK-NEXT:    blt cr0, .LBB2_4
+; CHECK-NEXT:    cmpdi r6, 0
+; CHECK-NEXT:    ble cr0, .LBB2_4
 ; CHECK-NEXT:  # %bb.1: # %for.body.preheader
 ; CHECK-NEXT:    sldi r7, r4, 1
 ; CHECK-NEXT:    mtctr r6
 ; CHECK-NEXT:    add r5, r3, r5
 ; CHECK-NEXT:    li r3, 0
 ; CHECK-NEXT:    add r4, r4, r7
 ; CHECK-NEXT:    .p2align 5
 ; CHECK-NEXT:  .LBB2_2: # %for.body

 ;     sum += x1 * x2 * x3 * x4;
 ;   }
 ;   return sum;
 ; }
 ;
 define i64 @no_reuseable_offset_fail(i8* %p, i64 %offset, i64 %base1, i64 %n) {
 ; CHECK-LABEL: no_reuseable_offset_fail:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    cmpdi r6, 1
-; CHECK-NEXT:    blt cr0, .LBB3_4
+; CHECK-NEXT:    cmpdi r6, 0
+; CHECK-NEXT:    ble cr0, .LBB3_4
 ; CHECK-NEXT:  # %bb.1: # %for.body.preheader
 ; CHECK-NEXT:    sldi r9, r4, 3
 ; CHECK-NEXT:    mtctr r6
 ; CHECK-NEXT:    add r5, r3, r5
 ; CHECK-NEXT:    li r3, 0
 ; CHECK-NEXT:    sldi r7, r4, 1
 ; CHECK-NEXT:    sldi r8, r4, 2
 ; CHECK-NEXT:    sub r4, r9, r4

 ;     sum += x1 * x2 * x3 * x4 * x5 * x6;
 ;   }
 ;   return sum;
 ; }
 ;
 define i64 @not_same_offset_fail(i8* %p, i64 %offset, i64 %base1, i64 %n) {
 ; CHECK-LABEL: not_same_offset_fail:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    cmpdi r6, 1
+; CHECK-NEXT:    cmpdi r6, 0
 ; CHECK-NEXT:    std r28, -32(r1) # 8-byte Folded Spill
 ; CHECK-NEXT:    std r29, -24(r1) # 8-byte Folded Spill
 ; CHECK-NEXT:    std r30, -16(r1) # 8-byte Folded Spill
-; CHECK-NEXT:    blt cr0, .LBB4_3
+; CHECK-NEXT:    ble cr0, .LBB4_3
 ; CHECK-NEXT:  # %bb.1: # %for.body.preheader
 ; CHECK-NEXT:    mulli r11, r4, 10
 ; CHECK-NEXT:    sldi r8, r4, 2
 ; CHECK-NEXT:    add r5, r3, r5
 ; CHECK-NEXT:    li r3, 0
 ; CHECK-NEXT:    add r8, r4, r8
 ; CHECK-NEXT:    sldi r9, r4, 3
 ; CHECK-NEXT:    mtctr r6

 ;     sum += x1 * x2 * x3 * x4;
 ;   }
 ;   return sum;
 ; }
 ;
 define i64 @two_chain_different_offsets_succ(i8* %p, i64 %offset, i64 %base1, i64 %n) {
 ; CHECK-LABEL: two_chain_different_offsets_succ:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    cmpdi r6, 1
-; CHECK-NEXT:    blt cr0, .LBB5_4
+; CHECK-NEXT:    cmpdi r6, 0
+; CHECK-NEXT:    ble cr0, .LBB5_4
 ; CHECK-NEXT:  # %bb.1: # %for.body.preheader
 ; CHECK-NEXT:    sldi r8, r4, 2
 ; CHECK-NEXT:    add r7, r5, r4
 ; CHECK-NEXT:    mtctr r6
 ; CHECK-NEXT:    add r5, r5, r8
 ; CHECK-NEXT:    add r7, r3, r7
 ; CHECK-NEXT:    sldi r4, r4, 1
 ; CHECK-NEXT:    add r5, r3, r5

 ;     sum += x1 * x2 * x3 * x4;
 ;   }
 ;   return sum;
 ; }
 ;
 define i64 @two_chain_two_bases_succ(i8* %p, i64 %offset, i64 %base1, i64 %base2, i64 %n) {
 ; CHECK-LABEL: two_chain_two_bases_succ:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    cmpdi r7, 1
-; CHECK-NEXT:    blt cr0, .LBB6_4
+; CHECK-NEXT:    cmpdi r7, 0
+; CHECK-NEXT:    ble cr0, .LBB6_4
 ; CHECK-NEXT:  # %bb.1: # %for.body.preheader
 ; CHECK-NEXT:    add r6, r6, r4
 ; CHECK-NEXT:    add r5, r5, r4
 ; CHECK-NEXT:    mtctr r7
 ; CHECK-NEXT:    sldi r4, r4, 1
 ; CHECK-NEXT:    add r5, r3, r5
 ; CHECK-NEXT:    add r6, r3, r6
 ; CHECK-NEXT:    li r3, 0

 ;     inc =  inc + inc4;
 ;   }
 ;   return 0;
 ; }
 ;
 define signext i32 @spill_reduce_succ(double* %input1, double* %input2, double* %output, i64 %m, i64 %inc1, i64 %inc2, i64 %inc3, i64 %inc4, i64 %inc) {
 ; CHECK-LABEL: spill_reduce_succ:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    cmpdi r6, 1
+; CHECK-NEXT:    cmpdi r6, 0
 ; CHECK-NEXT:    std r14, -144(r1) # 8-byte Folded Spill
 ; CHECK-NEXT:    std r15, -136(r1) # 8-byte Folded Spill
 ; CHECK-NEXT:    std r16, -128(r1) # 8-byte Folded Spill
 ; CHECK-NEXT:    std r17, -120(r1) # 8-byte Folded Spill
 ; CHECK-NEXT:    std r18, -112(r1) # 8-byte Folded Spill
 ; CHECK-NEXT:    std r19, -104(r1) # 8-byte Folded Spill
 ; CHECK-NEXT:    std r20, -96(r1) # 8-byte Folded Spill
 ; CHECK-NEXT:    std r21, -88(r1) # 8-byte Folded Spill
 ; CHECK-NEXT:    std r22, -80(r1) # 8-byte Folded Spill
 ; CHECK-NEXT:    std r23, -72(r1) # 8-byte Folded Spill
 ; CHECK-NEXT:    std r24, -64(r1) # 8-byte Folded Spill
 ; CHECK-NEXT:    std r25, -56(r1) # 8-byte Folded Spill
 ; CHECK-NEXT:    std r26, -48(r1) # 8-byte Folded Spill
 ; CHECK-NEXT:    std r27, -40(r1) # 8-byte Folded Spill
 ; CHECK-NEXT:    std r28, -32(r1) # 8-byte Folded Spill
 ; CHECK-NEXT:    std r29, -24(r1) # 8-byte Folded Spill
 ; CHECK-NEXT:    std r30, -16(r1) # 8-byte Folded Spill
 ; CHECK-NEXT:    std r31, -8(r1) # 8-byte Folded Spill
 ; CHECK-NEXT:    std r2, -152(r1) # 8-byte Folded Spill
 ; CHECK-NEXT:    std r9, -160(r1) # 8-byte Folded Spill
 ; CHECK-NEXT:    std r8, -176(r1) # 8-byte Folded Spill
 ; CHECK-NEXT:    std r7, -168(r1) # 8-byte Folded Spill
-; CHECK-NEXT:    blt cr0, .LBB7_7
+; CHECK-NEXT:    ble cr0, .LBB7_7
 ; CHECK-NEXT:  # %bb.1: # %for.body.preheader
 ; CHECK-NEXT:    sldi r6, r6, 2
 ; CHECK-NEXT:    li r7, 1
 ; CHECK-NEXT:    mr r12, r10
 ; CHECK-NEXT:    cmpdi r6, 1
 ; CHECK-NEXT:    iselgt r7, r6, r7
 ; CHECK-NEXT:    addi r8, r7, -1
 ; CHECK-NEXT:    clrldi r6, r7, 63

llvm/test/CodeGen/PowerPC/f128-aggregates.ll

 }
 
 ; Function Attrs: nounwind
 define fp128 @sum_float128(i32 signext %count, ...) {
 ; CHECK-LABEL: sum_float128:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    std r4, 40(r1)
 ; CHECK-NEXT:    addis r4, r2, .LCPI17_0@toc@ha
-; CHECK-NEXT:    cmpwi r3, 1
+; CHECK-NEXT:    cmpwi r3, 0
 ; CHECK-NEXT:    std r5, 48(r1)
 ; CHECK-NEXT:    addi r4, r4, .LCPI17_0@toc@l
 ; CHECK-NEXT:    std r6, 56(r1)
 ; CHECK-NEXT:    std r7, 64(r1)
 ; CHECK-NEXT:    std r8, 72(r1)
 ; CHECK-NEXT:    lxv v2, 0(r4)
 ; CHECK-NEXT:    std r9, 80(r1)
 ; CHECK-NEXT:    std r10, 88(r1)
-; CHECK-NEXT:    bltlr cr0
+; CHECK-NEXT:    blelr cr0
 ; CHECK-NEXT:  # %bb.1: # %if.end
 ; CHECK-NEXT:    addi r3, r1, 40
 ; CHECK-NEXT:    addi r4, r1, 72
 ; CHECK-NEXT:    lxvx v3, 0, r3
 ; CHECK-NEXT:    std r4, -8(r1)
 ; CHECK-NEXT:    xsaddqp v2, v3, v2
 ; CHECK-NEXT:    lxv v3, 16(r3)
 ; CHECK-NEXT:    xsaddqp v2, v2, v3
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: sum_float128:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    std r4, 56(r1)
 ; CHECK-BE-NEXT:    addis r4, r2, .LCPI17_0@toc@ha
-; CHECK-BE-NEXT:    cmpwi r3, 1
+; CHECK-BE-NEXT:    cmpwi r3, 0
 ; CHECK-BE-NEXT:    std r5, 64(r1)
 ; CHECK-BE-NEXT:    addi r4, r4, .LCPI17_0@toc@l
 ; CHECK-BE-NEXT:    std r6, 72(r1)
 ; CHECK-BE-NEXT:    std r7, 80(r1)
 ; CHECK-BE-NEXT:    std r8, 88(r1)
 ; CHECK-BE-NEXT:    lxv v2, 0(r4)
 ; CHECK-BE-NEXT:    std r9, 96(r1)
 ; CHECK-BE-NEXT:    std r10, 104(r1)
-; CHECK-BE-NEXT:    bltlr cr0
+; CHECK-BE-NEXT:    blelr cr0
 ; CHECK-BE-NEXT:  # %bb.1: # %if.end
 ; CHECK-BE-NEXT:    addi r3, r1, 56
 ; CHECK-BE-NEXT:    addi r4, r1, 88
 ; CHECK-BE-NEXT:    lxvx v3, 0, r3
 ; CHECK-BE-NEXT:    std r4, -8(r1)
 ; CHECK-BE-NEXT:    xsaddqp v2, v3, v2
 ; CHECK-BE-NEXT:    lxv v3, 16(r3)
 ; CHECK-BE-NEXT:    xsaddqp v2, v2, v3
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: sum_float128:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    mflr r0
 ; CHECK-P8-NEXT:    .cfi_def_cfa_offset 64
 ; CHECK-P8-NEXT:    .cfi_offset lr, 16
 ; CHECK-P8-NEXT:    .cfi_offset r30, -16
 ; CHECK-P8-NEXT:    std r30, -16(r1) # 8-byte Folded Spill
 ; CHECK-P8-NEXT:    std r0, 16(r1)
 ; CHECK-P8-NEXT:    stdu r1, -64(r1)
 ; CHECK-P8-NEXT:    addis r11, r2, .LCPI17_0@toc@ha
-; CHECK-P8-NEXT:    cmpwi r3, 1
+; CHECK-P8-NEXT:    cmpwi r3, 0
 ; CHECK-P8-NEXT:    std r4, 104(r1)
 ; CHECK-P8-NEXT:    std r5, 112(r1)
 ; CHECK-P8-NEXT:    std r6, 120(r1)
 ; CHECK-P8-NEXT:    std r7, 128(r1)
 ; CHECK-P8-NEXT:    addi r11, r11, .LCPI17_0@toc@l
 ; CHECK-P8-NEXT:    lxvd2x vs0, 0, r11
 ; CHECK-P8-NEXT:    std r8, 136(r1)
 ; CHECK-P8-NEXT:    std r9, 144(r1)
 ; CHECK-P8-NEXT:    std r10, 152(r1)
 ; CHECK-P8-NEXT:    xxswapd v3, vs0
-; CHECK-P8-NEXT:    blt cr0, .LBB17_2
+; CHECK-P8-NEXT:    ble cr0, .LBB17_2
 ; CHECK-P8-NEXT:  # %bb.1: # %if.end
 ; CHECK-P8-NEXT:    addi r30, r1, 104
 ; CHECK-P8-NEXT:    lxvd2x vs0, 0, r30
 ; CHECK-P8-NEXT:    xxswapd v2, vs0
 ; CHECK-P8-NEXT:    bl __addkf3
 ; CHECK-P8-NEXT:    nop
 ; CHECK-P8-NEXT:    li r3, 16
 ; CHECK-P8-NEXT:    lxvd2x vs0, r30, r3

llvm/test/CodeGen/PowerPC/loop-instr-form-prepare.ll

 ;    res += x1*x2*x3*x4;
 ;  }
 ;  return res;
 ;}
 
 define float @test_ds_float(i8* %0, i32 signext %1) {
 ; CHECK-LABEL: test_ds_float:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    cmpwi r4, 1
-; CHECK-NEXT:    blt cr0, .LBB7_4
+; CHECK-NEXT:    cmpwi r4, 0
+; CHECK-NEXT:    ble cr0, .LBB7_4
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    clrldi r4, r4, 32
 ; CHECK-NEXT:    addi r3, r3, 4002
 ; CHECK-NEXT:    xxlxor f1, f1, f1
 ; CHECK-NEXT:    mtctr r4
 ; CHECK-NEXT:    li r4, -1
 ; CHECK-NEXT:    .p2align 4
 ; CHECK-NEXT:  .LBB7_2:

 ;    res += x1*x2*x3*x4;
 ;  }
 ;  return res;
 ;}
 
 define float @test_ds_combine_float_int(i8* %0, i32 signext %1) {
 ; CHECK-LABEL: test_ds_combine_float_int:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    cmpwi r4, 1
-; CHECK-NEXT:    blt cr0, .LBB8_4
+; CHECK-NEXT:    cmpwi r4, 0
+; CHECK-NEXT:    ble cr0, .LBB8_4
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    clrldi r4, r4, 32
 ; CHECK-NEXT:    addi r3, r3, 4002
 ; CHECK-NEXT:    xxlxor f1, f1, f1
 ; CHECK-NEXT:    mtctr r4
 ; CHECK-NEXT:    li r4, -1
 ; CHECK-NEXT:    .p2align 4
 ; CHECK-NEXT:  .LBB8_2:

 ;     res += x1*x2*x3*x4;
 ;   }
 ;   return res + count;
 ; }
 
 define i64 @test_ds_lwa_prep(i8* %0, i32 signext %1) {
 ; CHECK-LABEL: test_ds_lwa_prep:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    cmpwi r4, 1
-; CHECK-NEXT:    blt cr0, .LBB9_4
+; CHECK-NEXT:    cmpwi r4, 0
+; CHECK-NEXT:    ble cr0, .LBB9_4
 ; CHECK-NEXT:  # %bb.1: # %.preheader
 ; CHECK-NEXT:    mtctr r4
 ; CHECK-NEXT:    addi r5, r3, 2
 ; CHECK-NEXT:    li r3, 0
 ; CHECK-NEXT:    li r6, -1
 ; CHECK-NEXT:    .p2align 4
 ; CHECK-NEXT:  .LBB9_2:
 ; CHECK-NEXT:    lwax r7, r5, r6

llvm/test/CodeGen/PowerPC/loop-instr-prep-non-const-increasement.ll

 ;     j += count;
 ;   }
 ;   return sum;
 ; }
 
 define i64 @foo(i8* %p, i32 signext %n, i32 signext %count) {
 ; CHECK-LABEL: foo:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    cmpwi r4, 1
-; CHECK-NEXT:    blt cr0, .LBB0_4
+; CHECK-NEXT:    cmpwi r4, 0
+; CHECK-NEXT:    ble cr0, .LBB0_4
 ; CHECK-NEXT:  # %bb.1: # %for.body.preheader
 ; CHECK-NEXT:    addi r6, r3, 5
 ; CHECK-NEXT:    addi r3, r4, -1
 ; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    addi r3, r3, 1
 ; CHECK-NEXT:    mtctr r3
 ; CHECK-NEXT:    li r3, 0
 ; CHECK-NEXT:    .p2align 5

 ;     j += count;
 ;    }
 ;   return sum;
 ; }
 
 define zeroext i8 @foo1(i8* %p, i32 signext %n, i32 signext %count) {
 ; CHECK-LABEL: foo1:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    cmpwi r4, 1
-; CHECK-NEXT:    blt cr0, .LBB1_4
+; CHECK-NEXT:    cmpwi r4, 0
+; CHECK-NEXT:    ble cr0, .LBB1_4
 ; CHECK-NEXT:  # %bb.1: # %for.body.preheader
 ; CHECK-NEXT:    sub r3, r3, r5
 ; CHECK-NEXT:    addi r6, r3, 1000
 ; CHECK-NEXT:    addi r3, r4, -1
 ; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    addi r3, r3, 1
 ; CHECK-NEXT:    mtctr r3
 ; CHECK-NEXT:    li r3, 0

llvm/test/CodeGen/PowerPC/loop-p10-pair-prepare.ll

 
 %_elem_type_of_x = type <{ double }>
 %_elem_type_of_y = type <{ double }>
 
 define void @foo(i64* %.n, [0 x %_elem_type_of_x]* %.x, [0 x %_elem_type_of_y]* %.y, <2 x double>* %.sum) {
 ; CHECK-LABEL: foo:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    ld r5, 0(r3)
-; CHECK-NEXT:    cmpdi r5, 1
-; CHECK-NEXT:    bltlr cr0
+; CHECK-NEXT:    cmpdi r5, 0
+; CHECK-NEXT:    blelr cr0
 ; CHECK-NEXT:  # %bb.1: # %_loop_1_do_.lr.ph
 ; CHECK-NEXT:    addi r3, r4, 1
 ; CHECK-NEXT:    addi r4, r5, -1
 ; CHECK-NEXT:    lxv vs0, 0(r6)
 ; CHECK-NEXT:    rldicl r4, r4, 60, 4
 ; CHECK-NEXT:    addi r4, r4, 1
 ; CHECK-NEXT:    mtctr r4
 ; CHECK-NEXT:    .p2align 5

 ; CHECK-NEXT:    bdnz .LBB0_2
 ; CHECK-NEXT:  # %bb.3: # %_loop_1_loopHeader_._return_bb_crit_edge
 ; CHECK-NEXT:    stxv vs0, 0(r6)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: foo:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    ld r5, 0(r3)
-; CHECK-BE-NEXT:    cmpdi r5, 1
-; CHECK-BE-NEXT:    bltlr cr0
+; CHECK-BE-NEXT:    cmpdi r5, 0
+; CHECK-BE-NEXT:    blelr cr0
 ; CHECK-BE-NEXT:  # %bb.1: # %_loop_1_do_.lr.ph
 ; CHECK-BE-NEXT:    addi r3, r4, 1
 ; CHECK-BE-NEXT:    addi r4, r5, -1
 ; CHECK-BE-NEXT:    lxv vs0, 0(r6)
 ; CHECK-BE-NEXT:    rldicl r4, r4, 60, 4
 ; CHECK-BE-NEXT:    addi r4, r4, 1
 ; CHECK-BE-NEXT:    mtctr r4
 ; CHECK-BE-NEXT:    .p2align 5

llvm/test/CodeGen/PowerPC/pr47373.ll

 ; CHECK-NEXT:    ld r3, .LC0@toc@l(r3)
 ; CHECK-NEXT:    std r30, 192(r1) # 8-byte Folded Spill
 ; CHECK-NEXT:    ld r29, 0(r3)
 ; CHECK-NEXT:    bl c
 ; CHECK-NEXT:    nop
 ; CHECK-NEXT:    mr r30, r3
 ; CHECK-NEXT:    bl b
 ; CHECK-NEXT:    nop
-; CHECK-NEXT:    cmpwi r30, 1
-; CHECK-NEXT:    blt cr0, .LBB0_9
+; CHECK-NEXT:    cmpwi r30, 0
+; CHECK-NEXT:    ble cr0, .LBB0_9
 ; CHECK-NEXT:  # %bb.1: # %for.body.preheader
 ; CHECK-NEXT:    cmplwi r30, 4
 ; CHECK-NEXT:    clrldi r4, r30, 32
 ; CHECK-NEXT:    li r5, 0
 ; CHECK-NEXT:    blt cr0, .LBB0_7
 ; CHECK-NEXT:  # %bb.2: # %vector.memcheck
 ; CHECK-NEXT:    rldic r6, r30, 2, 30
 ; CHECK-NEXT:    add r7, r3, r6

llvm/test/CodeGen/PowerPC/shrink-wrap.ll

 ; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-unknown -mcpu=pwr9 | FileCheck  %s --check-prefixes=CHECK,CHECK64
 ; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-ibm-aix-xcoff -mcpu=pwr9 -mattr=-altivec | FileCheck  %s --check-prefixes=CHECK,CHECK32
-; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-ibm-aix-xcoff -mcpu=pwr9 -mattr=-altivec | FileCheck  %s --check-prefixes=CHECK,CHECK64
+; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-ibm-aix-xcoff -mcpu=pwr9 -mattr=-altivec | FileCheck  %s --check-prefixes=CHECKAIX,CHECK64
 
 define signext i32 @shrinkwrapme(i32 signext %a, i32 signext %lim) {
 entry:
   %cmp5 = icmp sgt i32 %lim, 0
   br i1 %cmp5, label %for.body.preheader, label %for.cond.cleanup
 
  for.body.preheader:                               ; preds = %entry
   br label %for.body

 ; CHECK-LABEL: {{[\.]?}}shrinkwrapme:
 ; CHECK:            # %bb.0:
 ; CHECK-NEXT:         cmpwi
 ; Prolog code
 ; CHECK64-COUNT-18:   std
 
 ; CHECK32-COUNT-18:   stw
 
-; CHECK:              blt 0, {{.*}}BB0_3
+; CHECK:              ble 0, {{.*}}BB0_3
+; CHECKAIX:           blt 0, {{.*}}BB0_3
 ; CHECK:            # %bb.1:
 ; CHECK:              li
 ; CHECK:            {{.*}}BB0_2:
 ; CHECK:              add
 ; CHECK:              bdnz {{.*}}BB0_2
 ; CHECK-NEXT:         b {{.*}}BB0_4
 ; CHECK:            {{.*}}BB0_3:
 ; CHECK-NEXT:         li

llvm/test/CodeGen/PowerPC/spe.ll

 ; SPE-NEXT:    blr
 ;
 ; EFPU2-LABEL: test_dcmpgt:
 ; EFPU2:       # %bb.0: # %entry
 ; EFPU2-NEXT:    mflr 0
 ; EFPU2-NEXT:    stw 0, 4(1)
 ; EFPU2-NEXT:    stwu 1, -16(1)
 ; EFPU2-NEXT:    bl __gtdf2
-; EFPU2-NEXT:    cmpwi 3, 1
-; EFPU2-NEXT:    blt 0, .LBB37_2
+; EFPU2-NEXT:    cmpwi 3, 0
+; EFPU2-NEXT:    ble 0, .LBB37_2
 ; EFPU2-NEXT:  # %bb.1: # %tr
 ; EFPU2-NEXT:    li 3, 1
 ; EFPU2-NEXT:    b .LBB37_3
 ; EFPU2-NEXT:  .LBB37_2: # %fa
 ; EFPU2-NEXT:    li 3, 0
 ; EFPU2-NEXT:  .LBB37_3: # %ret
 ; EFPU2-NEXT:    stw 3, 12(1)
 ; EFPU2-NEXT:    lwz 3, 12(1)

 ; SPE-NEXT:    blr
 ;
 ; EFPU2-LABEL: test_dcmpugt:
 ; EFPU2:       # %bb.0: # %entry
 ; EFPU2-NEXT:    mflr 0
 ; EFPU2-NEXT:    stw 0, 4(1)
 ; EFPU2-NEXT:    stwu 1, -16(1)
 ; EFPU2-NEXT:    bl __ledf2
-; EFPU2-NEXT:    cmpwi 3, 1
-; EFPU2-NEXT:    blt 0, .LBB38_2
+; EFPU2-NEXT:    cmpwi 3, 0
+; EFPU2-NEXT:    ble 0, .LBB38_2
 ; EFPU2-NEXT:  # %bb.1: # %tr
 ; EFPU2-NEXT:    li 3, 1
 ; EFPU2-NEXT:    b .LBB38_3
 ; EFPU2-NEXT:  .LBB38_2: # %fa
 ; EFPU2-NEXT:    li 3, 0
 ; EFPU2-NEXT:  .LBB38_3: # %ret
 ; EFPU2-NEXT:    stw 3, 12(1)
 ; EFPU2-NEXT:    lwz 3, 12(1)

 ; SPE-NEXT:    blr
 ;
 ; EFPU2-LABEL: test_dcmplt:
 ; EFPU2:       # %bb.0: # %entry
 ; EFPU2-NEXT:    mflr 0
 ; EFPU2-NEXT:    stw 0, 4(1)
 ; EFPU2-NEXT:    stwu 1, -16(1)
 ; EFPU2-NEXT:    bl __ltdf2
-; EFPU2-NEXT:    cmpwi 3, -1
-; EFPU2-NEXT:    bgt 0, .LBB45_2
+; EFPU2-NEXT:    cmpwi 3, 0
+; EFPU2-NEXT:    bge 0, .LBB45_2
 ; EFPU2-NEXT:  # %bb.1: # %tr
 ; EFPU2-NEXT:    li 3, 1
 ; EFPU2-NEXT:    b .LBB45_3
 ; EFPU2-NEXT:  .LBB45_2: # %fa
 ; EFPU2-NEXT:    li 3, 0
 ; EFPU2-NEXT:  .LBB45_3: # %ret
 ; EFPU2-NEXT:    stw 3, 12(1)
 ; EFPU2-NEXT:    lwz 3, 12(1)

 ; SPE-NEXT:    blr
 ;
 ; EFPU2-LABEL: test_dcmpult:
 ; EFPU2:       # %bb.0: # %entry
 ; EFPU2-NEXT:    mflr 0
 ; EFPU2-NEXT:    stw 0, 4(1)
 ; EFPU2-NEXT:    stwu 1, -16(1)
 ; EFPU2-NEXT:    bl __gedf2
-; EFPU2-NEXT:    cmpwi 3, -1
-; EFPU2-NEXT:    bgt 0, .LBB46_2
+; EFPU2-NEXT:    cmpwi 3, 0
+; EFPU2-NEXT:    bge 0, .LBB46_2
 ; EFPU2-NEXT:  # %bb.1: # %tr
 ; EFPU2-NEXT:    li 3, 1
 ; EFPU2-NEXT:    b .LBB46_3
 ; EFPU2-NEXT:  .LBB46_2: # %fa
 ; EFPU2-NEXT:    li 3, 0
 ; EFPU2-NEXT:  .LBB46_3: # %ret
 ; EFPU2-NEXT:    stw 3, 12(1)
 ; EFPU2-NEXT:    lwz 3, 12(1)

 }
 
 define dso_local float @test_fma(i32 %d) local_unnamed_addr #0 {
 ; CHECK-LABEL: test_fma:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    mflr 0
 ; CHECK-NEXT:    stw 0, 4(1)
 ; CHECK-NEXT:    stwu 1, -32(1)
-; CHECK-NEXT:    cmpwi 3, 1
+; CHECK-NEXT:    cmpwi 3, 0
 ; CHECK-NEXT:    evstdd 29, 8(1) # 8-byte Folded Spill
 ; CHECK-NEXT:    evstdd 30, 16(1) # 8-byte Folded Spill
-; CHECK-NEXT:    blt 0, .LBB56_3
+; CHECK-NEXT:    ble 0, .LBB56_3
 ; CHECK-NEXT:  # %bb.1: # %for.body.preheader
 ; CHECK-NEXT:    mr 30, 3
 ; CHECK-NEXT:    li 29, 0
 ; CHECK-NEXT:    # implicit-def: $r5
 ; CHECK-NEXT:  .LBB56_2: # %for.body
 ; CHECK-NEXT:    #
 ; CHECK-NEXT:    efscfsi 3, 29
 ; CHECK-NEXT:    mr 4, 3

llvm/test/CodeGen/PowerPC/store-constant.ll

entry:
   store i32 32768, i32* @IVal, align 4
   store i64 32768, i64* @LVal, align 8
   ret void
 }
 
 define void @SetArr(i32 signext %Len) {
 ; CHECK-LABEL: SetArr:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    cmpwi 3, 1
-; CHECK-NEXT:    bltlr 0
+; CHECK-NEXT:    cmpwi 3, 0
+; CHECK-NEXT:    blelr 0
 ; CHECK-NEXT:  # %bb.1: # %for.body.lr.ph
 ; CHECK-NEXT:    addis 4, 2, .LC5@toc@ha
 ; CHECK-NEXT:    addis 5, 2, .LC6@toc@ha
 ; CHECK-NEXT:    clrldi 6, 3, 32
 ; CHECK-NEXT:    ld 4, .LC5@toc@l(4)
 ; CHECK-NEXT:    ld 5, .LC6@toc@l(5)
 ; CHECK-NEXT:    ld 4, 0(4)
 ; CHECK-NEXT:    ld 5, 0(5)