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[AArch64][SVE] Allow XZR as offset reg in contiguous loads/stores
AbandonedPublic

Authored by c-rhodes on Jul 22 2022, 7:58 AM.

Details

Summary

The spec [1] doesn't restrict the offset register (i.e. Rm != 11111) in
SVE contiguous load/store (scalar plus scalar) instructions, permit XZR.

[1] https://developer.arm.com/documentation/ddi0596/2020-12/SVE-Instructions

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c-rhodes created this revision.Jul 22 2022, 7:58 AM
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c-rhodes requested review of this revision.Jul 22 2022, 7:58 AM
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Matt added a subscriber: Matt.Jul 23 2022, 7:54 PM

Following the link in the summary and looking at LD1H I see if Rm == '11111' then UNDEFINED; which suggests whilst the encoding might be valid the result is undefined and so I doubt we want users to fall into such a trap.

c-rhodes abandoned this revision.Jul 25 2022, 8:58 AM

Following the link in the summary and looking at LD1H I see if Rm == '11111' then UNDEFINED; which suggests whilst the encoding might be valid the result is undefined and so I doubt we want users to fall into such a trap.

ah, well spotted, I didn't see that. I was looking for Rm != 11111 in the encoding as I've seen for other instructions in the past, not at the pseudo code. It seems XZR shouldn't be accepted by the assembler after all, abandoning this.