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Differential D130365

[AArch64][SVE] Allow XZR as offset reg in contiguous loads/stores
AbandonedPublic

Authored by c-rhodes on Jul 22 2022, 7:58 AM.

Details

Reviewers
paulwalker-arm
sdesmalen
efriedma
Summary

The spec [1] doesn't restrict the offset register (i.e. Rm != 11111) in
SVE contiguous load/store (scalar plus scalar) instructions, permit XZR.

[1] https://developer.arm.com/documentation/ddi0596/2020-12/SVE-Instructions

Diff Detail

Event Timeline

c-rhodes created this revision.Jul 22 2022, 7:58 AM
Herald added a reviewer: efriedma. · View Herald TranscriptJul 22 2022, 7:58 AM
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Herald added subscribers: ctetreau, psnobl, hiraditya and 2 others. · View Herald Transcript
c-rhodes requested review of this revision.Jul 22 2022, 7:58 AM
Herald added a project: Restricted Project. · View Herald TranscriptJul 22 2022, 7:58 AM
Harbormaster completed remote builds in B177011: Diff 446837.Jul 22 2022, 8:48 AM
Matt added a subscriber: Matt.Jul 23 2022, 7:54 PM
paulwalker-arm added a comment.Jul 25 2022, 8:23 AM

Following the link in the summary and looking at LD1H I see if Rm == '11111' then UNDEFINED; which suggests whilst the encoding might be valid the result is undefined and so I doubt we want users to fall into such a trap.

c-rhodes abandoned this revision.Jul 25 2022, 8:58 AM
In D130365#3676362, @paulwalker-arm wrote:

Following the link in the summary and looking at LD1H I see if Rm == '11111' then UNDEFINED; which suggests whilst the encoding might be valid the result is undefined and so I doubt we want users to fall into such a trap.

ah, well spotted, I didn't see that. I was looking for Rm != 11111 in the encoding as I've seen for other instructions in the past, not at the pseudo code. It seems XZR shouldn't be accepted by the assembler after all, abandoning this.

Revision Contents

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llvm/
lib/
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AArch64/
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test/
MC/
AArch64/
SVE/
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Diff 446837

llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td

Show First 20 Lines • Show All 880 Lines • ▼ Show 20 Lines class LD1RQPat<ValueType vt1, ValueType vt2, SDPatternOperator op, Instruction load_instr, Instruction ptrue> :
(load_instr (ptrue 31), GPR64sp:$Xn, 0)>; (load_instr (ptrue 31), GPR64sp:$Xn, 0)>;
} }
def : LD1RQPat<nxv16i8, v16i8, AArch64duplane128, LD1RQ_B_IMM, PTRUE_B>; def : LD1RQPat<nxv16i8, v16i8, AArch64duplane128, LD1RQ_B_IMM, PTRUE_B>;
def : LD1RQPat<nxv8i16, v8i16, AArch64duplane128, LD1RQ_H_IMM, PTRUE_H>; def : LD1RQPat<nxv8i16, v8i16, AArch64duplane128, LD1RQ_H_IMM, PTRUE_H>;
def : LD1RQPat<nxv4i32, v4i32, AArch64duplane128, LD1RQ_W_IMM, PTRUE_S>; def : LD1RQPat<nxv4i32, v4i32, AArch64duplane128, LD1RQ_W_IMM, PTRUE_S>;
def : LD1RQPat<nxv2i64, v2i64, AArch64duplane128, LD1RQ_D_IMM, PTRUE_D>; def : LD1RQPat<nxv2i64, v2i64, AArch64duplane128, LD1RQ_D_IMM, PTRUE_D>;
// continuous load with reg+reg addressing. // continuous load with reg+reg addressing.
defm LD1B : sve_mem_cld_ss<0b0000, "ld1b", Z_b, ZPR8, GPR64NoXZRshifted8>; defm LD1B : sve_mem_cld_ss<0b0000, "ld1b", Z_b, ZPR8, GPR64shifted8>;
defm LD1B_H : sve_mem_cld_ss<0b0001, "ld1b", Z_h, ZPR16, GPR64NoXZRshifted8>; defm LD1B_H : sve_mem_cld_ss<0b0001, "ld1b", Z_h, ZPR16, GPR64shifted8>;
defm LD1B_S : sve_mem_cld_ss<0b0010, "ld1b", Z_s, ZPR32, GPR64NoXZRshifted8>; defm LD1B_S : sve_mem_cld_ss<0b0010, "ld1b", Z_s, ZPR32, GPR64shifted8>;
defm LD1B_D : sve_mem_cld_ss<0b0011, "ld1b", Z_d, ZPR64, GPR64NoXZRshifted8>; defm LD1B_D : sve_mem_cld_ss<0b0011, "ld1b", Z_d, ZPR64, GPR64shifted8>;
defm LD1SW_D : sve_mem_cld_ss<0b0100, "ld1sw", Z_d, ZPR64, GPR64NoXZRshifted32>; defm LD1SW_D : sve_mem_cld_ss<0b0100, "ld1sw", Z_d, ZPR64, GPR64shifted32>;
defm LD1H : sve_mem_cld_ss<0b0101, "ld1h", Z_h, ZPR16, GPR64NoXZRshifted16>; defm LD1H : sve_mem_cld_ss<0b0101, "ld1h", Z_h, ZPR16, GPR64shifted16>;
defm LD1H_S : sve_mem_cld_ss<0b0110, "ld1h", Z_s, ZPR32, GPR64NoXZRshifted16>; defm LD1H_S : sve_mem_cld_ss<0b0110, "ld1h", Z_s, ZPR32, GPR64shifted16>;
defm LD1H_D : sve_mem_cld_ss<0b0111, "ld1h", Z_d, ZPR64, GPR64NoXZRshifted16>; defm LD1H_D : sve_mem_cld_ss<0b0111, "ld1h", Z_d, ZPR64, GPR64shifted16>;
defm LD1SH_D : sve_mem_cld_ss<0b1000, "ld1sh", Z_d, ZPR64, GPR64NoXZRshifted16>; defm LD1SH_D : sve_mem_cld_ss<0b1000, "ld1sh", Z_d, ZPR64, GPR64shifted16>;
defm LD1SH_S : sve_mem_cld_ss<0b1001, "ld1sh", Z_s, ZPR32, GPR64NoXZRshifted16>; defm LD1SH_S : sve_mem_cld_ss<0b1001, "ld1sh", Z_s, ZPR32, GPR64shifted16>;
defm LD1W : sve_mem_cld_ss<0b1010, "ld1w", Z_s, ZPR32, GPR64NoXZRshifted32>; defm LD1W : sve_mem_cld_ss<0b1010, "ld1w", Z_s, ZPR32, GPR64shifted32>;
defm LD1W_D : sve_mem_cld_ss<0b1011, "ld1w", Z_d, ZPR64, GPR64NoXZRshifted32>; defm LD1W_D : sve_mem_cld_ss<0b1011, "ld1w", Z_d, ZPR64, GPR64shifted32>;
defm LD1SB_D : sve_mem_cld_ss<0b1100, "ld1sb", Z_d, ZPR64, GPR64NoXZRshifted8>; defm LD1SB_D : sve_mem_cld_ss<0b1100, "ld1sb", Z_d, ZPR64, GPR64shifted8>;
defm LD1SB_S : sve_mem_cld_ss<0b1101, "ld1sb", Z_s, ZPR32, GPR64NoXZRshifted8>; defm LD1SB_S : sve_mem_cld_ss<0b1101, "ld1sb", Z_s, ZPR32, GPR64shifted8>;
defm LD1SB_H : sve_mem_cld_ss<0b1110, "ld1sb", Z_h, ZPR16, GPR64NoXZRshifted8>; defm LD1SB_H : sve_mem_cld_ss<0b1110, "ld1sb", Z_h, ZPR16, GPR64shifted8>;
defm LD1D : sve_mem_cld_ss<0b1111, "ld1d", Z_d, ZPR64, GPR64NoXZRshifted64>; defm LD1D : sve_mem_cld_ss<0b1111, "ld1d", Z_d, ZPR64, GPR64shifted64>;
} // End HasSVEorSME } // End HasSVEorSME
let Predicates = [HasSVE] in { let Predicates = [HasSVE] in {
// non-faulting continuous load with reg+immediate // non-faulting continuous load with reg+immediate
defm LDNF1B_IMM : sve_mem_cldnf_si<0b0000, "ldnf1b", Z_b, ZPR8>; defm LDNF1B_IMM : sve_mem_cldnf_si<0b0000, "ldnf1b", Z_b, ZPR8>;
defm LDNF1B_H_IMM : sve_mem_cldnf_si<0b0001, "ldnf1b", Z_h, ZPR16>; defm LDNF1B_H_IMM : sve_mem_cldnf_si<0b0001, "ldnf1b", Z_h, ZPR16>;
defm LDNF1B_S_IMM : sve_mem_cldnf_si<0b0010, "ldnf1b", Z_s, ZPR32>; defm LDNF1B_S_IMM : sve_mem_cldnf_si<0b0010, "ldnf1b", Z_s, ZPR32>;
defm LDNF1B_D_IMM : sve_mem_cldnf_si<0b0011, "ldnf1b", Z_d, ZPR64>; defm LDNF1B_D_IMM : sve_mem_cldnf_si<0b0011, "ldnf1b", Z_d, ZPR64>;
▲ Show 20 Lines • Show All 280 Lines • ▼ Show 20 Lineslet Predicates = [HasSVEorSME] in {
defm ST1H_IMM : sve_mem_cst_si<0b01, 0b01, "st1h", Z_h, ZPR16>; defm ST1H_IMM : sve_mem_cst_si<0b01, 0b01, "st1h", Z_h, ZPR16>;
defm ST1H_S_IMM : sve_mem_cst_si<0b01, 0b10, "st1h", Z_s, ZPR32>; defm ST1H_S_IMM : sve_mem_cst_si<0b01, 0b10, "st1h", Z_s, ZPR32>;
defm ST1H_D_IMM : sve_mem_cst_si<0b01, 0b11, "st1h", Z_d, ZPR64>; defm ST1H_D_IMM : sve_mem_cst_si<0b01, 0b11, "st1h", Z_d, ZPR64>;
defm ST1W_IMM : sve_mem_cst_si<0b10, 0b10, "st1w", Z_s, ZPR32>; defm ST1W_IMM : sve_mem_cst_si<0b10, 0b10, "st1w", Z_s, ZPR32>;
defm ST1W_D_IMM : sve_mem_cst_si<0b10, 0b11, "st1w", Z_d, ZPR64>; defm ST1W_D_IMM : sve_mem_cst_si<0b10, 0b11, "st1w", Z_d, ZPR64>;
defm ST1D_IMM : sve_mem_cst_si<0b11, 0b11, "st1d", Z_d, ZPR64>; defm ST1D_IMM : sve_mem_cst_si<0b11, 0b11, "st1d", Z_d, ZPR64>;
// contiguous store with reg+reg addressing. // contiguous store with reg+reg addressing.
defm ST1B : sve_mem_cst_ss<0b0000, "st1b", Z_b, ZPR8, GPR64NoXZRshifted8>; defm ST1B : sve_mem_cst_ss<0b0000, "st1b", Z_b, ZPR8, GPR64shifted8>;
defm ST1B_H : sve_mem_cst_ss<0b0001, "st1b", Z_h, ZPR16, GPR64NoXZRshifted8>; defm ST1B_H : sve_mem_cst_ss<0b0001, "st1b", Z_h, ZPR16, GPR64shifted8>;
defm ST1B_S : sve_mem_cst_ss<0b0010, "st1b", Z_s, ZPR32, GPR64NoXZRshifted8>; defm ST1B_S : sve_mem_cst_ss<0b0010, "st1b", Z_s, ZPR32, GPR64shifted8>;
defm ST1B_D : sve_mem_cst_ss<0b0011, "st1b", Z_d, ZPR64, GPR64NoXZRshifted8>; defm ST1B_D : sve_mem_cst_ss<0b0011, "st1b", Z_d, ZPR64, GPR64shifted8>;
defm ST1H : sve_mem_cst_ss<0b0101, "st1h", Z_h, ZPR16, GPR64NoXZRshifted16>; defm ST1H : sve_mem_cst_ss<0b0101, "st1h", Z_h, ZPR16, GPR64shifted16>;
defm ST1H_S : sve_mem_cst_ss<0b0110, "st1h", Z_s, ZPR32, GPR64NoXZRshifted16>; defm ST1H_S : sve_mem_cst_ss<0b0110, "st1h", Z_s, ZPR32, GPR64shifted16>;
defm ST1H_D : sve_mem_cst_ss<0b0111, "st1h", Z_d, ZPR64, GPR64NoXZRshifted16>; defm ST1H_D : sve_mem_cst_ss<0b0111, "st1h", Z_d, ZPR64, GPR64shifted16>;
defm ST1W : sve_mem_cst_ss<0b1010, "st1w", Z_s, ZPR32, GPR64NoXZRshifted32>; defm ST1W : sve_mem_cst_ss<0b1010, "st1w", Z_s, ZPR32, GPR64shifted32>;
defm ST1W_D : sve_mem_cst_ss<0b1011, "st1w", Z_d, ZPR64, GPR64NoXZRshifted32>; defm ST1W_D : sve_mem_cst_ss<0b1011, "st1w", Z_d, ZPR64, GPR64shifted32>;
defm ST1D : sve_mem_cst_ss<0b1111, "st1d", Z_d, ZPR64, GPR64NoXZRshifted64>; defm ST1D : sve_mem_cst_ss<0b1111, "st1d", Z_d, ZPR64, GPR64shifted64>;
} // End HasSVEorSME } // End HasSVEorSME
let Predicates = [HasSVE] in { let Predicates = [HasSVE] in {
// Scatters using unpacked, unscaled 32-bit offsets, e.g. // Scatters using unpacked, unscaled 32-bit offsets, e.g.
// st1h z0.d, p0, [x0, z0.d, uxtw] // st1h z0.d, p0, [x0, z0.d, uxtw]
defm SST1B_D : sve_mem_64b_sst_sv_32_unscaled<0b000, "st1b", AArch64st1_scatter_sxtw, AArch64st1_scatter_uxtw, ZPR64ExtSXTW8Only, ZPR64ExtUXTW8Only, nxv2i8>; defm SST1B_D : sve_mem_64b_sst_sv_32_unscaled<0b000, "st1b", AArch64st1_scatter_sxtw, AArch64st1_scatter_uxtw, ZPR64ExtSXTW8Only, ZPR64ExtUXTW8Only, nxv2i8>;
defm SST1H_D : sve_mem_64b_sst_sv_32_unscaled<0b010, "st1h", AArch64st1_scatter_sxtw, AArch64st1_scatter_uxtw, ZPR64ExtSXTW8, ZPR64ExtUXTW8, nxv2i16>; defm SST1H_D : sve_mem_64b_sst_sv_32_unscaled<0b010, "st1h", AArch64st1_scatter_sxtw, AArch64st1_scatter_uxtw, ZPR64ExtSXTW8, ZPR64ExtUXTW8, nxv2i16>;
defm SST1W_D : sve_mem_64b_sst_sv_32_unscaled<0b100, "st1w", AArch64st1_scatter_sxtw, AArch64st1_scatter_uxtw, ZPR64ExtSXTW8, ZPR64ExtUXTW8, nxv2i32>; defm SST1W_D : sve_mem_64b_sst_sv_32_unscaled<0b100, "st1w", AArch64st1_scatter_sxtw, AArch64st1_scatter_uxtw, ZPR64ExtSXTW8, ZPR64ExtUXTW8, nxv2i32>;
▲ Show 20 Lines • Show All 2,274 Lines • Show Last 20 Lines

llvm/test/MC/AArch64/SVE/ld1b-diagnostics.s

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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: ld1b { v0.2d }, p0/z, [x1, #1, MUL VL] // CHECK-NEXT: ld1b { v0.2d }, p0/z, [x1, #1, MUL VL]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Invalid scalar + scalar addressing modes // Invalid scalar + scalar addressing modes
ld1b z0.b, p0/z, [x0, xzr]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 without shift
// CHECK-NEXT: ld1b z0.b, p0/z, [x0, xzr]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ld1b z0.b, p0/z, [x0, x0, lsl #1] ld1b z0.b, p0/z, [x0, x0, lsl #1]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 without shift // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, without shift
// CHECK-NEXT: ld1b z0.b, p0/z, [x0, x0, lsl #1] // CHECK-NEXT: ld1b z0.b, p0/z, [x0, x0, lsl #1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ld1b z0.b, p0/z, [x0, w0] ld1b z0.b, p0/z, [x0, w0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 without shift // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, without shift
// CHECK-NEXT: ld1b z0.b, p0/z, [x0, w0] // CHECK-NEXT: ld1b z0.b, p0/z, [x0, w0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ld1b z0.b, p0/z, [x0, w0, uxtw] ld1b z0.b, p0/z, [x0, w0, uxtw]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 without shift // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, without shift
// CHECK-NEXT: ld1b z0.b, p0/z, [x0, w0, uxtw] // CHECK-NEXT: ld1b z0.b, p0/z, [x0, w0, uxtw]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Invalid scalar + vector addressing modes // Invalid scalar + vector addressing modes
ld1b z0.d, p0/z, [x0, z0.b] ld1b z0.d, p0/z, [x0, z0.b]
▲ Show 20 Lines • Show All 78 Lines • Show Last 20 Lines

llvm/test/MC/AArch64/SVE/ld1b.s

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// CHECK-ERROR: instruction requires: sve or sme // CHECK-ERROR: instruction requires: sve or sme
// CHECK-UNKNOWN: 55 55 55 a4 <unknown> // CHECK-UNKNOWN: 55 55 55 a4 <unknown>
ld1b { z23.d }, p3/z, [x13, x8] ld1b { z23.d }, p3/z, [x13, x8]
// CHECK-INST: ld1b { z23.d }, p3/z, [x13, x8] // CHECK-INST: ld1b { z23.d }, p3/z, [x13, x8]
// CHECK-ENCODING: [0xb7,0x4d,0x68,0xa4] // CHECK-ENCODING: [0xb7,0x4d,0x68,0xa4]
// CHECK-ERROR: instruction requires: sve or sme // CHECK-ERROR: instruction requires: sve or sme
// CHECK-UNKNOWN: b7 4d 68 a4 <unknown> // CHECK-UNKNOWN: b7 4d 68 a4 <unknown>
ld1b { z0.b }, p0/z, [x0, xzr]
// CHECK-INST: ld1b { z0.b }, p0/z, [x0, xzr]
// CHECK-ENCODING: [0x00,0x40,0x1f,0xa4]
// CHECK-ERROR: instruction requires: sve or sme
// CHECK-UNKNOWN: 00 40 1f a4 <unknown>
ld1b { z0.h }, p0/z, [x0, xzr]
// CHECK-INST: ld1b { z0.h }, p0/z, [x0, xzr]
// CHECK-ENCODING: [0x00,0x40,0x3f,0xa4]
// CHECK-ERROR: instruction requires: sve or sme
// CHECK-UNKNOWN: 00 40 3f a4 <unknown>
ld1b { z0.s }, p0/z, [x0, xzr]
// CHECK-INST: ld1b { z0.s }, p0/z, [x0, xzr]
// CHECK-ENCODING: [0x00,0x40,0x5f,0xa4]
// CHECK-ERROR: instruction requires: sve or sme
// CHECK-UNKNOWN: 00 40 5f a4 <unknown>
ld1b { z0.d }, p0/z, [x0, xzr]
// CHECK-INST: ld1b { z0.d }, p0/z, [x0, xzr]
// CHECK-ENCODING: [0x00,0x40,0x7f,0xa4]
// CHECK-ERROR: instruction requires: sve or sme
// CHECK-UNKNOWN: 00 40 7f a4 <unknown>

llvm/test/MC/AArch64/SVE/ld1d-diagnostics.s

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// CHECK-NEXT: ld1d { v0.2d }, p0/z, [x1, #1, MUL VL] // CHECK-NEXT: ld1d { v0.2d }, p0/z, [x1, #1, MUL VL]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Invalid scalar + scalar addressing modes // Invalid scalar + scalar addressing modes
ld1d z0.d, p0/z, [x0, x0] ld1d z0.d, p0/z, [x0, x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3' // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #3'
// CHECK-NEXT: ld1d z0.d, p0/z, [x0, x0] // CHECK-NEXT: ld1d z0.d, p0/z, [x0, x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ld1d z0.d, p0/z, [x0, xzr]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3'
// CHECK-NEXT: ld1d z0.d, p0/z, [x0, xzr]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ld1d z0.d, p0/z, [x0, x0, lsl #2] ld1d z0.d, p0/z, [x0, x0, lsl #2]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3' // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #3'
// CHECK-NEXT: ld1d z0.d, p0/z, [x0, x0, lsl #2] // CHECK-NEXT: ld1d z0.d, p0/z, [x0, x0, lsl #2]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ld1d z0.d, p0/z, [x0, w0] ld1d z0.d, p0/z, [x0, w0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3' // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #3'
// CHECK-NEXT: ld1d z0.d, p0/z, [x0, w0] // CHECK-NEXT: ld1d z0.d, p0/z, [x0, w0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ld1d z0.d, p0/z, [x0, w0, uxtw] ld1d z0.d, p0/z, [x0, w0, uxtw]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3' // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #3'
// CHECK-NEXT: ld1d z0.d, p0/z, [x0, w0, uxtw] // CHECK-NEXT: ld1d z0.d, p0/z, [x0, w0, uxtw]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Invalid scalar + vector addressing modes // Invalid scalar + vector addressing modes
ld1d z0.d, p0/z, [x0, z0.s] ld1d z0.d, p0/z, [x0, z0.s]
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llvm/test/MC/AArch64/SVE/ld1d.s

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// CHECK-ERROR: instruction requires: sve or sme // CHECK-ERROR: instruction requires: sve or sme
// CHECK-UNKNOWN: f7 4f e8 a5 <unknown> // CHECK-UNKNOWN: f7 4f e8 a5 <unknown>
ld1d { z23.d }, p3/z, [x13, x8, lsl #3] ld1d { z23.d }, p3/z, [x13, x8, lsl #3]
// CHECK-INST: ld1d { z23.d }, p3/z, [x13, x8, lsl #3] // CHECK-INST: ld1d { z23.d }, p3/z, [x13, x8, lsl #3]
// CHECK-ENCODING: [0xb7,0x4d,0xe8,0xa5] // CHECK-ENCODING: [0xb7,0x4d,0xe8,0xa5]
// CHECK-ERROR: instruction requires: sve or sme // CHECK-ERROR: instruction requires: sve or sme
// CHECK-UNKNOWN: b7 4d e8 a5 <unknown> // CHECK-UNKNOWN: b7 4d e8 a5 <unknown>
ld1d { z0.d }, p0/z, [x0, xzr, lsl #3]
// CHECK-INST: ld1d { z0.d }, p0/z, [x0, xzr, lsl #3]
// CHECK-ENCODING: [0x00,0x40,0xff,0xa5]
// CHECK-ERROR: instruction requires: sve or sme
// CHECK-UNKNOWN: 00 40 ff a5 <unknown>

llvm/test/MC/AArch64/SVE/ld1h-diagnostics.s

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// CHECK-NEXT: ld1h { v0.2d }, p0/z, [x1, #1, MUL VL] // CHECK-NEXT: ld1h { v0.2d }, p0/z, [x1, #1, MUL VL]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Invalid scalar + scalar addressing modes // Invalid scalar + scalar addressing modes
ld1h z0.h, p0/z, [x0, x0] ld1h z0.h, p0/z, [x0, x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1' // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #1'
// CHECK-NEXT: ld1h z0.h, p0/z, [x0, x0] // CHECK-NEXT: ld1h z0.h, p0/z, [x0, x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ld1h z0.h, p0/z, [x0, xzr]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1'
// CHECK-NEXT: ld1h z0.h, p0/z, [x0, xzr]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ld1h z0.h, p0/z, [x0, x0, lsl #2] ld1h z0.h, p0/z, [x0, x0, lsl #2]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1' // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #1'
// CHECK-NEXT: ld1h z0.h, p0/z, [x0, x0, lsl #2] // CHECK-NEXT: ld1h z0.h, p0/z, [x0, x0, lsl #2]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ld1h z0.h, p0/z, [x0, w0] ld1h z0.h, p0/z, [x0, w0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1' // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #1'
// CHECK-NEXT: ld1h z0.h, p0/z, [x0, w0] // CHECK-NEXT: ld1h z0.h, p0/z, [x0, w0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ld1h z0.h, p0/z, [x0, w0, uxtw] ld1h z0.h, p0/z, [x0, w0, uxtw]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1' // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #1'
// CHECK-NEXT: ld1h z0.h, p0/z, [x0, w0, uxtw] // CHECK-NEXT: ld1h z0.h, p0/z, [x0, w0, uxtw]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Invalid scalar + vector addressing modes // Invalid scalar + vector addressing modes
ld1h z0.d, p0/z, [x0, z0.h] ld1h z0.d, p0/z, [x0, z0.h]
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llvm/test/MC/AArch64/SVE/ld1h.s

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// CHECK-ERROR: instruction requires: sve or sme // CHECK-ERROR: instruction requires: sve or sme
// CHECK-UNKNOWN: 55 55 d5 a4 <unknown> // CHECK-UNKNOWN: 55 55 d5 a4 <unknown>
ld1h { z23.d }, p3/z, [x13, x8, lsl #1] ld1h { z23.d }, p3/z, [x13, x8, lsl #1]
// CHECK-INST: ld1h { z23.d }, p3/z, [x13, x8, lsl #1] // CHECK-INST: ld1h { z23.d }, p3/z, [x13, x8, lsl #1]
// CHECK-ENCODING: [0xb7,0x4d,0xe8,0xa4] // CHECK-ENCODING: [0xb7,0x4d,0xe8,0xa4]
// CHECK-ERROR: instruction requires: sve or sme // CHECK-ERROR: instruction requires: sve or sme
// CHECK-UNKNOWN: b7 4d e8 a4 <unknown> // CHECK-UNKNOWN: b7 4d e8 a4 <unknown>
ld1h { z0.h }, p0/z, [x0, xzr, lsl #1]
// CHECK-INST: ld1h { z0.h }, p0/z, [x0, xzr, lsl #1]
// CHECK-ENCODING: [0x00,0x40,0xbf,0xa4]
// CHECK-ERROR: instruction requires: sve or sme
// CHECK-UNKNOWN: 00 40 bf a4 <unknown>
ld1h { z0.s }, p0/z, [x0, xzr, lsl #1]
// CHECK-INST: ld1h { z0.s }, p0/z, [x0, xzr, lsl #1]
// CHECK-ENCODING: [0x00,0x40,0xdf,0xa4]
// CHECK-ERROR: instruction requires: sve or sme
// CHECK-UNKNOWN: 00 40 df a4 <unknown>
ld1h { z0.d }, p0/z, [x0, xzr, lsl #1]
// CHECK-INST: ld1h { z0.d }, p0/z, [x0, xzr, lsl #1]
// CHECK-ENCODING: [0x00,0x40,0xff,0xa4]
// CHECK-ERROR: instruction requires: sve or sme
// CHECK-UNKNOWN: 00 40 ff a4 <unknown>

llvm/test/MC/AArch64/SVE/ld1sb-diagnostics.s

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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: ld1sb { v0.2d }, p0/z, [x1, #1, MUL VL] // CHECK-NEXT: ld1sb { v0.2d }, p0/z, [x1, #1, MUL VL]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Invalid scalar + scalar addressing modes // Invalid scalar + scalar addressing modes
ld1sb z0.h, p0/z, [x0, xzr]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 without shift
// CHECK-NEXT: ld1sb z0.h, p0/z, [x0, xzr]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ld1sb z0.h, p0/z, [x0, x0, lsl #1] ld1sb z0.h, p0/z, [x0, x0, lsl #1]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 without shift // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, without shift
// CHECK-NEXT: ld1sb z0.h, p0/z, [x0, x0, lsl #1] // CHECK-NEXT: ld1sb z0.h, p0/z, [x0, x0, lsl #1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ld1sb z0.h, p0/z, [x0, w0] ld1sb z0.h, p0/z, [x0, w0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 without shift // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, without shift
// CHECK-NEXT: ld1sb z0.h, p0/z, [x0, w0] // CHECK-NEXT: ld1sb z0.h, p0/z, [x0, w0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ld1sb z0.h, p0/z, [x0, w0, uxtw] ld1sb z0.h, p0/z, [x0, w0, uxtw]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 without shift // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, without shift
// CHECK-NEXT: ld1sb z0.h, p0/z, [x0, w0, uxtw] // CHECK-NEXT: ld1sb z0.h, p0/z, [x0, w0, uxtw]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Invalid scalar + vector addressing modes // Invalid scalar + vector addressing modes
ld1sb z0.d, p0/z, [x0, z0.b] ld1sb z0.d, p0/z, [x0, z0.b]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
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llvm/test/MC/AArch64/SVE/ld1sb.s

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// CHECK-ERROR: instruction requires: sve or sme // CHECK-ERROR: instruction requires: sve or sme
// CHECK-UNKNOWN: 55 55 b5 a5 <unknown> // CHECK-UNKNOWN: 55 55 b5 a5 <unknown>
ld1sb { z23.d }, p3/z, [x13, x8] ld1sb { z23.d }, p3/z, [x13, x8]
// CHECK-INST: ld1sb { z23.d }, p3/z, [x13, x8] // CHECK-INST: ld1sb { z23.d }, p3/z, [x13, x8]
// CHECK-ENCODING: [0xb7,0x4d,0x88,0xa5] // CHECK-ENCODING: [0xb7,0x4d,0x88,0xa5]
// CHECK-ERROR: instruction requires: sve or sme // CHECK-ERROR: instruction requires: sve or sme
// CHECK-UNKNOWN: b7 4d 88 a5 <unknown> // CHECK-UNKNOWN: b7 4d 88 a5 <unknown>
ld1sb { z0.h }, p0/z, [x0, xzr]
// CHECK-INST: ld1sb { z0.h }, p0/z, [x0, xzr]
// CHECK-ENCODING: [0x00,0x40,0xdf,0xa5]
// CHECK-ERROR: instruction requires: sve or sme
// CHECK-UNKNOWN: 00 40 df a5 <unknown>
ld1sb { z0.s }, p0/z, [x0, xzr]
// CHECK-INST: ld1sb { z0.s }, p0/z, [x0, xzr]
// CHECK-ENCODING: [0x00,0x40,0xbf,0xa5]
// CHECK-ERROR: instruction requires: sve or sme
// CHECK-UNKNOWN: 00 40 bf a5 <unknown>
ld1sb { z0.d }, p0/z, [x0, xzr]
// CHECK-INST: ld1sb { z0.d }, p0/z, [x0, xzr]
// CHECK-ENCODING: [0x00,0x40,0x9f,0xa5]
// CHECK-ERROR: instruction requires: sve or sme
// CHECK-UNKNOWN: 00 40 9f a5 <unknown>

llvm/test/MC/AArch64/SVE/ld1sh-diagnostics.s

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// CHECK-NEXT: ld1sh { v0.2d }, p0/z, [x1, #1, MUL VL] // CHECK-NEXT: ld1sh { v0.2d }, p0/z, [x1, #1, MUL VL]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Invalid scalar + scalar addressing modes // Invalid scalar + scalar addressing modes
ld1sh z0.s, p0/z, [x0, x0] ld1sh z0.s, p0/z, [x0, x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1' // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #1'
// CHECK-NEXT: ld1sh z0.s, p0/z, [x0, x0] // CHECK-NEXT: ld1sh z0.s, p0/z, [x0, x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ld1sh z0.s, p0/z, [x0, xzr]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1'
// CHECK-NEXT: ld1sh z0.s, p0/z, [x0, xzr]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ld1sh z0.s, p0/z, [x0, x0, lsl #2] ld1sh z0.s, p0/z, [x0, x0, lsl #2]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1' // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #1'
// CHECK-NEXT: ld1sh z0.s, p0/z, [x0, x0, lsl #2] // CHECK-NEXT: ld1sh z0.s, p0/z, [x0, x0, lsl #2]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ld1sh z0.s, p0/z, [x0, w0] ld1sh z0.s, p0/z, [x0, w0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1' // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #1'
// CHECK-NEXT: ld1sh z0.s, p0/z, [x0, w0] // CHECK-NEXT: ld1sh z0.s, p0/z, [x0, w0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ld1sh z0.s, p0/z, [x0, w0, uxtw] ld1sh z0.s, p0/z, [x0, w0, uxtw]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1' // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #1'
// CHECK-NEXT: ld1sh z0.s, p0/z, [x0, w0, uxtw] // CHECK-NEXT: ld1sh z0.s, p0/z, [x0, w0, uxtw]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Invalid scalar + vector addressing modes // Invalid scalar + vector addressing modes
ld1sh z0.d, p0/z, [x0, z0.h] ld1sh z0.d, p0/z, [x0, z0.h]
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llvm/test/MC/AArch64/SVE/ld1sh.s

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// CHECK-ERROR: instruction requires: sve or sme // CHECK-ERROR: instruction requires: sve or sme
// CHECK-UNKNOWN: 55 55 35 a5 <unknown> // CHECK-UNKNOWN: 55 55 35 a5 <unknown>
ld1sh { z23.d }, p3/z, [x13, x8, lsl #1] ld1sh { z23.d }, p3/z, [x13, x8, lsl #1]
// CHECK-INST: ld1sh { z23.d }, p3/z, [x13, x8, lsl #1] // CHECK-INST: ld1sh { z23.d }, p3/z, [x13, x8, lsl #1]
// CHECK-ENCODING: [0xb7,0x4d,0x08,0xa5] // CHECK-ENCODING: [0xb7,0x4d,0x08,0xa5]
// CHECK-ERROR: instruction requires: sve or sme // CHECK-ERROR: instruction requires: sve or sme
// CHECK-UNKNOWN: b7 4d 08 a5 <unknown> // CHECK-UNKNOWN: b7 4d 08 a5 <unknown>
ld1sh { z0.s }, p0/z, [x0, xzr, lsl #1]
// CHECK-INST: ld1sh { z0.s }, p0/z, [x0, xzr, lsl #1]
// CHECK-ENCODING: [0x00,0x40,0x3f,0xa5]
// CHECK-ERROR: instruction requires: sve or sme
// CHECK-UNKNOWN: 00 40 3f a5 <unknown>
ld1sh { z0.d }, p0/z, [x0, xzr, lsl #1]
// CHECK-INST: ld1sh { z0.d }, p0/z, [x0, xzr, lsl #1]
// CHECK-ENCODING: [0x00,0x40,0x1f,0xa5]
// CHECK-ERROR: instruction requires: sve or sme
// CHECK-UNKNOWN: 00 40 1f a5 <unknown>

llvm/test/MC/AArch64/SVE/ld1sw-diagnostics.s

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// CHECK-NEXT: ld1sw { v0.2d }, p0/z, [x1, #1, MUL VL] // CHECK-NEXT: ld1sw { v0.2d }, p0/z, [x1, #1, MUL VL]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Invalid scalar + scalar addressing modes // Invalid scalar + scalar addressing modes
ld1sw z0.d, p0/z, [x0, x0] ld1sw z0.d, p0/z, [x0, x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2' // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #2'
// CHECK-NEXT: ld1sw z0.d, p0/z, [x0, x0] // CHECK-NEXT: ld1sw z0.d, p0/z, [x0, x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ld1sw z0.d, p0/z, [x0, xzr]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2'
// CHECK-NEXT: ld1sw z0.d, p0/z, [x0, xzr]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ld1sw z0.d, p0/z, [x0, x0, lsl #3] ld1sw z0.d, p0/z, [x0, x0, lsl #3]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2' // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #2'
// CHECK-NEXT: ld1sw z0.d, p0/z, [x0, x0, lsl #3] // CHECK-NEXT: ld1sw z0.d, p0/z, [x0, x0, lsl #3]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ld1sw z0.d, p0/z, [x0, w0] ld1sw z0.d, p0/z, [x0, w0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2' // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #2'
// CHECK-NEXT: ld1sw z0.d, p0/z, [x0, w0] // CHECK-NEXT: ld1sw z0.d, p0/z, [x0, w0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ld1sw z0.d, p0/z, [x0, w0, uxtw] ld1sw z0.d, p0/z, [x0, w0, uxtw]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2' // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #2'
// CHECK-NEXT: ld1sw z0.d, p0/z, [x0, w0, uxtw] // CHECK-NEXT: ld1sw z0.d, p0/z, [x0, w0, uxtw]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Invalid scalar + vector addressing modes // Invalid scalar + vector addressing modes
ld1sw z0.d, p0/z, [x0, z0.h] ld1sw z0.d, p0/z, [x0, z0.h]
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llvm/test/MC/AArch64/SVE/ld1sw.s

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// CHECK-ERROR: instruction requires: sve or sme // CHECK-ERROR: instruction requires: sve or sme
// CHECK-UNKNOWN: f7 4f 88 a4 <unknown> // CHECK-UNKNOWN: f7 4f 88 a4 <unknown>
ld1sw { z23.d }, p3/z, [x13, x8, lsl #2] ld1sw { z23.d }, p3/z, [x13, x8, lsl #2]
// CHECK-INST: ld1sw { z23.d }, p3/z, [x13, x8, lsl #2] // CHECK-INST: ld1sw { z23.d }, p3/z, [x13, x8, lsl #2]
// CHECK-ENCODING: [0xb7,0x4d,0x88,0xa4] // CHECK-ENCODING: [0xb7,0x4d,0x88,0xa4]
// CHECK-ERROR: instruction requires: sve or sme // CHECK-ERROR: instruction requires: sve or sme
// CHECK-UNKNOWN: b7 4d 88 a4 <unknown> // CHECK-UNKNOWN: b7 4d 88 a4 <unknown>
ld1sw { z0.d }, p0/z, [x0, xzr, lsl #2]
// CHECK-INST: ld1sw { z0.d }, p0/z, [x0, xzr, lsl #2]
// CHECK-ENCODING: [0x00,0x40,0x9f,0xa4]
// CHECK-ERROR: instruction requires: sve or sme
// CHECK-UNKNOWN: 00 40 9f a4 <unknown>

llvm/test/MC/AArch64/SVE/ld1w-diagnostics.s

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// CHECK-NEXT: ld1w { v0.2d }, p0/z, [x1, #1, MUL VL] // CHECK-NEXT: ld1w { v0.2d }, p0/z, [x1, #1, MUL VL]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Invalid scalar + scalar addressing modes // Invalid scalar + scalar addressing modes
ld1w z0.s, p0/z, [x0, x0] ld1w z0.s, p0/z, [x0, x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2' // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #2'
// CHECK-NEXT: ld1w z0.s, p0/z, [x0, x0] // CHECK-NEXT: ld1w z0.s, p0/z, [x0, x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ld1w z0.s, p0/z, [x0, xzr]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2'
// CHECK-NEXT: ld1w z0.s, p0/z, [x0, xzr]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ld1w z0.s, p0/z, [x0, x0, lsl #3] ld1w z0.s, p0/z, [x0, x0, lsl #3]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2' // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #2'
// CHECK-NEXT: ld1w z0.s, p0/z, [x0, x0, lsl #3] // CHECK-NEXT: ld1w z0.s, p0/z, [x0, x0, lsl #3]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ld1w z0.s, p0/z, [x0, w0] ld1w z0.s, p0/z, [x0, w0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2' // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #2'
// CHECK-NEXT: ld1w z0.s, p0/z, [x0, w0] // CHECK-NEXT: ld1w z0.s, p0/z, [x0, w0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ld1w z0.s, p0/z, [x0, w0, uxtw] ld1w z0.s, p0/z, [x0, w0, uxtw]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2' // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #2'
// CHECK-NEXT: ld1w z0.s, p0/z, [x0, w0, uxtw] // CHECK-NEXT: ld1w z0.s, p0/z, [x0, w0, uxtw]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Invalid scalar + vector addressing modes // Invalid scalar + vector addressing modes
ld1w z0.d, p0/z, [x0, z0.h] ld1w z0.d, p0/z, [x0, z0.h]
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llvm/test/MC/AArch64/SVE/ld1w.s

Show First 20 Lines • Show All 68 Lines • ▼ Show 20 Lines
// CHECK-ERROR: instruction requires: sve or sme // CHECK-ERROR: instruction requires: sve or sme
// CHECK-UNKNOWN: 55 55 55 a5 <unknown> // CHECK-UNKNOWN: 55 55 55 a5 <unknown>
ld1w { z23.d }, p3/z, [x13, x8, lsl #2] ld1w { z23.d }, p3/z, [x13, x8, lsl #2]
// CHECK-INST: ld1w { z23.d }, p3/z, [x13, x8, lsl #2] // CHECK-INST: ld1w { z23.d }, p3/z, [x13, x8, lsl #2]
// CHECK-ENCODING: [0xb7,0x4d,0x68,0xa5] // CHECK-ENCODING: [0xb7,0x4d,0x68,0xa5]
// CHECK-ERROR: instruction requires: sve or sme // CHECK-ERROR: instruction requires: sve or sme
// CHECK-UNKNOWN: b7 4d 68 a5 <unknown> // CHECK-UNKNOWN: b7 4d 68 a5 <unknown>
ld1w { z0.s }, p0/z, [x0, xzr, lsl #2]
// CHECK-INST: ld1w { z0.s }, p0/z, [x0, xzr, lsl #2]
// CHECK-ENCODING: [0x00,0x40,0x5f,0xa5]
// CHECK-ERROR: instruction requires: sve or sme
// CHECK-UNKNOWN: 00 40 5f a5 <unknown>
ld1w { z0.d }, p0/z, [x0, xzr, lsl #2]
// CHECK-INST: ld1w { z0.d }, p0/z, [x0, xzr, lsl #2]
// CHECK-ENCODING: [0x00,0x40,0x7f,0xa5]
// CHECK-ERROR: instruction requires: sve or sme
// CHECK-UNKNOWN: 00 40 7f a5 <unknown>

llvm/test/MC/AArch64/SVE/st1b-diagnostics.s

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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: st1b { v0.16b }, p0, [x0] // CHECK-NEXT: st1b { v0.16b }, p0, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Invalid scalar + scalar addressing modes // Invalid scalar + scalar addressing modes
st1b z0.b, p0, [x0, xzr]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 without shift
// CHECK-NEXT: st1b z0.b, p0, [x0, xzr]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
st1b z0.b, p0, [x0, x0, lsl #1] st1b z0.b, p0, [x0, x0, lsl #1]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 without shift // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, without shift
// CHECK-NEXT: st1b z0.b, p0, [x0, x0, lsl #1] // CHECK-NEXT: st1b z0.b, p0, [x0, x0, lsl #1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
st1b z0.b, p0, [x0, w0] st1b z0.b, p0, [x0, w0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 without shift // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, without shift
// CHECK-NEXT: st1b z0.b, p0, [x0, w0] // CHECK-NEXT: st1b z0.b, p0, [x0, w0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
st1b z0.b, p0, [x0, w0, uxtw] st1b z0.b, p0, [x0, w0, uxtw]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 without shift // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, without shift
// CHECK-NEXT: st1b z0.b, p0, [x0, w0, uxtw] // CHECK-NEXT: st1b z0.b, p0, [x0, w0, uxtw]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Invalid scalar + vector addressing modes // Invalid scalar + vector addressing modes
st1b z0.d, p0, [x0, z0.b] st1b z0.d, p0, [x0, z0.b]
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llvm/test/MC/AArch64/SVE/st1b.s

Show First 20 Lines • Show All 122 Lines • ▼ Show 20 Lines
// CHECK-ERROR: instruction requires: sve or sme // CHECK-ERROR: instruction requires: sve or sme
// CHECK-UNKNOWN: 00 40 40 e4 <unknown> // CHECK-UNKNOWN: 00 40 40 e4 <unknown>
st1b { z0.d }, p0, [x0, x0] st1b { z0.d }, p0, [x0, x0]
// CHECK-INST: st1b { z0.d }, p0, [x0, x0] // CHECK-INST: st1b { z0.d }, p0, [x0, x0]
// CHECK-ENCODING: [0x00,0x40,0x60,0xe4] // CHECK-ENCODING: [0x00,0x40,0x60,0xe4]
// CHECK-ERROR: instruction requires: sve or sme // CHECK-ERROR: instruction requires: sve or sme
// CHECK-UNKNOWN: 00 40 60 e4 <unknown> // CHECK-UNKNOWN: 00 40 60 e4 <unknown>
st1b { z0.b }, p0, [x0, xzr]
// CHECK-INST: st1b { z0.b }, p0, [x0, xzr]
// CHECK-ENCODING: [0x00,0x40,0x1f,0xe4]
// CHECK-ERROR: instruction requires: sve or sme
// CHECK-UNKNOWN: 00 40 1f e4 <unknown>
st1b { z0.h }, p0, [x0, xzr]
// CHECK-INST: st1b { z0.h }, p0, [x0, xzr]
// CHECK-ENCODING: [0x00,0x40,0x3f,0xe4]
// CHECK-ERROR: instruction requires: sve or sme
// CHECK-UNKNOWN: 00 40 3f e4 <unknown>
st1b { z0.s }, p0, [x0, xzr]
// CHECK-INST: st1b { z0.s }, p0, [x0, xzr]
// CHECK-ENCODING: [0x00,0x40,0x5f,0xe4]
// CHECK-ERROR: instruction requires: sve or sme
// CHECK-UNKNOWN: 00 40 5f e4 <unknown>
st1b { z0.d }, p0, [x0, xzr]
// CHECK-INST: st1b { z0.d }, p0, [x0, xzr]
// CHECK-ENCODING: [0x00,0x40,0x7f,0xe4]
// CHECK-ERROR: instruction requires: sve or sme
// CHECK-UNKNOWN: 00 40 7f e4 <unknown>

llvm/test/MC/AArch64/SVE/st1d-diagnostics.s

Show First 20 Lines • Show All 49 Lines • ▼ Show 20 Lines
// CHECK-NEXT: st1d { v0.2d }, p0, [x0] // CHECK-NEXT: st1d { v0.2d }, p0, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Invalid scalar + scalar addressing modes // Invalid scalar + scalar addressing modes
st1d z0.d, p0, [x0, x0] st1d z0.d, p0, [x0, x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3' // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #3'
// CHECK-NEXT: st1d z0.d, p0, [x0, x0] // CHECK-NEXT: st1d z0.d, p0, [x0, x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
st1d z0.d, p0, [x0, xzr]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3'
// CHECK-NEXT: st1d z0.d, p0, [x0, xzr]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
st1d z0.d, p0, [x0, x0, lsl #2] st1d z0.d, p0, [x0, x0, lsl #2]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3' // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #3'
// CHECK-NEXT: st1d z0.d, p0, [x0, x0, lsl #2] // CHECK-NEXT: st1d z0.d, p0, [x0, x0, lsl #2]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
st1d z0.d, p0, [x0, w0] st1d z0.d, p0, [x0, w0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3' // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #3'
// CHECK-NEXT: st1d z0.d, p0, [x0, w0] // CHECK-NEXT: st1d z0.d, p0, [x0, w0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
st1d z0.d, p0, [x0, w0, uxtw] st1d z0.d, p0, [x0, w0, uxtw]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3' // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #3'
// CHECK-NEXT: st1d z0.d, p0, [x0, w0, uxtw] // CHECK-NEXT: st1d z0.d, p0, [x0, w0, uxtw]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Invalid scalar + vector addressing modes // Invalid scalar + vector addressing modes
st1d z0.d, p0, [x0, z0.s] st1d z0.d, p0, [x0, z0.s]
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llvm/test/MC/AArch64/SVE/st1d.s

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// CHECK-ERROR: instruction requires: sve or sme // CHECK-ERROR: instruction requires: sve or sme
// CHECK-UNKNOWN: 55 f5 e5 e5 <unknown> // CHECK-UNKNOWN: 55 f5 e5 e5 <unknown>
st1d { z0.d }, p0, [x0, x0, lsl #3] st1d { z0.d }, p0, [x0, x0, lsl #3]
// CHECK-INST: st1d { z0.d }, p0, [x0, x0, lsl #3] // CHECK-INST: st1d { z0.d }, p0, [x0, x0, lsl #3]
// CHECK-ENCODING: [0x00,0x40,0xe0,0xe5] // CHECK-ENCODING: [0x00,0x40,0xe0,0xe5]
// CHECK-ERROR: instruction requires: sve or sme // CHECK-ERROR: instruction requires: sve or sme
// CHECK-UNKNOWN: 00 40 e0 e5 <unknown> // CHECK-UNKNOWN: 00 40 e0 e5 <unknown>
st1d { z0.d }, p0, [x0, xzr, lsl #3]
// CHECK-INST: st1d { z0.d }, p0, [x0, xzr, lsl #3]
// CHECK-ENCODING: [0x00,0x40,0xff,0xe5]
// CHECK-ERROR: instruction requires: sve or sme
// CHECK-UNKNOWN: 00 40 ff e5 <unknown>

llvm/test/MC/AArch64/SVE/st1h-diagnostics.s

Show First 20 Lines • Show All 78 Lines • ▼ Show 20 Lines
// CHECK-NEXT: st1h { v0.8h }, p0, [x0] // CHECK-NEXT: st1h { v0.8h }, p0, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Invalid scalar + scalar addressing modes // Invalid scalar + scalar addressing modes
st1h z0.h, p0, [x0, x0] st1h z0.h, p0, [x0, x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1' // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #1'
// CHECK-NEXT: st1h z0.h, p0, [x0, x0] // CHECK-NEXT: st1h z0.h, p0, [x0, x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
st1h z0.h, p0, [x0, xzr]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1'
// CHECK-NEXT: st1h z0.h, p0, [x0, xzr]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
st1h z0.h, p0, [x0, x0, lsl #2] st1h z0.h, p0, [x0, x0, lsl #2]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1' // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #1'
// CHECK-NEXT: st1h z0.h, p0, [x0, x0, lsl #2] // CHECK-NEXT: st1h z0.h, p0, [x0, x0, lsl #2]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
st1h z0.h, p0, [x0, w0] st1h z0.h, p0, [x0, w0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1' // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #1'
// CHECK-NEXT: st1h z0.h, p0, [x0, w0] // CHECK-NEXT: st1h z0.h, p0, [x0, w0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
st1h z0.h, p0, [x0, w0, uxtw] st1h z0.h, p0, [x0, w0, uxtw]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1' // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #1'
// CHECK-NEXT: st1h z0.h, p0, [x0, w0, uxtw] // CHECK-NEXT: st1h z0.h, p0, [x0, w0, uxtw]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Invalid scalar + vector addressing modes // Invalid scalar + vector addressing modes
st1h z0.d, p0, [x0, z0.h] st1h z0.d, p0, [x0, z0.h]
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llvm/test/MC/AArch64/SVE/st1h.s

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// CHECK-ERROR: instruction requires: sve or sme // CHECK-ERROR: instruction requires: sve or sme
// CHECK-UNKNOWN: 00 40 c0 e4 <unknown> // CHECK-UNKNOWN: 00 40 c0 e4 <unknown>
st1h { z0.d }, p0, [x0, x0, lsl #1] st1h { z0.d }, p0, [x0, x0, lsl #1]
// CHECK-INST: st1h { z0.d }, p0, [x0, x0, lsl #1] // CHECK-INST: st1h { z0.d }, p0, [x0, x0, lsl #1]
// CHECK-ENCODING: [0x00,0x40,0xe0,0xe4] // CHECK-ENCODING: [0x00,0x40,0xe0,0xe4]
// CHECK-ERROR: instruction requires: sve or sme // CHECK-ERROR: instruction requires: sve or sme
// CHECK-UNKNOWN: 00 40 e0 e4 <unknown> // CHECK-UNKNOWN: 00 40 e0 e4 <unknown>
st1h { z0.h }, p0, [x0, xzr, lsl #1]
// CHECK-INST: st1h { z0.h }, p0, [x0, xzr, lsl #1]
// CHECK-ENCODING: [0x00,0x40,0xbf,0xe4]
// CHECK-ERROR: instruction requires: sve or sme
// CHECK-UNKNOWN: 00 40 bf e4 <unknown>
st1h { z0.s }, p0, [x0, xzr, lsl #1]
// CHECK-INST: st1h { z0.s }, p0, [x0, xzr, lsl #1]
// CHECK-ENCODING: [0x00,0x40,0xdf,0xe4]
// CHECK-ERROR: instruction requires: sve or sme
// CHECK-UNKNOWN: 00 40 df e4 <unknown>
st1h { z0.d }, p0, [x0, xzr, lsl #1]
// CHECK-INST: st1h { z0.d }, p0, [x0, xzr, lsl #1]
// CHECK-ENCODING: [0x00,0x40,0xff,0xe4]
// CHECK-ERROR: instruction requires: sve or sme
// CHECK-UNKNOWN: 00 40 ff e4 <unknown>

llvm/test/MC/AArch64/SVE/st1w-diagnostics.s

Show First 20 Lines • Show All 66 Lines • ▼ Show 20 Lines
// CHECK-NEXT: st1w { v0.4s }, p0, [x0] // CHECK-NEXT: st1w { v0.4s }, p0, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Invalid scalar + scalar addressing modes // Invalid scalar + scalar addressing modes
st1w z0.s, p0, [x0, x0] st1w z0.s, p0, [x0, x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2' // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #2'
// CHECK-NEXT: st1w z0.s, p0, [x0, x0] // CHECK-NEXT: st1w z0.s, p0, [x0, x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
st1w z0.s, p0, [x0, xzr]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2'
// CHECK-NEXT: st1w z0.s, p0, [x0, xzr]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
st1w z0.s, p0, [x0, x0, lsl #3] st1w z0.s, p0, [x0, x0, lsl #3]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2' // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #2'
// CHECK-NEXT: st1w z0.s, p0, [x0, x0, lsl #3] // CHECK-NEXT: st1w z0.s, p0, [x0, x0, lsl #3]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
st1w z0.s, p0, [x0, w0] st1w z0.s, p0, [x0, w0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2' // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #2'
// CHECK-NEXT: st1w z0.s, p0, [x0, w0] // CHECK-NEXT: st1w z0.s, p0, [x0, w0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
st1w z0.s, p0, [x0, w0, uxtw] st1w z0.s, p0, [x0, w0, uxtw]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2' // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #2'
// CHECK-NEXT: st1w z0.s, p0, [x0, w0, uxtw] // CHECK-NEXT: st1w z0.s, p0, [x0, w0, uxtw]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Invalid scalar + vector addressing modes // Invalid scalar + vector addressing modes
st1w z0.d, p0, [x0, z0.h] st1w z0.d, p0, [x0, z0.h]
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llvm/test/MC/AArch64/SVE/st1w.s

Show First 20 Lines • Show All 62 Lines • ▼ Show 20 Lines
// CHECK-ERROR: instruction requires: sve or sme // CHECK-ERROR: instruction requires: sve or sme
// CHECK-UNKNOWN: 00 40 40 e5 <unknown> // CHECK-UNKNOWN: 00 40 40 e5 <unknown>
st1w { z0.d }, p0, [x0, x0, lsl #2] st1w { z0.d }, p0, [x0, x0, lsl #2]
// CHECK-INST: st1w { z0.d }, p0, [x0, x0, lsl #2] // CHECK-INST: st1w { z0.d }, p0, [x0, x0, lsl #2]
// CHECK-ENCODING: [0x00,0x40,0x60,0xe5] // CHECK-ENCODING: [0x00,0x40,0x60,0xe5]
// CHECK-ERROR: instruction requires: sve or sme // CHECK-ERROR: instruction requires: sve or sme
// CHECK-UNKNOWN: 00 40 60 e5 <unknown> // CHECK-UNKNOWN: 00 40 60 e5 <unknown>
st1w { z0.s }, p0, [x0, xzr, lsl #2]
// CHECK-INST: st1w { z0.s }, p0, [x0, xzr, lsl #2]
// CHECK-ENCODING: [0x00,0x40,0x5f,0xe5]
// CHECK-ERROR: instruction requires: sve or sme
// CHECK-UNKNOWN: 00 40 5f e5 <unknown>
st1w { z0.d }, p0, [x0, xzr, lsl #2]
// CHECK-INST: st1w { z0.d }, p0, [x0, xzr, lsl #2]
// CHECK-ENCODING: [0x00,0x40,0x7f,0xe5]
// CHECK-ERROR: instruction requires: sve or sme
// CHECK-UNKNOWN: 00 40 7f e5 <unknown>