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Differential D130216

AMDGPU: Refine user-sgpr-init16-bug
ClosedPublic

Authored by arsenm on Jul 20 2022, 6:17 PM.

Details

Reviewers
foad
Joe_Nash
rampitec
dstuttard
Group Reviewers
Restricted Project
Summary

It only applies to gfx1100 and for wave32.

Diff Detail

Event Timeline

arsenm created this revision.Jul 20 2022, 6:17 PM
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arsenm requested review of this revision.Jul 20 2022, 6:17 PM
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arsenm mentioned this in D128664: AMDGPU: Add gfx11 feature to force initializing 16 input SGPRs.Jul 20 2022, 6:18 PM
Harbormaster completed remote builds in B176636: Diff 446320.Jul 20 2022, 6:57 PM
foad accepted this revision.Jul 21 2022, 1:45 AM
foad added a reviewer: dstuttard.

LGTM, thanks!

It only applies to gfx1100 and for wave32.

"... and gfx1102"

This revision is now accepted and ready to land.Jul 21 2022, 1:45 AM
arsenm closed this revision.Jul 21 2022, 5:57 AM

5a5439cb7332b9f4456026642ef4dc37224ae183

Revision Contents

PathSize
llvm/
lib/
Target/
AMDGPU/
7 lines
4 lines
2 lines
test/
CodeGen/
AMDGPU/
68 lines

Diff 446320

llvm/lib/Target/AMDGPU/AMDGPU.td

Show First 20 Lines • Show All 1,266 Lines • ▼ Show 20 Linesdef FeatureISAVersion11_Common : FeatureSet<
FeatureShaderCyclesRegister, FeatureShaderCyclesRegister,
FeatureArchitectedFlatScratch, FeatureArchitectedFlatScratch,
FeatureAtomicFaddRtnInsts, FeatureAtomicFaddRtnInsts,
FeatureAtomicFaddNoRtnInsts, FeatureAtomicFaddNoRtnInsts,
FeatureImageInsts, FeatureImageInsts,
FeaturePackedTID, FeaturePackedTID,
FeatureVcmpxPermlaneHazard]>; FeatureVcmpxPermlaneHazard]>;
// Features for GFX 11.0.0 and 11.0.1 def FeatureISAVersion11_0_0 : FeatureSet<
def FeatureISAVersion11_0 : FeatureSet<
!listconcat(FeatureISAVersion11_Common.Features, !listconcat(FeatureISAVersion11_Common.Features,
[FeatureUserSGPRInit16Bug])>; [FeatureUserSGPRInit16Bug])>;
def FeatureISAVersion11_0_1 : FeatureSet<
!listconcat(FeatureISAVersion11_Common.Features,
[])>;
def FeatureISAVersion11_0_2 : FeatureSet< def FeatureISAVersion11_0_2 : FeatureSet<
!listconcat(FeatureISAVersion11_Common.Features, !listconcat(FeatureISAVersion11_Common.Features,
[FeatureUserSGPRInit16Bug])>; [FeatureUserSGPRInit16Bug])>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
def AMDGPUInstrInfo : InstrInfo { def AMDGPUInstrInfo : InstrInfo {
let guessInstructionProperties = 1; let guessInstructionProperties = 1;
▲ Show 20 Lines • Show All 469 Lines • Show Last 20 Lines

llvm/lib/Target/AMDGPU/GCNProcessors.td

Show First 20 Lines • Show All 243 Lines • ▼ Show 20 Linesdef : ProcessorModel<"gfx1036", GFX10SpeedModel,
FeatureISAVersion10_3_0.Features FeatureISAVersion10_3_0.Features
>; >;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// GCN GFX11. // GCN GFX11.
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
def : ProcessorModel<"gfx1100", GFX11SpeedModel, def : ProcessorModel<"gfx1100", GFX11SpeedModel,
FeatureISAVersion11_0.Features FeatureISAVersion11_0_0.Features
>; >;
def : ProcessorModel<"gfx1101", GFX11SpeedModel, def : ProcessorModel<"gfx1101", GFX11SpeedModel,
FeatureISAVersion11_0.Features FeatureISAVersion11_0_1.Features
>; >;
def : ProcessorModel<"gfx1102", GFX11SpeedModel, def : ProcessorModel<"gfx1102", GFX11SpeedModel,
FeatureISAVersion11_0_2.Features FeatureISAVersion11_0_2.Features
>; >;
def : ProcessorModel<"gfx1103", GFX11SpeedModel, def : ProcessorModel<"gfx1103", GFX11SpeedModel,
FeatureISAVersion11_0_2.Features FeatureISAVersion11_0_2.Features
>; >;

llvm/lib/Target/AMDGPU/GCNSubtarget.h

Show First 20 Lines • Show All 929 Lines • ▼ Show 20 Lines bool loadStoreOptEnabled() const {
return EnableLoadStoreOpt; return EnableLoadStoreOpt;
} }
bool hasSGPRInitBug() const { bool hasSGPRInitBug() const {
return SGPRInitBug; return SGPRInitBug;
} }
bool hasUserSGPRInit16Bug() const { bool hasUserSGPRInit16Bug() const {
return UserSGPRInit16Bug; return UserSGPRInit16Bug && isWave32();
} }
bool hasNegativeScratchOffsetBug() const { return NegativeScratchOffsetBug; } bool hasNegativeScratchOffsetBug() const { return NegativeScratchOffsetBug; }
bool hasNegativeUnalignedScratchOffsetBug() const { bool hasNegativeUnalignedScratchOffsetBug() const {
return NegativeUnalignedScratchOffsetBug; return NegativeUnalignedScratchOffsetBug;
} }
▲ Show 20 Lines • Show All 344 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/gfx11-user-sgpr-init16-bug.ll

; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -amdgpu-enable-vopd=0 < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -amdgpu-enable-vopd=0 < %s | FileCheck -check-prefixes=GCN,WORKAROUND %s
; RUN: llc -global-isel=1 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -amdgpu-enable-vopd=0 < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -global-isel=1 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -amdgpu-enable-vopd=0 < %s | FileCheck -check-prefixes=GCN,WORKAROUND %s
; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1102 -amdgpu-enable-vopd=0 < %s | FileCheck -check-prefix=GCN %s
; RUN: llc -global-isel=1 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1102 -amdgpu-enable-vopd=0 < %s | FileCheck -check-prefix=GCN %s ; Does not apply to wave64
; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=+wavefrontsize64 -amdgpu-enable-vopd=0 < %s | FileCheck -check-prefixes=GCN,NOWORKAROUND %s
; RUN: llc -global-isel=1 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=+wavefrontsize64 -amdgpu-enable-vopd=0 < %s | FileCheck -check-prefixes=GCN,NOWORKAROUND %s
; Does not apply to gfx1101
; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1101 -amdgpu-enable-vopd=0 < %s | FileCheck -check-prefixes=GCN,NOWORKAROUND %s
; RUN: llc -global-isel=1 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1101 -amdgpu-enable-vopd=0 < %s | FileCheck -check-prefixes=GCN,NOWORKAROUND %s
; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1102 -amdgpu-enable-vopd=0 < %s | FileCheck -check-prefixes=GCN,WORKAROUND %s
; RUN: llc -global-isel=1 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1102 -amdgpu-enable-vopd=0 < %s | FileCheck -check-prefixes=GCN,WORKAROUND %s
; There aren't any stack objects, but we still enable the ; There aren't any stack objects, but we still enable the
; private_segment_wavefront_offset to get to 16, and the workgroup ID ; private_segment_wavefront_offset to get to 16, and the workgroup ID
; is in s14. ; is in s14.
; private_segment_buffer + workgroup_id_x = 5, + 11 padding ; private_segment_buffer + workgroup_id_x = 5, + 11 padding
; GCN-LABEL: {{^}}minimal_kernel_inputs: ; GCN-LABEL: {{^}}minimal_kernel_inputs:
; GCN: v_mov_b32_e32 [[V:v[0-9]+]], s15 ; WORKAROUND: v_mov_b32_e32 [[V:v[0-9]+]], s15
; NOWORKAROUND: v_mov_b32_e32 [[V:v[0-9]+]], s0
; GCN-NEXT: global_store_b32 v{{\[[0-9]+:[0-9]+\]}}, [[V]], off ; GCN-NEXT: global_store_b32 v{{\[[0-9]+:[0-9]+\]}}, [[V]], off
; GCN: .amdhsa_kernel minimal_kernel_inputs ; GCN: .amdhsa_kernel minimal_kernel_inputs
; GCN: .amdhsa_user_sgpr_count 15 ; WORKAROUND: .amdhsa_user_sgpr_count 15
; NOWORKAROUND: .amdhsa_user_sgpr_count 0
; GCN-NEXT: .amdhsa_user_sgpr_dispatch_ptr 0 ; GCN-NEXT: .amdhsa_user_sgpr_dispatch_ptr 0
; GCN-NEXT: .amdhsa_user_sgpr_queue_ptr 0 ; GCN-NEXT: .amdhsa_user_sgpr_queue_ptr 0
; GCN-NEXT: .amdhsa_user_sgpr_kernarg_segment_ptr 0 ; GCN-NEXT: .amdhsa_user_sgpr_kernarg_segment_ptr 0
; GCN-NEXT: .amdhsa_user_sgpr_dispatch_id 0 ; GCN-NEXT: .amdhsa_user_sgpr_dispatch_id 0
; GCN-NEXT: .amdhsa_user_sgpr_private_segment_size 0 ; GCN-NEXT: .amdhsa_user_sgpr_private_segment_size 0
; GCN-NEXT: .amdhsa_wavefront_size32 1 ; GCN-NEXT: .amdhsa_wavefront_size32
; GCN-NEXT: .amdhsa_uses_dynamic_stack 0 ; GCN-NEXT: .amdhsa_uses_dynamic_stack 0
; GCN-NEXT: .amdhsa_enable_private_segment 0 ; GCN-NEXT: .amdhsa_enable_private_segment 0
; GCN-NEXT: .amdhsa_system_sgpr_workgroup_id_x 1 ; GCN-NEXT: .amdhsa_system_sgpr_workgroup_id_x 1
; GCN-NEXT: .amdhsa_system_sgpr_workgroup_id_y 0 ; GCN-NEXT: .amdhsa_system_sgpr_workgroup_id_y 0
; GCN-NEXT: .amdhsa_system_sgpr_workgroup_id_z 0 ; GCN-NEXT: .amdhsa_system_sgpr_workgroup_id_z 0
; GCN-NEXT: .amdhsa_system_sgpr_workgroup_info 0 ; GCN-NEXT: .amdhsa_system_sgpr_workgroup_info 0
; GCN-NEXT: .amdhsa_system_vgpr_workitem_id 0 ; GCN-NEXT: .amdhsa_system_vgpr_workitem_id 0
; GCN: ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; WORKAROUND: ; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; NOWORKAROUND: ; COMPUTE_PGM_RSRC2:USER_SGPR: 0
define amdgpu_kernel void @minimal_kernel_inputs() { define amdgpu_kernel void @minimal_kernel_inputs() {
%id = call i32 @llvm.amdgcn.workgroup.id.x() %id = call i32 @llvm.amdgcn.workgroup.id.x()
store volatile i32 %id, i32 addrspace(1)* undef store volatile i32 %id, i32 addrspace(1)* undef
ret void ret void
} }
; GCN-LABEL: {{^}}minimal_kernel_inputs_with_stack: ; GCN-LABEL: {{^}}minimal_kernel_inputs_with_stack:
; GCN: v_mov_b32_e32 [[V:v[0-9]+]], s15 ; WORKAROUND: v_mov_b32_e32 [[V:v[0-9]+]], s15
; NOWORKAROUND: v_mov_b32_e32 [[V:v[0-9]+]], s0
; GCN: global_store_b32 v{{\[[0-9]+:[0-9]+\]}}, [[V]], off ; GCN: global_store_b32 v{{\[[0-9]+:[0-9]+\]}}, [[V]], off
; GCN: .amdhsa_kernel minimal_kernel_inputs ; GCN: .amdhsa_kernel minimal_kernel_inputs
; GCN: .amdhsa_user_sgpr_count 15 ; WORKAROUND: .amdhsa_user_sgpr_count 15
; NOWORKAROUND: .amdhsa_user_sgpr_count 0
; GCN-NEXT: .amdhsa_user_sgpr_dispatch_ptr 0 ; GCN-NEXT: .amdhsa_user_sgpr_dispatch_ptr 0
; GCN-NEXT: .amdhsa_user_sgpr_queue_ptr 0 ; GCN-NEXT: .amdhsa_user_sgpr_queue_ptr 0
; GCN-NEXT: .amdhsa_user_sgpr_kernarg_segment_ptr 0 ; GCN-NEXT: .amdhsa_user_sgpr_kernarg_segment_ptr 0
; GCN-NEXT: .amdhsa_user_sgpr_dispatch_id 0 ; GCN-NEXT: .amdhsa_user_sgpr_dispatch_id 0
; GCN-NEXT: .amdhsa_user_sgpr_private_segment_size 0 ; GCN-NEXT: .amdhsa_user_sgpr_private_segment_size 0
; GCN-NEXT: .amdhsa_wavefront_size32 1 ; GCN-NEXT: .amdhsa_wavefront_size32
; GCN-NEXT: .amdhsa_uses_dynamic_stack 0 ; GCN-NEXT: .amdhsa_uses_dynamic_stack 0
; GCN-NEXT: .amdhsa_enable_private_segment 1 ; GCN-NEXT: .amdhsa_enable_private_segment 1
; GCN-NEXT: .amdhsa_system_sgpr_workgroup_id_x 1 ; GCN-NEXT: .amdhsa_system_sgpr_workgroup_id_x 1
; GCN-NEXT: .amdhsa_system_sgpr_workgroup_id_y 0 ; GCN-NEXT: .amdhsa_system_sgpr_workgroup_id_y 0
; GCN-NEXT: .amdhsa_system_sgpr_workgroup_id_z 0 ; GCN-NEXT: .amdhsa_system_sgpr_workgroup_id_z 0
; GCN-NEXT: .amdhsa_system_sgpr_workgroup_info 0 ; GCN-NEXT: .amdhsa_system_sgpr_workgroup_info 0
; GCN-NEXT: .amdhsa_system_vgpr_workitem_id 0 ; GCN-NEXT: .amdhsa_system_vgpr_workitem_id 0
; GCN: ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; WORKAROUND: ; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; NOWORKAROUND: ; COMPUTE_PGM_RSRC2:USER_SGPR: 0
define amdgpu_kernel void @minimal_kernel_inputs_with_stack() { define amdgpu_kernel void @minimal_kernel_inputs_with_stack() {
%alloca = alloca i32, addrspace(5) %alloca = alloca i32, addrspace(5)
%id = call i32 @llvm.amdgcn.workgroup.id.x() %id = call i32 @llvm.amdgcn.workgroup.id.x()
store volatile i32 %id, i32 addrspace(1)* undef store volatile i32 %id, i32 addrspace(1)* undef
store volatile i32 0, i32 addrspace(5)* %alloca store volatile i32 0, i32 addrspace(5)* %alloca
ret void ret void
} }
; GCN-LABEL: {{^}}queue_ptr: ; GCN-LABEL: {{^}}queue_ptr:
; GCN: global_load_u8 v{{[0-9]+}}, v{{[0-9]+}}, s[0:1] ; GCN: global_load_u8 v{{[0-9]+}}, v{{[0-9]+}}, s[0:1]
; GCN: v_mov_b32_e32 [[V:v[0-9]+]], s15 ; WORKAROUND: v_mov_b32_e32 [[V:v[0-9]+]], s15
; NOWORKAROUND: v_mov_b32_e32 [[V:v[0-9]+]], s2
; GCN-NEXT: global_store_b32 v{{\[[0-9]+:[0-9]+\]}}, [[V]], off ; GCN-NEXT: global_store_b32 v{{\[[0-9]+:[0-9]+\]}}, [[V]], off
; GCN: .amdhsa_kernel queue_ptr ; GCN: .amdhsa_kernel queue_ptr
; GCN: .amdhsa_user_sgpr_count 15 ; WORKAROUND: .amdhsa_user_sgpr_count 15
; NOWORKAROUND: .amdhsa_user_sgpr_count 2
; GCN-NEXT: .amdhsa_user_sgpr_dispatch_ptr 0 ; GCN-NEXT: .amdhsa_user_sgpr_dispatch_ptr 0
; GCN-NEXT: .amdhsa_user_sgpr_queue_ptr 1 ; GCN-NEXT: .amdhsa_user_sgpr_queue_ptr 1
; GCN-NEXT: .amdhsa_user_sgpr_kernarg_segment_ptr 0 ; GCN-NEXT: .amdhsa_user_sgpr_kernarg_segment_ptr 0
; GCN-NEXT: .amdhsa_user_sgpr_dispatch_id 0 ; GCN-NEXT: .amdhsa_user_sgpr_dispatch_id 0
; GCN-NEXT: .amdhsa_user_sgpr_private_segment_size 0 ; GCN-NEXT: .amdhsa_user_sgpr_private_segment_size 0
; GCN-NEXT: .amdhsa_wavefront_size32 1 ; GCN-NEXT: .amdhsa_wavefront_size32
; GCN-NEXT: .amdhsa_uses_dynamic_stack 0 ; GCN-NEXT: .amdhsa_uses_dynamic_stack 0
; GCN-NEXT: .amdhsa_enable_private_segment 0 ; GCN-NEXT: .amdhsa_enable_private_segment 0
; GCN-NEXT: .amdhsa_system_sgpr_workgroup_id_x 1 ; GCN-NEXT: .amdhsa_system_sgpr_workgroup_id_x 1
; GCN-NEXT: .amdhsa_system_sgpr_workgroup_id_y 0 ; GCN-NEXT: .amdhsa_system_sgpr_workgroup_id_y 0
; GCN-NEXT: .amdhsa_system_sgpr_workgroup_id_z 0 ; GCN-NEXT: .amdhsa_system_sgpr_workgroup_id_z 0
; GCN-NEXT: .amdhsa_system_sgpr_workgroup_info 0 ; GCN-NEXT: .amdhsa_system_sgpr_workgroup_info 0
; GCN-NEXT: .amdhsa_system_vgpr_workitem_id 0 ; GCN-NEXT: .amdhsa_system_vgpr_workitem_id 0
; GCN: ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 ; WORKAROUND: ; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; NOWORKAROUND: ; COMPUTE_PGM_RSRC2:USER_SGPR: 2
define amdgpu_kernel void @queue_ptr() { define amdgpu_kernel void @queue_ptr() {
%queue.ptr = call noalias i8 addrspace(4)* @llvm.amdgcn.queue.ptr() #0 %queue.ptr = call noalias i8 addrspace(4)* @llvm.amdgcn.queue.ptr() #0
%load = load volatile i8, i8 addrspace(4)* %queue.ptr %load = load volatile i8, i8 addrspace(4)* %queue.ptr
%id = call i32 @llvm.amdgcn.workgroup.id.x() %id = call i32 @llvm.amdgcn.workgroup.id.x()
store volatile i32 %id, i32 addrspace(1)* undef store volatile i32 %id, i32 addrspace(1)* undef
ret void ret void
} }
; GCN-LABEL: {{^}}all_inputs: ; GCN-LABEL: {{^}}all_inputs:
; GCN: v_mov_b32_e32 [[V_X:v[0-9]+]], s13 ; WORKAROUND: v_mov_b32_e32 [[V_X:v[0-9]+]], s13
; GCN: v_mov_b32_e32 [[V_Y:v[0-9]+]], s14 ; WORKAROUND: v_mov_b32_e32 [[V_Y:v[0-9]+]], s14
; GCN: v_mov_b32_e32 [[V_Z:v[0-9]+]], s15 ; WORKAROUND: v_mov_b32_e32 [[V_Z:v[0-9]+]], s15
; NOWORKAROUND: v_mov_b32_e32 [[V_X:v[0-9]+]], s8
; NOWORKAROUND: v_mov_b32_e32 [[V_Y:v[0-9]+]], s9
; NOWORKAROUND: v_mov_b32_e32 [[V_Z:v[0-9]+]], s10
; GCN: global_load_u8 v{{[0-9]+}}, v{{[0-9]+}}, s[0:1] ; GCN: global_load_u8 v{{[0-9]+}}, v{{[0-9]+}}, s[0:1]
; GCN: global_load_u8 v{{[0-9]+}}, v{{[0-9]+}}, s[2:3] ; GCN: global_load_u8 v{{[0-9]+}}, v{{[0-9]+}}, s[2:3]
; GCN: global_load_u8 v{{[0-9]+}}, v{{[0-9]+}}, s[4:5] ; GCN: global_load_u8 v{{[0-9]+}}, v{{[0-9]+}}, s[4:5]
; GCN-DAG: v_mov_b32_e32 v[[DISPATCH_LO:[0-9]+]], s6 ; GCN-DAG: v_mov_b32_e32 v[[DISPATCH_LO:[0-9]+]], s6
; GCN-DAG: v_mov_b32_e32 v[[DISPATCH_HI:[0-9]+]], s7 ; GCN-DAG: v_mov_b32_e32 v[[DISPATCH_HI:[0-9]+]], s7
; GCN: global_store_b32 v{{\[[0-9]+:[0-9]+\]}}, [[V_X]], off ; GCN: global_store_b32 v{{\[[0-9]+:[0-9]+\]}}, [[V_X]], off
; GCN: global_store_b32 v{{\[[0-9]+:[0-9]+\]}}, [[V_Y]], off ; GCN: global_store_b32 v{{\[[0-9]+:[0-9]+\]}}, [[V_Y]], off
; GCN: global_store_b32 v{{\[[0-9]+:[0-9]+\]}}, [[V_Z]], off ; GCN: global_store_b32 v{{\[[0-9]+:[0-9]+\]}}, [[V_Z]], off
; GCN: global_store_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[DISPATCH_LO]]:[[DISPATCH_HI]]{{\]}}, off ; GCN: global_store_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[DISPATCH_LO]]:[[DISPATCH_HI]]{{\]}}, off
; GCN: .amdhsa_kernel all_inputs ; GCN: .amdhsa_kernel all_inputs
; GCN: .amdhsa_user_sgpr_count 13 ; WORKAROUND: .amdhsa_user_sgpr_count 13
; NOWORKAROUND: .amdhsa_user_sgpr_count 8
; GCN-NEXT: .amdhsa_user_sgpr_dispatch_ptr 1 ; GCN-NEXT: .amdhsa_user_sgpr_dispatch_ptr 1
; GCN-NEXT: .amdhsa_user_sgpr_queue_ptr 1 ; GCN-NEXT: .amdhsa_user_sgpr_queue_ptr 1
; GCN-NEXT: .amdhsa_user_sgpr_kernarg_segment_ptr 1 ; GCN-NEXT: .amdhsa_user_sgpr_kernarg_segment_ptr 1
; GCN-NEXT: .amdhsa_user_sgpr_dispatch_id 1 ; GCN-NEXT: .amdhsa_user_sgpr_dispatch_id 1
; GCN-NEXT: .amdhsa_user_sgpr_private_segment_size 0 ; GCN-NEXT: .amdhsa_user_sgpr_private_segment_size 0
; GCN-NEXT: .amdhsa_wavefront_size32 1 ; GCN-NEXT: .amdhsa_wavefront_size32
; GCN-NEXT: .amdhsa_uses_dynamic_stack 0 ; GCN-NEXT: .amdhsa_uses_dynamic_stack 0
; GCN-NEXT: .amdhsa_enable_private_segment 1 ; GCN-NEXT: .amdhsa_enable_private_segment 1
; GCN-NEXT: .amdhsa_system_sgpr_workgroup_id_x 1 ; GCN-NEXT: .amdhsa_system_sgpr_workgroup_id_x 1
; GCN-NEXT: .amdhsa_system_sgpr_workgroup_id_y 1 ; GCN-NEXT: .amdhsa_system_sgpr_workgroup_id_y 1
; GCN-NEXT: .amdhsa_system_sgpr_workgroup_id_z 1 ; GCN-NEXT: .amdhsa_system_sgpr_workgroup_id_z 1
; GCN-NEXT: .amdhsa_system_sgpr_workgroup_info 0 ; GCN-NEXT: .amdhsa_system_sgpr_workgroup_info 0
; GCN-NEXT: .amdhsa_system_vgpr_workitem_id 0 ; GCN-NEXT: .amdhsa_system_vgpr_workitem_id 0
; GCN: ; COMPUTE_PGM_RSRC2:USER_SGPR: 13 ; WORKAROUND: ; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; NOWORKAROUND: ; COMPUTE_PGM_RSRC2:USER_SGPR: 8
define amdgpu_kernel void @all_inputs() { define amdgpu_kernel void @all_inputs() {
%alloca = alloca i32, addrspace(5) %alloca = alloca i32, addrspace(5)
store volatile i32 0, i32 addrspace(5)* %alloca store volatile i32 0, i32 addrspace(5)* %alloca
%dispatch.ptr = call noalias i8 addrspace(4)* @llvm.amdgcn.dispatch.ptr() %dispatch.ptr = call noalias i8 addrspace(4)* @llvm.amdgcn.dispatch.ptr()
%load.dispatch = load volatile i8, i8 addrspace(4)* %dispatch.ptr %load.dispatch = load volatile i8, i8 addrspace(4)* %dispatch.ptr
%queue.ptr = call noalias i8 addrspace(4)* @llvm.amdgcn.queue.ptr() %queue.ptr = call noalias i8 addrspace(4)* @llvm.amdgcn.queue.ptr()
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