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Differential D130090

[PowerPC][NFC] Convert the MMA test cases to use opaque pointers.
ClosedPublic

Authored by stefanp on Jul 19 2022, 7:46 AM.

Details

Reviewers
nemanjai
lei
• Ahsan
amyk
Group Reviewers
Restricted Project
Commits
rG475a39fbc3c7: [PowerPC][NFC] Convert the MMA test cases to use opaque pointers.
Summary

This patch modifies only test cases.
Converted the MMA test cases to use opaque pointers.

Diff Detail

Event Timeline

stefanp created this revision.Jul 19 2022, 7:46 AM
Herald added a project: Restricted Project. · View Herald TranscriptJul 19 2022, 7:46 AM
Herald added subscribers: shchenz, nemanjai, qcolombet. · View Herald Transcript
stefanp requested review of this revision.Jul 19 2022, 7:46 AM
Herald added a project: Restricted Project. · View Herald TranscriptJul 19 2022, 7:46 AM
Herald added a subscriber: llvm-commits. · View Herald Transcript
stefanp added reviewers: nemanjai, lei, • Ahsan, amyk, Restricted Project.Jul 19 2022, 7:46 AM
Harbormaster completed remote builds in B176258: Diff 445821.Jul 19 2022, 8:37 AM
lei accepted this revision as: lei.Jul 20 2022, 7:18 AM

1 missed bitcast, otherwise LGTM

llvm/test/CodeGen/PowerPC/mma-intrinsics.ll
616–618

is this bitcast still needed?

This revision is now accepted and ready to land.Jul 20 2022, 7:18 AM
amyk added a comment.Jul 20 2022, 2:55 PM

I agree with Lei - LGTM, with some minor questions.

llvm/test/CodeGen/PowerPC/mma-integer-based-outer-product.ll
10

If %vqp and %vpp are not used, do we still need to keep them?

40

If %vqp and %vpp are not used, do we still need to keep them?

70

If %vpp is not used, do we still need to keep them? (Here and in the functions below)

stefanp added inline comments.Jul 21 2022, 6:28 PM
llvm/test/CodeGen/PowerPC/mma-integer-based-outer-product.ll
70

You are correct that this is not used.
I had noticed that when I originally edited the test and I was debating whether or not to fix it.
There are other tests that were written around the same time that have a similar issue
(see test/CodeGen/PowerPC/mma-outer-product.ll as well)

The reason I chose not to do this cleanup was because that was not really the point of this patch and because it would be a fairly significant change and so the much larger diff would distract from the rest of the changes.

I could however do this as a later patch.

llvm/test/CodeGen/PowerPC/mma-intrinsics.ll
616–618

No, it's not needed. I think I missed that on my fist pass through.

stefanp updated this revision to Diff 446684.Jul 21 2022, 6:32 PM

Rebased to top of trunk.
Removed the bitcast that was not required.

Harbormaster completed remote builds in B176903: Diff 446684.Jul 21 2022, 7:07 PM
amyk accepted this revision as: amyk.Jul 22 2022, 9:08 AM

Thanks for addressing the comments, LGTM.

This revision was landed with ongoing or failed builds.Jul 22 2022, 9:43 AM
Closed by commit rG475a39fbc3c7: [PowerPC][NFC] Convert the MMA test cases to use opaque pointers. (authored by stefanp). · Explain Why
This revision was automatically updated to reflect the committed changes.
stefanp added a commit: rG475a39fbc3c7: [PowerPC][NFC] Convert the MMA test cases to use opaque pointers..

Revision Contents

PathSize
llvm/
test/
CodeGen/
PowerPC/
54 lines
5 lines
50 lines
155 lines
418 lines
64 lines

Diff 446878

llvm/test/CodeGen/PowerPC/mma-acc-memops.ll

Show First 20 Lines • Show All 116 Lines • ▼ Show 20 Lines
; BE-PWR8-NEXT: stxvd2x vs1, r3, r4 ; BE-PWR8-NEXT: stxvd2x vs1, r3, r4
; BE-PWR8-NEXT: li r4, 144 ; BE-PWR8-NEXT: li r4, 144
; BE-PWR8-NEXT: stxvd2x vs0, r3, r5 ; BE-PWR8-NEXT: stxvd2x vs0, r3, r5
; BE-PWR8-NEXT: li r5, 128 ; BE-PWR8-NEXT: li r5, 128
; BE-PWR8-NEXT: stxvd2x vs3, r3, r4 ; BE-PWR8-NEXT: stxvd2x vs3, r3, r4
; BE-PWR8-NEXT: stxvd2x vs2, r3, r5 ; BE-PWR8-NEXT: stxvd2x vs2, r3, r5
; BE-PWR8-NEXT: blr ; BE-PWR8-NEXT: blr
entry: entry:
%arrayidx = getelementptr inbounds <512 x i1>, <512 x i1>* @f, i64 1 %arrayidx = getelementptr inbounds <512 x i1>, ptr @f, i64 1
%0 = load <512 x i1>, <512 x i1>* %arrayidx, align 64 %0 = load <512 x i1>, ptr %arrayidx, align 64
%arrayidx1 = getelementptr inbounds <512 x i1>, <512 x i1>* @f, i64 2 %arrayidx1 = getelementptr inbounds <512 x i1>, ptr @f, i64 2
store <512 x i1> %0, <512 x i1>* %arrayidx1, align 64 store <512 x i1> %0, ptr %arrayidx1, align 64
ret void ret void
} }
define dso_local void @testXLdSt(i64 %SrcIdx, i64 %DstIdx) { define dso_local void @testXLdSt(i64 %SrcIdx, i64 %DstIdx) {
; LE-PAIRED-LABEL: testXLdSt: ; LE-PAIRED-LABEL: testXLdSt:
; LE-PAIRED: # %bb.0: # %entry ; LE-PAIRED: # %bb.0: # %entry
; LE-PAIRED-NEXT: paddi r5, 0, f@PCREL, 1 ; LE-PAIRED-NEXT: paddi r5, 0, f@PCREL, 1
; LE-PAIRED-NEXT: sldi r3, r3, 6 ; LE-PAIRED-NEXT: sldi r3, r3, 6
▲ Show 20 Lines • Show All 101 Lines • ▼ Show 20 Lines
; BE-PWR8-NEXT: add r4, r5, r3 ; BE-PWR8-NEXT: add r4, r5, r3
; BE-PWR8-NEXT: lxvd2x vs3, r8, r9 ; BE-PWR8-NEXT: lxvd2x vs3, r8, r9
; BE-PWR8-NEXT: stxvd2x vs2, r5, r3 ; BE-PWR8-NEXT: stxvd2x vs2, r5, r3
; BE-PWR8-NEXT: stxvd2x vs1, r4, r7 ; BE-PWR8-NEXT: stxvd2x vs1, r4, r7
; BE-PWR8-NEXT: stxvd2x vs0, r4, r6 ; BE-PWR8-NEXT: stxvd2x vs0, r4, r6
; BE-PWR8-NEXT: stxvd2x vs3, r4, r9 ; BE-PWR8-NEXT: stxvd2x vs3, r4, r9
; BE-PWR8-NEXT: blr ; BE-PWR8-NEXT: blr
entry: entry:
%arrayidx = getelementptr inbounds <512 x i1>, <512 x i1>* @f, i64 %SrcIdx %arrayidx = getelementptr inbounds <512 x i1>, ptr @f, i64 %SrcIdx
%0 = load <512 x i1>, <512 x i1>* %arrayidx, align 64 %0 = load <512 x i1>, ptr %arrayidx, align 64
%arrayidx1 = getelementptr inbounds <512 x i1>, <512 x i1>* @f, i64 %DstIdx %arrayidx1 = getelementptr inbounds <512 x i1>, ptr @f, i64 %DstIdx
store <512 x i1> %0, <512 x i1>* %arrayidx1, align 64 store <512 x i1> %0, ptr %arrayidx1, align 64
ret void ret void
} }
define dso_local void @testUnalignedLdSt() { define dso_local void @testUnalignedLdSt() {
; LE-PAIRED-LABEL: testUnalignedLdSt: ; LE-PAIRED-LABEL: testUnalignedLdSt:
; LE-PAIRED: # %bb.0: # %entry ; LE-PAIRED: # %bb.0: # %entry
; LE-PAIRED-NEXT: plxv vs1, f@PCREL+43(0), 1 ; LE-PAIRED-NEXT: plxv vs1, f@PCREL+43(0), 1
; LE-PAIRED-NEXT: plxv vs0, f@PCREL+59(0), 1 ; LE-PAIRED-NEXT: plxv vs0, f@PCREL+59(0), 1
▲ Show 20 Lines • Show All 102 Lines • ▼ Show 20 Lines
; BE-PWR8-NEXT: stxvd2x vs1, r3, r4 ; BE-PWR8-NEXT: stxvd2x vs1, r3, r4
; BE-PWR8-NEXT: li r4, 35 ; BE-PWR8-NEXT: li r4, 35
; BE-PWR8-NEXT: stxvd2x vs0, r3, r5 ; BE-PWR8-NEXT: stxvd2x vs0, r3, r5
; BE-PWR8-NEXT: li r5, 19 ; BE-PWR8-NEXT: li r5, 19
; BE-PWR8-NEXT: stxvd2x vs3, r3, r4 ; BE-PWR8-NEXT: stxvd2x vs3, r3, r4
; BE-PWR8-NEXT: stxvd2x vs2, r3, r5 ; BE-PWR8-NEXT: stxvd2x vs2, r3, r5
; BE-PWR8-NEXT: blr ; BE-PWR8-NEXT: blr
entry: entry:
%0 = bitcast <512 x i1>* @f to i8* %add.ptr = getelementptr inbounds i8, ptr @f, i64 11
%add.ptr = getelementptr inbounds i8, i8* %0, i64 11 %add.ptr1 = getelementptr inbounds i8, ptr @f, i64 19
%add.ptr1 = getelementptr inbounds i8, i8* %0, i64 19 %0 = load <512 x i1>, ptr %add.ptr, align 64
%1 = bitcast i8* %add.ptr to <512 x i1>* store <512 x i1> %0, ptr %add.ptr1, align 64
%2 = bitcast i8* %add.ptr1 to <512 x i1>*
%3 = load <512 x i1>, <512 x i1>* %1, align 64
store <512 x i1> %3, <512 x i1>* %2, align 64
ret void ret void
} }
define dso_local void @testLdStPair(i64 %SrcIdx, i64 %DstIdx) { define dso_local void @testLdStPair(i64 %SrcIdx, i64 %DstIdx) {
; LE-PAIRED-LABEL: testLdStPair: ; LE-PAIRED-LABEL: testLdStPair:
; LE-PAIRED: # %bb.0: # %entry ; LE-PAIRED: # %bb.0: # %entry
; LE-PAIRED-NEXT: plxv v3, g@PCREL+32(0), 1 ; LE-PAIRED-NEXT: plxv v3, g@PCREL+32(0), 1
; LE-PAIRED-NEXT: plxv v2, g@PCREL+48(0), 1 ; LE-PAIRED-NEXT: plxv v2, g@PCREL+48(0), 1
▲ Show 20 Lines • Show All 54 Lines • ▼ Show 20 Lines
; BE-PWR8-NEXT: lxvd2x vs0, r3, r4 ; BE-PWR8-NEXT: lxvd2x vs0, r3, r4
; BE-PWR8-NEXT: lxvd2x vs1, r3, r5 ; BE-PWR8-NEXT: lxvd2x vs1, r3, r5
; BE-PWR8-NEXT: li r4, 80 ; BE-PWR8-NEXT: li r4, 80
; BE-PWR8-NEXT: li r5, 64 ; BE-PWR8-NEXT: li r5, 64
; BE-PWR8-NEXT: stxvd2x vs1, r3, r4 ; BE-PWR8-NEXT: stxvd2x vs1, r3, r4
; BE-PWR8-NEXT: stxvd2x vs0, r3, r5 ; BE-PWR8-NEXT: stxvd2x vs0, r3, r5
; BE-PWR8-NEXT: blr ; BE-PWR8-NEXT: blr
entry: entry:
%arrayidx = getelementptr inbounds <256 x i1>, <256 x i1>* @g, i64 1 %arrayidx = getelementptr inbounds <256 x i1>, ptr @g, i64 1
%0 = load <256 x i1>, <256 x i1>* %arrayidx, align 64 %0 = load <256 x i1>, ptr %arrayidx, align 64
%arrayidx1 = getelementptr inbounds <256 x i1>, <256 x i1>* @g, i64 2 %arrayidx1 = getelementptr inbounds <256 x i1>, ptr @g, i64 2
store <256 x i1> %0, <256 x i1>* %arrayidx1, align 64 store <256 x i1> %0, ptr %arrayidx1, align 64
ret void ret void
} }
define dso_local void @testXLdStPair(i64 %SrcIdx, i64 %DstIdx) { define dso_local void @testXLdStPair(i64 %SrcIdx, i64 %DstIdx) {
; LE-PAIRED-LABEL: testXLdStPair: ; LE-PAIRED-LABEL: testXLdStPair:
; LE-PAIRED: # %bb.0: # %entry ; LE-PAIRED: # %bb.0: # %entry
; LE-PAIRED-NEXT: sldi r3, r3, 5 ; LE-PAIRED-NEXT: sldi r3, r3, 5
; LE-PAIRED-NEXT: paddi r5, 0, g@PCREL, 1 ; LE-PAIRED-NEXT: paddi r5, 0, g@PCREL, 1
▲ Show 20 Lines • Show All 73 Lines • ▼ Show 20 Lines
; BE-PWR8-NEXT: lxvd2x vs0, r5, r3 ; BE-PWR8-NEXT: lxvd2x vs0, r5, r3
; BE-PWR8-NEXT: sldi r3, r4, 5 ; BE-PWR8-NEXT: sldi r3, r4, 5
; BE-PWR8-NEXT: lxvd2x vs1, r6, r7 ; BE-PWR8-NEXT: lxvd2x vs1, r6, r7
; BE-PWR8-NEXT: add r4, r5, r3 ; BE-PWR8-NEXT: add r4, r5, r3
; BE-PWR8-NEXT: stxvd2x vs0, r5, r3 ; BE-PWR8-NEXT: stxvd2x vs0, r5, r3
; BE-PWR8-NEXT: stxvd2x vs1, r4, r7 ; BE-PWR8-NEXT: stxvd2x vs1, r4, r7
; BE-PWR8-NEXT: blr ; BE-PWR8-NEXT: blr
entry: entry:
%arrayidx = getelementptr inbounds <256 x i1>, <256 x i1>* @g, i64 %SrcIdx %arrayidx = getelementptr inbounds <256 x i1>, ptr @g, i64 %SrcIdx
%0 = load <256 x i1>, <256 x i1>* %arrayidx, align 64 %0 = load <256 x i1>, ptr %arrayidx, align 64
%arrayidx1 = getelementptr inbounds <256 x i1>, <256 x i1>* @g, i64 %DstIdx %arrayidx1 = getelementptr inbounds <256 x i1>, ptr @g, i64 %DstIdx
store <256 x i1> %0, <256 x i1>* %arrayidx1, align 64 store <256 x i1> %0, ptr %arrayidx1, align 64
ret void ret void
} }
define dso_local void @testUnalignedLdStPair() { define dso_local void @testUnalignedLdStPair() {
; LE-PAIRED-LABEL: testUnalignedLdStPair: ; LE-PAIRED-LABEL: testUnalignedLdStPair:
; LE-PAIRED: # %bb.0: # %entry ; LE-PAIRED: # %bb.0: # %entry
; LE-PAIRED-NEXT: plxv v3, g@PCREL+11(0), 1 ; LE-PAIRED-NEXT: plxv v3, g@PCREL+11(0), 1
; LE-PAIRED-NEXT: plxv v2, g@PCREL+27(0), 1 ; LE-PAIRED-NEXT: plxv v2, g@PCREL+27(0), 1
▲ Show 20 Lines • Show All 62 Lines • ▼ Show 20 Lines
; BE-PWR8-NEXT: lxvd2x vs0, r3, r4 ; BE-PWR8-NEXT: lxvd2x vs0, r3, r4
; BE-PWR8-NEXT: lxvd2x vs1, r3, r5 ; BE-PWR8-NEXT: lxvd2x vs1, r3, r5
; BE-PWR8-NEXT: li r4, 35 ; BE-PWR8-NEXT: li r4, 35
; BE-PWR8-NEXT: li r5, 19 ; BE-PWR8-NEXT: li r5, 19
; BE-PWR8-NEXT: stxvd2x vs1, r3, r4 ; BE-PWR8-NEXT: stxvd2x vs1, r3, r4
; BE-PWR8-NEXT: stxvd2x vs0, r3, r5 ; BE-PWR8-NEXT: stxvd2x vs0, r3, r5
; BE-PWR8-NEXT: blr ; BE-PWR8-NEXT: blr
entry: entry:
%0 = bitcast <256 x i1>* @g to i8* %add.ptr = getelementptr inbounds i8, ptr @g, i64 11
%add.ptr = getelementptr inbounds i8, i8* %0, i64 11 %add.ptr1 = getelementptr inbounds i8, ptr @g, i64 19
%add.ptr1 = getelementptr inbounds i8, i8* %0, i64 19 %0 = load <256 x i1>, ptr %add.ptr, align 64
%1 = bitcast i8* %add.ptr to <256 x i1>* store <256 x i1> %0, ptr %add.ptr1, align 64
%2 = bitcast i8* %add.ptr1 to <256 x i1>*
%3 = load <256 x i1>, <256 x i1>* %1, align 64
store <256 x i1> %3, <256 x i1>* %2, align 64
ret void ret void
} }

llvm/test/CodeGen/PowerPC/mma-acc-spill.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -disable-auto-paired-vec-st=false \ ; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -disable-auto-paired-vec-st=false \
; RUN: -ppc-vsr-nums-as-vr < %s | FileCheck %s ; RUN: -ppc-vsr-nums-as-vr < %s | FileCheck %s
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -disable-auto-paired-vec-st=false \ ; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -disable-auto-paired-vec-st=false \
; RUN: -ppc-vsr-nums-as-vr < %s | FileCheck %s --check-prefix=CHECK-BE ; RUN: -ppc-vsr-nums-as-vr < %s | FileCheck %s --check-prefix=CHECK-BE
declare <512 x i1> @llvm.ppc.mma.xvf16ger2pp(<512 x i1>, <16 x i8>, <16 x i8>) declare <512 x i1> @llvm.ppc.mma.xvf16ger2pp(<512 x i1>, <16 x i8>, <16 x i8>)
declare <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>) declare <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>)
declare void @foo() declare void @foo()
define void @intrinsics1(<16 x i8> %vc1, <16 x i8> %vc2, <16 x i8> %vc3, <16 x i8> %vc4, i8* %ptr) { define void @intrinsics1(<16 x i8> %vc1, <16 x i8> %vc2, <16 x i8> %vc3, <16 x i8> %vc4, ptr %ptr) {
; CHECK-LABEL: intrinsics1: ; CHECK-LABEL: intrinsics1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: mflr r0 ; CHECK-NEXT: mflr r0
; CHECK-NEXT: std r0, 16(r1) ; CHECK-NEXT: std r0, 16(r1)
; CHECK-NEXT: stdu r1, -176(r1) ; CHECK-NEXT: stdu r1, -176(r1)
; CHECK-NEXT: .cfi_def_cfa_offset 176 ; CHECK-NEXT: .cfi_def_cfa_offset 176
; CHECK-NEXT: .cfi_offset lr, 16 ; CHECK-NEXT: .cfi_offset lr, 16
; CHECK-NEXT: .cfi_offset r30, -16 ; CHECK-NEXT: .cfi_offset r30, -16
▲ Show 20 Lines • Show All 90 Lines • ▼ Show 20 Lines
; CHECK-BE-NEXT: addi r1, r1, 256 ; CHECK-BE-NEXT: addi r1, r1, 256
; CHECK-BE-NEXT: ld r0, 16(r1) ; CHECK-BE-NEXT: ld r0, 16(r1)
; CHECK-BE-NEXT: mtlr r0 ; CHECK-BE-NEXT: mtlr r0
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
%1 = tail call <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8> %vc1, <16 x i8> %vc2, <16 x i8> %vc3, <16 x i8> %vc4) %1 = tail call <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8> %vc1, <16 x i8> %vc2, <16 x i8> %vc3, <16 x i8> %vc4)
%2 = tail call <512 x i1> @llvm.ppc.mma.xvf16ger2pp(<512 x i1> %1, <16 x i8> %vc1, <16 x i8> %vc3) %2 = tail call <512 x i1> @llvm.ppc.mma.xvf16ger2pp(<512 x i1> %1, <16 x i8> %vc1, <16 x i8> %vc3)
tail call void @foo() tail call void @foo()
%3 = tail call <512 x i1> @llvm.ppc.mma.xvf16ger2pp(<512 x i1> %2, <16 x i8> %vc1, <16 x i8> %vc3) %3 = tail call <512 x i1> @llvm.ppc.mma.xvf16ger2pp(<512 x i1> %2, <16 x i8> %vc1, <16 x i8> %vc3)
%4 = bitcast i8* %ptr to <512 x i1>* store <512 x i1> %3, ptr %ptr, align 64
store <512 x i1> %3, <512 x i1>* %4, align 64
ret void ret void
} }

llvm/test/CodeGen/PowerPC/mma-integer-based-outer-product.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names \ ; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names \
; RUN: -ppc-vsr-nums-as-vr < %s | FileCheck %s ; RUN: -ppc-vsr-nums-as-vr < %s | FileCheck %s
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names \ ; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names \
; RUN: -ppc-vsr-nums-as-vr < %s | FileCheck %s --check-prefix=CHECK-BE ; RUN: -ppc-vsr-nums-as-vr < %s | FileCheck %s --check-prefix=CHECK-BE
; Function Attrs: nofree nounwind writeonly ; Function Attrs: nofree nounwind writeonly
define dso_local void @test1(i8* nocapture readnone %vqp, i8* nocapture readnone %vpp, <16 x i8> %vc, i8* nocapture %resp) { define dso_local void @test1(ptr nocapture readnone %vqp, ptr nocapture readnone %vpp, <16 x i8> %vc, ptr nocapture %resp) {
amykUnsubmitted
Not Done
ReplyInline Actions

If %vqp and %vpp are not used, do we still need to keep them?

amyk: If `%vqp` and `%vpp` are not used, do we still need to keep them?
; CHECK-LABEL: test1: ; CHECK-LABEL: test1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xvi16ger2 acc0, v2, v2 ; CHECK-NEXT: xvi16ger2 acc0, v2, v2
; CHECK-NEXT: xxmfacc acc0 ; CHECK-NEXT: xxmfacc acc0
; CHECK-NEXT: stxv vs0, 48(r7) ; CHECK-NEXT: stxv vs0, 48(r7)
; CHECK-NEXT: stxv vs1, 32(r7) ; CHECK-NEXT: stxv vs1, 32(r7)
; CHECK-NEXT: stxv vs2, 16(r7) ; CHECK-NEXT: stxv vs2, 16(r7)
; CHECK-NEXT: stxv vs3, 0(r7) ; CHECK-NEXT: stxv vs3, 0(r7)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-BE-LABEL: test1: ; CHECK-BE-LABEL: test1:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: xvi16ger2 acc0, v2, v2 ; CHECK-BE-NEXT: xvi16ger2 acc0, v2, v2
; CHECK-BE-NEXT: xxmfacc acc0 ; CHECK-BE-NEXT: xxmfacc acc0
; CHECK-BE-NEXT: stxv vs1, 16(r7) ; CHECK-BE-NEXT: stxv vs1, 16(r7)
; CHECK-BE-NEXT: stxv vs0, 0(r7) ; CHECK-BE-NEXT: stxv vs0, 0(r7)
; CHECK-BE-NEXT: stxv vs3, 48(r7) ; CHECK-BE-NEXT: stxv vs3, 48(r7)
; CHECK-BE-NEXT: stxv vs2, 32(r7) ; CHECK-BE-NEXT: stxv vs2, 32(r7)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = tail call <512 x i1> @llvm.ppc.mma.xvi16ger2(<16 x i8> %vc, <16 x i8> %vc) %0 = tail call <512 x i1> @llvm.ppc.mma.xvi16ger2(<16 x i8> %vc, <16 x i8> %vc)
%1 = bitcast i8* %resp to <512 x i1>* store <512 x i1> %0, ptr %resp, align 64
store <512 x i1> %0, <512 x i1>* %1, align 64
ret void ret void
} }
; Function Attrs: nounwind readnone ; Function Attrs: nounwind readnone
declare <512 x i1> @llvm.ppc.mma.xvi16ger2(<16 x i8>, <16 x i8>) declare <512 x i1> @llvm.ppc.mma.xvi16ger2(<16 x i8>, <16 x i8>)
; Function Attrs: nofree nounwind writeonly ; Function Attrs: nofree nounwind writeonly
define dso_local void @test2(i8* nocapture readnone %vqp, i8* nocapture readnone %vpp, <16 x i8> %vc, i8* nocapture %resp) { define dso_local void @test2(ptr nocapture readnone %vqp, ptr nocapture readnone %vpp, <16 x i8> %vc, ptr nocapture %resp) {
amykUnsubmitted
Not Done
ReplyInline Actions

If %vqp and %vpp are not used, do we still need to keep them?

amyk: If `%vqp` and `%vpp` are not used, do we still need to keep them?
; CHECK-LABEL: test2: ; CHECK-LABEL: test2:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pmxvi16ger2 acc0, v2, v2, 0, 0, 0 ; CHECK-NEXT: pmxvi16ger2 acc0, v2, v2, 0, 0, 0
; CHECK-NEXT: xxmfacc acc0 ; CHECK-NEXT: xxmfacc acc0
; CHECK-NEXT: stxv vs0, 48(r7) ; CHECK-NEXT: stxv vs0, 48(r7)
; CHECK-NEXT: stxv vs1, 32(r7) ; CHECK-NEXT: stxv vs1, 32(r7)
; CHECK-NEXT: stxv vs2, 16(r7) ; CHECK-NEXT: stxv vs2, 16(r7)
; CHECK-NEXT: stxv vs3, 0(r7) ; CHECK-NEXT: stxv vs3, 0(r7)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-BE-LABEL: test2: ; CHECK-BE-LABEL: test2:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: pmxvi16ger2 acc0, v2, v2, 0, 0, 0 ; CHECK-BE-NEXT: pmxvi16ger2 acc0, v2, v2, 0, 0, 0
; CHECK-BE-NEXT: xxmfacc acc0 ; CHECK-BE-NEXT: xxmfacc acc0
; CHECK-BE-NEXT: stxv vs1, 16(r7) ; CHECK-BE-NEXT: stxv vs1, 16(r7)
; CHECK-BE-NEXT: stxv vs0, 0(r7) ; CHECK-BE-NEXT: stxv vs0, 0(r7)
; CHECK-BE-NEXT: stxv vs3, 48(r7) ; CHECK-BE-NEXT: stxv vs3, 48(r7)
; CHECK-BE-NEXT: stxv vs2, 32(r7) ; CHECK-BE-NEXT: stxv vs2, 32(r7)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = tail call <512 x i1> @llvm.ppc.mma.pmxvi16ger2(<16 x i8> %vc, <16 x i8> %vc, i32 0, i32 0, i32 0) %0 = tail call <512 x i1> @llvm.ppc.mma.pmxvi16ger2(<16 x i8> %vc, <16 x i8> %vc, i32 0, i32 0, i32 0)
%1 = bitcast i8* %resp to <512 x i1>* store <512 x i1> %0, ptr %resp, align 64
store <512 x i1> %0, <512 x i1>* %1, align 64
ret void ret void
} }
; Function Attrs: nounwind readnone ; Function Attrs: nounwind readnone
declare <512 x i1> @llvm.ppc.mma.pmxvi16ger2(<16 x i8>, <16 x i8>, i32, i32, i32) declare <512 x i1> @llvm.ppc.mma.pmxvi16ger2(<16 x i8>, <16 x i8>, i32, i32, i32)
; Function Attrs: nofree nounwind ; Function Attrs: nofree nounwind
define dso_local void @test3(i8* nocapture readonly %vqp, i8* nocapture readnone %vpp, <16 x i8> %vc, i8* nocapture %resp) { define dso_local void @test3(ptr nocapture readonly %vqp, ptr nocapture readnone %vpp, <16 x i8> %vc, ptr nocapture %resp) {
amykUnsubmitted
Not Done
ReplyInline Actions

If %vpp is not used, do we still need to keep them? (Here and in the functions below)

amyk: If `%vpp` is not used, do we still need to keep them? (Here and in the functions below)
stefanpAuthorUnsubmitted
Not Done
ReplyInline Actions

You are correct that this is not used.
I had noticed that when I originally edited the test and I was debating whether or not to fix it.
There are other tests that were written around the same time that have a similar issue
(see test/CodeGen/PowerPC/mma-outer-product.ll as well)

The reason I chose not to do this cleanup was because that was not really the point of this patch and because it would be a fairly significant change and so the much larger diff would distract from the rest of the changes.

I could however do this as a later patch.

stefanp: You are correct that this is not used. I had noticed that when I originally edited the test and…
; CHECK-LABEL: test3: ; CHECK-LABEL: test3:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lxv vs1, 32(r3) ; CHECK-NEXT: lxv vs1, 32(r3)
; CHECK-NEXT: lxv vs0, 48(r3) ; CHECK-NEXT: lxv vs0, 48(r3)
; CHECK-NEXT: lxv vs3, 0(r3) ; CHECK-NEXT: lxv vs3, 0(r3)
; CHECK-NEXT: lxv vs2, 16(r3) ; CHECK-NEXT: lxv vs2, 16(r3)
; CHECK-NEXT: xxmtacc acc0 ; CHECK-NEXT: xxmtacc acc0
; CHECK-NEXT: xvi8ger4spp acc0, v2, v2 ; CHECK-NEXT: xvi8ger4spp acc0, v2, v2
Show All 14 Lines
; CHECK-BE-NEXT: xvi8ger4spp acc0, v2, v2 ; CHECK-BE-NEXT: xvi8ger4spp acc0, v2, v2
; CHECK-BE-NEXT: xxmfacc acc0 ; CHECK-BE-NEXT: xxmfacc acc0
; CHECK-BE-NEXT: stxv vs1, 16(r7) ; CHECK-BE-NEXT: stxv vs1, 16(r7)
; CHECK-BE-NEXT: stxv vs0, 0(r7) ; CHECK-BE-NEXT: stxv vs0, 0(r7)
; CHECK-BE-NEXT: stxv vs3, 48(r7) ; CHECK-BE-NEXT: stxv vs3, 48(r7)
; CHECK-BE-NEXT: stxv vs2, 32(r7) ; CHECK-BE-NEXT: stxv vs2, 32(r7)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = bitcast i8* %vqp to <512 x i1>* %0 = load <512 x i1>, ptr %vqp, align 64
%1 = load <512 x i1>, <512 x i1>* %0, align 64 %1 = tail call <512 x i1> @llvm.ppc.mma.xvi8ger4spp(<512 x i1> %0, <16 x i8> %vc, <16 x i8> %vc)
%2 = tail call <512 x i1> @llvm.ppc.mma.xvi8ger4spp(<512 x i1> %1, <16 x i8> %vc, <16 x i8> %vc) store <512 x i1> %1, ptr %resp, align 64
%3 = bitcast i8* %resp to <512 x i1>*
store <512 x i1> %2, <512 x i1>* %3, align 64
ret void ret void
} }
; Function Attrs: nounwind readnone ; Function Attrs: nounwind readnone
declare <512 x i1> @llvm.ppc.mma.xvi8ger4spp(<512 x i1>, <16 x i8>, <16 x i8>) declare <512 x i1> @llvm.ppc.mma.xvi8ger4spp(<512 x i1>, <16 x i8>, <16 x i8>)
; Function Attrs: nofree nounwind ; Function Attrs: nofree nounwind
define dso_local void @test4(i8* nocapture readonly %vqp, i8* nocapture readnone %vpp, <16 x i8> %vc, i8* nocapture %resp) { define dso_local void @test4(ptr nocapture readonly %vqp, ptr nocapture readnone %vpp, <16 x i8> %vc, ptr nocapture %resp) {
; CHECK-LABEL: test4: ; CHECK-LABEL: test4:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lxv vs1, 32(r3) ; CHECK-NEXT: lxv vs1, 32(r3)
; CHECK-NEXT: lxv vs0, 48(r3) ; CHECK-NEXT: lxv vs0, 48(r3)
; CHECK-NEXT: lxv vs3, 0(r3) ; CHECK-NEXT: lxv vs3, 0(r3)
; CHECK-NEXT: lxv vs2, 16(r3) ; CHECK-NEXT: lxv vs2, 16(r3)
; CHECK-NEXT: xxmtacc acc0 ; CHECK-NEXT: xxmtacc acc0
; CHECK-NEXT: xvi16ger2pp acc0, v2, v2 ; CHECK-NEXT: xvi16ger2pp acc0, v2, v2
Show All 14 Lines
; CHECK-BE-NEXT: xvi16ger2pp acc0, v2, v2 ; CHECK-BE-NEXT: xvi16ger2pp acc0, v2, v2
; CHECK-BE-NEXT: xxmfacc acc0 ; CHECK-BE-NEXT: xxmfacc acc0
; CHECK-BE-NEXT: stxv vs1, 16(r7) ; CHECK-BE-NEXT: stxv vs1, 16(r7)
; CHECK-BE-NEXT: stxv vs0, 0(r7) ; CHECK-BE-NEXT: stxv vs0, 0(r7)
; CHECK-BE-NEXT: stxv vs3, 48(r7) ; CHECK-BE-NEXT: stxv vs3, 48(r7)
; CHECK-BE-NEXT: stxv vs2, 32(r7) ; CHECK-BE-NEXT: stxv vs2, 32(r7)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = bitcast i8* %vqp to <512 x i1>* %0 = load <512 x i1>, ptr %vqp, align 64
%1 = load <512 x i1>, <512 x i1>* %0, align 64 %1 = tail call <512 x i1> @llvm.ppc.mma.xvi16ger2pp(<512 x i1> %0, <16 x i8> %vc, <16 x i8> %vc)
%2 = tail call <512 x i1> @llvm.ppc.mma.xvi16ger2pp(<512 x i1> %1, <16 x i8> %vc, <16 x i8> %vc) store <512 x i1> %1, ptr %resp, align 64
%3 = bitcast i8* %resp to <512 x i1>*
store <512 x i1> %2, <512 x i1>* %3, align 64
ret void ret void
} }
; Function Attrs: nounwind readnone ; Function Attrs: nounwind readnone
declare <512 x i1> @llvm.ppc.mma.xvi16ger2pp(<512 x i1>, <16 x i8>, <16 x i8>) declare <512 x i1> @llvm.ppc.mma.xvi16ger2pp(<512 x i1>, <16 x i8>, <16 x i8>)
; Function Attrs: nofree nounwind ; Function Attrs: nofree nounwind
define dso_local void @test5(i8* nocapture readonly %vqp, i8* nocapture readnone %vpp, <16 x i8> %vc, i8* nocapture %resp) { define dso_local void @test5(ptr nocapture readonly %vqp, ptr nocapture readnone %vpp, <16 x i8> %vc, ptr nocapture %resp) {
; CHECK-LABEL: test5: ; CHECK-LABEL: test5:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lxv vs1, 32(r3) ; CHECK-NEXT: lxv vs1, 32(r3)
; CHECK-NEXT: lxv vs0, 48(r3) ; CHECK-NEXT: lxv vs0, 48(r3)
; CHECK-NEXT: lxv vs3, 0(r3) ; CHECK-NEXT: lxv vs3, 0(r3)
; CHECK-NEXT: lxv vs2, 16(r3) ; CHECK-NEXT: lxv vs2, 16(r3)
; CHECK-NEXT: xxmtacc acc0 ; CHECK-NEXT: xxmtacc acc0
; CHECK-NEXT: pmxvi8ger4spp acc0, v2, v2, 0, 0, 0 ; CHECK-NEXT: pmxvi8ger4spp acc0, v2, v2, 0, 0, 0
Show All 14 Lines
; CHECK-BE-NEXT: pmxvi8ger4spp acc0, v2, v2, 0, 0, 0 ; CHECK-BE-NEXT: pmxvi8ger4spp acc0, v2, v2, 0, 0, 0
; CHECK-BE-NEXT: xxmfacc acc0 ; CHECK-BE-NEXT: xxmfacc acc0
; CHECK-BE-NEXT: stxv vs1, 16(r7) ; CHECK-BE-NEXT: stxv vs1, 16(r7)
; CHECK-BE-NEXT: stxv vs0, 0(r7) ; CHECK-BE-NEXT: stxv vs0, 0(r7)
; CHECK-BE-NEXT: stxv vs3, 48(r7) ; CHECK-BE-NEXT: stxv vs3, 48(r7)
; CHECK-BE-NEXT: stxv vs2, 32(r7) ; CHECK-BE-NEXT: stxv vs2, 32(r7)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = bitcast i8* %vqp to <512 x i1>* %0 = load <512 x i1>, ptr %vqp, align 64
%1 = load <512 x i1>, <512 x i1>* %0, align 64 %1 = tail call <512 x i1> @llvm.ppc.mma.pmxvi8ger4spp(<512 x i1> %0, <16 x i8> %vc, <16 x i8> %vc, i32 0, i32 0, i32 0)
%2 = tail call <512 x i1> @llvm.ppc.mma.pmxvi8ger4spp(<512 x i1> %1, <16 x i8> %vc, <16 x i8> %vc, i32 0, i32 0, i32 0) store <512 x i1> %1, ptr %resp, align 64
%3 = bitcast i8* %resp to <512 x i1>*
store <512 x i1> %2, <512 x i1>* %3, align 64
ret void ret void
} }
; Function Attrs: nounwind readnone ; Function Attrs: nounwind readnone
declare <512 x i1> @llvm.ppc.mma.pmxvi8ger4spp(<512 x i1>, <16 x i8>, <16 x i8>, i32, i32, i32) declare <512 x i1> @llvm.ppc.mma.pmxvi8ger4spp(<512 x i1>, <16 x i8>, <16 x i8>, i32, i32, i32)
; Function Attrs: nofree nounwind ; Function Attrs: nofree nounwind
define dso_local void @test6(i8* nocapture readonly %vqp, i8* nocapture readnone %vpp, <16 x i8> %vc, i8* nocapture %resp) { define dso_local void @test6(ptr nocapture readonly %vqp, ptr nocapture readnone %vpp, <16 x i8> %vc, ptr nocapture %resp) {
; CHECK-LABEL: test6: ; CHECK-LABEL: test6:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lxv vs1, 32(r3) ; CHECK-NEXT: lxv vs1, 32(r3)
; CHECK-NEXT: lxv vs0, 48(r3) ; CHECK-NEXT: lxv vs0, 48(r3)
; CHECK-NEXT: lxv vs3, 0(r3) ; CHECK-NEXT: lxv vs3, 0(r3)
; CHECK-NEXT: lxv vs2, 16(r3) ; CHECK-NEXT: lxv vs2, 16(r3)
; CHECK-NEXT: xxmtacc acc0 ; CHECK-NEXT: xxmtacc acc0
; CHECK-NEXT: pmxvi16ger2pp acc0, v2, v2, 0, 0, 0 ; CHECK-NEXT: pmxvi16ger2pp acc0, v2, v2, 0, 0, 0
Show All 14 Lines
; CHECK-BE-NEXT: pmxvi16ger2pp acc0, v2, v2, 0, 0, 0 ; CHECK-BE-NEXT: pmxvi16ger2pp acc0, v2, v2, 0, 0, 0
; CHECK-BE-NEXT: xxmfacc acc0 ; CHECK-BE-NEXT: xxmfacc acc0
; CHECK-BE-NEXT: stxv vs1, 16(r7) ; CHECK-BE-NEXT: stxv vs1, 16(r7)
; CHECK-BE-NEXT: stxv vs0, 0(r7) ; CHECK-BE-NEXT: stxv vs0, 0(r7)
; CHECK-BE-NEXT: stxv vs3, 48(r7) ; CHECK-BE-NEXT: stxv vs3, 48(r7)
; CHECK-BE-NEXT: stxv vs2, 32(r7) ; CHECK-BE-NEXT: stxv vs2, 32(r7)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = bitcast i8* %vqp to <512 x i1>* %0 = load <512 x i1>, ptr %vqp, align 64
%1 = load <512 x i1>, <512 x i1>* %0, align 64 %1 = tail call <512 x i1> @llvm.ppc.mma.pmxvi16ger2pp(<512 x i1> %0, <16 x i8> %vc, <16 x i8> %vc, i32 0, i32 0, i32 0)
%2 = tail call <512 x i1> @llvm.ppc.mma.pmxvi16ger2pp(<512 x i1> %1, <16 x i8> %vc, <16 x i8> %vc, i32 0, i32 0, i32 0) store <512 x i1> %1, ptr %resp, align 64
%3 = bitcast i8* %resp to <512 x i1>*
store <512 x i1> %2, <512 x i1>* %3, align 64
ret void ret void
} }
; Function Attrs: nounwind readnone ; Function Attrs: nounwind readnone
declare <512 x i1> @llvm.ppc.mma.pmxvi16ger2pp(<512 x i1>, <16 x i8>, <16 x i8>, i32, i32, i32) declare <512 x i1> @llvm.ppc.mma.pmxvi16ger2pp(<512 x i1>, <16 x i8>, <16 x i8>, i32, i32, i32)

llvm/test/CodeGen/PowerPC/mma-intrinsics.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names \ ; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names \
; RUN: -ppc-vsr-nums-as-vr < %s | FileCheck %s ; RUN: -ppc-vsr-nums-as-vr < %s | FileCheck %s
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names \ ; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names \
; RUN: -ppc-vsr-nums-as-vr < %s | FileCheck %s --check-prefix=CHECK-BE ; RUN: -ppc-vsr-nums-as-vr < %s | FileCheck %s --check-prefix=CHECK-BE
; assemble_acc ; assemble_acc
declare <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>) declare <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>)
define void @ass_acc(<512 x i1>* %ptr, <16 x i8> %vc) { define void @ass_acc(ptr %ptr, <16 x i8> %vc) {
; CHECK-LABEL: ass_acc: ; CHECK-LABEL: ass_acc:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmr v3, v2 ; CHECK-NEXT: vmr v3, v2
; CHECK-NEXT: xxlor vs0, v2, v2 ; CHECK-NEXT: xxlor vs0, v2, v2
; CHECK-NEXT: xxlor vs1, v3, v3 ; CHECK-NEXT: xxlor vs1, v3, v3
; CHECK-NEXT: xxlor vs2, v2, v2 ; CHECK-NEXT: xxlor vs2, v2, v2
; CHECK-NEXT: xxlor vs3, v3, v3 ; CHECK-NEXT: xxlor vs3, v3, v3
; CHECK-NEXT: stxv vs0, 48(r3) ; CHECK-NEXT: stxv vs0, 48(r3)
Show All 11 Lines
; CHECK-BE-NEXT: xxlor vs3, v3, v3 ; CHECK-BE-NEXT: xxlor vs3, v3, v3
; CHECK-BE-NEXT: stxv vs1, 16(r3) ; CHECK-BE-NEXT: stxv vs1, 16(r3)
; CHECK-BE-NEXT: stxv vs0, 0(r3) ; CHECK-BE-NEXT: stxv vs0, 0(r3)
; CHECK-BE-NEXT: stxv vs3, 48(r3) ; CHECK-BE-NEXT: stxv vs3, 48(r3)
; CHECK-BE-NEXT: stxv vs2, 32(r3) ; CHECK-BE-NEXT: stxv vs2, 32(r3)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = tail call <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8> %vc, <16 x i8> %vc, <16 x i8> %vc, <16 x i8> %vc) %0 = tail call <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8> %vc, <16 x i8> %vc, <16 x i8> %vc, <16 x i8> %vc)
store <512 x i1> %0, <512 x i1>* %ptr, align 64 store <512 x i1> %0, ptr %ptr, align 64
ret void ret void
} }
; xxmtacc ; xxmtacc
declare <512 x i1> @llvm.ppc.mma.xxmtacc(<512 x i1>) declare <512 x i1> @llvm.ppc.mma.xxmtacc(<512 x i1>)
define void @int_xxmtacc(<512 x i1>* %ptr, <16 x i8> %vc) { define void @int_xxmtacc(ptr %ptr, <16 x i8> %vc) {
; CHECK-LABEL: int_xxmtacc: ; CHECK-LABEL: int_xxmtacc:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmr v3, v2 ; CHECK-NEXT: vmr v3, v2
; CHECK-NEXT: xxlor vs0, v2, v2 ; CHECK-NEXT: xxlor vs0, v2, v2
; CHECK-NEXT: xxlor vs1, v3, v3 ; CHECK-NEXT: xxlor vs1, v3, v3
; CHECK-NEXT: xxlor vs2, v2, v2 ; CHECK-NEXT: xxlor vs2, v2, v2
; CHECK-NEXT: xxlor vs3, v3, v3 ; CHECK-NEXT: xxlor vs3, v3, v3
; CHECK-NEXT: xxmtacc acc0 ; CHECK-NEXT: xxmtacc acc0
Show All 16 Lines
; CHECK-BE-NEXT: stxv vs3, 48(r3) ; CHECK-BE-NEXT: stxv vs3, 48(r3)
; CHECK-BE-NEXT: stxv vs2, 32(r3) ; CHECK-BE-NEXT: stxv vs2, 32(r3)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
; One xxmtacc is generated from the call to assemble.acc then one xxmtacc is ; One xxmtacc is generated from the call to assemble.acc then one xxmtacc is
; generated from the call to xxmtacc then one xxmfacc is generated for the store ; generated from the call to xxmtacc then one xxmfacc is generated for the store
%0 = tail call <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8> %vc, <16 x i8> %vc, <16 x i8> %vc, <16 x i8> %vc) %0 = tail call <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8> %vc, <16 x i8> %vc, <16 x i8> %vc, <16 x i8> %vc)
%1 = tail call <512 x i1> @llvm.ppc.mma.xxmtacc(<512 x i1> %0) %1 = tail call <512 x i1> @llvm.ppc.mma.xxmtacc(<512 x i1> %0)
store <512 x i1> %1, <512 x i1>* %ptr, align 64 store <512 x i1> %1, ptr %ptr, align 64
ret void ret void
} }
; xxmfacc ; xxmfacc
declare <512 x i1> @llvm.ppc.mma.xxmfacc(<512 x i1>) declare <512 x i1> @llvm.ppc.mma.xxmfacc(<512 x i1>)
define void @int_xxmfacc(<512 x i1>* %ptr, <16 x i8> %vc) { define void @int_xxmfacc(ptr %ptr, <16 x i8> %vc) {
; CHECK-LABEL: int_xxmfacc: ; CHECK-LABEL: int_xxmfacc:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmr v3, v2 ; CHECK-NEXT: vmr v3, v2
; CHECK-NEXT: xxlor vs0, v2, v2 ; CHECK-NEXT: xxlor vs0, v2, v2
; CHECK-NEXT: xxlor vs1, v3, v3 ; CHECK-NEXT: xxlor vs1, v3, v3
; CHECK-NEXT: xxlor vs2, v2, v2 ; CHECK-NEXT: xxlor vs2, v2, v2
; CHECK-NEXT: xxlor vs3, v3, v3 ; CHECK-NEXT: xxlor vs3, v3, v3
; CHECK-NEXT: stxv vs0, 48(r3) ; CHECK-NEXT: stxv vs0, 48(r3)
Show All 14 Lines
; CHECK-BE-NEXT: stxv vs3, 48(r3) ; CHECK-BE-NEXT: stxv vs3, 48(r3)
; CHECK-BE-NEXT: stxv vs2, 32(r3) ; CHECK-BE-NEXT: stxv vs2, 32(r3)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
; One xxmtacc is generated from the call to assemble.acc then one xxmfacc is ; One xxmtacc is generated from the call to assemble.acc then one xxmfacc is
; generated from the call to xxmfacc then one xxmfacc is generated for the store ; generated from the call to xxmfacc then one xxmfacc is generated for the store
%0 = tail call <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8> %vc, <16 x i8> %vc, <16 x i8> %vc, <16 x i8> %vc) %0 = tail call <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8> %vc, <16 x i8> %vc, <16 x i8> %vc, <16 x i8> %vc)
%1 = tail call <512 x i1> @llvm.ppc.mma.xxmfacc(<512 x i1> %0) %1 = tail call <512 x i1> @llvm.ppc.mma.xxmfacc(<512 x i1> %0)
store <512 x i1> %1, <512 x i1>* %ptr, align 64 store <512 x i1> %1, ptr %ptr, align 64
ret void ret void
} }
; xxsetaccz ; xxsetaccz
declare <512 x i1> @llvm.ppc.mma.xxsetaccz() declare <512 x i1> @llvm.ppc.mma.xxsetaccz()
define void @int_xxsetaccz(<512 x i1>* %ptr) { define void @int_xxsetaccz(ptr %ptr) {
; CHECK-LABEL: int_xxsetaccz: ; CHECK-LABEL: int_xxsetaccz:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xxsetaccz acc0 ; CHECK-NEXT: xxsetaccz acc0
; CHECK-NEXT: xxmfacc acc0 ; CHECK-NEXT: xxmfacc acc0
; CHECK-NEXT: stxv vs0, 48(r3) ; CHECK-NEXT: stxv vs0, 48(r3)
; CHECK-NEXT: stxv vs1, 32(r3) ; CHECK-NEXT: stxv vs1, 32(r3)
; CHECK-NEXT: stxv vs2, 16(r3) ; CHECK-NEXT: stxv vs2, 16(r3)
; CHECK-NEXT: stxv vs3, 0(r3) ; CHECK-NEXT: stxv vs3, 0(r3)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-BE-LABEL: int_xxsetaccz: ; CHECK-BE-LABEL: int_xxsetaccz:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: xxsetaccz acc0 ; CHECK-BE-NEXT: xxsetaccz acc0
; CHECK-BE-NEXT: xxmfacc acc0 ; CHECK-BE-NEXT: xxmfacc acc0
; CHECK-BE-NEXT: stxv vs1, 16(r3) ; CHECK-BE-NEXT: stxv vs1, 16(r3)
; CHECK-BE-NEXT: stxv vs0, 0(r3) ; CHECK-BE-NEXT: stxv vs0, 0(r3)
; CHECK-BE-NEXT: stxv vs3, 48(r3) ; CHECK-BE-NEXT: stxv vs3, 48(r3)
; CHECK-BE-NEXT: stxv vs2, 32(r3) ; CHECK-BE-NEXT: stxv vs2, 32(r3)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = tail call <512 x i1> @llvm.ppc.mma.xxsetaccz() %0 = tail call <512 x i1> @llvm.ppc.mma.xxsetaccz()
store <512 x i1> %0, <512 x i1>* %ptr, align 64 store <512 x i1> %0, ptr %ptr, align 64
ret void ret void
} }
; disassemble_acc ; disassemble_acc
declare { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.ppc.mma.disassemble.acc(<512 x i1>) declare { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.ppc.mma.disassemble.acc(<512 x i1>)
define void @disass_acc(<16 x i8>* %ptr1, <16 x i8>* %ptr2, <16 x i8>* %ptr3, <16 x i8>* %ptr4) { define void @disass_acc(ptr %ptr1, ptr %ptr2, ptr %ptr3, ptr %ptr4) {
; CHECK-LABEL: disass_acc: ; CHECK-LABEL: disass_acc:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xxsetaccz acc0 ; CHECK-NEXT: xxsetaccz acc0
; CHECK-NEXT: xxmfacc acc0 ; CHECK-NEXT: xxmfacc acc0
; CHECK-NEXT: stxv vs3, 0(r3) ; CHECK-NEXT: stxv vs3, 0(r3)
; CHECK-NEXT: stxv vs2, 0(r4) ; CHECK-NEXT: stxv vs2, 0(r4)
; CHECK-NEXT: stxv vs1, 0(r5) ; CHECK-NEXT: stxv vs1, 0(r5)
; CHECK-NEXT: stxv vs0, 0(r6) ; CHECK-NEXT: stxv vs0, 0(r6)
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; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = tail call <512 x i1> @llvm.ppc.mma.xxsetaccz() %0 = tail call <512 x i1> @llvm.ppc.mma.xxsetaccz()
%1 = tail call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.ppc.mma.disassemble.acc(<512 x i1> %0) %1 = tail call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.ppc.mma.disassemble.acc(<512 x i1> %0)
%2 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %1, 0 %2 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %1, 0
%3 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %1, 1 %3 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %1, 1
%4 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %1, 2 %4 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %1, 2
%5 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %1, 3 %5 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %1, 3
store <16 x i8> %2, <16 x i8>* %ptr1, align 16 store <16 x i8> %2, ptr %ptr1, align 16
store <16 x i8> %3, <16 x i8>* %ptr2, align 16 store <16 x i8> %3, ptr %ptr2, align 16
store <16 x i8> %4, <16 x i8>* %ptr3, align 16 store <16 x i8> %4, ptr %ptr3, align 16
store <16 x i8> %5, <16 x i8>* %ptr4, align 16 store <16 x i8> %5, ptr %ptr4, align 16
ret void ret void
} }
declare <512 x i1> @llvm.ppc.mma.xvi4ger8pp(<512 x i1>, <16 x i8>, <16 x i8>) declare <512 x i1> @llvm.ppc.mma.xvi4ger8pp(<512 x i1>, <16 x i8>, <16 x i8>)
define void @testBranch(<512 x i1>* %ptr, <16 x i8> %vc, i32 %val) { define void @testBranch(ptr %ptr, <16 x i8> %vc, i32 %val) {
; CHECK-LABEL: testBranch: ; CHECK-LABEL: testBranch:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cmplwi r7, 0 ; CHECK-NEXT: cmplwi r7, 0
; CHECK-NEXT: beq cr0, .LBB5_2 ; CHECK-NEXT: beq cr0, .LBB5_2
; CHECK-NEXT: # %bb.1: # %if.then ; CHECK-NEXT: # %bb.1: # %if.then
; CHECK-NEXT: xxsetaccz acc0 ; CHECK-NEXT: xxsetaccz acc0
; CHECK-NEXT: b .LBB5_3 ; CHECK-NEXT: b .LBB5_3
; CHECK-NEXT: .LBB5_2: # %if.else ; CHECK-NEXT: .LBB5_2: # %if.else
Show All 36 Linesentry:
%tobool = icmp eq i32 %val, 0 %tobool = icmp eq i32 %val, 0
br i1 %tobool, label %if.else, label %if.then br i1 %tobool, label %if.else, label %if.then
if.then: if.then:
%0 = tail call <512 x i1> @llvm.ppc.mma.xxsetaccz() %0 = tail call <512 x i1> @llvm.ppc.mma.xxsetaccz()
br label %if.end br label %if.end
if.else: if.else:
%1 = load <512 x i1>, <512 x i1>* %ptr, align 64 %1 = load <512 x i1>, ptr %ptr, align 64
%2 = tail call <512 x i1> @llvm.ppc.mma.xvi4ger8pp(<512 x i1> %1, <16 x i8> %vc, <16 x i8> %vc) %2 = tail call <512 x i1> @llvm.ppc.mma.xvi4ger8pp(<512 x i1> %1, <16 x i8> %vc, <16 x i8> %vc)
br label %if.end br label %if.end
if.end: if.end:
%vq1.0 = phi <512 x i1> [ %0, %if.then ], [ %2, %if.else ] %vq1.0 = phi <512 x i1> [ %0, %if.then ], [ %2, %if.else ]
store <512 x i1> %vq1.0, <512 x i1>* %ptr, align 64 store <512 x i1> %vq1.0, ptr %ptr, align 64
ret void ret void
} }
; The following test cases check that the xxsetaccz instruction is correctly rematerialized ; The following test cases check that the xxsetaccz instruction is correctly rematerialized
declare <512 x i1> @llvm.ppc.mma.xvf32gerpp(<512 x i1>, <16 x i8>, <16 x i8>) declare <512 x i1> @llvm.ppc.mma.xvf32gerpp(<512 x i1>, <16 x i8>, <16 x i8>)
declare <512 x i1> @llvm.ppc.mma.xvf32gerpn(<512 x i1>, <16 x i8>, <16 x i8>) declare <512 x i1> @llvm.ppc.mma.xvf32gerpn(<512 x i1>, <16 x i8>, <16 x i8>)
declare <512 x i1> @llvm.ppc.mma.xvf32gernp(<512 x i1>, <16 x i8>, <16 x i8>) declare <512 x i1> @llvm.ppc.mma.xvf32gernp(<512 x i1>, <16 x i8>, <16 x i8>)
define void @testcse(<512 x i1>* %res, <16 x i8> %vc) { define void @testcse(ptr %res, <16 x i8> %vc) {
; CHECK-LABEL: testcse: ; CHECK-LABEL: testcse:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xxsetaccz acc0 ; CHECK-NEXT: xxsetaccz acc0
; CHECK-NEXT: xvf32gerpp acc0, v2, v2 ; CHECK-NEXT: xvf32gerpp acc0, v2, v2
; CHECK-NEXT: xxmfacc acc0 ; CHECK-NEXT: xxmfacc acc0
; CHECK-NEXT: stxv vs0, 48(r3) ; CHECK-NEXT: stxv vs0, 48(r3)
; CHECK-NEXT: stxv vs1, 32(r3) ; CHECK-NEXT: stxv vs1, 32(r3)
; CHECK-NEXT: stxv vs2, 16(r3) ; CHECK-NEXT: stxv vs2, 16(r3)
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; CHECK-BE-NEXT: stxv vs3, 112(r3) ; CHECK-BE-NEXT: stxv vs3, 112(r3)
; CHECK-BE-NEXT: stxv vs2, 96(r3) ; CHECK-BE-NEXT: stxv vs2, 96(r3)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = call <512 x i1> @llvm.ppc.mma.xxsetaccz() %0 = call <512 x i1> @llvm.ppc.mma.xxsetaccz()
%1 = call <512 x i1> @llvm.ppc.mma.xxsetaccz() %1 = call <512 x i1> @llvm.ppc.mma.xxsetaccz()
%2 = call <512 x i1> @llvm.ppc.mma.xvf32gerpp(<512 x i1> %0, <16 x i8> %vc, <16 x i8> %vc) %2 = call <512 x i1> @llvm.ppc.mma.xvf32gerpp(<512 x i1> %0, <16 x i8> %vc, <16 x i8> %vc)
%3 = call <512 x i1> @llvm.ppc.mma.xvf32gerpp(<512 x i1> %1, <16 x i8> %vc, <16 x i8> %vc) %3 = call <512 x i1> @llvm.ppc.mma.xvf32gerpp(<512 x i1> %1, <16 x i8> %vc, <16 x i8> %vc)
%4 = getelementptr inbounds <512 x i1>, <512 x i1>* %res, i64 0 %4 = getelementptr inbounds <512 x i1>, ptr %res, i64 0
%5 = getelementptr inbounds <512 x i1>, <512 x i1>* %res, i64 1 %5 = getelementptr inbounds <512 x i1>, ptr %res, i64 1
store <512 x i1> %2, <512 x i1>* %4, align 64 store <512 x i1> %2, ptr %4, align 64
store <512 x i1> %3, <512 x i1>* %5, align 64 store <512 x i1> %3, ptr %5, align 64
ret void ret void
} }
define void @testcse2(<512 x i1>* %res, <16 x i8> %vc) { define void @testcse2(ptr %res, <16 x i8> %vc) {
; CHECK-LABEL: testcse2: ; CHECK-LABEL: testcse2:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xxsetaccz acc0 ; CHECK-NEXT: xxsetaccz acc0
; CHECK-NEXT: xxsetaccz acc1 ; CHECK-NEXT: xxsetaccz acc1
; CHECK-NEXT: xvf32gerpp acc1, v2, v2 ; CHECK-NEXT: xvf32gerpp acc1, v2, v2
; CHECK-NEXT: xvf32gerpn acc0, v2, v2 ; CHECK-NEXT: xvf32gerpn acc0, v2, v2
; CHECK-NEXT: xxmfacc acc1 ; CHECK-NEXT: xxmfacc acc1
; CHECK-NEXT: xxmfacc acc0 ; CHECK-NEXT: xxmfacc acc0
Show All 24 Lines
; CHECK-BE-NEXT: stxv vs3, 112(r3) ; CHECK-BE-NEXT: stxv vs3, 112(r3)
; CHECK-BE-NEXT: stxv vs2, 96(r3) ; CHECK-BE-NEXT: stxv vs2, 96(r3)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = call <512 x i1> @llvm.ppc.mma.xxsetaccz() %0 = call <512 x i1> @llvm.ppc.mma.xxsetaccz()
%1 = call <512 x i1> @llvm.ppc.mma.xxsetaccz() %1 = call <512 x i1> @llvm.ppc.mma.xxsetaccz()
%2 = call <512 x i1> @llvm.ppc.mma.xvf32gerpp(<512 x i1> %0, <16 x i8> %vc, <16 x i8> %vc) %2 = call <512 x i1> @llvm.ppc.mma.xvf32gerpp(<512 x i1> %0, <16 x i8> %vc, <16 x i8> %vc)
%3 = call <512 x i1> @llvm.ppc.mma.xvf32gerpn(<512 x i1> %1, <16 x i8> %vc, <16 x i8> %vc) %3 = call <512 x i1> @llvm.ppc.mma.xvf32gerpn(<512 x i1> %1, <16 x i8> %vc, <16 x i8> %vc)
%4 = getelementptr inbounds <512 x i1>, <512 x i1>* %res, i64 0 %4 = getelementptr inbounds <512 x i1>, ptr %res, i64 0
%5 = getelementptr inbounds <512 x i1>, <512 x i1>* %res, i64 1 %5 = getelementptr inbounds <512 x i1>, ptr %res, i64 1
store <512 x i1> %2, <512 x i1>* %4, align 64 store <512 x i1> %2, ptr %4, align 64
store <512 x i1> %3, <512 x i1>* %5, align 64 store <512 x i1> %3, ptr %5, align 64
ret void ret void
} }
define void @testcse3(<512 x i1>* %res, <16 x i8> %vc) { define void @testcse3(ptr %res, <16 x i8> %vc) {
; CHECK-LABEL: testcse3: ; CHECK-LABEL: testcse3:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xxsetaccz acc0 ; CHECK-NEXT: xxsetaccz acc0
; CHECK-NEXT: xxsetaccz acc1 ; CHECK-NEXT: xxsetaccz acc1
; CHECK-NEXT: xvf32gerpp acc1, v2, v2 ; CHECK-NEXT: xvf32gerpp acc1, v2, v2
; CHECK-NEXT: xvf32gerpn acc0, v2, v2 ; CHECK-NEXT: xvf32gerpn acc0, v2, v2
; CHECK-NEXT: xxmfacc acc1 ; CHECK-NEXT: xxmfacc acc1
; CHECK-NEXT: xxmfacc acc0 ; CHECK-NEXT: xxmfacc acc0
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; CHECK-BE-NEXT: stxv vs0, 64(r3) ; CHECK-BE-NEXT: stxv vs0, 64(r3)
; CHECK-BE-NEXT: stxv vs3, 112(r3) ; CHECK-BE-NEXT: stxv vs3, 112(r3)
; CHECK-BE-NEXT: stxv vs2, 96(r3) ; CHECK-BE-NEXT: stxv vs2, 96(r3)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = call <512 x i1> @llvm.ppc.mma.xxsetaccz() %0 = call <512 x i1> @llvm.ppc.mma.xxsetaccz()
%1 = call <512 x i1> @llvm.ppc.mma.xvf32gerpp(<512 x i1> %0, <16 x i8> %vc, <16 x i8> %vc) %1 = call <512 x i1> @llvm.ppc.mma.xvf32gerpp(<512 x i1> %0, <16 x i8> %vc, <16 x i8> %vc)
%2 = call <512 x i1> @llvm.ppc.mma.xvf32gerpn(<512 x i1> %0, <16 x i8> %vc, <16 x i8> %vc) %2 = call <512 x i1> @llvm.ppc.mma.xvf32gerpn(<512 x i1> %0, <16 x i8> %vc, <16 x i8> %vc)
%3 = getelementptr inbounds <512 x i1>, <512 x i1>* %res, i64 0 %3 = getelementptr inbounds <512 x i1>, ptr %res, i64 0
%4 = getelementptr inbounds <512 x i1>, <512 x i1>* %res, i64 1 %4 = getelementptr inbounds <512 x i1>, ptr %res, i64 1
store <512 x i1> %1, <512 x i1>* %3, align 64 store <512 x i1> %1, ptr %3, align 64
store <512 x i1> %2, <512 x i1>* %4, align 64 store <512 x i1> %2, ptr %4, align 64
ret void ret void
} }
define void @testcse4(<512 x i1>* %res, i32 %lim, <16 x i8>* %vc) { define void @testcse4(ptr %res, i32 %lim, ptr %vc) {
; CHECK-LABEL: testcse4: ; CHECK-LABEL: testcse4:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cmpwi r4, 1 ; CHECK-NEXT: cmpwi r4, 1
; CHECK-NEXT: bltlr cr0 ; CHECK-NEXT: bltlr cr0
; CHECK-NEXT: # %bb.1: # %for.body.preheader ; CHECK-NEXT: # %bb.1: # %for.body.preheader
; CHECK-NEXT: clrldi r4, r4, 32 ; CHECK-NEXT: clrldi r4, r4, 32
; CHECK-NEXT: li r6, 0 ; CHECK-NEXT: li r6, 0
; CHECK-NEXT: mtctr r4 ; CHECK-NEXT: mtctr r4
▲ Show 20 Lines • Show All 100 Lines • ▼ Show 20 Lines
for.body: ; preds = %for.body, %for.body.preheader for.body: ; preds = %for.body, %for.body.preheader
%indvars.iv = phi i64 [ 0, %for.body.preheader ], [ %indvars.iv.next, %for.body ] %indvars.iv = phi i64 [ 0, %for.body.preheader ], [ %indvars.iv.next, %for.body ]
%0 = tail call <512 x i1> @llvm.ppc.mma.xxsetaccz() %0 = tail call <512 x i1> @llvm.ppc.mma.xxsetaccz()
%1 = tail call <512 x i1> @llvm.ppc.mma.xxsetaccz() %1 = tail call <512 x i1> @llvm.ppc.mma.xxsetaccz()
%2 = tail call <512 x i1> @llvm.ppc.mma.xxsetaccz() %2 = tail call <512 x i1> @llvm.ppc.mma.xxsetaccz()
%3 = trunc i64 %indvars.iv to i32 %3 = trunc i64 %indvars.iv to i32
%mul = mul nsw i32 %3, 6 %mul = mul nsw i32 %3, 6
%idxprom = zext i32 %mul to i64 %idxprom = zext i32 %mul to i64
%arrayidx = getelementptr inbounds <16 x i8>, <16 x i8>* %vc, i64 %idxprom %arrayidx = getelementptr inbounds <16 x i8>, ptr %vc, i64 %idxprom
%4 = load <16 x i8>, <16 x i8>* %arrayidx, align 16 %4 = load <16 x i8>, ptr %arrayidx, align 16
%add2 = or i32 %mul, 1 %add2 = or i32 %mul, 1
%idxprom3 = zext i32 %add2 to i64 %idxprom3 = zext i32 %add2 to i64
%arrayidx4 = getelementptr inbounds <16 x i8>, <16 x i8>* %vc, i64 %idxprom3 %arrayidx4 = getelementptr inbounds <16 x i8>, ptr %vc, i64 %idxprom3
%5 = load <16 x i8>, <16 x i8>* %arrayidx4, align 16 %5 = load <16 x i8>, ptr %arrayidx4, align 16
%6 = tail call <512 x i1> @llvm.ppc.mma.xvf32gerpp(<512 x i1> %0, <16 x i8> %4, <16 x i8> %5) %6 = tail call <512 x i1> @llvm.ppc.mma.xvf32gerpp(<512 x i1> %0, <16 x i8> %4, <16 x i8> %5)
%add6 = add nuw nsw i32 %mul, 2 %add6 = add nuw nsw i32 %mul, 2
%idxprom7 = zext i32 %add6 to i64 %idxprom7 = zext i32 %add6 to i64
%arrayidx8 = getelementptr inbounds <16 x i8>, <16 x i8>* %vc, i64 %idxprom7 %arrayidx8 = getelementptr inbounds <16 x i8>, ptr %vc, i64 %idxprom7
%7 = load <16 x i8>, <16 x i8>* %arrayidx8, align 16 %7 = load <16 x i8>, ptr %arrayidx8, align 16
%add10 = add nuw nsw i32 %mul, 3 %add10 = add nuw nsw i32 %mul, 3
%idxprom11 = zext i32 %add10 to i64 %idxprom11 = zext i32 %add10 to i64
%arrayidx12 = getelementptr inbounds <16 x i8>, <16 x i8>* %vc, i64 %idxprom11 %arrayidx12 = getelementptr inbounds <16 x i8>, ptr %vc, i64 %idxprom11
%8 = load <16 x i8>, <16 x i8>* %arrayidx12, align 16 %8 = load <16 x i8>, ptr %arrayidx12, align 16
%9 = tail call <512 x i1> @llvm.ppc.mma.xvf32gerpn(<512 x i1> %1, <16 x i8> %7, <16 x i8> %8) %9 = tail call <512 x i1> @llvm.ppc.mma.xvf32gerpn(<512 x i1> %1, <16 x i8> %7, <16 x i8> %8)
%add14 = add nuw nsw i32 %mul, 4 %add14 = add nuw nsw i32 %mul, 4
%idxprom15 = zext i32 %add14 to i64 %idxprom15 = zext i32 %add14 to i64
%arrayidx16 = getelementptr inbounds <16 x i8>, <16 x i8>* %vc, i64 %idxprom15 %arrayidx16 = getelementptr inbounds <16 x i8>, ptr %vc, i64 %idxprom15
%10 = load <16 x i8>, <16 x i8>* %arrayidx16, align 16 %10 = load <16 x i8>, ptr %arrayidx16, align 16
%add18 = add nuw nsw i32 %mul, 5 %add18 = add nuw nsw i32 %mul, 5
%idxprom19 = zext i32 %add18 to i64 %idxprom19 = zext i32 %add18 to i64
%arrayidx20 = getelementptr inbounds <16 x i8>, <16 x i8>* %vc, i64 %idxprom19 %arrayidx20 = getelementptr inbounds <16 x i8>, ptr %vc, i64 %idxprom19
%11 = load <16 x i8>, <16 x i8>* %arrayidx20, align 16 %11 = load <16 x i8>, ptr %arrayidx20, align 16
%12 = tail call <512 x i1> @llvm.ppc.mma.xvf32gernp(<512 x i1> %2, <16 x i8> %10, <16 x i8> %11) %12 = tail call <512 x i1> @llvm.ppc.mma.xvf32gernp(<512 x i1> %2, <16 x i8> %10, <16 x i8> %11)
%mul21 = mul i64 %indvars.iv, 3 %mul21 = mul i64 %indvars.iv, 3
%idx.ext = and i64 %mul21, 4294967295 %idx.ext = and i64 %mul21, 4294967295
%add.ptr = getelementptr inbounds <512 x i1>, <512 x i1>* %res, i64 %idx.ext %add.ptr = getelementptr inbounds <512 x i1>, ptr %res, i64 %idx.ext
store <512 x i1> %6, <512 x i1>* %add.ptr, align 64 store <512 x i1> %6, ptr %add.ptr, align 64
%add.ptr26 = getelementptr inbounds <512 x i1>, <512 x i1>* %add.ptr, i64 1 %add.ptr26 = getelementptr inbounds <512 x i1>, ptr %add.ptr, i64 1
store <512 x i1> %9, <512 x i1>* %add.ptr26, align 64 store <512 x i1> %9, ptr %add.ptr26, align 64
%add.ptr30 = getelementptr inbounds <512 x i1>, <512 x i1>* %add.ptr, i64 2 %add.ptr30 = getelementptr inbounds <512 x i1>, ptr %add.ptr, i64 2
store <512 x i1> %12, <512 x i1>* %add.ptr30, align 64 store <512 x i1> %12, ptr %add.ptr30, align 64
%indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
%exitcond.not = icmp eq i64 %indvars.iv.next, %wide.trip.count %exitcond.not = icmp eq i64 %indvars.iv.next, %wide.trip.count
br i1 %exitcond.not, label %for.cond.cleanup, label %for.body br i1 %exitcond.not, label %for.cond.cleanup, label %for.body
} }
declare i32 @testRedundantPrimeUnprimeF() declare i32 @testRedundantPrimeUnprimeF()
define void @testRedundantPrimeUnprime(<512 x i1>* %dst, <16 x i8> %vc) nounwind { define void @testRedundantPrimeUnprime(ptr %dst, <16 x i8> %vc) nounwind {
; CHECK-LABEL: testRedundantPrimeUnprime: ; CHECK-LABEL: testRedundantPrimeUnprime:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mflr r0 ; CHECK-NEXT: mflr r0
; CHECK-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-NEXT: std r0, 16(r1) ; CHECK-NEXT: std r0, 16(r1)
; CHECK-NEXT: stdu r1, -112(r1) ; CHECK-NEXT: stdu r1, -112(r1)
; CHECK-NEXT: xxsetaccz acc0 ; CHECK-NEXT: xxsetaccz acc0
; CHECK-NEXT: xxsetaccz acc1 ; CHECK-NEXT: xxsetaccz acc1
▲ Show 20 Lines • Show All 52 Lines • ▼ Show 20 Lines
; CHECK-BE-NEXT: stxv vs0, 64(r30) ; CHECK-BE-NEXT: stxv vs0, 64(r30)
; CHECK-BE-NEXT: ld r30, 176(r1) # 8-byte Folded Reload ; CHECK-BE-NEXT: ld r30, 176(r1) # 8-byte Folded Reload
; CHECK-BE-NEXT: addi r1, r1, 192 ; CHECK-BE-NEXT: addi r1, r1, 192
; CHECK-BE-NEXT: ld r0, 16(r1) ; CHECK-BE-NEXT: ld r0, 16(r1)
; CHECK-BE-NEXT: mtlr r0 ; CHECK-BE-NEXT: mtlr r0
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = tail call <512 x i1> @llvm.ppc.mma.xxsetaccz() %0 = tail call <512 x i1> @llvm.ppc.mma.xxsetaccz()
store <512 x i1> %0, <512 x i1>* %dst, align 64 store <512 x i1> %0, ptr %dst, align 64
%1 = tail call <512 x i1> @llvm.ppc.mma.xvf32gerpp(<512 x i1> %0, <16 x i8> %vc, <16 x i8> %vc) %1 = tail call <512 x i1> @llvm.ppc.mma.xvf32gerpp(<512 x i1> %0, <16 x i8> %vc, <16 x i8> %vc)
%call = tail call signext i32 bitcast (i32 ()* @testRedundantPrimeUnprimeF to i32 ()*)() %call = tail call signext i32 @testRedundantPrimeUnprimeF()
%add.ptr1 = getelementptr inbounds <512 x i1>, <512 x i1>* %dst, i64 1 %add.ptr1 = getelementptr inbounds <512 x i1>, ptr %dst, i64 1
store <512 x i1> %1, <512 x i1>* %add.ptr1, align 64 store <512 x i1> %1, ptr %add.ptr1, align 64
leiUnsubmitted
Not Done
ReplyInline Actions

is this bitcast still needed?

lei: is this bitcast still needed?
stefanpAuthorUnsubmitted
Done
ReplyInline Actions

No, it's not needed. I think I missed that on my fist pass through.

stefanp: No, it's not needed. I think I missed that on my fist pass through.
ret void ret void
} }
declare <256 x i1> @llvm.ppc.vsx.lxvp(i8*) declare <256 x i1> @llvm.ppc.vsx.lxvp(ptr)
declare void @llvm.ppc.vsx.stxvp(<256 x i1>, i8*) declare void @llvm.ppc.vsx.stxvp(<256 x i1>, ptr)
; Function Attrs: nofree nounwind ; Function Attrs: nofree nounwind
define void @test_ldst_1(i8* nocapture readonly %vqp, <256 x i1>* %vpp, <16 x i8> %vc, i8* nocapture %resp) { define void @test_ldst_1(ptr nocapture readonly %vqp, ptr %vpp, <16 x i8> %vc, ptr nocapture %resp) {
; CHECK-LABEL: test_ldst_1: ; CHECK-LABEL: test_ldst_1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lxv vs1, 32(r3) ; CHECK-NEXT: lxv vs1, 32(r3)
; CHECK-NEXT: lxv vs0, 48(r3) ; CHECK-NEXT: lxv vs0, 48(r3)
; CHECK-NEXT: lxv vs3, 0(r3) ; CHECK-NEXT: lxv vs3, 0(r3)
; CHECK-NEXT: lxv vs2, 16(r3) ; CHECK-NEXT: lxv vs2, 16(r3)
; CHECK-NEXT: plxvp vsp36, 8(r4), 0 ; CHECK-NEXT: plxvp vsp36, 8(r4), 0
; CHECK-NEXT: xxmtacc acc0 ; CHECK-NEXT: xxmtacc acc0
Show All 16 Lines
; CHECK-BE-NEXT: pmxvf64gernn acc0, vsp36, v2, 0, 0 ; CHECK-BE-NEXT: pmxvf64gernn acc0, vsp36, v2, 0, 0
; CHECK-BE-NEXT: xxmfacc acc0 ; CHECK-BE-NEXT: xxmfacc acc0
; CHECK-BE-NEXT: stxv vs1, 16(r7) ; CHECK-BE-NEXT: stxv vs1, 16(r7)
; CHECK-BE-NEXT: stxv vs0, 0(r7) ; CHECK-BE-NEXT: stxv vs0, 0(r7)
; CHECK-BE-NEXT: stxv vs3, 48(r7) ; CHECK-BE-NEXT: stxv vs3, 48(r7)
; CHECK-BE-NEXT: stxv vs2, 32(r7) ; CHECK-BE-NEXT: stxv vs2, 32(r7)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = bitcast i8* %vqp to <512 x i1>* %0 = load <512 x i1>, ptr %vqp, align 64
%1 = load <512 x i1>, <512 x i1>* %0, align 64 %1 = getelementptr i8, ptr %vpp, i64 8
%2 = bitcast <256 x i1>* %vpp to i8* %2 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(ptr %1)
%3 = getelementptr i8, i8* %2, i64 8 %3 = tail call <512 x i1> @llvm.ppc.mma.pmxvf64gernn(<512 x i1> %0, <256 x i1> %2, <16 x i8> %vc, i32 0, i32 0)
%4 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* %3) store <512 x i1> %3, ptr %resp, align 64
%5 = tail call <512 x i1> @llvm.ppc.mma.pmxvf64gernn(<512 x i1> %1, <256 x i1> %4, <16 x i8> %vc, i32 0, i32 0)
%6 = bitcast i8* %resp to <512 x i1>*
store <512 x i1> %5, <512 x i1>* %6, align 64
ret void ret void
} }
; Function Attrs: nofree nounwind ; Function Attrs: nofree nounwind
define void @test_ldst_2(i8* nocapture readonly %vqp, <256 x i1>* %vpp, <16 x i8> %vc, i8* nocapture %resp) { define void @test_ldst_2(ptr nocapture readonly %vqp, ptr %vpp, <16 x i8> %vc, ptr nocapture %resp) {
; CHECK-LABEL: test_ldst_2: ; CHECK-LABEL: test_ldst_2:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lxv vs1, 32(r3) ; CHECK-NEXT: lxv vs1, 32(r3)
; CHECK-NEXT: lxv vs0, 48(r3) ; CHECK-NEXT: lxv vs0, 48(r3)
; CHECK-NEXT: lxv vs3, 0(r3) ; CHECK-NEXT: lxv vs3, 0(r3)
; CHECK-NEXT: lxv vs2, 16(r3) ; CHECK-NEXT: lxv vs2, 16(r3)
; CHECK-NEXT: xxmtacc acc0 ; CHECK-NEXT: xxmtacc acc0
; CHECK-NEXT: lxvp vsp36, 0(r4) ; CHECK-NEXT: lxvp vsp36, 0(r4)
Show All 16 Lines
; CHECK-BE-NEXT: xvf64gernp acc0, vsp36, v2 ; CHECK-BE-NEXT: xvf64gernp acc0, vsp36, v2
; CHECK-BE-NEXT: xxmfacc acc0 ; CHECK-BE-NEXT: xxmfacc acc0
; CHECK-BE-NEXT: stxv vs1, 16(r7) ; CHECK-BE-NEXT: stxv vs1, 16(r7)
; CHECK-BE-NEXT: stxv vs0, 0(r7) ; CHECK-BE-NEXT: stxv vs0, 0(r7)
; CHECK-BE-NEXT: stxv vs3, 48(r7) ; CHECK-BE-NEXT: stxv vs3, 48(r7)
; CHECK-BE-NEXT: stxv vs2, 32(r7) ; CHECK-BE-NEXT: stxv vs2, 32(r7)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = bitcast i8* %vqp to <512 x i1>* %0 = load <512 x i1>, ptr %vqp, align 64
%1 = load <512 x i1>, <512 x i1>* %0, align 64 %1 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(ptr %vpp)
%2 = bitcast <256 x i1>* %vpp to i8* %2 = tail call <512 x i1> @llvm.ppc.mma.xvf64gernp(<512 x i1> %0, <256 x i1> %1, <16 x i8> %vc)
%3 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* %2) store <512 x i1> %2, ptr %resp, align 64
%4 = tail call <512 x i1> @llvm.ppc.mma.xvf64gernp(<512 x i1> %1, <256 x i1> %3, <16 x i8> %vc)
%5 = bitcast i8* %resp to <512 x i1>*
store <512 x i1> %4, <512 x i1>* %5, align 64
ret void ret void
} }
; Function Attrs: nofree nounwind ; Function Attrs: nofree nounwind
define void @test_ldst_3(i8* nocapture readonly %vqp, i64 %offs, <256 x i1>* %vpp, <16 x i8> %vc, i8* nocapture %resp) { define void @test_ldst_3(ptr nocapture readonly %vqp, i64 %offs, ptr %vpp, <16 x i8> %vc, ptr nocapture %resp) {
; CHECK-LABEL: test_ldst_3: ; CHECK-LABEL: test_ldst_3:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lxv vs1, 32(r3) ; CHECK-NEXT: lxv vs1, 32(r3)
; CHECK-NEXT: lxv vs0, 48(r3) ; CHECK-NEXT: lxv vs0, 48(r3)
; CHECK-NEXT: lxv vs3, 0(r3) ; CHECK-NEXT: lxv vs3, 0(r3)
; CHECK-NEXT: lxv vs2, 16(r3) ; CHECK-NEXT: lxv vs2, 16(r3)
; CHECK-NEXT: xxmtacc acc0 ; CHECK-NEXT: xxmtacc acc0
; CHECK-NEXT: lxvp vsp36, 0(r5) ; CHECK-NEXT: lxvp vsp36, 0(r5)
Show All 16 Lines
; CHECK-BE-NEXT: xvf64gernp acc0, vsp36, v2 ; CHECK-BE-NEXT: xvf64gernp acc0, vsp36, v2
; CHECK-BE-NEXT: xxmfacc acc0 ; CHECK-BE-NEXT: xxmfacc acc0
; CHECK-BE-NEXT: stxv vs1, 16(r9) ; CHECK-BE-NEXT: stxv vs1, 16(r9)
; CHECK-BE-NEXT: stxv vs0, 0(r9) ; CHECK-BE-NEXT: stxv vs0, 0(r9)
; CHECK-BE-NEXT: stxv vs3, 48(r9) ; CHECK-BE-NEXT: stxv vs3, 48(r9)
; CHECK-BE-NEXT: stxv vs2, 32(r9) ; CHECK-BE-NEXT: stxv vs2, 32(r9)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = bitcast i8* %vqp to <512 x i1>* %0 = load <512 x i1>, ptr %vqp, align 64
%1 = load <512 x i1>, <512 x i1>* %0, align 64 %1 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(ptr %vpp)
%2 = bitcast <256 x i1>* %vpp to i8* %2 = tail call <512 x i1> @llvm.ppc.mma.xvf64gernp(<512 x i1> %0, <256 x i1> %1, <16 x i8> %vc)
%3 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* %2) store <512 x i1> %2, ptr %resp, align 64
%4 = tail call <512 x i1> @llvm.ppc.mma.xvf64gernp(<512 x i1> %1, <256 x i1> %3, <16 x i8> %vc)
%5 = bitcast i8* %resp to <512 x i1>*
store <512 x i1> %4, <512 x i1>* %5, align 64
ret void ret void
} }
declare <512 x i1> @llvm.ppc.mma.pmxvf64gernn(<512 x i1>, <256 x i1>, <16 x i8>, i32, i32) declare <512 x i1> @llvm.ppc.mma.pmxvf64gernn(<512 x i1>, <256 x i1>, <16 x i8>, i32, i32)
declare <512 x i1> @llvm.ppc.mma.xvf64gernp(<512 x i1>, <256 x i1>, <16 x i8>) declare <512 x i1> @llvm.ppc.mma.xvf64gernp(<512 x i1>, <256 x i1>, <16 x i8>)

llvm/test/CodeGen/PowerPC/mma-outer-product.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: -mcpu=pwr10 -ppc-track-subreg-liveness -ppc-asm-full-reg-names \ ; RUN: -mcpu=pwr10 -ppc-track-subreg-liveness -ppc-asm-full-reg-names \
; RUN: -ppc-vsr-nums-as-vr < %s | FileCheck %s ; RUN: -ppc-vsr-nums-as-vr < %s | FileCheck %s
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
; RUN: -mcpu=pwr10 -ppc-track-subreg-liveness -ppc-asm-full-reg-names \ ; RUN: -mcpu=pwr10 -ppc-track-subreg-liveness -ppc-asm-full-reg-names \
; RUN: -ppc-vsr-nums-as-vr < %s | FileCheck %s --check-prefix=CHECK-BE ; RUN: -ppc-vsr-nums-as-vr < %s | FileCheck %s --check-prefix=CHECK-BE
declare <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>) declare <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>)
declare <256 x i1> @llvm.ppc.vsx.assemble.pair(<16 x i8>, <16 x i8>) declare <256 x i1> @llvm.ppc.vsx.assemble.pair(<16 x i8>, <16 x i8>)
define void @intrinsics1(<16 x i8> %vc1, <16 x i8> %vc2, <16 x i8> %vc3, <16 x i8> %vc4, i8* %ptr) { define void @intrinsics1(<16 x i8> %vc1, <16 x i8> %vc2, <16 x i8> %vc3, <16 x i8> %vc4, ptr %ptr) {
; CHECK-LABEL: intrinsics1: ; CHECK-LABEL: intrinsics1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vmr v1, v4 ; CHECK-NEXT: vmr v1, v4
; CHECK-NEXT: vmr v4, v3 ; CHECK-NEXT: vmr v4, v3
; CHECK-NEXT: vmr v0, v2 ; CHECK-NEXT: vmr v0, v2
; CHECK-NEXT: xxlor vs3, v5, v5 ; CHECK-NEXT: xxlor vs3, v5, v5
; CHECK-NEXT: ld r3, 96(r1) ; CHECK-NEXT: ld r3, 96(r1)
; CHECK-NEXT: xxlor vs0, v0, v0 ; CHECK-NEXT: xxlor vs0, v0, v0
Show All 37 Lines
; CHECK-BE-NEXT: stxv vs2, 32(r3) ; CHECK-BE-NEXT: stxv vs2, 32(r3)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
%1 = tail call <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8> %vc1, <16 x i8> %vc3, <16 x i8> %vc2, <16 x i8> %vc4) %1 = tail call <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8> %vc1, <16 x i8> %vc3, <16 x i8> %vc2, <16 x i8> %vc4)
%2 = tail call <512 x i1> @llvm.ppc.mma.xvi4ger8pp(<512 x i1> %1, <16 x i8> %vc1, <16 x i8> %vc2) %2 = tail call <512 x i1> @llvm.ppc.mma.xvi4ger8pp(<512 x i1> %1, <16 x i8> %vc1, <16 x i8> %vc2)
%3 = tail call <512 x i1> @llvm.ppc.mma.xvf16ger2pp(<512 x i1> %2, <16 x i8> %vc1, <16 x i8> %vc3) %3 = tail call <512 x i1> @llvm.ppc.mma.xvf16ger2pp(<512 x i1> %2, <16 x i8> %vc1, <16 x i8> %vc3)
%4 = tail call <512 x i1> @llvm.ppc.mma.pmxvf32gerpn(<512 x i1> %3, <16 x i8> %vc2, <16 x i8> %vc4, i32 0, i32 0) %4 = tail call <512 x i1> @llvm.ppc.mma.pmxvf32gerpn(<512 x i1> %3, <16 x i8> %vc2, <16 x i8> %vc4, i32 0, i32 0)
%5 = tail call <256 x i1> @llvm.ppc.vsx.assemble.pair(<16 x i8> %vc4, <16 x i8> %vc1) %5 = tail call <256 x i1> @llvm.ppc.vsx.assemble.pair(<16 x i8> %vc4, <16 x i8> %vc1)
%6 = tail call <512 x i1> @llvm.ppc.mma.pmxvf64gernp(<512 x i1> %4, <256 x i1> %5, <16 x i8> %vc1, i32 0, i32 0) %6 = tail call <512 x i1> @llvm.ppc.mma.pmxvf64gernp(<512 x i1> %4, <256 x i1> %5, <16 x i8> %vc1, i32 0, i32 0)
%7 = bitcast i8* %ptr to <512 x i1>* store <512 x i1> %6, ptr %ptr, align 64
store <512 x i1> %6, <512 x i1>* %7, align 64
ret void ret void
} }
declare { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.ppc.mma.disassemble.acc(<512 x i1>) declare { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.ppc.mma.disassemble.acc(<512 x i1>)
define void @intrinsics2(<16 x i8>* %ptr1, <16 x i8>* %ptr2, <16 x i8>* %ptr3, <16 x i8>* %ptr4, i8* %ptr) { define void @intrinsics2(ptr %ptr1, ptr %ptr2, ptr %ptr3, ptr %ptr4, ptr %ptr) {
; CHECK-LABEL: intrinsics2: ; CHECK-LABEL: intrinsics2:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lxv v2, 0(r3) ; CHECK-NEXT: lxv v2, 0(r3)
; CHECK-NEXT: lxv v3, 0(r4) ; CHECK-NEXT: lxv v3, 0(r4)
; CHECK-NEXT: xxlor vs0, v2, v2 ; CHECK-NEXT: xxlor vs0, v2, v2
; CHECK-NEXT: lxv v4, 0(r5) ; CHECK-NEXT: lxv v4, 0(r5)
; CHECK-NEXT: lxv v5, 0(r6) ; CHECK-NEXT: lxv v5, 0(r6)
; CHECK-NEXT: xxlor vs1, v3, v3 ; CHECK-NEXT: xxlor vs1, v3, v3
Show All 31 Lines
; CHECK-BE-NEXT: pmxvf32gernn acc0, v3, v5, 0, 0 ; CHECK-BE-NEXT: pmxvf32gernn acc0, v3, v5, 0, 0
; CHECK-BE-NEXT: pmxvf64gernn acc0, vsp32, v2, 0, 0 ; CHECK-BE-NEXT: pmxvf64gernn acc0, vsp32, v2, 0, 0
; CHECK-BE-NEXT: xxmfacc acc0 ; CHECK-BE-NEXT: xxmfacc acc0
; CHECK-BE-NEXT: stxv vs0, 0(r3) ; CHECK-BE-NEXT: stxv vs0, 0(r3)
; CHECK-BE-NEXT: stxv vs1, 0(r4) ; CHECK-BE-NEXT: stxv vs1, 0(r4)
; CHECK-BE-NEXT: stxv vs2, 0(r5) ; CHECK-BE-NEXT: stxv vs2, 0(r5)
; CHECK-BE-NEXT: stxv vs3, 0(r6) ; CHECK-BE-NEXT: stxv vs3, 0(r6)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
%vc1 = load <16 x i8>, <16 x i8>* %ptr1, align 16 %vc1 = load <16 x i8>, ptr %ptr1, align 16
%vc2 = load <16 x i8>, <16 x i8>* %ptr2, align 16 %vc2 = load <16 x i8>, ptr %ptr2, align 16
%vc3 = load <16 x i8>, <16 x i8>* %ptr3, align 16 %vc3 = load <16 x i8>, ptr %ptr3, align 16
%vc4 = load <16 x i8>, <16 x i8>* %ptr4, align 16 %vc4 = load <16 x i8>, ptr %ptr4, align 16
%1 = tail call <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8> %vc1, <16 x i8> %vc2, <16 x i8> %vc3, <16 x i8> %vc4) %1 = tail call <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8> %vc1, <16 x i8> %vc2, <16 x i8> %vc3, <16 x i8> %vc4)
%2 = tail call <512 x i1> @llvm.ppc.mma.xvi8ger4pp(<512 x i1> %1, <16 x i8> %vc1, <16 x i8> %vc2) %2 = tail call <512 x i1> @llvm.ppc.mma.xvi8ger4pp(<512 x i1> %1, <16 x i8> %vc1, <16 x i8> %vc2)
%3 = tail call <512 x i1> @llvm.ppc.mma.xvf16ger2pn(<512 x i1> %2, <16 x i8> %vc1, <16 x i8> %vc3) %3 = tail call <512 x i1> @llvm.ppc.mma.xvf16ger2pn(<512 x i1> %2, <16 x i8> %vc1, <16 x i8> %vc3)
%4 = tail call <512 x i1> @llvm.ppc.mma.pmxvf32gernn(<512 x i1> %3, <16 x i8> %vc2, <16 x i8> %vc4, i32 0, i32 0) %4 = tail call <512 x i1> @llvm.ppc.mma.pmxvf32gernn(<512 x i1> %3, <16 x i8> %vc2, <16 x i8> %vc4, i32 0, i32 0)
%5 = tail call <256 x i1> @llvm.ppc.vsx.assemble.pair(<16 x i8> %vc4, <16 x i8> %vc1) %5 = tail call <256 x i1> @llvm.ppc.vsx.assemble.pair(<16 x i8> %vc4, <16 x i8> %vc1)
%6 = tail call <512 x i1> @llvm.ppc.mma.pmxvf64gernn(<512 x i1> %4, <256 x i1> %5, <16 x i8> %vc1, i32 0, i32 0) %6 = tail call <512 x i1> @llvm.ppc.mma.pmxvf64gernn(<512 x i1> %4, <256 x i1> %5, <16 x i8> %vc1, i32 0, i32 0)
%7 = tail call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.ppc.mma.disassemble.acc(<512 x i1> %6) %7 = tail call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.ppc.mma.disassemble.acc(<512 x i1> %6)
%8 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %7, 0 %8 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %7, 0
%9 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %7, 1 %9 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %7, 1
%10 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %7, 2 %10 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %7, 2
%11 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %7, 3 %11 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %7, 3
%12 = bitcast i8* %ptr to <512 x i1>* store <16 x i8> %8, ptr %ptr1, align 16
store <16 x i8> %8, <16 x i8>* %ptr1, align 16 store <16 x i8> %9, ptr %ptr2, align 16
store <16 x i8> %9, <16 x i8>* %ptr2, align 16 store <16 x i8> %10, ptr %ptr3, align 16
store <16 x i8> %10, <16 x i8>* %ptr3, align 16 store <16 x i8> %11, ptr %ptr4, align 16
store <16 x i8> %11, <16 x i8>* %ptr4, align 16
ret void ret void
} }
define void @test1(i8* %vqp, i8* %vpp, <16 x i8> %vc, i8* %resp) { define void @test1(ptr %vqp, ptr %vpp, <16 x i8> %vc, ptr %resp) {
; CHECK-LABEL: test1: ; CHECK-LABEL: test1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xvi4ger8 acc0, v2, v2 ; CHECK-NEXT: xvi4ger8 acc0, v2, v2
; CHECK-NEXT: xxmfacc acc0 ; CHECK-NEXT: xxmfacc acc0
; CHECK-NEXT: stxv vs0, 48(r7) ; CHECK-NEXT: stxv vs0, 48(r7)
; CHECK-NEXT: stxv vs1, 32(r7) ; CHECK-NEXT: stxv vs1, 32(r7)
; CHECK-NEXT: stxv vs2, 16(r7) ; CHECK-NEXT: stxv vs2, 16(r7)
; CHECK-NEXT: stxv vs3, 0(r7) ; CHECK-NEXT: stxv vs3, 0(r7)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-BE-LABEL: test1: ; CHECK-BE-LABEL: test1:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: xvi4ger8 acc0, v2, v2 ; CHECK-BE-NEXT: xvi4ger8 acc0, v2, v2
; CHECK-BE-NEXT: xxmfacc acc0 ; CHECK-BE-NEXT: xxmfacc acc0
; CHECK-BE-NEXT: stxv vs1, 16(r7) ; CHECK-BE-NEXT: stxv vs1, 16(r7)
; CHECK-BE-NEXT: stxv vs0, 0(r7) ; CHECK-BE-NEXT: stxv vs0, 0(r7)
; CHECK-BE-NEXT: stxv vs3, 48(r7) ; CHECK-BE-NEXT: stxv vs3, 48(r7)
; CHECK-BE-NEXT: stxv vs2, 32(r7) ; CHECK-BE-NEXT: stxv vs2, 32(r7)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = tail call <512 x i1> @llvm.ppc.mma.xvi4ger8(<16 x i8> %vc, <16 x i8> %vc) %0 = tail call <512 x i1> @llvm.ppc.mma.xvi4ger8(<16 x i8> %vc, <16 x i8> %vc)
%1 = bitcast i8* %resp to <512 x i1>* store <512 x i1> %0, ptr %resp, align 64
store <512 x i1> %0, <512 x i1>* %1, align 64
ret void ret void
} }
declare <512 x i1> @llvm.ppc.mma.xvi4ger8(<16 x i8>, <16 x i8>) declare <512 x i1> @llvm.ppc.mma.xvi4ger8(<16 x i8>, <16 x i8>)
define void @test2(i8* %vqp, i8* %vpp, <16 x i8> %vc, i8* %resp) { define void @test2(ptr %vqp, ptr %vpp, <16 x i8> %vc, ptr %resp) {
; CHECK-LABEL: test2: ; CHECK-LABEL: test2:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lxv vs1, 32(r3) ; CHECK-NEXT: lxv vs1, 32(r3)
; CHECK-NEXT: lxv vs0, 48(r3) ; CHECK-NEXT: lxv vs0, 48(r3)
; CHECK-NEXT: lxv vs3, 0(r3) ; CHECK-NEXT: lxv vs3, 0(r3)
; CHECK-NEXT: lxv vs2, 16(r3) ; CHECK-NEXT: lxv vs2, 16(r3)
; CHECK-NEXT: xxmtacc acc0 ; CHECK-NEXT: xxmtacc acc0
; CHECK-NEXT: xvi4ger8pp acc0, v2, v2 ; CHECK-NEXT: xvi4ger8pp acc0, v2, v2
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; CHECK-BE-NEXT: xvi4ger8pp acc0, v2, v2 ; CHECK-BE-NEXT: xvi4ger8pp acc0, v2, v2
; CHECK-BE-NEXT: xxmfacc acc0 ; CHECK-BE-NEXT: xxmfacc acc0
; CHECK-BE-NEXT: stxv vs1, 16(r7) ; CHECK-BE-NEXT: stxv vs1, 16(r7)
; CHECK-BE-NEXT: stxv vs0, 0(r7) ; CHECK-BE-NEXT: stxv vs0, 0(r7)
; CHECK-BE-NEXT: stxv vs3, 48(r7) ; CHECK-BE-NEXT: stxv vs3, 48(r7)
; CHECK-BE-NEXT: stxv vs2, 32(r7) ; CHECK-BE-NEXT: stxv vs2, 32(r7)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = bitcast i8* %vqp to <512 x i1>* %0 = load <512 x i1>, ptr %vqp, align 64
%1 = load <512 x i1>, <512 x i1>* %0, align 64 %1 = tail call <512 x i1> @llvm.ppc.mma.xvi4ger8pp(<512 x i1> %0, <16 x i8> %vc, <16 x i8> %vc)
%2 = tail call <512 x i1> @llvm.ppc.mma.xvi4ger8pp(<512 x i1> %1, <16 x i8> %vc, <16 x i8> %vc) store <512 x i1> %1, ptr %resp, align 64
%3 = bitcast i8* %resp to <512 x i1>*
store <512 x i1> %2, <512 x i1>* %3, align 64
ret void ret void
} }
declare <512 x i1> @llvm.ppc.mma.xvi4ger8pp(<512 x i1>, <16 x i8>, <16 x i8>) declare <512 x i1> @llvm.ppc.mma.xvi4ger8pp(<512 x i1>, <16 x i8>, <16 x i8>)
define void @test3(i8* %vqp, i8* %vpp, <16 x i8> %vc, i8* %resp) { define void @test3(ptr %vqp, ptr %vpp, <16 x i8> %vc, ptr %resp) {
; CHECK-LABEL: test3: ; CHECK-LABEL: test3:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pmxvi4ger8 acc0, v2, v2, 0, 0, 0 ; CHECK-NEXT: pmxvi4ger8 acc0, v2, v2, 0, 0, 0
; CHECK-NEXT: xxmfacc acc0 ; CHECK-NEXT: xxmfacc acc0
; CHECK-NEXT: stxv vs0, 48(r7) ; CHECK-NEXT: stxv vs0, 48(r7)
; CHECK-NEXT: stxv vs1, 32(r7) ; CHECK-NEXT: stxv vs1, 32(r7)
; CHECK-NEXT: stxv vs2, 16(r7) ; CHECK-NEXT: stxv vs2, 16(r7)
; CHECK-NEXT: stxv vs3, 0(r7) ; CHECK-NEXT: stxv vs3, 0(r7)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-BE-LABEL: test3: ; CHECK-BE-LABEL: test3:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: pmxvi4ger8 acc0, v2, v2, 0, 0, 0 ; CHECK-BE-NEXT: pmxvi4ger8 acc0, v2, v2, 0, 0, 0
; CHECK-BE-NEXT: xxmfacc acc0 ; CHECK-BE-NEXT: xxmfacc acc0
; CHECK-BE-NEXT: stxv vs1, 16(r7) ; CHECK-BE-NEXT: stxv vs1, 16(r7)
; CHECK-BE-NEXT: stxv vs0, 0(r7) ; CHECK-BE-NEXT: stxv vs0, 0(r7)
; CHECK-BE-NEXT: stxv vs3, 48(r7) ; CHECK-BE-NEXT: stxv vs3, 48(r7)
; CHECK-BE-NEXT: stxv vs2, 32(r7) ; CHECK-BE-NEXT: stxv vs2, 32(r7)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = tail call <512 x i1> @llvm.ppc.mma.pmxvi4ger8(<16 x i8> %vc, <16 x i8> %vc, i32 0, i32 0, i32 0) %0 = tail call <512 x i1> @llvm.ppc.mma.pmxvi4ger8(<16 x i8> %vc, <16 x i8> %vc, i32 0, i32 0, i32 0)
%1 = bitcast i8* %resp to <512 x i1>* store <512 x i1> %0, ptr %resp, align 64
store <512 x i1> %0, <512 x i1>* %1, align 64
ret void ret void
} }
declare <512 x i1> @llvm.ppc.mma.pmxvi4ger8(<16 x i8>, <16 x i8>, i32, i32, i32) declare <512 x i1> @llvm.ppc.mma.pmxvi4ger8(<16 x i8>, <16 x i8>, i32, i32, i32)
define void @test4(i8* %vqp, i8* %vpp, <16 x i8> %vc, i8* %resp) { define void @test4(ptr %vqp, ptr %vpp, <16 x i8> %vc, ptr %resp) {
; CHECK-LABEL: test4: ; CHECK-LABEL: test4:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lxv vs1, 32(r3) ; CHECK-NEXT: lxv vs1, 32(r3)
; CHECK-NEXT: lxv vs0, 48(r3) ; CHECK-NEXT: lxv vs0, 48(r3)
; CHECK-NEXT: lxv vs3, 0(r3) ; CHECK-NEXT: lxv vs3, 0(r3)
; CHECK-NEXT: lxv vs2, 16(r3) ; CHECK-NEXT: lxv vs2, 16(r3)
; CHECK-NEXT: xxmtacc acc0 ; CHECK-NEXT: xxmtacc acc0
; CHECK-NEXT: pmxvi4ger8pp acc0, v2, v2, 0, 0, 0 ; CHECK-NEXT: pmxvi4ger8pp acc0, v2, v2, 0, 0, 0
Show All 14 Lines
; CHECK-BE-NEXT: pmxvi4ger8pp acc0, v2, v2, 0, 0, 0 ; CHECK-BE-NEXT: pmxvi4ger8pp acc0, v2, v2, 0, 0, 0
; CHECK-BE-NEXT: xxmfacc acc0 ; CHECK-BE-NEXT: xxmfacc acc0
; CHECK-BE-NEXT: stxv vs1, 16(r7) ; CHECK-BE-NEXT: stxv vs1, 16(r7)
; CHECK-BE-NEXT: stxv vs0, 0(r7) ; CHECK-BE-NEXT: stxv vs0, 0(r7)
; CHECK-BE-NEXT: stxv vs3, 48(r7) ; CHECK-BE-NEXT: stxv vs3, 48(r7)
; CHECK-BE-NEXT: stxv vs2, 32(r7) ; CHECK-BE-NEXT: stxv vs2, 32(r7)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = bitcast i8* %vqp to <512 x i1>* %0 = load <512 x i1>, ptr %vqp, align 64
%1 = load <512 x i1>, <512 x i1>* %0, align 64 %1 = tail call <512 x i1> @llvm.ppc.mma.pmxvi4ger8pp(<512 x i1> %0, <16 x i8> %vc, <16 x i8> %vc, i32 0, i32 0, i32 0)
%2 = tail call <512 x i1> @llvm.ppc.mma.pmxvi4ger8pp(<512 x i1> %1, <16 x i8> %vc, <16 x i8> %vc, i32 0, i32 0, i32 0) store <512 x i1> %1, ptr %resp, align 64
%3 = bitcast i8* %resp to <512 x i1>*
store <512 x i1> %2, <512 x i1>* %3, align 64
ret void ret void
} }
declare <512 x i1> @llvm.ppc.mma.pmxvi4ger8pp(<512 x i1>, <16 x i8>, <16 x i8>, i32, i32, i32) declare <512 x i1> @llvm.ppc.mma.pmxvi4ger8pp(<512 x i1>, <16 x i8>, <16 x i8>, i32, i32, i32)
define void @test5(i8* %vqp, i8* %vpp, <16 x i8> %vc, i8* %resp) { define void @test5(ptr %vqp, ptr %vpp, <16 x i8> %vc, ptr %resp) {
; CHECK-LABEL: test5: ; CHECK-LABEL: test5:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xvi8ger4 acc0, v2, v2 ; CHECK-NEXT: xvi8ger4 acc0, v2, v2
; CHECK-NEXT: xxmfacc acc0 ; CHECK-NEXT: xxmfacc acc0
; CHECK-NEXT: stxv vs0, 48(r7) ; CHECK-NEXT: stxv vs0, 48(r7)
; CHECK-NEXT: stxv vs1, 32(r7) ; CHECK-NEXT: stxv vs1, 32(r7)
; CHECK-NEXT: stxv vs2, 16(r7) ; CHECK-NEXT: stxv vs2, 16(r7)
; CHECK-NEXT: stxv vs3, 0(r7) ; CHECK-NEXT: stxv vs3, 0(r7)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-BE-LABEL: test5: ; CHECK-BE-LABEL: test5:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: xvi8ger4 acc0, v2, v2 ; CHECK-BE-NEXT: xvi8ger4 acc0, v2, v2
; CHECK-BE-NEXT: xxmfacc acc0 ; CHECK-BE-NEXT: xxmfacc acc0
; CHECK-BE-NEXT: stxv vs1, 16(r7) ; CHECK-BE-NEXT: stxv vs1, 16(r7)
; CHECK-BE-NEXT: stxv vs0, 0(r7) ; CHECK-BE-NEXT: stxv vs0, 0(r7)
; CHECK-BE-NEXT: stxv vs3, 48(r7) ; CHECK-BE-NEXT: stxv vs3, 48(r7)
; CHECK-BE-NEXT: stxv vs2, 32(r7) ; CHECK-BE-NEXT: stxv vs2, 32(r7)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = tail call <512 x i1> @llvm.ppc.mma.xvi8ger4(<16 x i8> %vc, <16 x i8> %vc) %0 = tail call <512 x i1> @llvm.ppc.mma.xvi8ger4(<16 x i8> %vc, <16 x i8> %vc)
%1 = bitcast i8* %resp to <512 x i1>* store <512 x i1> %0, ptr %resp, align 64
store <512 x i1> %0, <512 x i1>* %1, align 64
ret void ret void
} }
declare <512 x i1> @llvm.ppc.mma.xvi8ger4(<16 x i8>, <16 x i8>) declare <512 x i1> @llvm.ppc.mma.xvi8ger4(<16 x i8>, <16 x i8>)
define void @test6(i8* %vqp, i8* %vpp, <16 x i8> %vc, i8* %resp) { define void @test6(ptr %vqp, ptr %vpp, <16 x i8> %vc, ptr %resp) {
; CHECK-LABEL: test6: ; CHECK-LABEL: test6:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lxv vs1, 32(r3) ; CHECK-NEXT: lxv vs1, 32(r3)
; CHECK-NEXT: lxv vs0, 48(r3) ; CHECK-NEXT: lxv vs0, 48(r3)
; CHECK-NEXT: lxv vs3, 0(r3) ; CHECK-NEXT: lxv vs3, 0(r3)
; CHECK-NEXT: lxv vs2, 16(r3) ; CHECK-NEXT: lxv vs2, 16(r3)
; CHECK-NEXT: xxmtacc acc0 ; CHECK-NEXT: xxmtacc acc0
; CHECK-NEXT: xvi8ger4pp acc0, v2, v2 ; CHECK-NEXT: xvi8ger4pp acc0, v2, v2
Show All 14 Lines
; CHECK-BE-NEXT: xvi8ger4pp acc0, v2, v2 ; CHECK-BE-NEXT: xvi8ger4pp acc0, v2, v2
; CHECK-BE-NEXT: xxmfacc acc0 ; CHECK-BE-NEXT: xxmfacc acc0
; CHECK-BE-NEXT: stxv vs1, 16(r7) ; CHECK-BE-NEXT: stxv vs1, 16(r7)
; CHECK-BE-NEXT: stxv vs0, 0(r7) ; CHECK-BE-NEXT: stxv vs0, 0(r7)
; CHECK-BE-NEXT: stxv vs3, 48(r7) ; CHECK-BE-NEXT: stxv vs3, 48(r7)
; CHECK-BE-NEXT: stxv vs2, 32(r7) ; CHECK-BE-NEXT: stxv vs2, 32(r7)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = bitcast i8* %vqp to <512 x i1>* %0 = load <512 x i1>, ptr %vqp, align 64
%1 = load <512 x i1>, <512 x i1>* %0, align 64 %1 = tail call <512 x i1> @llvm.ppc.mma.xvi8ger4pp(<512 x i1> %0, <16 x i8> %vc, <16 x i8> %vc)
%2 = tail call <512 x i1> @llvm.ppc.mma.xvi8ger4pp(<512 x i1> %1, <16 x i8> %vc, <16 x i8> %vc) store <512 x i1> %1, ptr %resp, align 64
%3 = bitcast i8* %resp to <512 x i1>*
store <512 x i1> %2, <512 x i1>* %3, align 64
ret void ret void
} }
declare <512 x i1> @llvm.ppc.mma.xvi8ger4pp(<512 x i1>, <16 x i8>, <16 x i8>) declare <512 x i1> @llvm.ppc.mma.xvi8ger4pp(<512 x i1>, <16 x i8>, <16 x i8>)
define void @test7(i8* %vqp, i8* %vpp, <16 x i8> %vc, i8* %resp) { define void @test7(ptr %vqp, ptr %vpp, <16 x i8> %vc, ptr %resp) {
; CHECK-LABEL: test7: ; CHECK-LABEL: test7:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pmxvi8ger4 acc0, v2, v2, 0, 0, 0 ; CHECK-NEXT: pmxvi8ger4 acc0, v2, v2, 0, 0, 0
; CHECK-NEXT: xxmfacc acc0 ; CHECK-NEXT: xxmfacc acc0
; CHECK-NEXT: stxv vs0, 48(r7) ; CHECK-NEXT: stxv vs0, 48(r7)
; CHECK-NEXT: stxv vs1, 32(r7) ; CHECK-NEXT: stxv vs1, 32(r7)
; CHECK-NEXT: stxv vs2, 16(r7) ; CHECK-NEXT: stxv vs2, 16(r7)
; CHECK-NEXT: stxv vs3, 0(r7) ; CHECK-NEXT: stxv vs3, 0(r7)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-BE-LABEL: test7: ; CHECK-BE-LABEL: test7:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: pmxvi8ger4 acc0, v2, v2, 0, 0, 0 ; CHECK-BE-NEXT: pmxvi8ger4 acc0, v2, v2, 0, 0, 0
; CHECK-BE-NEXT: xxmfacc acc0 ; CHECK-BE-NEXT: xxmfacc acc0
; CHECK-BE-NEXT: stxv vs1, 16(r7) ; CHECK-BE-NEXT: stxv vs1, 16(r7)
; CHECK-BE-NEXT: stxv vs0, 0(r7) ; CHECK-BE-NEXT: stxv vs0, 0(r7)
; CHECK-BE-NEXT: stxv vs3, 48(r7) ; CHECK-BE-NEXT: stxv vs3, 48(r7)
; CHECK-BE-NEXT: stxv vs2, 32(r7) ; CHECK-BE-NEXT: stxv vs2, 32(r7)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = tail call <512 x i1> @llvm.ppc.mma.pmxvi8ger4(<16 x i8> %vc, <16 x i8> %vc, i32 0, i32 0, i32 0) %0 = tail call <512 x i1> @llvm.ppc.mma.pmxvi8ger4(<16 x i8> %vc, <16 x i8> %vc, i32 0, i32 0, i32 0)
%1 = bitcast i8* %resp to <512 x i1>* store <512 x i1> %0, ptr %resp, align 64
store <512 x i1> %0, <512 x i1>* %1, align 64
ret void ret void
} }
declare <512 x i1> @llvm.ppc.mma.pmxvi8ger4(<16 x i8>, <16 x i8>, i32, i32, i32) declare <512 x i1> @llvm.ppc.mma.pmxvi8ger4(<16 x i8>, <16 x i8>, i32, i32, i32)
define void @test8(i8* %vqp, i8* %vpp, <16 x i8> %vc, i8* %resp) { define void @test8(ptr %vqp, ptr %vpp, <16 x i8> %vc, ptr %resp) {
; CHECK-LABEL: test8: ; CHECK-LABEL: test8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lxv vs1, 32(r3) ; CHECK-NEXT: lxv vs1, 32(r3)
; CHECK-NEXT: lxv vs0, 48(r3) ; CHECK-NEXT: lxv vs0, 48(r3)
; CHECK-NEXT: lxv vs3, 0(r3) ; CHECK-NEXT: lxv vs3, 0(r3)
; CHECK-NEXT: lxv vs2, 16(r3) ; CHECK-NEXT: lxv vs2, 16(r3)
; CHECK-NEXT: xxmtacc acc0 ; CHECK-NEXT: xxmtacc acc0
; CHECK-NEXT: pmxvi8ger4pp acc0, v2, v2, 0, 0, 0 ; CHECK-NEXT: pmxvi8ger4pp acc0, v2, v2, 0, 0, 0
Show All 14 Lines
; CHECK-BE-NEXT: pmxvi8ger4pp acc0, v2, v2, 0, 0, 0 ; CHECK-BE-NEXT: pmxvi8ger4pp acc0, v2, v2, 0, 0, 0
; CHECK-BE-NEXT: xxmfacc acc0 ; CHECK-BE-NEXT: xxmfacc acc0
; CHECK-BE-NEXT: stxv vs1, 16(r7) ; CHECK-BE-NEXT: stxv vs1, 16(r7)
; CHECK-BE-NEXT: stxv vs0, 0(r7) ; CHECK-BE-NEXT: stxv vs0, 0(r7)
; CHECK-BE-NEXT: stxv vs3, 48(r7) ; CHECK-BE-NEXT: stxv vs3, 48(r7)
; CHECK-BE-NEXT: stxv vs2, 32(r7) ; CHECK-BE-NEXT: stxv vs2, 32(r7)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = bitcast i8* %vqp to <512 x i1>* %0 = load <512 x i1>, ptr %vqp, align 64
%1 = load <512 x i1>, <512 x i1>* %0, align 64 %1 = tail call <512 x i1> @llvm.ppc.mma.pmxvi8ger4pp(<512 x i1> %0, <16 x i8> %vc, <16 x i8> %vc, i32 0, i32 0, i32 0)
%2 = tail call <512 x i1> @llvm.ppc.mma.pmxvi8ger4pp(<512 x i1> %1, <16 x i8> %vc, <16 x i8> %vc, i32 0, i32 0, i32 0) store <512 x i1> %1, ptr %resp, align 64
%3 = bitcast i8* %resp to <512 x i1>*
store <512 x i1> %2, <512 x i1>* %3, align 64
ret void ret void
} }
declare <512 x i1> @llvm.ppc.mma.pmxvi8ger4pp(<512 x i1>, <16 x i8>, <16 x i8>, i32, i32, i32) declare <512 x i1> @llvm.ppc.mma.pmxvi8ger4pp(<512 x i1>, <16 x i8>, <16 x i8>, i32, i32, i32)
define void @test9(i8* %vqp, i8* %vpp, <16 x i8> %vc, i8* %resp) { define void @test9(ptr %vqp, ptr %vpp, <16 x i8> %vc, ptr %resp) {
; CHECK-LABEL: test9: ; CHECK-LABEL: test9:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xvi16ger2s acc0, v2, v2 ; CHECK-NEXT: xvi16ger2s acc0, v2, v2
; CHECK-NEXT: xxmfacc acc0 ; CHECK-NEXT: xxmfacc acc0
; CHECK-NEXT: stxv vs0, 48(r7) ; CHECK-NEXT: stxv vs0, 48(r7)
; CHECK-NEXT: stxv vs1, 32(r7) ; CHECK-NEXT: stxv vs1, 32(r7)
; CHECK-NEXT: stxv vs2, 16(r7) ; CHECK-NEXT: stxv vs2, 16(r7)
; CHECK-NEXT: stxv vs3, 0(r7) ; CHECK-NEXT: stxv vs3, 0(r7)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-BE-LABEL: test9: ; CHECK-BE-LABEL: test9:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: xvi16ger2s acc0, v2, v2 ; CHECK-BE-NEXT: xvi16ger2s acc0, v2, v2
; CHECK-BE-NEXT: xxmfacc acc0 ; CHECK-BE-NEXT: xxmfacc acc0
; CHECK-BE-NEXT: stxv vs1, 16(r7) ; CHECK-BE-NEXT: stxv vs1, 16(r7)
; CHECK-BE-NEXT: stxv vs0, 0(r7) ; CHECK-BE-NEXT: stxv vs0, 0(r7)
; CHECK-BE-NEXT: stxv vs3, 48(r7) ; CHECK-BE-NEXT: stxv vs3, 48(r7)
; CHECK-BE-NEXT: stxv vs2, 32(r7) ; CHECK-BE-NEXT: stxv vs2, 32(r7)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = tail call <512 x i1> @llvm.ppc.mma.xvi16ger2s(<16 x i8> %vc, <16 x i8> %vc) %0 = tail call <512 x i1> @llvm.ppc.mma.xvi16ger2s(<16 x i8> %vc, <16 x i8> %vc)
%1 = bitcast i8* %resp to <512 x i1>* store <512 x i1> %0, ptr %resp, align 64
store <512 x i1> %0, <512 x i1>* %1, align 64
ret void ret void
} }
declare <512 x i1> @llvm.ppc.mma.xvi16ger2s(<16 x i8>, <16 x i8>) declare <512 x i1> @llvm.ppc.mma.xvi16ger2s(<16 x i8>, <16 x i8>)
define void @test10(i8* %vqp, i8* %vpp, <16 x i8> %vc, i8* %resp) { define void @test10(ptr %vqp, ptr %vpp, <16 x i8> %vc, ptr %resp) {
; CHECK-LABEL: test10: ; CHECK-LABEL: test10:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lxv vs1, 32(r3) ; CHECK-NEXT: lxv vs1, 32(r3)
; CHECK-NEXT: lxv vs0, 48(r3) ; CHECK-NEXT: lxv vs0, 48(r3)
; CHECK-NEXT: lxv vs3, 0(r3) ; CHECK-NEXT: lxv vs3, 0(r3)
; CHECK-NEXT: lxv vs2, 16(r3) ; CHECK-NEXT: lxv vs2, 16(r3)
; CHECK-NEXT: xxmtacc acc0 ; CHECK-NEXT: xxmtacc acc0
; CHECK-NEXT: xvi16ger2spp acc0, v2, v2 ; CHECK-NEXT: xvi16ger2spp acc0, v2, v2
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; CHECK-BE-NEXT: xvi16ger2spp acc0, v2, v2 ; CHECK-BE-NEXT: xvi16ger2spp acc0, v2, v2
; CHECK-BE-NEXT: xxmfacc acc0 ; CHECK-BE-NEXT: xxmfacc acc0
; CHECK-BE-NEXT: stxv vs1, 16(r7) ; CHECK-BE-NEXT: stxv vs1, 16(r7)
; CHECK-BE-NEXT: stxv vs0, 0(r7) ; CHECK-BE-NEXT: stxv vs0, 0(r7)
; CHECK-BE-NEXT: stxv vs3, 48(r7) ; CHECK-BE-NEXT: stxv vs3, 48(r7)
; CHECK-BE-NEXT: stxv vs2, 32(r7) ; CHECK-BE-NEXT: stxv vs2, 32(r7)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = bitcast i8* %vqp to <512 x i1>* %0 = load <512 x i1>, ptr %vqp, align 64
%1 = load <512 x i1>, <512 x i1>* %0, align 64 %1 = tail call <512 x i1> @llvm.ppc.mma.xvi16ger2spp(<512 x i1> %0, <16 x i8> %vc, <16 x i8> %vc)
%2 = tail call <512 x i1> @llvm.ppc.mma.xvi16ger2spp(<512 x i1> %1, <16 x i8> %vc, <16 x i8> %vc) store <512 x i1> %1, ptr %resp, align 64
%3 = bitcast i8* %resp to <512 x i1>*
store <512 x i1> %2, <512 x i1>* %3, align 64
ret void ret void
} }
declare <512 x i1> @llvm.ppc.mma.xvi16ger2spp(<512 x i1>, <16 x i8>, <16 x i8>) declare <512 x i1> @llvm.ppc.mma.xvi16ger2spp(<512 x i1>, <16 x i8>, <16 x i8>)
define void @test11(i8* %vqp, i8* %vpp, <16 x i8> %vc, i8* %resp) { define void @test11(ptr %vqp, ptr %vpp, <16 x i8> %vc, ptr %resp) {
; CHECK-LABEL: test11: ; CHECK-LABEL: test11:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pmxvi16ger2s acc0, v2, v2, 0, 0, 0 ; CHECK-NEXT: pmxvi16ger2s acc0, v2, v2, 0, 0, 0
; CHECK-NEXT: xxmfacc acc0 ; CHECK-NEXT: xxmfacc acc0
; CHECK-NEXT: stxv vs0, 48(r7) ; CHECK-NEXT: stxv vs0, 48(r7)
; CHECK-NEXT: stxv vs1, 32(r7) ; CHECK-NEXT: stxv vs1, 32(r7)
; CHECK-NEXT: stxv vs2, 16(r7) ; CHECK-NEXT: stxv vs2, 16(r7)
; CHECK-NEXT: stxv vs3, 0(r7) ; CHECK-NEXT: stxv vs3, 0(r7)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-BE-LABEL: test11: ; CHECK-BE-LABEL: test11:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: pmxvi16ger2s acc0, v2, v2, 0, 0, 0 ; CHECK-BE-NEXT: pmxvi16ger2s acc0, v2, v2, 0, 0, 0
; CHECK-BE-NEXT: xxmfacc acc0 ; CHECK-BE-NEXT: xxmfacc acc0
; CHECK-BE-NEXT: stxv vs1, 16(r7) ; CHECK-BE-NEXT: stxv vs1, 16(r7)
; CHECK-BE-NEXT: stxv vs0, 0(r7) ; CHECK-BE-NEXT: stxv vs0, 0(r7)
; CHECK-BE-NEXT: stxv vs3, 48(r7) ; CHECK-BE-NEXT: stxv vs3, 48(r7)
; CHECK-BE-NEXT: stxv vs2, 32(r7) ; CHECK-BE-NEXT: stxv vs2, 32(r7)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = tail call <512 x i1> @llvm.ppc.mma.pmxvi16ger2s(<16 x i8> %vc, <16 x i8> %vc, i32 0, i32 0, i32 0) %0 = tail call <512 x i1> @llvm.ppc.mma.pmxvi16ger2s(<16 x i8> %vc, <16 x i8> %vc, i32 0, i32 0, i32 0)
%1 = bitcast i8* %resp to <512 x i1>* store <512 x i1> %0, ptr %resp, align 64
store <512 x i1> %0, <512 x i1>* %1, align 64
ret void ret void
} }
declare <512 x i1> @llvm.ppc.mma.pmxvi16ger2s(<16 x i8>, <16 x i8>, i32, i32, i32) declare <512 x i1> @llvm.ppc.mma.pmxvi16ger2s(<16 x i8>, <16 x i8>, i32, i32, i32)
define void @test12(i8* %vqp, i8* %vpp, <16 x i8> %vc, i8* %resp) { define void @test12(ptr %vqp, ptr %vpp, <16 x i8> %vc, ptr %resp) {
; CHECK-LABEL: test12: ; CHECK-LABEL: test12:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lxv vs1, 32(r3) ; CHECK-NEXT: lxv vs1, 32(r3)
; CHECK-NEXT: lxv vs0, 48(r3) ; CHECK-NEXT: lxv vs0, 48(r3)
; CHECK-NEXT: lxv vs3, 0(r3) ; CHECK-NEXT: lxv vs3, 0(r3)
; CHECK-NEXT: lxv vs2, 16(r3) ; CHECK-NEXT: lxv vs2, 16(r3)
; CHECK-NEXT: xxmtacc acc0 ; CHECK-NEXT: xxmtacc acc0
; CHECK-NEXT: pmxvi16ger2spp acc0, v2, v2, 0, 0, 0 ; CHECK-NEXT: pmxvi16ger2spp acc0, v2, v2, 0, 0, 0
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; CHECK-BE-NEXT: pmxvi16ger2spp acc0, v2, v2, 0, 0, 0 ; CHECK-BE-NEXT: pmxvi16ger2spp acc0, v2, v2, 0, 0, 0
; CHECK-BE-NEXT: xxmfacc acc0 ; CHECK-BE-NEXT: xxmfacc acc0
; CHECK-BE-NEXT: stxv vs1, 16(r7) ; CHECK-BE-NEXT: stxv vs1, 16(r7)
; CHECK-BE-NEXT: stxv vs0, 0(r7) ; CHECK-BE-NEXT: stxv vs0, 0(r7)
; CHECK-BE-NEXT: stxv vs3, 48(r7) ; CHECK-BE-NEXT: stxv vs3, 48(r7)
; CHECK-BE-NEXT: stxv vs2, 32(r7) ; CHECK-BE-NEXT: stxv vs2, 32(r7)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = bitcast i8* %vqp to <512 x i1>* %0 = load <512 x i1>, ptr %vqp, align 64
%1 = load <512 x i1>, <512 x i1>* %0, align 64 %1 = tail call <512 x i1> @llvm.ppc.mma.pmxvi16ger2spp(<512 x i1> %0, <16 x i8> %vc, <16 x i8> %vc, i32 0, i32 0, i32 0)
%2 = tail call <512 x i1> @llvm.ppc.mma.pmxvi16ger2spp(<512 x i1> %1, <16 x i8> %vc, <16 x i8> %vc, i32 0, i32 0, i32 0) store <512 x i1> %1, ptr %resp, align 64
%3 = bitcast i8* %resp to <512 x i1>*
store <512 x i1> %2, <512 x i1>* %3, align 64
ret void ret void
} }
declare <512 x i1> @llvm.ppc.mma.pmxvi16ger2spp(<512 x i1>, <16 x i8>, <16 x i8>, i32, i32, i32) declare <512 x i1> @llvm.ppc.mma.pmxvi16ger2spp(<512 x i1>, <16 x i8>, <16 x i8>, i32, i32, i32)
define void @test13(i8* %vqp, i8* %vpp, <16 x i8> %vc, i8* %resp) { define void @test13(ptr %vqp, ptr %vpp, <16 x i8> %vc, ptr %resp) {
; CHECK-LABEL: test13: ; CHECK-LABEL: test13:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xvf16ger2 acc0, v2, v2 ; CHECK-NEXT: xvf16ger2 acc0, v2, v2
; CHECK-NEXT: xxmfacc acc0 ; CHECK-NEXT: xxmfacc acc0
; CHECK-NEXT: stxv vs0, 48(r7) ; CHECK-NEXT: stxv vs0, 48(r7)
; CHECK-NEXT: stxv vs1, 32(r7) ; CHECK-NEXT: stxv vs1, 32(r7)
; CHECK-NEXT: stxv vs2, 16(r7) ; CHECK-NEXT: stxv vs2, 16(r7)
; CHECK-NEXT: stxv vs3, 0(r7) ; CHECK-NEXT: stxv vs3, 0(r7)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-BE-LABEL: test13: ; CHECK-BE-LABEL: test13:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: xvf16ger2 acc0, v2, v2 ; CHECK-BE-NEXT: xvf16ger2 acc0, v2, v2
; CHECK-BE-NEXT: xxmfacc acc0 ; CHECK-BE-NEXT: xxmfacc acc0
; CHECK-BE-NEXT: stxv vs1, 16(r7) ; CHECK-BE-NEXT: stxv vs1, 16(r7)
; CHECK-BE-NEXT: stxv vs0, 0(r7) ; CHECK-BE-NEXT: stxv vs0, 0(r7)
; CHECK-BE-NEXT: stxv vs3, 48(r7) ; CHECK-BE-NEXT: stxv vs3, 48(r7)
; CHECK-BE-NEXT: stxv vs2, 32(r7) ; CHECK-BE-NEXT: stxv vs2, 32(r7)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = tail call <512 x i1> @llvm.ppc.mma.xvf16ger2(<16 x i8> %vc, <16 x i8> %vc) %0 = tail call <512 x i1> @llvm.ppc.mma.xvf16ger2(<16 x i8> %vc, <16 x i8> %vc)
%1 = bitcast i8* %resp to <512 x i1>* store <512 x i1> %0, ptr %resp, align 64
store <512 x i1> %0, <512 x i1>* %1, align 64
ret void ret void
} }
declare <512 x i1> @llvm.ppc.mma.xvf16ger2(<16 x i8>, <16 x i8>) declare <512 x i1> @llvm.ppc.mma.xvf16ger2(<16 x i8>, <16 x i8>)
define void @test14(i8* %vqp, i8* %vpp, <16 x i8> %vc, i8* %resp) { define void @test14(ptr %vqp, ptr %vpp, <16 x i8> %vc, ptr %resp) {
; CHECK-LABEL: test14: ; CHECK-LABEL: test14:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lxv vs1, 32(r3) ; CHECK-NEXT: lxv vs1, 32(r3)
; CHECK-NEXT: lxv vs0, 48(r3) ; CHECK-NEXT: lxv vs0, 48(r3)
; CHECK-NEXT: lxv vs3, 0(r3) ; CHECK-NEXT: lxv vs3, 0(r3)
; CHECK-NEXT: lxv vs2, 16(r3) ; CHECK-NEXT: lxv vs2, 16(r3)
; CHECK-NEXT: xxmtacc acc0 ; CHECK-NEXT: xxmtacc acc0
; CHECK-NEXT: xvf16ger2pp acc0, v2, v2 ; CHECK-NEXT: xvf16ger2pp acc0, v2, v2
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; CHECK-BE-NEXT: xvf16ger2pp acc0, v2, v2 ; CHECK-BE-NEXT: xvf16ger2pp acc0, v2, v2
; CHECK-BE-NEXT: xxmfacc acc0 ; CHECK-BE-NEXT: xxmfacc acc0
; CHECK-BE-NEXT: stxv vs1, 16(r7) ; CHECK-BE-NEXT: stxv vs1, 16(r7)
; CHECK-BE-NEXT: stxv vs0, 0(r7) ; CHECK-BE-NEXT: stxv vs0, 0(r7)
; CHECK-BE-NEXT: stxv vs3, 48(r7) ; CHECK-BE-NEXT: stxv vs3, 48(r7)
; CHECK-BE-NEXT: stxv vs2, 32(r7) ; CHECK-BE-NEXT: stxv vs2, 32(r7)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = bitcast i8* %vqp to <512 x i1>* %0 = load <512 x i1>, ptr %vqp, align 64
%1 = load <512 x i1>, <512 x i1>* %0, align 64 %1 = tail call <512 x i1> @llvm.ppc.mma.xvf16ger2pp(<512 x i1> %0, <16 x i8> %vc, <16 x i8> %vc)
%2 = tail call <512 x i1> @llvm.ppc.mma.xvf16ger2pp(<512 x i1> %1, <16 x i8> %vc, <16 x i8> %vc) store <512 x i1> %1, ptr %resp, align 64
%3 = bitcast i8* %resp to <512 x i1>*
store <512 x i1> %2, <512 x i1>* %3, align 64
ret void ret void
} }
declare <512 x i1> @llvm.ppc.mma.xvf16ger2pp(<512 x i1>, <16 x i8>, <16 x i8>) declare <512 x i1> @llvm.ppc.mma.xvf16ger2pp(<512 x i1>, <16 x i8>, <16 x i8>)
define void @test15(i8* %vqp, i8* %vpp, <16 x i8> %vc, i8* %resp) { define void @test15(ptr %vqp, ptr %vpp, <16 x i8> %vc, ptr %resp) {
; CHECK-LABEL: test15: ; CHECK-LABEL: test15:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lxv vs1, 32(r3) ; CHECK-NEXT: lxv vs1, 32(r3)
; CHECK-NEXT: lxv vs0, 48(r3) ; CHECK-NEXT: lxv vs0, 48(r3)
; CHECK-NEXT: lxv vs3, 0(r3) ; CHECK-NEXT: lxv vs3, 0(r3)
; CHECK-NEXT: lxv vs2, 16(r3) ; CHECK-NEXT: lxv vs2, 16(r3)
; CHECK-NEXT: xxmtacc acc0 ; CHECK-NEXT: xxmtacc acc0
; CHECK-NEXT: xvf16ger2pn acc0, v2, v2 ; CHECK-NEXT: xvf16ger2pn acc0, v2, v2
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; CHECK-BE-NEXT: xvf16ger2pn acc0, v2, v2 ; CHECK-BE-NEXT: xvf16ger2pn acc0, v2, v2
; CHECK-BE-NEXT: xxmfacc acc0 ; CHECK-BE-NEXT: xxmfacc acc0
; CHECK-BE-NEXT: stxv vs1, 16(r7) ; CHECK-BE-NEXT: stxv vs1, 16(r7)
; CHECK-BE-NEXT: stxv vs0, 0(r7) ; CHECK-BE-NEXT: stxv vs0, 0(r7)
; CHECK-BE-NEXT: stxv vs3, 48(r7) ; CHECK-BE-NEXT: stxv vs3, 48(r7)
; CHECK-BE-NEXT: stxv vs2, 32(r7) ; CHECK-BE-NEXT: stxv vs2, 32(r7)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = bitcast i8* %vqp to <512 x i1>* %0 = load <512 x i1>, ptr %vqp, align 64
%1 = load <512 x i1>, <512 x i1>* %0, align 64 %1 = tail call <512 x i1> @llvm.ppc.mma.xvf16ger2pn(<512 x i1> %0, <16 x i8> %vc, <16 x i8> %vc)
%2 = tail call <512 x i1> @llvm.ppc.mma.xvf16ger2pn(<512 x i1> %1, <16 x i8> %vc, <16 x i8> %vc) store <512 x i1> %1, ptr %resp, align 64
%3 = bitcast i8* %resp to <512 x i1>*
store <512 x i1> %2, <512 x i1>* %3, align 64
ret void ret void
} }
declare <512 x i1> @llvm.ppc.mma.xvf16ger2pn(<512 x i1>, <16 x i8>, <16 x i8>) declare <512 x i1> @llvm.ppc.mma.xvf16ger2pn(<512 x i1>, <16 x i8>, <16 x i8>)
define void @test16(i8* %vqp, i8* %vpp, <16 x i8> %vc, i8* %resp) { define void @test16(ptr %vqp, ptr %vpp, <16 x i8> %vc, ptr %resp) {
; CHECK-LABEL: test16: ; CHECK-LABEL: test16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lxv vs1, 32(r3) ; CHECK-NEXT: lxv vs1, 32(r3)
; CHECK-NEXT: lxv vs0, 48(r3) ; CHECK-NEXT: lxv vs0, 48(r3)
; CHECK-NEXT: lxv vs3, 0(r3) ; CHECK-NEXT: lxv vs3, 0(r3)
; CHECK-NEXT: lxv vs2, 16(r3) ; CHECK-NEXT: lxv vs2, 16(r3)
; CHECK-NEXT: xxmtacc acc0 ; CHECK-NEXT: xxmtacc acc0
; CHECK-NEXT: xvf16ger2np acc0, v2, v2 ; CHECK-NEXT: xvf16ger2np acc0, v2, v2
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; CHECK-BE-NEXT: xvf16ger2np acc0, v2, v2 ; CHECK-BE-NEXT: xvf16ger2np acc0, v2, v2
; CHECK-BE-NEXT: xxmfacc acc0 ; CHECK-BE-NEXT: xxmfacc acc0
; CHECK-BE-NEXT: stxv vs1, 16(r7) ; CHECK-BE-NEXT: stxv vs1, 16(r7)
; CHECK-BE-NEXT: stxv vs0, 0(r7) ; CHECK-BE-NEXT: stxv vs0, 0(r7)
; CHECK-BE-NEXT: stxv vs3, 48(r7) ; CHECK-BE-NEXT: stxv vs3, 48(r7)
; CHECK-BE-NEXT: stxv vs2, 32(r7) ; CHECK-BE-NEXT: stxv vs2, 32(r7)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = bitcast i8* %vqp to <512 x i1>* %0 = load <512 x i1>, ptr %vqp, align 64
%1 = load <512 x i1>, <512 x i1>* %0, align 64 %1 = tail call <512 x i1> @llvm.ppc.mma.xvf16ger2np(<512 x i1> %0, <16 x i8> %vc, <16 x i8> %vc)
%2 = tail call <512 x i1> @llvm.ppc.mma.xvf16ger2np(<512 x i1> %1, <16 x i8> %vc, <16 x i8> %vc) store <512 x i1> %1, ptr %resp, align 64
%3 = bitcast i8* %resp to <512 x i1>*
store <512 x i1> %2, <512 x i1>* %3, align 64
ret void ret void
} }
declare <512 x i1> @llvm.ppc.mma.xvf16ger2np(<512 x i1>, <16 x i8>, <16 x i8>) declare <512 x i1> @llvm.ppc.mma.xvf16ger2np(<512 x i1>, <16 x i8>, <16 x i8>)
define void @test17(i8* %vqp, i8* %vpp, <16 x i8> %vc, i8* %resp) { define void @test17(ptr %vqp, ptr %vpp, <16 x i8> %vc, ptr %resp) {
; CHECK-LABEL: test17: ; CHECK-LABEL: test17:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lxv vs1, 32(r3) ; CHECK-NEXT: lxv vs1, 32(r3)
; CHECK-NEXT: lxv vs0, 48(r3) ; CHECK-NEXT: lxv vs0, 48(r3)
; CHECK-NEXT: lxv vs3, 0(r3) ; CHECK-NEXT: lxv vs3, 0(r3)
; CHECK-NEXT: lxv vs2, 16(r3) ; CHECK-NEXT: lxv vs2, 16(r3)
; CHECK-NEXT: xxmtacc acc0 ; CHECK-NEXT: xxmtacc acc0
; CHECK-NEXT: xvf16ger2nn acc0, v2, v2 ; CHECK-NEXT: xvf16ger2nn acc0, v2, v2
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; CHECK-BE-NEXT: xvf16ger2nn acc0, v2, v2 ; CHECK-BE-NEXT: xvf16ger2nn acc0, v2, v2
; CHECK-BE-NEXT: xxmfacc acc0 ; CHECK-BE-NEXT: xxmfacc acc0
; CHECK-BE-NEXT: stxv vs1, 16(r7) ; CHECK-BE-NEXT: stxv vs1, 16(r7)
; CHECK-BE-NEXT: stxv vs0, 0(r7) ; CHECK-BE-NEXT: stxv vs0, 0(r7)
; CHECK-BE-NEXT: stxv vs3, 48(r7) ; CHECK-BE-NEXT: stxv vs3, 48(r7)
; CHECK-BE-NEXT: stxv vs2, 32(r7) ; CHECK-BE-NEXT: stxv vs2, 32(r7)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = bitcast i8* %vqp to <512 x i1>* %0 = load <512 x i1>, ptr %vqp, align 64
%1 = load <512 x i1>, <512 x i1>* %0, align 64 %1 = tail call <512 x i1> @llvm.ppc.mma.xvf16ger2nn(<512 x i1> %0, <16 x i8> %vc, <16 x i8> %vc)
%2 = tail call <512 x i1> @llvm.ppc.mma.xvf16ger2nn(<512 x i1> %1, <16 x i8> %vc, <16 x i8> %vc) store <512 x i1> %1, ptr %resp, align 64
%3 = bitcast i8* %resp to <512 x i1>*
store <512 x i1> %2, <512 x i1>* %3, align 64
ret void ret void
} }
declare <512 x i1> @llvm.ppc.mma.xvf16ger2nn(<512 x i1>, <16 x i8>, <16 x i8>) declare <512 x i1> @llvm.ppc.mma.xvf16ger2nn(<512 x i1>, <16 x i8>, <16 x i8>)
define void @test18(i8* %vqp, i8* %vpp, <16 x i8> %vc, i8* %resp) { define void @test18(ptr %vqp, ptr %vpp, <16 x i8> %vc, ptr %resp) {
; CHECK-LABEL: test18: ; CHECK-LABEL: test18:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pmxvf16ger2 acc0, v2, v2, 0, 0, 0 ; CHECK-NEXT: pmxvf16ger2 acc0, v2, v2, 0, 0, 0
; CHECK-NEXT: xxmfacc acc0 ; CHECK-NEXT: xxmfacc acc0
; CHECK-NEXT: stxv vs0, 48(r7) ; CHECK-NEXT: stxv vs0, 48(r7)
; CHECK-NEXT: stxv vs1, 32(r7) ; CHECK-NEXT: stxv vs1, 32(r7)
; CHECK-NEXT: stxv vs2, 16(r7) ; CHECK-NEXT: stxv vs2, 16(r7)
; CHECK-NEXT: stxv vs3, 0(r7) ; CHECK-NEXT: stxv vs3, 0(r7)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-BE-LABEL: test18: ; CHECK-BE-LABEL: test18:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: pmxvf16ger2 acc0, v2, v2, 0, 0, 0 ; CHECK-BE-NEXT: pmxvf16ger2 acc0, v2, v2, 0, 0, 0
; CHECK-BE-NEXT: xxmfacc acc0 ; CHECK-BE-NEXT: xxmfacc acc0
; CHECK-BE-NEXT: stxv vs1, 16(r7) ; CHECK-BE-NEXT: stxv vs1, 16(r7)
; CHECK-BE-NEXT: stxv vs0, 0(r7) ; CHECK-BE-NEXT: stxv vs0, 0(r7)
; CHECK-BE-NEXT: stxv vs3, 48(r7) ; CHECK-BE-NEXT: stxv vs3, 48(r7)
; CHECK-BE-NEXT: stxv vs2, 32(r7) ; CHECK-BE-NEXT: stxv vs2, 32(r7)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = tail call <512 x i1> @llvm.ppc.mma.pmxvf16ger2(<16 x i8> %vc, <16 x i8> %vc, i32 0, i32 0, i32 0) %0 = tail call <512 x i1> @llvm.ppc.mma.pmxvf16ger2(<16 x i8> %vc, <16 x i8> %vc, i32 0, i32 0, i32 0)
%1 = bitcast i8* %resp to <512 x i1>* store <512 x i1> %0, ptr %resp, align 64
store <512 x i1> %0, <512 x i1>* %1, align 64
ret void ret void
} }
declare <512 x i1> @llvm.ppc.mma.pmxvf16ger2(<16 x i8>, <16 x i8>, i32, i32, i32) declare <512 x i1> @llvm.ppc.mma.pmxvf16ger2(<16 x i8>, <16 x i8>, i32, i32, i32)
define void @test19(i8* %vqp, i8* %vpp, <16 x i8> %vc, i8* %resp) { define void @test19(ptr %vqp, ptr %vpp, <16 x i8> %vc, ptr %resp) {
; CHECK-LABEL: test19: ; CHECK-LABEL: test19:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lxv vs1, 32(r3) ; CHECK-NEXT: lxv vs1, 32(r3)
; CHECK-NEXT: lxv vs0, 48(r3) ; CHECK-NEXT: lxv vs0, 48(r3)
; CHECK-NEXT: lxv vs3, 0(r3) ; CHECK-NEXT: lxv vs3, 0(r3)
; CHECK-NEXT: lxv vs2, 16(r3) ; CHECK-NEXT: lxv vs2, 16(r3)
; CHECK-NEXT: xxmtacc acc0 ; CHECK-NEXT: xxmtacc acc0
; CHECK-NEXT: pmxvf16ger2pp acc0, v2, v2, 0, 0, 0 ; CHECK-NEXT: pmxvf16ger2pp acc0, v2, v2, 0, 0, 0
Show All 14 Lines
; CHECK-BE-NEXT: pmxvf16ger2pp acc0, v2, v2, 0, 0, 0 ; CHECK-BE-NEXT: pmxvf16ger2pp acc0, v2, v2, 0, 0, 0
; CHECK-BE-NEXT: xxmfacc acc0 ; CHECK-BE-NEXT: xxmfacc acc0
; CHECK-BE-NEXT: stxv vs1, 16(r7) ; CHECK-BE-NEXT: stxv vs1, 16(r7)
; CHECK-BE-NEXT: stxv vs0, 0(r7) ; CHECK-BE-NEXT: stxv vs0, 0(r7)
; CHECK-BE-NEXT: stxv vs3, 48(r7) ; CHECK-BE-NEXT: stxv vs3, 48(r7)
; CHECK-BE-NEXT: stxv vs2, 32(r7) ; CHECK-BE-NEXT: stxv vs2, 32(r7)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = bitcast i8* %vqp to <512 x i1>* %0 = load <512 x i1>, ptr %vqp, align 64
%1 = load <512 x i1>, <512 x i1>* %0, align 64 %1 = tail call <512 x i1> @llvm.ppc.mma.pmxvf16ger2pp(<512 x i1> %0, <16 x i8> %vc, <16 x i8> %vc, i32 0, i32 0, i32 0)
%2 = tail call <512 x i1> @llvm.ppc.mma.pmxvf16ger2pp(<512 x i1> %1, <16 x i8> %vc, <16 x i8> %vc, i32 0, i32 0, i32 0) store <512 x i1> %1, ptr %resp, align 64
%3 = bitcast i8* %resp to <512 x i1>*
store <512 x i1> %2, <512 x i1>* %3, align 64
ret void ret void
} }
declare <512 x i1> @llvm.ppc.mma.pmxvf16ger2pp(<512 x i1>, <16 x i8>, <16 x i8>, i32, i32, i32) declare <512 x i1> @llvm.ppc.mma.pmxvf16ger2pp(<512 x i1>, <16 x i8>, <16 x i8>, i32, i32, i32)
define void @test20(i8* %vqp, i8* %vpp, <16 x i8> %vc, i8* %resp) { define void @test20(ptr %vqp, ptr %vpp, <16 x i8> %vc, ptr %resp) {
; CHECK-LABEL: test20: ; CHECK-LABEL: test20:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lxv vs1, 32(r3) ; CHECK-NEXT: lxv vs1, 32(r3)
; CHECK-NEXT: lxv vs0, 48(r3) ; CHECK-NEXT: lxv vs0, 48(r3)
; CHECK-NEXT: lxv vs3, 0(r3) ; CHECK-NEXT: lxv vs3, 0(r3)
; CHECK-NEXT: lxv vs2, 16(r3) ; CHECK-NEXT: lxv vs2, 16(r3)
; CHECK-NEXT: xxmtacc acc0 ; CHECK-NEXT: xxmtacc acc0
; CHECK-NEXT: pmxvf16ger2pn acc0, v2, v2, 0, 0, 0 ; CHECK-NEXT: pmxvf16ger2pn acc0, v2, v2, 0, 0, 0
Show All 14 Lines
; CHECK-BE-NEXT: pmxvf16ger2pn acc0, v2, v2, 0, 0, 0 ; CHECK-BE-NEXT: pmxvf16ger2pn acc0, v2, v2, 0, 0, 0
; CHECK-BE-NEXT: xxmfacc acc0 ; CHECK-BE-NEXT: xxmfacc acc0
; CHECK-BE-NEXT: stxv vs1, 16(r7) ; CHECK-BE-NEXT: stxv vs1, 16(r7)
; CHECK-BE-NEXT: stxv vs0, 0(r7) ; CHECK-BE-NEXT: stxv vs0, 0(r7)
; CHECK-BE-NEXT: stxv vs3, 48(r7) ; CHECK-BE-NEXT: stxv vs3, 48(r7)
; CHECK-BE-NEXT: stxv vs2, 32(r7) ; CHECK-BE-NEXT: stxv vs2, 32(r7)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = bitcast i8* %vqp to <512 x i1>* %0 = load <512 x i1>, ptr %vqp, align 64
%1 = load <512 x i1>, <512 x i1>* %0, align 64 %1 = tail call <512 x i1> @llvm.ppc.mma.pmxvf16ger2pn(<512 x i1> %0, <16 x i8> %vc, <16 x i8> %vc, i32 0, i32 0, i32 0)
%2 = tail call <512 x i1> @llvm.ppc.mma.pmxvf16ger2pn(<512 x i1> %1, <16 x i8> %vc, <16 x i8> %vc, i32 0, i32 0, i32 0) store <512 x i1> %1, ptr %resp, align 64
%3 = bitcast i8* %resp to <512 x i1>*
store <512 x i1> %2, <512 x i1>* %3, align 64
ret void ret void
} }
declare <512 x i1> @llvm.ppc.mma.pmxvf16ger2pn(<512 x i1>, <16 x i8>, <16 x i8>, i32, i32, i32) declare <512 x i1> @llvm.ppc.mma.pmxvf16ger2pn(<512 x i1>, <16 x i8>, <16 x i8>, i32, i32, i32)
define void @test21(i8* %vqp, i8* %vpp, <16 x i8> %vc, i8* %resp) { define void @test21(ptr %vqp, ptr %vpp, <16 x i8> %vc, ptr %resp) {
; CHECK-LABEL: test21: ; CHECK-LABEL: test21:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lxv vs1, 32(r3) ; CHECK-NEXT: lxv vs1, 32(r3)
; CHECK-NEXT: lxv vs0, 48(r3) ; CHECK-NEXT: lxv vs0, 48(r3)
; CHECK-NEXT: lxv vs3, 0(r3) ; CHECK-NEXT: lxv vs3, 0(r3)
; CHECK-NEXT: lxv vs2, 16(r3) ; CHECK-NEXT: lxv vs2, 16(r3)
; CHECK-NEXT: xxmtacc acc0 ; CHECK-NEXT: xxmtacc acc0
; CHECK-NEXT: pmxvf16ger2np acc0, v2, v2, 0, 0, 0 ; CHECK-NEXT: pmxvf16ger2np acc0, v2, v2, 0, 0, 0
Show All 14 Lines
; CHECK-BE-NEXT: pmxvf16ger2np acc0, v2, v2, 0, 0, 0 ; CHECK-BE-NEXT: pmxvf16ger2np acc0, v2, v2, 0, 0, 0
; CHECK-BE-NEXT: xxmfacc acc0 ; CHECK-BE-NEXT: xxmfacc acc0
; CHECK-BE-NEXT: stxv vs1, 16(r7) ; CHECK-BE-NEXT: stxv vs1, 16(r7)
; CHECK-BE-NEXT: stxv vs0, 0(r7) ; CHECK-BE-NEXT: stxv vs0, 0(r7)
; CHECK-BE-NEXT: stxv vs3, 48(r7) ; CHECK-BE-NEXT: stxv vs3, 48(r7)
; CHECK-BE-NEXT: stxv vs2, 32(r7) ; CHECK-BE-NEXT: stxv vs2, 32(r7)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = bitcast i8* %vqp to <512 x i1>* %0 = load <512 x i1>, ptr %vqp, align 64
%1 = load <512 x i1>, <512 x i1>* %0, align 64 %1 = tail call <512 x i1> @llvm.ppc.mma.pmxvf16ger2np(<512 x i1> %0, <16 x i8> %vc, <16 x i8> %vc, i32 0, i32 0, i32 0)
%2 = tail call <512 x i1> @llvm.ppc.mma.pmxvf16ger2np(<512 x i1> %1, <16 x i8> %vc, <16 x i8> %vc, i32 0, i32 0, i32 0) store <512 x i1> %1, ptr %resp, align 64
%3 = bitcast i8* %resp to <512 x i1>*
store <512 x i1> %2, <512 x i1>* %3, align 64
ret void ret void
} }
declare <512 x i1> @llvm.ppc.mma.pmxvf16ger2np(<512 x i1>, <16 x i8>, <16 x i8>, i32, i32, i32) declare <512 x i1> @llvm.ppc.mma.pmxvf16ger2np(<512 x i1>, <16 x i8>, <16 x i8>, i32, i32, i32)
define void @test22(i8* %vqp, i8* %vpp, <16 x i8> %vc, i8* %resp) { define void @test22(ptr %vqp, ptr %vpp, <16 x i8> %vc, ptr %resp) {
; CHECK-LABEL: test22: ; CHECK-LABEL: test22:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lxv vs1, 32(r3) ; CHECK-NEXT: lxv vs1, 32(r3)
; CHECK-NEXT: lxv vs0, 48(r3) ; CHECK-NEXT: lxv vs0, 48(r3)
; CHECK-NEXT: lxv vs3, 0(r3) ; CHECK-NEXT: lxv vs3, 0(r3)
; CHECK-NEXT: lxv vs2, 16(r3) ; CHECK-NEXT: lxv vs2, 16(r3)
; CHECK-NEXT: xxmtacc acc0 ; CHECK-NEXT: xxmtacc acc0
; CHECK-NEXT: pmxvf16ger2nn acc0, v2, v2, 0, 0, 0 ; CHECK-NEXT: pmxvf16ger2nn acc0, v2, v2, 0, 0, 0
Show All 14 Lines
; CHECK-BE-NEXT: pmxvf16ger2nn acc0, v2, v2, 0, 0, 0 ; CHECK-BE-NEXT: pmxvf16ger2nn acc0, v2, v2, 0, 0, 0
; CHECK-BE-NEXT: xxmfacc acc0 ; CHECK-BE-NEXT: xxmfacc acc0
; CHECK-BE-NEXT: stxv vs1, 16(r7) ; CHECK-BE-NEXT: stxv vs1, 16(r7)
; CHECK-BE-NEXT: stxv vs0, 0(r7) ; CHECK-BE-NEXT: stxv vs0, 0(r7)
; CHECK-BE-NEXT: stxv vs3, 48(r7) ; CHECK-BE-NEXT: stxv vs3, 48(r7)
; CHECK-BE-NEXT: stxv vs2, 32(r7) ; CHECK-BE-NEXT: stxv vs2, 32(r7)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = bitcast i8* %vqp to <512 x i1>* %0 = load <512 x i1>, ptr %vqp, align 64
%1 = load <512 x i1>, <512 x i1>* %0, align 64 %1 = tail call <512 x i1> @llvm.ppc.mma.pmxvf16ger2nn(<512 x i1> %0, <16 x i8> %vc, <16 x i8> %vc, i32 0, i32 0, i32 0)
%2 = tail call <512 x i1> @llvm.ppc.mma.pmxvf16ger2nn(<512 x i1> %1, <16 x i8> %vc, <16 x i8> %vc, i32 0, i32 0, i32 0) store <512 x i1> %1, ptr %resp, align 64
%3 = bitcast i8* %resp to <512 x i1>*
store <512 x i1> %2, <512 x i1>* %3, align 64
ret void ret void
} }
declare <512 x i1> @llvm.ppc.mma.pmxvf16ger2nn(<512 x i1>, <16 x i8>, <16 x i8>, i32, i32, i32) declare <512 x i1> @llvm.ppc.mma.pmxvf16ger2nn(<512 x i1>, <16 x i8>, <16 x i8>, i32, i32, i32)
define void @test23(i8* %vqp, i8* %vpp, <16 x i8> %vc, i8* %resp) { define void @test23(ptr %vqp, ptr %vpp, <16 x i8> %vc, ptr %resp) {
; CHECK-LABEL: test23: ; CHECK-LABEL: test23:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xvf32ger acc0, v2, v2 ; CHECK-NEXT: xvf32ger acc0, v2, v2
; CHECK-NEXT: xxmfacc acc0 ; CHECK-NEXT: xxmfacc acc0
; CHECK-NEXT: stxv vs0, 48(r7) ; CHECK-NEXT: stxv vs0, 48(r7)
; CHECK-NEXT: stxv vs1, 32(r7) ; CHECK-NEXT: stxv vs1, 32(r7)
; CHECK-NEXT: stxv vs2, 16(r7) ; CHECK-NEXT: stxv vs2, 16(r7)
; CHECK-NEXT: stxv vs3, 0(r7) ; CHECK-NEXT: stxv vs3, 0(r7)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-BE-LABEL: test23: ; CHECK-BE-LABEL: test23:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: xvf32ger acc0, v2, v2 ; CHECK-BE-NEXT: xvf32ger acc0, v2, v2
; CHECK-BE-NEXT: xxmfacc acc0 ; CHECK-BE-NEXT: xxmfacc acc0
; CHECK-BE-NEXT: stxv vs1, 16(r7) ; CHECK-BE-NEXT: stxv vs1, 16(r7)
; CHECK-BE-NEXT: stxv vs0, 0(r7) ; CHECK-BE-NEXT: stxv vs0, 0(r7)
; CHECK-BE-NEXT: stxv vs3, 48(r7) ; CHECK-BE-NEXT: stxv vs3, 48(r7)
; CHECK-BE-NEXT: stxv vs2, 32(r7) ; CHECK-BE-NEXT: stxv vs2, 32(r7)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = tail call <512 x i1> @llvm.ppc.mma.xvf32ger(<16 x i8> %vc, <16 x i8> %vc) %0 = tail call <512 x i1> @llvm.ppc.mma.xvf32ger(<16 x i8> %vc, <16 x i8> %vc)
%1 = bitcast i8* %resp to <512 x i1>* store <512 x i1> %0, ptr %resp, align 64
store <512 x i1> %0, <512 x i1>* %1, align 64
ret void ret void
} }
declare <512 x i1> @llvm.ppc.mma.xvf32ger(<16 x i8>, <16 x i8>) declare <512 x i1> @llvm.ppc.mma.xvf32ger(<16 x i8>, <16 x i8>)
define void @test24(i8* %vqp, i8* %vpp, <16 x i8> %vc, i8* %resp) { define void @test24(ptr %vqp, ptr %vpp, <16 x i8> %vc, ptr %resp) {
; CHECK-LABEL: test24: ; CHECK-LABEL: test24:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lxv vs1, 32(r3) ; CHECK-NEXT: lxv vs1, 32(r3)
; CHECK-NEXT: lxv vs0, 48(r3) ; CHECK-NEXT: lxv vs0, 48(r3)
; CHECK-NEXT: lxv vs3, 0(r3) ; CHECK-NEXT: lxv vs3, 0(r3)
; CHECK-NEXT: lxv vs2, 16(r3) ; CHECK-NEXT: lxv vs2, 16(r3)
; CHECK-NEXT: xxmtacc acc0 ; CHECK-NEXT: xxmtacc acc0
; CHECK-NEXT: xvf32gerpp acc0, v2, v2 ; CHECK-NEXT: xvf32gerpp acc0, v2, v2
Show All 14 Lines
; CHECK-BE-NEXT: xvf32gerpp acc0, v2, v2 ; CHECK-BE-NEXT: xvf32gerpp acc0, v2, v2
; CHECK-BE-NEXT: xxmfacc acc0 ; CHECK-BE-NEXT: xxmfacc acc0
; CHECK-BE-NEXT: stxv vs1, 16(r7) ; CHECK-BE-NEXT: stxv vs1, 16(r7)
; CHECK-BE-NEXT: stxv vs0, 0(r7) ; CHECK-BE-NEXT: stxv vs0, 0(r7)
; CHECK-BE-NEXT: stxv vs3, 48(r7) ; CHECK-BE-NEXT: stxv vs3, 48(r7)
; CHECK-BE-NEXT: stxv vs2, 32(r7) ; CHECK-BE-NEXT: stxv vs2, 32(r7)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = bitcast i8* %vqp to <512 x i1>* %0 = load <512 x i1>, ptr %vqp, align 64
%1 = load <512 x i1>, <512 x i1>* %0, align 64 %1 = tail call <512 x i1> @llvm.ppc.mma.xvf32gerpp(<512 x i1> %0, <16 x i8> %vc, <16 x i8> %vc)
%2 = tail call <512 x i1> @llvm.ppc.mma.xvf32gerpp(<512 x i1> %1, <16 x i8> %vc, <16 x i8> %vc) store <512 x i1> %1, ptr %resp, align 64
%3 = bitcast i8* %resp to <512 x i1>*
store <512 x i1> %2, <512 x i1>* %3, align 64
ret void ret void
} }
declare <512 x i1> @llvm.ppc.mma.xvf32gerpp(<512 x i1>, <16 x i8>, <16 x i8>) declare <512 x i1> @llvm.ppc.mma.xvf32gerpp(<512 x i1>, <16 x i8>, <16 x i8>)
define void @test25(i8* %vqp, i8* %vpp, <16 x i8> %vc, i8* %resp) { define void @test25(ptr %vqp, ptr %vpp, <16 x i8> %vc, ptr %resp) {
; CHECK-LABEL: test25: ; CHECK-LABEL: test25:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lxv vs1, 32(r3) ; CHECK-NEXT: lxv vs1, 32(r3)
; CHECK-NEXT: lxv vs0, 48(r3) ; CHECK-NEXT: lxv vs0, 48(r3)
; CHECK-NEXT: lxv vs3, 0(r3) ; CHECK-NEXT: lxv vs3, 0(r3)
; CHECK-NEXT: lxv vs2, 16(r3) ; CHECK-NEXT: lxv vs2, 16(r3)
; CHECK-NEXT: xxmtacc acc0 ; CHECK-NEXT: xxmtacc acc0
; CHECK-NEXT: xvf32gerpn acc0, v2, v2 ; CHECK-NEXT: xvf32gerpn acc0, v2, v2
Show All 14 Lines
; CHECK-BE-NEXT: xvf32gerpn acc0, v2, v2 ; CHECK-BE-NEXT: xvf32gerpn acc0, v2, v2
; CHECK-BE-NEXT: xxmfacc acc0 ; CHECK-BE-NEXT: xxmfacc acc0
; CHECK-BE-NEXT: stxv vs1, 16(r7) ; CHECK-BE-NEXT: stxv vs1, 16(r7)
; CHECK-BE-NEXT: stxv vs0, 0(r7) ; CHECK-BE-NEXT: stxv vs0, 0(r7)
; CHECK-BE-NEXT: stxv vs3, 48(r7) ; CHECK-BE-NEXT: stxv vs3, 48(r7)
; CHECK-BE-NEXT: stxv vs2, 32(r7) ; CHECK-BE-NEXT: stxv vs2, 32(r7)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = bitcast i8* %vqp to <512 x i1>* %0 = load <512 x i1>, ptr %vqp, align 64
%1 = load <512 x i1>, <512 x i1>* %0, align 64 %1 = tail call <512 x i1> @llvm.ppc.mma.xvf32gerpn(<512 x i1> %0, <16 x i8> %vc, <16 x i8> %vc)
%2 = tail call <512 x i1> @llvm.ppc.mma.xvf32gerpn(<512 x i1> %1, <16 x i8> %vc, <16 x i8> %vc) store <512 x i1> %1, ptr %resp, align 64
%3 = bitcast i8* %resp to <512 x i1>*
store <512 x i1> %2, <512 x i1>* %3, align 64
ret void ret void
} }
declare <512 x i1> @llvm.ppc.mma.xvf32gerpn(<512 x i1>, <16 x i8>, <16 x i8>) declare <512 x i1> @llvm.ppc.mma.xvf32gerpn(<512 x i1>, <16 x i8>, <16 x i8>)
define void @test26(i8* %vqp, i8* %vpp, <16 x i8> %vc, i8* %resp) { define void @test26(ptr %vqp, ptr %vpp, <16 x i8> %vc, ptr %resp) {
; CHECK-LABEL: test26: ; CHECK-LABEL: test26:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lxv vs1, 32(r3) ; CHECK-NEXT: lxv vs1, 32(r3)
; CHECK-NEXT: lxv vs0, 48(r3) ; CHECK-NEXT: lxv vs0, 48(r3)
; CHECK-NEXT: lxv vs3, 0(r3) ; CHECK-NEXT: lxv vs3, 0(r3)
; CHECK-NEXT: lxv vs2, 16(r3) ; CHECK-NEXT: lxv vs2, 16(r3)
; CHECK-NEXT: xxmtacc acc0 ; CHECK-NEXT: xxmtacc acc0
; CHECK-NEXT: xvf32gernp acc0, v2, v2 ; CHECK-NEXT: xvf32gernp acc0, v2, v2
Show All 14 Lines
; CHECK-BE-NEXT: xvf32gernp acc0, v2, v2 ; CHECK-BE-NEXT: xvf32gernp acc0, v2, v2
; CHECK-BE-NEXT: xxmfacc acc0 ; CHECK-BE-NEXT: xxmfacc acc0
; CHECK-BE-NEXT: stxv vs1, 16(r7) ; CHECK-BE-NEXT: stxv vs1, 16(r7)
; CHECK-BE-NEXT: stxv vs0, 0(r7) ; CHECK-BE-NEXT: stxv vs0, 0(r7)
; CHECK-BE-NEXT: stxv vs3, 48(r7) ; CHECK-BE-NEXT: stxv vs3, 48(r7)
; CHECK-BE-NEXT: stxv vs2, 32(r7) ; CHECK-BE-NEXT: stxv vs2, 32(r7)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = bitcast i8* %vqp to <512 x i1>* %0 = load <512 x i1>, ptr %vqp, align 64
%1 = load <512 x i1>, <512 x i1>* %0, align 64 %1 = tail call <512 x i1> @llvm.ppc.mma.xvf32gernp(<512 x i1> %0, <16 x i8> %vc, <16 x i8> %vc)
%2 = tail call <512 x i1> @llvm.ppc.mma.xvf32gernp(<512 x i1> %1, <16 x i8> %vc, <16 x i8> %vc) store <512 x i1> %1, ptr %resp, align 64
%3 = bitcast i8* %resp to <512 x i1>*
store <512 x i1> %2, <512 x i1>* %3, align 64
ret void ret void
} }
declare <512 x i1> @llvm.ppc.mma.xvf32gernp(<512 x i1>, <16 x i8>, <16 x i8>) declare <512 x i1> @llvm.ppc.mma.xvf32gernp(<512 x i1>, <16 x i8>, <16 x i8>)
define void @test27(i8* %vqp, i8* %vpp, <16 x i8> %vc, i8* %resp) { define void @test27(ptr %vqp, ptr %vpp, <16 x i8> %vc, ptr %resp) {
; CHECK-LABEL: test27: ; CHECK-LABEL: test27:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lxv vs1, 32(r3) ; CHECK-NEXT: lxv vs1, 32(r3)
; CHECK-NEXT: lxv vs0, 48(r3) ; CHECK-NEXT: lxv vs0, 48(r3)
; CHECK-NEXT: lxv vs3, 0(r3) ; CHECK-NEXT: lxv vs3, 0(r3)
; CHECK-NEXT: lxv vs2, 16(r3) ; CHECK-NEXT: lxv vs2, 16(r3)
; CHECK-NEXT: xxmtacc acc0 ; CHECK-NEXT: xxmtacc acc0
; CHECK-NEXT: xvf32gernn acc0, v2, v2 ; CHECK-NEXT: xvf32gernn acc0, v2, v2
Show All 14 Lines
; CHECK-BE-NEXT: xvf32gernn acc0, v2, v2 ; CHECK-BE-NEXT: xvf32gernn acc0, v2, v2
; CHECK-BE-NEXT: xxmfacc acc0 ; CHECK-BE-NEXT: xxmfacc acc0
; CHECK-BE-NEXT: stxv vs1, 16(r7) ; CHECK-BE-NEXT: stxv vs1, 16(r7)
; CHECK-BE-NEXT: stxv vs0, 0(r7) ; CHECK-BE-NEXT: stxv vs0, 0(r7)
; CHECK-BE-NEXT: stxv vs3, 48(r7) ; CHECK-BE-NEXT: stxv vs3, 48(r7)
; CHECK-BE-NEXT: stxv vs2, 32(r7) ; CHECK-BE-NEXT: stxv vs2, 32(r7)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = bitcast i8* %vqp to <512 x i1>* %0 = load <512 x i1>, ptr %vqp, align 64
%1 = load <512 x i1>, <512 x i1>* %0, align 64 %1 = tail call <512 x i1> @llvm.ppc.mma.xvf32gernn(<512 x i1> %0, <16 x i8> %vc, <16 x i8> %vc)
%2 = tail call <512 x i1> @llvm.ppc.mma.xvf32gernn(<512 x i1> %1, <16 x i8> %vc, <16 x i8> %vc) store <512 x i1> %1, ptr %resp, align 64
%3 = bitcast i8* %resp to <512 x i1>*
store <512 x i1> %2, <512 x i1>* %3, align 64
ret void ret void
} }
declare <512 x i1> @llvm.ppc.mma.xvf32gernn(<512 x i1>, <16 x i8>, <16 x i8>) declare <512 x i1> @llvm.ppc.mma.xvf32gernn(<512 x i1>, <16 x i8>, <16 x i8>)
define void @test28(i8* %vqp, i8* %vpp, <16 x i8> %vc, i8* %resp) { define void @test28(ptr %vqp, ptr %vpp, <16 x i8> %vc, ptr %resp) {
; CHECK-LABEL: test28: ; CHECK-LABEL: test28:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pmxvf32ger acc0, v2, v2, 0, 0 ; CHECK-NEXT: pmxvf32ger acc0, v2, v2, 0, 0
; CHECK-NEXT: xxmfacc acc0 ; CHECK-NEXT: xxmfacc acc0
; CHECK-NEXT: stxv vs0, 48(r7) ; CHECK-NEXT: stxv vs0, 48(r7)
; CHECK-NEXT: stxv vs1, 32(r7) ; CHECK-NEXT: stxv vs1, 32(r7)
; CHECK-NEXT: stxv vs2, 16(r7) ; CHECK-NEXT: stxv vs2, 16(r7)
; CHECK-NEXT: stxv vs3, 0(r7) ; CHECK-NEXT: stxv vs3, 0(r7)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-BE-LABEL: test28: ; CHECK-BE-LABEL: test28:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: pmxvf32ger acc0, v2, v2, 0, 0 ; CHECK-BE-NEXT: pmxvf32ger acc0, v2, v2, 0, 0
; CHECK-BE-NEXT: xxmfacc acc0 ; CHECK-BE-NEXT: xxmfacc acc0
; CHECK-BE-NEXT: stxv vs1, 16(r7) ; CHECK-BE-NEXT: stxv vs1, 16(r7)
; CHECK-BE-NEXT: stxv vs0, 0(r7) ; CHECK-BE-NEXT: stxv vs0, 0(r7)
; CHECK-BE-NEXT: stxv vs3, 48(r7) ; CHECK-BE-NEXT: stxv vs3, 48(r7)
; CHECK-BE-NEXT: stxv vs2, 32(r7) ; CHECK-BE-NEXT: stxv vs2, 32(r7)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = tail call <512 x i1> @llvm.ppc.mma.pmxvf32ger(<16 x i8> %vc, <16 x i8> %vc, i32 0, i32 0) %0 = tail call <512 x i1> @llvm.ppc.mma.pmxvf32ger(<16 x i8> %vc, <16 x i8> %vc, i32 0, i32 0)
%1 = bitcast i8* %resp to <512 x i1>* store <512 x i1> %0, ptr %resp, align 64
store <512 x i1> %0, <512 x i1>* %1, align 64
ret void ret void
} }
declare <512 x i1> @llvm.ppc.mma.pmxvf32ger(<16 x i8>, <16 x i8>, i32, i32) declare <512 x i1> @llvm.ppc.mma.pmxvf32ger(<16 x i8>, <16 x i8>, i32, i32)
define void @test29(i8* %vqp, i8* %vpp, <16 x i8> %vc, i8* %resp) { define void @test29(ptr %vqp, ptr %vpp, <16 x i8> %vc, ptr %resp) {
; CHECK-LABEL: test29: ; CHECK-LABEL: test29:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lxv vs1, 32(r3) ; CHECK-NEXT: lxv vs1, 32(r3)
; CHECK-NEXT: lxv vs0, 48(r3) ; CHECK-NEXT: lxv vs0, 48(r3)
; CHECK-NEXT: lxv vs3, 0(r3) ; CHECK-NEXT: lxv vs3, 0(r3)
; CHECK-NEXT: lxv vs2, 16(r3) ; CHECK-NEXT: lxv vs2, 16(r3)
; CHECK-NEXT: xxmtacc acc0 ; CHECK-NEXT: xxmtacc acc0
; CHECK-NEXT: pmxvf32gerpp acc0, v2, v2, 0, 0 ; CHECK-NEXT: pmxvf32gerpp acc0, v2, v2, 0, 0
Show All 14 Lines
; CHECK-BE-NEXT: pmxvf32gerpp acc0, v2, v2, 0, 0 ; CHECK-BE-NEXT: pmxvf32gerpp acc0, v2, v2, 0, 0
; CHECK-BE-NEXT: xxmfacc acc0 ; CHECK-BE-NEXT: xxmfacc acc0
; CHECK-BE-NEXT: stxv vs1, 16(r7) ; CHECK-BE-NEXT: stxv vs1, 16(r7)
; CHECK-BE-NEXT: stxv vs0, 0(r7) ; CHECK-BE-NEXT: stxv vs0, 0(r7)
; CHECK-BE-NEXT: stxv vs3, 48(r7) ; CHECK-BE-NEXT: stxv vs3, 48(r7)
; CHECK-BE-NEXT: stxv vs2, 32(r7) ; CHECK-BE-NEXT: stxv vs2, 32(r7)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = bitcast i8* %vqp to <512 x i1>* %0 = load <512 x i1>, ptr %vqp, align 64
%1 = load <512 x i1>, <512 x i1>* %0, align 64 %1 = tail call <512 x i1> @llvm.ppc.mma.pmxvf32gerpp(<512 x i1> %0, <16 x i8> %vc, <16 x i8> %vc, i32 0, i32 0)
%2 = tail call <512 x i1> @llvm.ppc.mma.pmxvf32gerpp(<512 x i1> %1, <16 x i8> %vc, <16 x i8> %vc, i32 0, i32 0) store <512 x i1> %1, ptr %resp, align 64
%3 = bitcast i8* %resp to <512 x i1>*
store <512 x i1> %2, <512 x i1>* %3, align 64
ret void ret void
} }
declare <512 x i1> @llvm.ppc.mma.pmxvf32gerpp(<512 x i1>, <16 x i8>, <16 x i8>, i32, i32) declare <512 x i1> @llvm.ppc.mma.pmxvf32gerpp(<512 x i1>, <16 x i8>, <16 x i8>, i32, i32)
define void @test30(i8* %vqp, i8* %vpp, <16 x i8> %vc, i8* %resp) { define void @test30(ptr %vqp, ptr %vpp, <16 x i8> %vc, ptr %resp) {
; CHECK-LABEL: test30: ; CHECK-LABEL: test30:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lxv vs1, 32(r3) ; CHECK-NEXT: lxv vs1, 32(r3)
; CHECK-NEXT: lxv vs0, 48(r3) ; CHECK-NEXT: lxv vs0, 48(r3)
; CHECK-NEXT: lxv vs3, 0(r3) ; CHECK-NEXT: lxv vs3, 0(r3)
; CHECK-NEXT: lxv vs2, 16(r3) ; CHECK-NEXT: lxv vs2, 16(r3)
; CHECK-NEXT: xxmtacc acc0 ; CHECK-NEXT: xxmtacc acc0
; CHECK-NEXT: pmxvf32gerpn acc0, v2, v2, 0, 0 ; CHECK-NEXT: pmxvf32gerpn acc0, v2, v2, 0, 0
Show All 14 Lines
; CHECK-BE-NEXT: pmxvf32gerpn acc0, v2, v2, 0, 0 ; CHECK-BE-NEXT: pmxvf32gerpn acc0, v2, v2, 0, 0
; CHECK-BE-NEXT: xxmfacc acc0 ; CHECK-BE-NEXT: xxmfacc acc0
; CHECK-BE-NEXT: stxv vs1, 16(r7) ; CHECK-BE-NEXT: stxv vs1, 16(r7)
; CHECK-BE-NEXT: stxv vs0, 0(r7) ; CHECK-BE-NEXT: stxv vs0, 0(r7)
; CHECK-BE-NEXT: stxv vs3, 48(r7) ; CHECK-BE-NEXT: stxv vs3, 48(r7)
; CHECK-BE-NEXT: stxv vs2, 32(r7) ; CHECK-BE-NEXT: stxv vs2, 32(r7)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = bitcast i8* %vqp to <512 x i1>* %0 = load <512 x i1>, ptr %vqp, align 64
%1 = load <512 x i1>, <512 x i1>* %0, align 64 %1 = tail call <512 x i1> @llvm.ppc.mma.pmxvf32gerpn(<512 x i1> %0, <16 x i8> %vc, <16 x i8> %vc, i32 0, i32 0)
%2 = tail call <512 x i1> @llvm.ppc.mma.pmxvf32gerpn(<512 x i1> %1, <16 x i8> %vc, <16 x i8> %vc, i32 0, i32 0) store <512 x i1> %1, ptr %resp, align 64
%3 = bitcast i8* %resp to <512 x i1>*
store <512 x i1> %2, <512 x i1>* %3, align 64
ret void ret void
} }
declare <512 x i1> @llvm.ppc.mma.pmxvf32gerpn(<512 x i1>, <16 x i8>, <16 x i8>, i32, i32) declare <512 x i1> @llvm.ppc.mma.pmxvf32gerpn(<512 x i1>, <16 x i8>, <16 x i8>, i32, i32)
define void @test31(i8* %vqp, i8* %vpp, <16 x i8> %vc, i8* %resp) { define void @test31(ptr %vqp, ptr %vpp, <16 x i8> %vc, ptr %resp) {
; CHECK-LABEL: test31: ; CHECK-LABEL: test31:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lxv vs1, 32(r3) ; CHECK-NEXT: lxv vs1, 32(r3)
; CHECK-NEXT: lxv vs0, 48(r3) ; CHECK-NEXT: lxv vs0, 48(r3)
; CHECK-NEXT: lxv vs3, 0(r3) ; CHECK-NEXT: lxv vs3, 0(r3)
; CHECK-NEXT: lxv vs2, 16(r3) ; CHECK-NEXT: lxv vs2, 16(r3)
; CHECK-NEXT: xxmtacc acc0 ; CHECK-NEXT: xxmtacc acc0
; CHECK-NEXT: pmxvf32gernp acc0, v2, v2, 0, 0 ; CHECK-NEXT: pmxvf32gernp acc0, v2, v2, 0, 0
Show All 14 Lines
; CHECK-BE-NEXT: pmxvf32gernp acc0, v2, v2, 0, 0 ; CHECK-BE-NEXT: pmxvf32gernp acc0, v2, v2, 0, 0
; CHECK-BE-NEXT: xxmfacc acc0 ; CHECK-BE-NEXT: xxmfacc acc0
; CHECK-BE-NEXT: stxv vs1, 16(r7) ; CHECK-BE-NEXT: stxv vs1, 16(r7)
; CHECK-BE-NEXT: stxv vs0, 0(r7) ; CHECK-BE-NEXT: stxv vs0, 0(r7)
; CHECK-BE-NEXT: stxv vs3, 48(r7) ; CHECK-BE-NEXT: stxv vs3, 48(r7)
; CHECK-BE-NEXT: stxv vs2, 32(r7) ; CHECK-BE-NEXT: stxv vs2, 32(r7)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = bitcast i8* %vqp to <512 x i1>* %0 = load <512 x i1>, ptr %vqp, align 64
%1 = load <512 x i1>, <512 x i1>* %0, align 64 %1 = tail call <512 x i1> @llvm.ppc.mma.pmxvf32gernp(<512 x i1> %0, <16 x i8> %vc, <16 x i8> %vc, i32 0, i32 0)
%2 = tail call <512 x i1> @llvm.ppc.mma.pmxvf32gernp(<512 x i1> %1, <16 x i8> %vc, <16 x i8> %vc, i32 0, i32 0) store <512 x i1> %1, ptr %resp, align 64
%3 = bitcast i8* %resp to <512 x i1>*
store <512 x i1> %2, <512 x i1>* %3, align 64
ret void ret void
} }
declare <512 x i1> @llvm.ppc.mma.pmxvf32gernp(<512 x i1>, <16 x i8>, <16 x i8>, i32, i32) declare <512 x i1> @llvm.ppc.mma.pmxvf32gernp(<512 x i1>, <16 x i8>, <16 x i8>, i32, i32)
define void @test32(i8* %vqp, i8* %vpp, <16 x i8> %vc, i8* %resp) { define void @test32(ptr %vqp, ptr %vpp, <16 x i8> %vc, ptr %resp) {
; CHECK-LABEL: test32: ; CHECK-LABEL: test32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lxv vs1, 32(r3) ; CHECK-NEXT: lxv vs1, 32(r3)
; CHECK-NEXT: lxv vs0, 48(r3) ; CHECK-NEXT: lxv vs0, 48(r3)
; CHECK-NEXT: lxv vs3, 0(r3) ; CHECK-NEXT: lxv vs3, 0(r3)
; CHECK-NEXT: lxv vs2, 16(r3) ; CHECK-NEXT: lxv vs2, 16(r3)
; CHECK-NEXT: xxmtacc acc0 ; CHECK-NEXT: xxmtacc acc0
; CHECK-NEXT: pmxvf32gernn acc0, v2, v2, 0, 0 ; CHECK-NEXT: pmxvf32gernn acc0, v2, v2, 0, 0
Show All 14 Lines
; CHECK-BE-NEXT: pmxvf32gernn acc0, v2, v2, 0, 0 ; CHECK-BE-NEXT: pmxvf32gernn acc0, v2, v2, 0, 0
; CHECK-BE-NEXT: xxmfacc acc0 ; CHECK-BE-NEXT: xxmfacc acc0
; CHECK-BE-NEXT: stxv vs1, 16(r7) ; CHECK-BE-NEXT: stxv vs1, 16(r7)
; CHECK-BE-NEXT: stxv vs0, 0(r7) ; CHECK-BE-NEXT: stxv vs0, 0(r7)
; CHECK-BE-NEXT: stxv vs3, 48(r7) ; CHECK-BE-NEXT: stxv vs3, 48(r7)
; CHECK-BE-NEXT: stxv vs2, 32(r7) ; CHECK-BE-NEXT: stxv vs2, 32(r7)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = bitcast i8* %vqp to <512 x i1>* %0 = load <512 x i1>, ptr %vqp, align 64
%1 = load <512 x i1>, <512 x i1>* %0, align 64 %1 = tail call <512 x i1> @llvm.ppc.mma.pmxvf32gernn(<512 x i1> %0, <16 x i8> %vc, <16 x i8> %vc, i32 0, i32 0)
%2 = tail call <512 x i1> @llvm.ppc.mma.pmxvf32gernn(<512 x i1> %1, <16 x i8> %vc, <16 x i8> %vc, i32 0, i32 0) store <512 x i1> %1, ptr %resp, align 64
%3 = bitcast i8* %resp to <512 x i1>*
store <512 x i1> %2, <512 x i1>* %3, align 64
ret void ret void
} }
declare <512 x i1> @llvm.ppc.mma.pmxvf32gernn(<512 x i1>, <16 x i8>, <16 x i8>, i32, i32) declare <512 x i1> @llvm.ppc.mma.pmxvf32gernn(<512 x i1>, <16 x i8>, <16 x i8>, i32, i32)
define void @test33(i8* %vqp, i8* %vpp, <16 x i8> %vc, i8* %resp) { define void @test33(ptr %vqp, ptr %vpp, <16 x i8> %vc, ptr %resp) {
; CHECK-LABEL: test33: ; CHECK-LABEL: test33:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lxv v5, 0(r4) ; CHECK-NEXT: lxv v5, 0(r4)
; CHECK-NEXT: lxv v4, 16(r4) ; CHECK-NEXT: lxv v4, 16(r4)
; CHECK-NEXT: xvf64ger acc0, vsp36, v2 ; CHECK-NEXT: xvf64ger acc0, vsp36, v2
; CHECK-NEXT: xxmfacc acc0 ; CHECK-NEXT: xxmfacc acc0
; CHECK-NEXT: stxv vs0, 48(r7) ; CHECK-NEXT: stxv vs0, 48(r7)
; CHECK-NEXT: stxv vs1, 32(r7) ; CHECK-NEXT: stxv vs1, 32(r7)
; CHECK-NEXT: stxv vs2, 16(r7) ; CHECK-NEXT: stxv vs2, 16(r7)
; CHECK-NEXT: stxv vs3, 0(r7) ; CHECK-NEXT: stxv vs3, 0(r7)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-BE-LABEL: test33: ; CHECK-BE-LABEL: test33:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxv v5, 16(r4) ; CHECK-BE-NEXT: lxv v5, 16(r4)
; CHECK-BE-NEXT: lxv v4, 0(r4) ; CHECK-BE-NEXT: lxv v4, 0(r4)
; CHECK-BE-NEXT: xvf64ger acc0, vsp36, v2 ; CHECK-BE-NEXT: xvf64ger acc0, vsp36, v2
; CHECK-BE-NEXT: xxmfacc acc0 ; CHECK-BE-NEXT: xxmfacc acc0
; CHECK-BE-NEXT: stxv vs1, 16(r7) ; CHECK-BE-NEXT: stxv vs1, 16(r7)
; CHECK-BE-NEXT: stxv vs0, 0(r7) ; CHECK-BE-NEXT: stxv vs0, 0(r7)
; CHECK-BE-NEXT: stxv vs3, 48(r7) ; CHECK-BE-NEXT: stxv vs3, 48(r7)
; CHECK-BE-NEXT: stxv vs2, 32(r7) ; CHECK-BE-NEXT: stxv vs2, 32(r7)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = bitcast i8* %vpp to <256 x i1>* %0 = load <256 x i1>, ptr %vpp, align 32
%1 = load <256 x i1>, <256 x i1>* %0, align 32 %1 = tail call <512 x i1> @llvm.ppc.mma.xvf64ger(<256 x i1> %0, <16 x i8> %vc)
%2 = tail call <512 x i1> @llvm.ppc.mma.xvf64ger(<256 x i1> %1, <16 x i8> %vc) store <512 x i1> %1, ptr %resp, align 64
%3 = bitcast i8* %resp to <512 x i1>*
store <512 x i1> %2, <512 x i1>* %3, align 64
ret void ret void
} }
declare <512 x i1> @llvm.ppc.mma.xvf64ger(<256 x i1>, <16 x i8>) declare <512 x i1> @llvm.ppc.mma.xvf64ger(<256 x i1>, <16 x i8>)
define void @test34(i8* %vqp, i8* %vpp, <16 x i8> %vc, i8* %resp) { define void @test34(ptr %vqp, ptr %vpp, <16 x i8> %vc, ptr %resp) {
; CHECK-LABEL: test34: ; CHECK-LABEL: test34:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lxv vs1, 32(r3) ; CHECK-NEXT: lxv vs1, 32(r3)
; CHECK-NEXT: lxv vs0, 48(r3) ; CHECK-NEXT: lxv vs0, 48(r3)
; CHECK-NEXT: lxv vs3, 0(r3) ; CHECK-NEXT: lxv vs3, 0(r3)
; CHECK-NEXT: lxv vs2, 16(r3) ; CHECK-NEXT: lxv vs2, 16(r3)
; CHECK-NEXT: lxv v5, 0(r4) ; CHECK-NEXT: lxv v5, 0(r4)
; CHECK-NEXT: xxmtacc acc0 ; CHECK-NEXT: xxmtacc acc0
Show All 18 Lines
; CHECK-BE-NEXT: xvf64gerpp acc0, vsp36, v2 ; CHECK-BE-NEXT: xvf64gerpp acc0, vsp36, v2
; CHECK-BE-NEXT: xxmfacc acc0 ; CHECK-BE-NEXT: xxmfacc acc0
; CHECK-BE-NEXT: stxv vs1, 16(r7) ; CHECK-BE-NEXT: stxv vs1, 16(r7)
; CHECK-BE-NEXT: stxv vs0, 0(r7) ; CHECK-BE-NEXT: stxv vs0, 0(r7)
; CHECK-BE-NEXT: stxv vs3, 48(r7) ; CHECK-BE-NEXT: stxv vs3, 48(r7)
; CHECK-BE-NEXT: stxv vs2, 32(r7) ; CHECK-BE-NEXT: stxv vs2, 32(r7)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = bitcast i8* %vqp to <512 x i1>* %0 = load <512 x i1>, ptr %vqp, align 64
%1 = load <512 x i1>, <512 x i1>* %0, align 64 %1 = load <256 x i1>, ptr %vpp, align 32
%2 = bitcast i8* %vpp to <256 x i1>* %2 = tail call <512 x i1> @llvm.ppc.mma.xvf64gerpp(<512 x i1> %0, <256 x i1> %1, <16 x i8> %vc)
%3 = load <256 x i1>, <256 x i1>* %2, align 32 store <512 x i1> %2, ptr %resp, align 64
%4 = tail call <512 x i1> @llvm.ppc.mma.xvf64gerpp(<512 x i1> %1, <256 x i1> %3, <16 x i8> %vc)
%5 = bitcast i8* %resp to <512 x i1>*
store <512 x i1> %4, <512 x i1>* %5, align 64
ret void ret void
} }
declare <512 x i1> @llvm.ppc.mma.xvf64gerpp(<512 x i1>, <256 x i1>, <16 x i8>) declare <512 x i1> @llvm.ppc.mma.xvf64gerpp(<512 x i1>, <256 x i1>, <16 x i8>)
define void @test35(i8* %vqp, i8* %vpp, <16 x i8> %vc, i8* %resp) { define void @test35(ptr %vqp, ptr %vpp, <16 x i8> %vc, ptr %resp) {
; CHECK-LABEL: test35: ; CHECK-LABEL: test35:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lxv vs1, 32(r3) ; CHECK-NEXT: lxv vs1, 32(r3)
; CHECK-NEXT: lxv vs0, 48(r3) ; CHECK-NEXT: lxv vs0, 48(r3)
; CHECK-NEXT: lxv vs3, 0(r3) ; CHECK-NEXT: lxv vs3, 0(r3)
; CHECK-NEXT: lxv vs2, 16(r3) ; CHECK-NEXT: lxv vs2, 16(r3)
; CHECK-NEXT: lxv v5, 0(r4) ; CHECK-NEXT: lxv v5, 0(r4)
; CHECK-NEXT: xxmtacc acc0 ; CHECK-NEXT: xxmtacc acc0
Show All 18 Lines
; CHECK-BE-NEXT: xvf64gerpn acc0, vsp36, v2 ; CHECK-BE-NEXT: xvf64gerpn acc0, vsp36, v2
; CHECK-BE-NEXT: xxmfacc acc0 ; CHECK-BE-NEXT: xxmfacc acc0
; CHECK-BE-NEXT: stxv vs1, 16(r7) ; CHECK-BE-NEXT: stxv vs1, 16(r7)
; CHECK-BE-NEXT: stxv vs0, 0(r7) ; CHECK-BE-NEXT: stxv vs0, 0(r7)
; CHECK-BE-NEXT: stxv vs3, 48(r7) ; CHECK-BE-NEXT: stxv vs3, 48(r7)
; CHECK-BE-NEXT: stxv vs2, 32(r7) ; CHECK-BE-NEXT: stxv vs2, 32(r7)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = bitcast i8* %vqp to <512 x i1>* %0 = load <512 x i1>, ptr %vqp, align 64
%1 = load <512 x i1>, <512 x i1>* %0, align 64 %1 = load <256 x i1>, ptr %vpp, align 32
%2 = bitcast i8* %vpp to <256 x i1>* %2 = tail call <512 x i1> @llvm.ppc.mma.xvf64gerpn(<512 x i1> %0, <256 x i1> %1, <16 x i8> %vc)
%3 = load <256 x i1>, <256 x i1>* %2, align 32 store <512 x i1> %2, ptr %resp, align 64
%4 = tail call <512 x i1> @llvm.ppc.mma.xvf64gerpn(<512 x i1> %1, <256 x i1> %3, <16 x i8> %vc)
%5 = bitcast i8* %resp to <512 x i1>*
store <512 x i1> %4, <512 x i1>* %5, align 64
ret void ret void
} }
declare <512 x i1> @llvm.ppc.mma.xvf64gerpn(<512 x i1>, <256 x i1>, <16 x i8>) declare <512 x i1> @llvm.ppc.mma.xvf64gerpn(<512 x i1>, <256 x i1>, <16 x i8>)
define void @test36(i8* %vqp, i8* %vpp, <16 x i8> %vc, i8* %resp) { define void @test36(ptr %vqp, ptr %vpp, <16 x i8> %vc, ptr %resp) {
; CHECK-LABEL: test36: ; CHECK-LABEL: test36:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lxv vs1, 32(r3) ; CHECK-NEXT: lxv vs1, 32(r3)
; CHECK-NEXT: lxv vs0, 48(r3) ; CHECK-NEXT: lxv vs0, 48(r3)
; CHECK-NEXT: lxv vs3, 0(r3) ; CHECK-NEXT: lxv vs3, 0(r3)
; CHECK-NEXT: lxv vs2, 16(r3) ; CHECK-NEXT: lxv vs2, 16(r3)
; CHECK-NEXT: lxv v5, 0(r4) ; CHECK-NEXT: lxv v5, 0(r4)
; CHECK-NEXT: xxmtacc acc0 ; CHECK-NEXT: xxmtacc acc0
Show All 18 Lines
; CHECK-BE-NEXT: xvf64gernp acc0, vsp36, v2 ; CHECK-BE-NEXT: xvf64gernp acc0, vsp36, v2
; CHECK-BE-NEXT: xxmfacc acc0 ; CHECK-BE-NEXT: xxmfacc acc0
; CHECK-BE-NEXT: stxv vs1, 16(r7) ; CHECK-BE-NEXT: stxv vs1, 16(r7)
; CHECK-BE-NEXT: stxv vs0, 0(r7) ; CHECK-BE-NEXT: stxv vs0, 0(r7)
; CHECK-BE-NEXT: stxv vs3, 48(r7) ; CHECK-BE-NEXT: stxv vs3, 48(r7)
; CHECK-BE-NEXT: stxv vs2, 32(r7) ; CHECK-BE-NEXT: stxv vs2, 32(r7)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = bitcast i8* %vqp to <512 x i1>* %0 = load <512 x i1>, ptr %vqp, align 64
%1 = load <512 x i1>, <512 x i1>* %0, align 64 %1 = load <256 x i1>, ptr %vpp, align 32
%2 = bitcast i8* %vpp to <256 x i1>* %2 = tail call <512 x i1> @llvm.ppc.mma.xvf64gernp(<512 x i1> %0, <256 x i1> %1, <16 x i8> %vc)
%3 = load <256 x i1>, <256 x i1>* %2, align 32 store <512 x i1> %2, ptr %resp, align 64
%4 = tail call <512 x i1> @llvm.ppc.mma.xvf64gernp(<512 x i1> %1, <256 x i1> %3, <16 x i8> %vc)
%5 = bitcast i8* %resp to <512 x i1>*
store <512 x i1> %4, <512 x i1>* %5, align 64
ret void ret void
} }
declare <512 x i1> @llvm.ppc.mma.xvf64gernp(<512 x i1>, <256 x i1>, <16 x i8>) declare <512 x i1> @llvm.ppc.mma.xvf64gernp(<512 x i1>, <256 x i1>, <16 x i8>)
define void @test37(i8* %vqp, i8* %vpp, <16 x i8> %vc, i8* %resp) { define void @test37(ptr %vqp, ptr %vpp, <16 x i8> %vc, ptr %resp) {
; CHECK-LABEL: test37: ; CHECK-LABEL: test37:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lxv vs1, 32(r3) ; CHECK-NEXT: lxv vs1, 32(r3)
; CHECK-NEXT: lxv vs0, 48(r3) ; CHECK-NEXT: lxv vs0, 48(r3)
; CHECK-NEXT: lxv vs3, 0(r3) ; CHECK-NEXT: lxv vs3, 0(r3)
; CHECK-NEXT: lxv vs2, 16(r3) ; CHECK-NEXT: lxv vs2, 16(r3)
; CHECK-NEXT: lxv v5, 0(r4) ; CHECK-NEXT: lxv v5, 0(r4)
; CHECK-NEXT: xxmtacc acc0 ; CHECK-NEXT: xxmtacc acc0
Show All 18 Lines
; CHECK-BE-NEXT: xvf64gernn acc0, vsp36, v2 ; CHECK-BE-NEXT: xvf64gernn acc0, vsp36, v2
; CHECK-BE-NEXT: xxmfacc acc0 ; CHECK-BE-NEXT: xxmfacc acc0
; CHECK-BE-NEXT: stxv vs1, 16(r7) ; CHECK-BE-NEXT: stxv vs1, 16(r7)
; CHECK-BE-NEXT: stxv vs0, 0(r7) ; CHECK-BE-NEXT: stxv vs0, 0(r7)
; CHECK-BE-NEXT: stxv vs3, 48(r7) ; CHECK-BE-NEXT: stxv vs3, 48(r7)
; CHECK-BE-NEXT: stxv vs2, 32(r7) ; CHECK-BE-NEXT: stxv vs2, 32(r7)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = bitcast i8* %vqp to <512 x i1>* %0 = load <512 x i1>, ptr %vqp, align 64
%1 = load <512 x i1>, <512 x i1>* %0, align 64 %1 = load <256 x i1>, ptr %vpp, align 32
%2 = bitcast i8* %vpp to <256 x i1>* %2 = tail call <512 x i1> @llvm.ppc.mma.xvf64gernn(<512 x i1> %0, <256 x i1> %1, <16 x i8> %vc)
%3 = load <256 x i1>, <256 x i1>* %2, align 32 store <512 x i1> %2, ptr %resp, align 64
%4 = tail call <512 x i1> @llvm.ppc.mma.xvf64gernn(<512 x i1> %1, <256 x i1> %3, <16 x i8> %vc)
%5 = bitcast i8* %resp to <512 x i1>*
store <512 x i1> %4, <512 x i1>* %5, align 64
ret void ret void
} }
declare <512 x i1> @llvm.ppc.mma.xvf64gernn(<512 x i1>, <256 x i1>, <16 x i8>) declare <512 x i1> @llvm.ppc.mma.xvf64gernn(<512 x i1>, <256 x i1>, <16 x i8>)
define void @test38(i8* %vqp, i8* %vpp, <16 x i8> %vc, i8* %resp) { define void @test38(ptr %vqp, ptr %vpp, <16 x i8> %vc, ptr %resp) {
; CHECK-LABEL: test38: ; CHECK-LABEL: test38:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lxv v5, 0(r4) ; CHECK-NEXT: lxv v5, 0(r4)
; CHECK-NEXT: lxv v4, 16(r4) ; CHECK-NEXT: lxv v4, 16(r4)
; CHECK-NEXT: pmxvf64ger acc0, vsp36, v2, 0, 0 ; CHECK-NEXT: pmxvf64ger acc0, vsp36, v2, 0, 0
; CHECK-NEXT: xxmfacc acc0 ; CHECK-NEXT: xxmfacc acc0
; CHECK-NEXT: stxv vs0, 48(r7) ; CHECK-NEXT: stxv vs0, 48(r7)
; CHECK-NEXT: stxv vs1, 32(r7) ; CHECK-NEXT: stxv vs1, 32(r7)
; CHECK-NEXT: stxv vs2, 16(r7) ; CHECK-NEXT: stxv vs2, 16(r7)
; CHECK-NEXT: stxv vs3, 0(r7) ; CHECK-NEXT: stxv vs3, 0(r7)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-BE-LABEL: test38: ; CHECK-BE-LABEL: test38:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxv v5, 16(r4) ; CHECK-BE-NEXT: lxv v5, 16(r4)
; CHECK-BE-NEXT: lxv v4, 0(r4) ; CHECK-BE-NEXT: lxv v4, 0(r4)
; CHECK-BE-NEXT: pmxvf64ger acc0, vsp36, v2, 0, 0 ; CHECK-BE-NEXT: pmxvf64ger acc0, vsp36, v2, 0, 0
; CHECK-BE-NEXT: xxmfacc acc0 ; CHECK-BE-NEXT: xxmfacc acc0
; CHECK-BE-NEXT: stxv vs1, 16(r7) ; CHECK-BE-NEXT: stxv vs1, 16(r7)
; CHECK-BE-NEXT: stxv vs0, 0(r7) ; CHECK-BE-NEXT: stxv vs0, 0(r7)
; CHECK-BE-NEXT: stxv vs3, 48(r7) ; CHECK-BE-NEXT: stxv vs3, 48(r7)
; CHECK-BE-NEXT: stxv vs2, 32(r7) ; CHECK-BE-NEXT: stxv vs2, 32(r7)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = bitcast i8* %vpp to <256 x i1>* %0 = load <256 x i1>, ptr %vpp, align 32
%1 = load <256 x i1>, <256 x i1>* %0, align 32 %1 = tail call <512 x i1> @llvm.ppc.mma.pmxvf64ger(<256 x i1> %0, <16 x i8> %vc, i32 0, i32 0)
%2 = tail call <512 x i1> @llvm.ppc.mma.pmxvf64ger(<256 x i1> %1, <16 x i8> %vc, i32 0, i32 0) store <512 x i1> %1, ptr %resp, align 64
%3 = bitcast i8* %resp to <512 x i1>*
store <512 x i1> %2, <512 x i1>* %3, align 64
ret void ret void
} }
declare <512 x i1> @llvm.ppc.mma.pmxvf64ger(<256 x i1>, <16 x i8>, i32, i32) declare <512 x i1> @llvm.ppc.mma.pmxvf64ger(<256 x i1>, <16 x i8>, i32, i32)
define void @test39(i8* %vqp, i8* %vpp, <16 x i8> %vc, i8* %resp) { define void @test39(ptr %vqp, ptr %vpp, <16 x i8> %vc, ptr %resp) {
; CHECK-LABEL: test39: ; CHECK-LABEL: test39:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lxv vs1, 32(r3) ; CHECK-NEXT: lxv vs1, 32(r3)
; CHECK-NEXT: lxv vs0, 48(r3) ; CHECK-NEXT: lxv vs0, 48(r3)
; CHECK-NEXT: lxv vs3, 0(r3) ; CHECK-NEXT: lxv vs3, 0(r3)
; CHECK-NEXT: lxv vs2, 16(r3) ; CHECK-NEXT: lxv vs2, 16(r3)
; CHECK-NEXT: lxv v5, 0(r4) ; CHECK-NEXT: lxv v5, 0(r4)
; CHECK-NEXT: xxmtacc acc0 ; CHECK-NEXT: xxmtacc acc0
Show All 18 Lines
; CHECK-BE-NEXT: pmxvf64gerpp acc0, vsp36, v2, 0, 0 ; CHECK-BE-NEXT: pmxvf64gerpp acc0, vsp36, v2, 0, 0
; CHECK-BE-NEXT: xxmfacc acc0 ; CHECK-BE-NEXT: xxmfacc acc0
; CHECK-BE-NEXT: stxv vs1, 16(r7) ; CHECK-BE-NEXT: stxv vs1, 16(r7)
; CHECK-BE-NEXT: stxv vs0, 0(r7) ; CHECK-BE-NEXT: stxv vs0, 0(r7)
; CHECK-BE-NEXT: stxv vs3, 48(r7) ; CHECK-BE-NEXT: stxv vs3, 48(r7)
; CHECK-BE-NEXT: stxv vs2, 32(r7) ; CHECK-BE-NEXT: stxv vs2, 32(r7)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = bitcast i8* %vqp to <512 x i1>* %0 = load <512 x i1>, ptr %vqp, align 64
%1 = load <512 x i1>, <512 x i1>* %0, align 64 %1 = load <256 x i1>, ptr %vpp, align 32
%2 = bitcast i8* %vpp to <256 x i1>* %2 = tail call <512 x i1> @llvm.ppc.mma.pmxvf64gerpp(<512 x i1> %0, <256 x i1> %1, <16 x i8> %vc, i32 0, i32 0)
%3 = load <256 x i1>, <256 x i1>* %2, align 32 store <512 x i1> %2, ptr %resp, align 64
%4 = tail call <512 x i1> @llvm.ppc.mma.pmxvf64gerpp(<512 x i1> %1, <256 x i1> %3, <16 x i8> %vc, i32 0, i32 0)
%5 = bitcast i8* %resp to <512 x i1>*
store <512 x i1> %4, <512 x i1>* %5, align 64
ret void ret void
} }
declare <512 x i1> @llvm.ppc.mma.pmxvf64gerpp(<512 x i1>, <256 x i1>, <16 x i8>, i32, i32) declare <512 x i1> @llvm.ppc.mma.pmxvf64gerpp(<512 x i1>, <256 x i1>, <16 x i8>, i32, i32)
define void @test40(i8* %vqp, i8* %vpp, <16 x i8> %vc, i8* %resp) { define void @test40(ptr %vqp, ptr %vpp, <16 x i8> %vc, ptr %resp) {
; CHECK-LABEL: test40: ; CHECK-LABEL: test40:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lxv vs1, 32(r3) ; CHECK-NEXT: lxv vs1, 32(r3)
; CHECK-NEXT: lxv vs0, 48(r3) ; CHECK-NEXT: lxv vs0, 48(r3)
; CHECK-NEXT: lxv vs3, 0(r3) ; CHECK-NEXT: lxv vs3, 0(r3)
; CHECK-NEXT: lxv vs2, 16(r3) ; CHECK-NEXT: lxv vs2, 16(r3)
; CHECK-NEXT: lxv v5, 0(r4) ; CHECK-NEXT: lxv v5, 0(r4)
; CHECK-NEXT: xxmtacc acc0 ; CHECK-NEXT: xxmtacc acc0
Show All 18 Lines
; CHECK-BE-NEXT: pmxvf64gerpn acc0, vsp36, v2, 0, 0 ; CHECK-BE-NEXT: pmxvf64gerpn acc0, vsp36, v2, 0, 0
; CHECK-BE-NEXT: xxmfacc acc0 ; CHECK-BE-NEXT: xxmfacc acc0
; CHECK-BE-NEXT: stxv vs1, 16(r7) ; CHECK-BE-NEXT: stxv vs1, 16(r7)
; CHECK-BE-NEXT: stxv vs0, 0(r7) ; CHECK-BE-NEXT: stxv vs0, 0(r7)
; CHECK-BE-NEXT: stxv vs3, 48(r7) ; CHECK-BE-NEXT: stxv vs3, 48(r7)
; CHECK-BE-NEXT: stxv vs2, 32(r7) ; CHECK-BE-NEXT: stxv vs2, 32(r7)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = bitcast i8* %vqp to <512 x i1>* %0 = load <512 x i1>, ptr %vqp, align 64
%1 = load <512 x i1>, <512 x i1>* %0, align 64 %1 = load <256 x i1>, ptr %vpp, align 32
%2 = bitcast i8* %vpp to <256 x i1>* %2 = tail call <512 x i1> @llvm.ppc.mma.pmxvf64gerpn(<512 x i1> %0, <256 x i1> %1, <16 x i8> %vc, i32 0, i32 0)
%3 = load <256 x i1>, <256 x i1>* %2, align 32 store <512 x i1> %2, ptr %resp, align 64
%4 = tail call <512 x i1> @llvm.ppc.mma.pmxvf64gerpn(<512 x i1> %1, <256 x i1> %3, <16 x i8> %vc, i32 0, i32 0)
%5 = bitcast i8* %resp to <512 x i1>*
store <512 x i1> %4, <512 x i1>* %5, align 64
ret void ret void
} }
declare <512 x i1> @llvm.ppc.mma.pmxvf64gerpn(<512 x i1>, <256 x i1>, <16 x i8>, i32, i32) declare <512 x i1> @llvm.ppc.mma.pmxvf64gerpn(<512 x i1>, <256 x i1>, <16 x i8>, i32, i32)
define void @test41(i8* %vqp, i8* %vpp, <16 x i8> %vc, i8* %resp) { define void @test41(ptr %vqp, ptr %vpp, <16 x i8> %vc, ptr %resp) {
; CHECK-LABEL: test41: ; CHECK-LABEL: test41:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lxv vs1, 32(r3) ; CHECK-NEXT: lxv vs1, 32(r3)
; CHECK-NEXT: lxv vs0, 48(r3) ; CHECK-NEXT: lxv vs0, 48(r3)
; CHECK-NEXT: lxv vs3, 0(r3) ; CHECK-NEXT: lxv vs3, 0(r3)
; CHECK-NEXT: lxv vs2, 16(r3) ; CHECK-NEXT: lxv vs2, 16(r3)
; CHECK-NEXT: lxv v5, 0(r4) ; CHECK-NEXT: lxv v5, 0(r4)
; CHECK-NEXT: xxmtacc acc0 ; CHECK-NEXT: xxmtacc acc0
Show All 18 Lines
; CHECK-BE-NEXT: pmxvf64gernp acc0, vsp36, v2, 0, 0 ; CHECK-BE-NEXT: pmxvf64gernp acc0, vsp36, v2, 0, 0
; CHECK-BE-NEXT: xxmfacc acc0 ; CHECK-BE-NEXT: xxmfacc acc0
; CHECK-BE-NEXT: stxv vs1, 16(r7) ; CHECK-BE-NEXT: stxv vs1, 16(r7)
; CHECK-BE-NEXT: stxv vs0, 0(r7) ; CHECK-BE-NEXT: stxv vs0, 0(r7)
; CHECK-BE-NEXT: stxv vs3, 48(r7) ; CHECK-BE-NEXT: stxv vs3, 48(r7)
; CHECK-BE-NEXT: stxv vs2, 32(r7) ; CHECK-BE-NEXT: stxv vs2, 32(r7)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = bitcast i8* %vqp to <512 x i1>* %0 = load <512 x i1>, ptr %vqp, align 64
%1 = load <512 x i1>, <512 x i1>* %0, align 64 %1 = load <256 x i1>, ptr %vpp, align 32
%2 = bitcast i8* %vpp to <256 x i1>* %2 = tail call <512 x i1> @llvm.ppc.mma.pmxvf64gernp(<512 x i1> %0, <256 x i1> %1, <16 x i8> %vc, i32 0, i32 0)
%3 = load <256 x i1>, <256 x i1>* %2, align 32 store <512 x i1> %2, ptr %resp, align 64
%4 = tail call <512 x i1> @llvm.ppc.mma.pmxvf64gernp(<512 x i1> %1, <256 x i1> %3, <16 x i8> %vc, i32 0, i32 0)
%5 = bitcast i8* %resp to <512 x i1>*
store <512 x i1> %4, <512 x i1>* %5, align 64
ret void ret void
} }
declare <512 x i1> @llvm.ppc.mma.pmxvf64gernp(<512 x i1>, <256 x i1>, <16 x i8>, i32, i32) declare <512 x i1> @llvm.ppc.mma.pmxvf64gernp(<512 x i1>, <256 x i1>, <16 x i8>, i32, i32)
define void @test42(i8* %vqp, i8* %vpp, <16 x i8> %vc, i8* %resp) { define void @test42(ptr %vqp, ptr %vpp, <16 x i8> %vc, ptr %resp) {
; CHECK-LABEL: test42: ; CHECK-LABEL: test42:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lxv vs1, 32(r3) ; CHECK-NEXT: lxv vs1, 32(r3)
; CHECK-NEXT: lxv vs0, 48(r3) ; CHECK-NEXT: lxv vs0, 48(r3)
; CHECK-NEXT: lxv vs3, 0(r3) ; CHECK-NEXT: lxv vs3, 0(r3)
; CHECK-NEXT: lxv vs2, 16(r3) ; CHECK-NEXT: lxv vs2, 16(r3)
; CHECK-NEXT: lxv v5, 0(r4) ; CHECK-NEXT: lxv v5, 0(r4)
; CHECK-NEXT: xxmtacc acc0 ; CHECK-NEXT: xxmtacc acc0
Show All 18 Lines
; CHECK-BE-NEXT: pmxvf64gernn acc0, vsp36, v2, 0, 0 ; CHECK-BE-NEXT: pmxvf64gernn acc0, vsp36, v2, 0, 0
; CHECK-BE-NEXT: xxmfacc acc0 ; CHECK-BE-NEXT: xxmfacc acc0
; CHECK-BE-NEXT: stxv vs1, 16(r7) ; CHECK-BE-NEXT: stxv vs1, 16(r7)
; CHECK-BE-NEXT: stxv vs0, 0(r7) ; CHECK-BE-NEXT: stxv vs0, 0(r7)
; CHECK-BE-NEXT: stxv vs3, 48(r7) ; CHECK-BE-NEXT: stxv vs3, 48(r7)
; CHECK-BE-NEXT: stxv vs2, 32(r7) ; CHECK-BE-NEXT: stxv vs2, 32(r7)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = bitcast i8* %vqp to <512 x i1>* %0 = load <512 x i1>, ptr %vqp, align 64
%1 = load <512 x i1>, <512 x i1>* %0, align 64 %1 = load <256 x i1>, ptr %vpp, align 32
%2 = bitcast i8* %vpp to <256 x i1>* %2 = tail call <512 x i1> @llvm.ppc.mma.pmxvf64gernn(<512 x i1> %0, <256 x i1> %1, <16 x i8> %vc, i32 0, i32 0)
%3 = load <256 x i1>, <256 x i1>* %2, align 32 store <512 x i1> %2, ptr %resp, align 64
%4 = tail call <512 x i1> @llvm.ppc.mma.pmxvf64gernn(<512 x i1> %1, <256 x i1> %3, <16 x i8> %vc, i32 0, i32 0)
%5 = bitcast i8* %resp to <512 x i1>*
store <512 x i1> %4, <512 x i1>* %5, align 64
ret void ret void
} }
declare <512 x i1> @llvm.ppc.mma.pmxvf64gernn(<512 x i1>, <256 x i1>, <16 x i8>, i32, i32) declare <512 x i1> @llvm.ppc.mma.pmxvf64gernn(<512 x i1>, <256 x i1>, <16 x i8>, i32, i32)

llvm/test/CodeGen/PowerPC/mma-phi-accs.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -O3 -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ ; RUN: llc -O3 -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names \ ; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names \
; RUN: -ppc-vsr-nums-as-vr < %s | FileCheck %s ; RUN: -ppc-vsr-nums-as-vr < %s | FileCheck %s
; RUN: llc -O3 -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \ ; RUN: llc -O3 -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names \ ; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names \
; RUN: -ppc-vsr-nums-as-vr < %s | FileCheck %s --check-prefix=CHECK-BE ; RUN: -ppc-vsr-nums-as-vr < %s | FileCheck %s --check-prefix=CHECK-BE
declare <256 x i1> @llvm.ppc.vsx.assemble.pair(<16 x i8>, <16 x i8>) declare <256 x i1> @llvm.ppc.vsx.assemble.pair(<16 x i8>, <16 x i8>)
declare <512 x i1> @llvm.ppc.mma.xxsetaccz() declare <512 x i1> @llvm.ppc.mma.xxsetaccz()
declare <512 x i1> @llvm.ppc.mma.xvf64gerpp(<512 x i1>, <256 x i1>, <16 x i8>) declare <512 x i1> @llvm.ppc.mma.xvf64gerpp(<512 x i1>, <256 x i1>, <16 x i8>)
declare { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.ppc.mma.disassemble.acc(<512 x i1>) declare { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.ppc.mma.disassemble.acc(<512 x i1>)
define void @testPHI1(<16 x i8>* %Dst, <16 x i8>* %Src, i32 signext %Len) { define void @testPHI1(ptr %Dst, ptr %Src, i32 signext %Len) {
; CHECK-LABEL: testPHI1: ; CHECK-LABEL: testPHI1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xxsetaccz acc0 ; CHECK-NEXT: xxsetaccz acc0
; CHECK-NEXT: cmpwi r5, 3 ; CHECK-NEXT: cmpwi r5, 3
; CHECK-NEXT: blt cr0, .LBB0_3 ; CHECK-NEXT: blt cr0, .LBB0_3
; CHECK-NEXT: # %bb.1: # %for.body.preheader ; CHECK-NEXT: # %bb.1: # %for.body.preheader
; CHECK-NEXT: lxv v2, 0(r4) ; CHECK-NEXT: lxv v2, 0(r4)
; CHECK-NEXT: lxv v3, 16(r4) ; CHECK-NEXT: lxv v3, 16(r4)
Show All 38 Lines
; CHECK-BE-NEXT: .LBB0_3: # %for.cond.cleanup ; CHECK-BE-NEXT: .LBB0_3: # %for.cond.cleanup
; CHECK-BE-NEXT: xxmfacc acc0 ; CHECK-BE-NEXT: xxmfacc acc0
; CHECK-BE-NEXT: stxv vs0, 0(r3) ; CHECK-BE-NEXT: stxv vs0, 0(r3)
; CHECK-BE-NEXT: stxv vs1, 16(r3) ; CHECK-BE-NEXT: stxv vs1, 16(r3)
; CHECK-BE-NEXT: stxv vs2, 32(r3) ; CHECK-BE-NEXT: stxv vs2, 32(r3)
; CHECK-BE-NEXT: stxv vs3, 48(r3) ; CHECK-BE-NEXT: stxv vs3, 48(r3)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = load <16 x i8>, <16 x i8>* %Src, align 16 %0 = load <16 x i8>, ptr %Src, align 16
%arrayidx1 = getelementptr inbounds <16 x i8>, <16 x i8>* %Src, i64 1 %arrayidx1 = getelementptr inbounds <16 x i8>, ptr %Src, i64 1
%1 = load <16 x i8>, <16 x i8>* %arrayidx1, align 16 %1 = load <16 x i8>, ptr %arrayidx1, align 16
%2 = tail call <256 x i1> @llvm.ppc.vsx.assemble.pair(<16 x i8> %0, <16 x i8> %1) %2 = tail call <256 x i1> @llvm.ppc.vsx.assemble.pair(<16 x i8> %0, <16 x i8> %1)
%3 = tail call <512 x i1> @llvm.ppc.mma.xxsetaccz() %3 = tail call <512 x i1> @llvm.ppc.mma.xxsetaccz()
%cmp11 = icmp sgt i32 %Len, 2 %cmp11 = icmp sgt i32 %Len, 2
br i1 %cmp11, label %for.body.preheader, label %for.cond.cleanup br i1 %cmp11, label %for.body.preheader, label %for.cond.cleanup
for.body.preheader: for.body.preheader:
%wide.trip.count = zext i32 %Len to i64 %wide.trip.count = zext i32 %Len to i64
br label %for.body br label %for.body
for.cond.cleanup: for.cond.cleanup:
%Acc.0.lcssa = phi <512 x i1> [ %3, %entry ], [ %13, %for.body ] %Acc.0.lcssa = phi <512 x i1> [ %3, %entry ], [ %13, %for.body ]
%4 = tail call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.ppc.mma.disassemble.acc(<512 x i1> %Acc.0.lcssa) %4 = tail call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.ppc.mma.disassemble.acc(<512 x i1> %Acc.0.lcssa)
%5 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %4, 0 %5 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %4, 0
store <16 x i8> %5, <16 x i8>* %Dst, align 16 store <16 x i8> %5, ptr %Dst, align 16
%6 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %4, 1 %6 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %4, 1
%7 = getelementptr inbounds <16 x i8>, <16 x i8>* %Dst, i64 1 %7 = getelementptr inbounds <16 x i8>, ptr %Dst, i64 1
store <16 x i8> %6, <16 x i8>* %7, align 16 store <16 x i8> %6, ptr %7, align 16
%8 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %4, 2 %8 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %4, 2
%9 = getelementptr inbounds <16 x i8>, <16 x i8>* %Dst, i64 2 %9 = getelementptr inbounds <16 x i8>, ptr %Dst, i64 2
store <16 x i8> %8, <16 x i8>* %9, align 16 store <16 x i8> %8, ptr %9, align 16
%10 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %4, 3 %10 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %4, 3
%11 = getelementptr inbounds <16 x i8>, <16 x i8>* %Dst, i64 3 %11 = getelementptr inbounds <16 x i8>, ptr %Dst, i64 3
store <16 x i8> %10, <16 x i8>* %11, align 16 store <16 x i8> %10, ptr %11, align 16
ret void ret void
for.body: for.body:
%indvars.iv = phi i64 [ 2, %for.body.preheader ], [ %indvars.iv.next, %for.body ] %indvars.iv = phi i64 [ 2, %for.body.preheader ], [ %indvars.iv.next, %for.body ]
%Acc.012 = phi <512 x i1> [ %3, %for.body.preheader ], [ %13, %for.body ] %Acc.012 = phi <512 x i1> [ %3, %for.body.preheader ], [ %13, %for.body ]
%arrayidx2 = getelementptr inbounds <16 x i8>, <16 x i8>* %Src, i64 %indvars.iv %arrayidx2 = getelementptr inbounds <16 x i8>, ptr %Src, i64 %indvars.iv
%12 = load <16 x i8>, <16 x i8>* %arrayidx2, align 16 %12 = load <16 x i8>, ptr %arrayidx2, align 16
%13 = tail call <512 x i1> @llvm.ppc.mma.xvf64gerpp(<512 x i1> %Acc.012, <256 x i1> %2, <16 x i8> %12) %13 = tail call <512 x i1> @llvm.ppc.mma.xvf64gerpp(<512 x i1> %Acc.012, <256 x i1> %2, <16 x i8> %12)
%indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
%exitcond.not = icmp eq i64 %indvars.iv.next, %wide.trip.count %exitcond.not = icmp eq i64 %indvars.iv.next, %wide.trip.count
br i1 %exitcond.not, label %for.cond.cleanup, label %for.body br i1 %exitcond.not, label %for.cond.cleanup, label %for.body
} }
declare <512 x i1> @llvm.ppc.mma.xvf64ger(<256 x i1>, <16 x i8>) declare <512 x i1> @llvm.ppc.mma.xvf64ger(<256 x i1>, <16 x i8>)
define dso_local void @testPHI2(<16 x i8>* %Dst, <16 x i8>* %Src, i32 signext %Len) { define dso_local void @testPHI2(ptr %Dst, ptr %Src, i32 signext %Len) {
; CHECK-LABEL: testPHI2: ; CHECK-LABEL: testPHI2:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lxv v2, 0(r4) ; CHECK-NEXT: lxv v2, 0(r4)
; CHECK-NEXT: lxv v3, 16(r4) ; CHECK-NEXT: lxv v3, 16(r4)
; CHECK-NEXT: cmpwi r5, 4 ; CHECK-NEXT: cmpwi r5, 4
; CHECK-NEXT: lxv vs4, 32(r4) ; CHECK-NEXT: lxv vs4, 32(r4)
; CHECK-NEXT: xvf64ger acc0, vsp34, vs4 ; CHECK-NEXT: xvf64ger acc0, vsp34, vs4
; CHECK-NEXT: blt cr0, .LBB1_3 ; CHECK-NEXT: blt cr0, .LBB1_3
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; CHECK-BE-NEXT: .LBB1_3: # %for.cond.cleanup ; CHECK-BE-NEXT: .LBB1_3: # %for.cond.cleanup
; CHECK-BE-NEXT: xxmfacc acc0 ; CHECK-BE-NEXT: xxmfacc acc0
; CHECK-BE-NEXT: stxv vs0, 0(r3) ; CHECK-BE-NEXT: stxv vs0, 0(r3)
; CHECK-BE-NEXT: stxv vs1, 16(r3) ; CHECK-BE-NEXT: stxv vs1, 16(r3)
; CHECK-BE-NEXT: stxv vs2, 32(r3) ; CHECK-BE-NEXT: stxv vs2, 32(r3)
; CHECK-BE-NEXT: stxv vs3, 48(r3) ; CHECK-BE-NEXT: stxv vs3, 48(r3)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = load <16 x i8>, <16 x i8>* %Src, align 16 %0 = load <16 x i8>, ptr %Src, align 16
%arrayidx1 = getelementptr inbounds <16 x i8>, <16 x i8>* %Src, i64 1 %arrayidx1 = getelementptr inbounds <16 x i8>, ptr %Src, i64 1
%1 = load <16 x i8>, <16 x i8>* %arrayidx1, align 16 %1 = load <16 x i8>, ptr %arrayidx1, align 16
%2 = tail call <256 x i1> @llvm.ppc.vsx.assemble.pair(<16 x i8> %0, <16 x i8> %1) %2 = tail call <256 x i1> @llvm.ppc.vsx.assemble.pair(<16 x i8> %0, <16 x i8> %1)
%arrayidx2 = getelementptr inbounds <16 x i8>, <16 x i8>* %Src, i64 2 %arrayidx2 = getelementptr inbounds <16 x i8>, ptr %Src, i64 2
%3 = load <16 x i8>, <16 x i8>* %arrayidx2, align 16 %3 = load <16 x i8>, ptr %arrayidx2, align 16
%4 = tail call <512 x i1> @llvm.ppc.mma.xvf64ger(<256 x i1> %2, <16 x i8> %3) %4 = tail call <512 x i1> @llvm.ppc.mma.xvf64ger(<256 x i1> %2, <16 x i8> %3)
%cmp14 = icmp sgt i32 %Len, 3 %cmp14 = icmp sgt i32 %Len, 3
br i1 %cmp14, label %for.body.preheader, label %for.cond.cleanup br i1 %cmp14, label %for.body.preheader, label %for.cond.cleanup
for.body.preheader: for.body.preheader:
%wide.trip.count = zext i32 %Len to i64 %wide.trip.count = zext i32 %Len to i64
br label %for.body br label %for.body
for.cond.cleanup: for.cond.cleanup:
%Acc.0.lcssa = phi <512 x i1> [ %4, %entry ], [ %14, %for.body ] %Acc.0.lcssa = phi <512 x i1> [ %4, %entry ], [ %14, %for.body ]
%5 = tail call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.ppc.mma.disassemble.acc(<512 x i1> %Acc.0.lcssa) %5 = tail call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.ppc.mma.disassemble.acc(<512 x i1> %Acc.0.lcssa)
%6 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %5, 0 %6 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %5, 0
store <16 x i8> %6, <16 x i8>* %Dst, align 16 store <16 x i8> %6, ptr %Dst, align 16
%7 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %5, 1 %7 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %5, 1
%8 = getelementptr inbounds <16 x i8>, <16 x i8>* %Dst, i64 1 %8 = getelementptr inbounds <16 x i8>, ptr %Dst, i64 1
store <16 x i8> %7, <16 x i8>* %8, align 16 store <16 x i8> %7, ptr %8, align 16
%9 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %5, 2 %9 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %5, 2
%10 = getelementptr inbounds <16 x i8>, <16 x i8>* %Dst, i64 2 %10 = getelementptr inbounds <16 x i8>, ptr %Dst, i64 2
store <16 x i8> %9, <16 x i8>* %10, align 16 store <16 x i8> %9, ptr %10, align 16
%11 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %5, 3 %11 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %5, 3
%12 = getelementptr inbounds <16 x i8>, <16 x i8>* %Dst, i64 3 %12 = getelementptr inbounds <16 x i8>, ptr %Dst, i64 3
store <16 x i8> %11, <16 x i8>* %12, align 16 store <16 x i8> %11, ptr %12, align 16
ret void ret void
for.body: for.body:
%indvars.iv = phi i64 [ 3, %for.body.preheader ], [ %indvars.iv.next, %for.body ] %indvars.iv = phi i64 [ 3, %for.body.preheader ], [ %indvars.iv.next, %for.body ]
%Acc.015 = phi <512 x i1> [ %4, %for.body.preheader ], [ %14, %for.body ] %Acc.015 = phi <512 x i1> [ %4, %for.body.preheader ], [ %14, %for.body ]
%arrayidx3 = getelementptr inbounds <16 x i8>, <16 x i8>* %Src, i64 %indvars.iv %arrayidx3 = getelementptr inbounds <16 x i8>, ptr %Src, i64 %indvars.iv
%13 = load <16 x i8>, <16 x i8>* %arrayidx3, align 16 %13 = load <16 x i8>, ptr %arrayidx3, align 16
%14 = tail call <512 x i1> @llvm.ppc.mma.xvf64gerpp(<512 x i1> %Acc.015, <256 x i1> %2, <16 x i8> %13) %14 = tail call <512 x i1> @llvm.ppc.mma.xvf64gerpp(<512 x i1> %Acc.015, <256 x i1> %2, <16 x i8> %13)
%indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
%exitcond.not = icmp eq i64 %indvars.iv.next, %wide.trip.count %exitcond.not = icmp eq i64 %indvars.iv.next, %wide.trip.count
br i1 %exitcond.not, label %for.cond.cleanup, label %for.body br i1 %exitcond.not, label %for.cond.cleanup, label %for.body
} }
; This test uses an unprimed accumulator PHI node with two operands: an ; This test uses an unprimed accumulator PHI node with two operands: an
; implicitely defined unprimed accumulator and the unprimed result of the call ; implicitely defined unprimed accumulator and the unprimed result of the call
; to xvf64gerpp. The compiler should replace this PHI node by a primed ; to xvf64gerpp. The compiler should replace this PHI node by a primed
; accumulator PHI node. ; accumulator PHI node.
define void @testImplicitDef(<16 x i8>* %ptr) { define void @testImplicitDef(ptr %ptr) {
; CHECK-LABEL: testImplicitDef: ; CHECK-LABEL: testImplicitDef:
; CHECK: # %bb.0: # %label1 ; CHECK: # %bb.0: # %label1
; CHECK-NEXT: # implicit-def: $acc0 ; CHECK-NEXT: # implicit-def: $acc0
; CHECK-NEXT: bc 12, 4*cr5+lt, .LBB2_2 ; CHECK-NEXT: bc 12, 4*cr5+lt, .LBB2_2
; CHECK-NEXT: # %bb.1: # %label2 ; CHECK-NEXT: # %bb.1: # %label2
; CHECK-NEXT: xvf64gerpp acc0, vsp34, vs0 ; CHECK-NEXT: xvf64gerpp acc0, vsp34, vs0
; CHECK-NEXT: .LBB2_2: # %label3 ; CHECK-NEXT: .LBB2_2: # %label3
; CHECK-NEXT: xxmfacc acc0 ; CHECK-NEXT: xxmfacc acc0
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label2: label2:
%0 = call <512 x i1> @llvm.ppc.mma.xvf64gerpp(<512 x i1> undef, <256 x i1> undef, <16 x i8> undef) %0 = call <512 x i1> @llvm.ppc.mma.xvf64gerpp(<512 x i1> undef, <256 x i1> undef, <16 x i8> undef)
br label %label3 br label %label3
label3: label3:
%1 = phi <512 x i1> [ undef, %label1 ], [ %0, %label2 ] %1 = phi <512 x i1> [ undef, %label1 ], [ %0, %label2 ]
%2 = call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.ppc.mma.disassemble.acc(<512 x i1> %1) %2 = call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.ppc.mma.disassemble.acc(<512 x i1> %1)
%3 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %2, 3 %3 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %2, 3
store <16 x i8> %3, <16 x i8>* %ptr, align 16 store <16 x i8> %3, ptr %ptr, align 16
ret void ret void
} }
; This test uses an unprimed accumulator PHI node with an unprimed accumulator ; This test uses an unprimed accumulator PHI node with an unprimed accumulator
; PHI node operand. The compiler should replace these PHI nodes by primed ; PHI node operand. The compiler should replace these PHI nodes by primed
; accumulator PHI nodes. ; accumulator PHI nodes.
declare <512 x i1> @llvm.ppc.mma.xvf32gernp(<512 x i1>, <16 x i8>, <16 x i8>) declare <512 x i1> @llvm.ppc.mma.xvf32gernp(<512 x i1>, <16 x i8>, <16 x i8>)
define dso_local signext i32 @testNestedPHI(i32 signext %cond, i32 signext %count, <512 x i1>* nocapture %ptr, <16 x i8> %vc) { define dso_local signext i32 @testNestedPHI(i32 signext %cond, i32 signext %count, ptr nocapture %ptr, <16 x i8> %vc) {
; CHECK-LABEL: testNestedPHI: ; CHECK-LABEL: testNestedPHI:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cmplwi r3, 0 ; CHECK-NEXT: cmplwi r3, 0
; CHECK-NEXT: beq cr0, .LBB3_2 ; CHECK-NEXT: beq cr0, .LBB3_2
; CHECK-NEXT: # %bb.1: # %if.then ; CHECK-NEXT: # %bb.1: # %if.then
; CHECK-NEXT: xvf32gernp acc0, v2, v2 ; CHECK-NEXT: xvf32gernp acc0, v2, v2
; CHECK-NEXT: cmpwi r4, 1 ; CHECK-NEXT: cmpwi r4, 1
; CHECK-NEXT: bge cr0, .LBB3_3 ; CHECK-NEXT: bge cr0, .LBB3_3
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if.end: if.end:
%vq.0 = phi <512 x i1> [ %0, %if.then ], [ undef, %entry ] %vq.0 = phi <512 x i1> [ %0, %if.then ], [ undef, %entry ]
%cmp9 = icmp sgt i32 %count, 0 %cmp9 = icmp sgt i32 %count, 0
br i1 %cmp9, label %for.body, label %for.cond.cleanup br i1 %cmp9, label %for.body, label %for.cond.cleanup
for.cond.cleanup: for.cond.cleanup:
%vq.1.lcssa = phi <512 x i1> [ %vq.0, %if.end ], [ %1, %for.body ] %vq.1.lcssa = phi <512 x i1> [ %vq.0, %if.end ], [ %1, %for.body ]
store <512 x i1> %vq.1.lcssa, <512 x i1>* %ptr, align 64 store <512 x i1> %vq.1.lcssa, ptr %ptr, align 64
ret i32 0 ret i32 0
for.body: for.body:
%i.011 = phi i32 [ %inc, %for.body ], [ 0, %if.end ] %i.011 = phi i32 [ %inc, %for.body ], [ 0, %if.end ]
%vq.110 = phi <512 x i1> [ %1, %for.body ], [ %vq.0, %if.end ] %vq.110 = phi <512 x i1> [ %1, %for.body ], [ %vq.0, %if.end ]
%1 = tail call <512 x i1> @llvm.ppc.mma.xvf32gernp(<512 x i1> %vq.110, <16 x i8> %vc, <16 x i8> %vc) %1 = tail call <512 x i1> @llvm.ppc.mma.xvf32gernp(<512 x i1> %vq.110, <16 x i8> %vc, <16 x i8> %vc)
%inc = add nuw nsw i32 %i.011, 1 %inc = add nuw nsw i32 %i.011, 1
%exitcond.not = icmp eq i32 %inc, %count %exitcond.not = icmp eq i32 %inc, %count
br i1 %exitcond.not, label %for.cond.cleanup, label %for.body br i1 %exitcond.not, label %for.cond.cleanup, label %for.body
} }