[HLSL] Add __builtin_hlsl_create_handle

[beanz]

Summary

This is pretty straightforward, it just adds a builtin to return a
pointer to a resource handle. This maps to a dx intrinsic.

The shape of this builtin and the underlying intrinsic will likely
shift a bit as this implementation becomes more feature complete, but
this is a good basis to get started.

Depends on D128569.

[python3kgae]

clang/test/CodeGenHLSL/builtins/create_handle.hlsl

5

What does the parameter 0 mean here?

[beanz]

clang/test/CodeGenHLSL/builtins/create_handle.hlsl

5

For the purposes of this test, the value doesn't matter, but in the next patch in the sequence D130017, I pass the resource class in that parameter.

clang/include/clang/Basic/Builtins.def

 BUILTIN(__builtin_os_log_format_buffer_size, "zcC*.", "p:0:nut")
 BUILTIN(__builtin_os_log_format, "v*v*cC*.", "p:0:nt")
 
 // CUDA/HIP
 LANGBUILTIN(__builtin_get_device_side_mangled_name, "cC*.", "ncT", CUDA_LANG)
 
 // HLSL
 LANGBUILTIN(__builtin_hlsl_wave_active_count_bits, "Uib", "nc", HLSL_LANG)
+LANGBUILTIN(__builtin_hlsl_create_handle, "v*Uc", "nc", HLSL_LANG)
 
 // Builtins for XRay
 BUILTIN(__xray_customevent, "vcC*z", "")
 BUILTIN(__xray_typedevent, "vzcC*z", "")
 
 // Win64-compatible va_list functions
 BUILTIN(__builtin_ms_va_start, "vc*&.", "nt")
 BUILTIN(__builtin_ms_va_end, "vc*&", "n")
 BUILTIN(__builtin_ms_va_copy, "vc*&c*&", "n")
 
 // Arithmetic Fence: to prevent FP reordering and reassociation optimizations
 LANGBUILTIN(__arithmetic_fence, "v.", "t", ALL_LANGUAGES)
 
 #undef BUILTIN
 #undef LIBBUILTIN
 #undef LANGBUILTIN

clang/test/CodeGenHLSL/builtins/create_handle.hlsl

+// RUN: %clang_cc1 -triple dxil-pc-shadermodel6.3-library -x hlsl -emit-llvm -disable-llvm-passes -o - %s | FileCheck %s
+
+void fn() {
+  (void)__builtin_hlsl_create_handle(0);
+}
+
+// CHECK: call ptr @llvm.dx.create.handle(i8 0)

llvm/include/llvm/IR/IntrinsicsDirectX.td

 
 let TargetPrefix = "dx" in {
 
 def int_dx_thread_id : Intrinsic<[llvm_i32_ty], [llvm_i32_ty], [IntrNoMem, IntrWillReturn]>;
 def int_dx_group_id : Intrinsic<[llvm_i32_ty], [llvm_i32_ty], [IntrNoMem, IntrWillReturn]>;
 def int_dx_thread_id_in_group : Intrinsic<[llvm_i32_ty], [llvm_i32_ty], [IntrNoMem, IntrWillReturn]>;
 def int_dx_flattened_thread_id_in_group : Intrinsic<[llvm_i32_ty], [], [IntrNoMem, IntrWillReturn]>;
 
+def int_dx_create_handle : ClangBuiltin<"__builtin_hlsl_create_handle">,
+    Intrinsic<[ llvm_ptr_ty ], [llvm_i8_ty], [IntrNoMem, IntrWillReturn]>;
 }