[LoongArch] Optimize the atomic store with amswap_db.[w/d]

[gonglingqin]

Summary

When AtomicOrdering is release or stronger, use

amswap_db.[w/d] $zero, $a1, $a0

instead of

dbar 0
st.[w/d] $a0, $a1, 0

Thanks to @xry111 for the suggestion: https://reviews.llvm.org/D128901#3626635

[xry111]

llvm/test/CodeGen/LoongArch/ir-instruction/load-store-atomic.ll

308

The manual says LA32 may lack amswap_db.w (its not in Table 2-1, page 12 in the Chinese version). If it's not a documentation error we need to keep the old behavior for LA32.

[gonglingqin]

llvm/test/CodeGen/LoongArch/ir-instruction/load-store-atomic.ll

308

Thanks, I will change that.

[gonglingqin]

Address @xry111's comments.

[gonglingqin]

A polite ping. Thanks:)

[xen0n]

I'm not sure about the changes (they are a little bit too much and I must admit I'm relatively weak at memory models) but the test case changes are good. I'd leave the LGTM to someone else for now...

[gonglingqin]

rebase

[SixWeining]

llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp

1754

No need to use else after return.

1755–1757

Size = isa<StoreInst>(I) ? I->getOperand(0)->getType()->getIntegerBitWidth() : 0;

[SixWeining]

llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp

1755–1761

How about:

if (isa<LoadInst>(I))
  return true;

// On LA64, atomic store operations with IntegerBitWidth of 32 and 64 do not
// require fences beacuse we can use amswap_db.[w/d].
if (isa<StoreInst>(I)) {
  unsigned Size = I->getOperand(0)->getType()->getIntegerBitWidth();
  return (Size == 8 || Size == 16);
}

return false;

[gonglingqin]

llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp

1754

Thanks.

1755–1757

Thanks.

1755–1761

Thanks, I will change it.

[gonglingqin]

Address @SixWeining's comments.

[gonglingqin]

rebase

[SixWeining]

LGTM.