Given a patch like D129506, using instructions not valid for the current target feature set becomes an error. This fixes an issue in ARMExpandPseudo::ExpandCMP_SWAP where Thumb2 compares were used in Thumb1Only code, such as thumbv8m.baseline targets.
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Is there some rule that ensures TempReg is a low register? I guess the register allocator for thumbv8m.baseline currently doesn't choose high registers, but that's sort of fragile. I'd prefer to make the pseudo-instruction explicitly constrain the register class if that's necessary.
llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp | ||
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1853 | strexd doesn't exist in thumbv8m.baseline? |
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This now adds a tCMP_SWAP_32 and uses tGPR for the tmp reg. The 64bit version was changes to an assert.
strexd doesn't exist in thumbv8m.baseline?