[ARM] Fix Thumb2 compare being emitted ExpandCMP_SWAP

[dmgreen]

Summary

Given a patch like D129506, using instructions not valid for the current target feature set becomes an error. This fixes an issue in ARMExpandPseudo::ExpandCMP_SWAP where Thumb2 compares were used in Thumb1Only code, such as thumbv8m.baseline targets.

[efriedma]

Is there some rule that ensures TempReg is a low register? I guess the register allocator for thumbv8m.baseline currently doesn't choose high registers, but that's sort of fragile. I'd prefer to make the pseudo-instruction explicitly constrain the register class if that's necessary.

llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp

1853

strexd doesn't exist in thumbv8m.baseline?

[dmgreen]

This now adds a tCMP_SWAP_32 and uses tGPR for the tmp reg. The 64bit version was changes to an assert.

[efriedma]

LGTM

llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp

 /// possible. This only gets used at -O0 so we don't care about efficiency of
 /// the generated code.
 bool ARMExpandPseudo::ExpandCMP_SWAP(MachineBasicBlock &MBB,
                                      MachineBasicBlock::iterator MBBI,
                                      unsigned LdrexOp, unsigned StrexOp,
                                      unsigned UxtOp,
                                      MachineBasicBlock::iterator &NextMBBI) {
   bool IsThumb = STI->isThumb();
+  bool IsThumb1Only = STI->isThumb1Only();
   MachineInstr &MI = *MBBI;
   DebugLoc DL = MI.getDebugLoc();
   const MachineOperand &Dest = MI.getOperand(0);
   Register TempReg = MI.getOperand(1).getReg();
   // Duplicating undef operands into 2 instructions does not guarantee the same
   // value on both; However undef should be replaced by xzr anyway.
   assert(!MI.getOperand(2).isUndef() && "cannot handle undef");
   Register AddrReg = MI.getOperand(2).getReg();
bool ARMExpandPseudo::ExpandCMP_SWAP(MachineBasicBlock &MBB,
   //     bne .Lloadcmp
   MIB = BuildMI(StoreBB, DL, TII->get(StrexOp), TempReg)
     .addReg(NewReg)
     .addReg(AddrReg);
   if (StrexOp == ARM::t2STREX)
     MIB.addImm(0); // a 32-bit Thumb strex (only) allows an offset.
   MIB.add(predOps(ARMCC::AL));
 
-  unsigned CMPri = IsThumb ? ARM::t2CMPri : ARM::CMPri;
+  unsigned CMPri =
+      IsThumb ? (IsThumb1Only ? ARM::tCMPi8 : ARM::t2CMPri) : ARM::CMPri;
   BuildMI(StoreBB, DL, TII->get(CMPri))
       .addReg(TempReg, RegState::Kill)
       .addImm(0)
       .add(predOps(ARMCC::AL));
   BuildMI(StoreBB, DL, TII->get(Bcc))
       .addMBB(LoadCmpBB)
       .addImm(ARMCC::NE)
       .addReg(ARM::CPSR, RegState::Kill);
if (IsThumb) {
     MIB.addReg(Reg.getReg(), Flags);
 }
 
 /// Expand a 64-bit CMP_SWAP to an ldrexd/strexd loop.
 bool ARMExpandPseudo::ExpandCMP_SWAP_64(MachineBasicBlock &MBB,
                                         MachineBasicBlock::iterator MBBI,
                                         MachineBasicBlock::iterator &NextMBBI) {
   bool IsThumb = STI->isThumb();
+  assert(!STI->isThumb1Only() && "CMP_SWAP_64 unsupported under Thumb1!");
   MachineInstr &MI = *MBBI;
   DebugLoc DL = MI.getDebugLoc();
   MachineOperand &Dest = MI.getOperand(0);
   Register TempReg = MI.getOperand(1).getReg();
   // Duplicating undef operands into 2 instructions does not guarantee the same
   // value on both; However undef should be replaced by xzr anyway.
   assert(!MI.getOperand(2).isUndef() && "cannot handle undef");
   Register AddrReg = MI.getOperand(2).getReg();
switch (Opcode) {
     case ARM::tCMP_SWAP_8:
       assert(STI->isThumb());
       return ExpandCMP_SWAP(MBB, MBBI, ARM::t2LDREXB, ARM::t2STREXB, ARM::tUXTB,
                             NextMBBI);
     case ARM::tCMP_SWAP_16:
       assert(STI->isThumb());
       return ExpandCMP_SWAP(MBB, MBBI, ARM::t2LDREXH, ARM::t2STREXH, ARM::tUXTH,
                             NextMBBI);
+    case ARM::tCMP_SWAP_32:
+      assert(STI->isThumb());
+      return ExpandCMP_SWAP(MBB, MBBI, ARM::t2LDREX, ARM::t2STREX, 0, NextMBBI);
 
     case ARM::CMP_SWAP_8:
       assert(!STI->isThumb());
       return ExpandCMP_SWAP(MBB, MBBI, ARM::LDREXB, ARM::STREXB, ARM::UXTB,
                             NextMBBI);
     case ARM::CMP_SWAP_16:
       assert(!STI->isThumb());
       return ExpandCMP_SWAP(MBB, MBBI, ARM::LDREXH, ARM::STREXH, ARM::UXTH,
                             NextMBBI);
     case ARM::CMP_SWAP_32:
-      if (STI->isThumb())
-        return ExpandCMP_SWAP(MBB, MBBI, ARM::t2LDREX, ARM::t2STREX, 0,
-                              NextMBBI);
-      else
-        return ExpandCMP_SWAP(MBB, MBBI, ARM::LDREX, ARM::STREX, 0, NextMBBI);
+      assert(!STI->isThumb());
 
     case ARM::CMP_SWAP_64:
       return ExpandCMP_SWAP_64(MBB, MBBI, NextMBBI);
 
     case ARM::tBL_PUSHLR:
     case ARM::BL_PUSHLR: {
       const bool Thumb = Opcode == ARM::tBL_PUSHLR;
       Register Reg = MI.getOperand(0).getReg();

llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp

 void ARMDAGToDAGISel::SelectCMP_SWAP(SDNode *N) {
   unsigned Opcode;
   EVT MemTy = cast<MemSDNode>(N)->getMemoryVT();
   if (MemTy == MVT::i8)
     Opcode = Subtarget->isThumb() ? ARM::tCMP_SWAP_8 : ARM::CMP_SWAP_8;
   else if (MemTy == MVT::i16)
     Opcode = Subtarget->isThumb() ? ARM::tCMP_SWAP_16 : ARM::CMP_SWAP_16;
   else if (MemTy == MVT::i32)
-    Opcode = ARM::CMP_SWAP_32;
+    Opcode = Subtarget->isThumb() ? ARM::tCMP_SWAP_32 : ARM::CMP_SWAP_32;
   else
     llvm_unreachable("Unknown AtomicCmpSwap type");
 
   SDValue Ops[] = {N->getOperand(1), N->getOperand(2), N->getOperand(3),
                    N->getOperand(0)};
   SDNode *CmpSwap = CurDAG->getMachineNode(
       Opcode, SDLoc(N),
       CurDAG->getVTList(MVT::i32, MVT::i32, MVT::Other), Ops);

llvm/lib/Target/ARM/ARMInstrThumb.td

 // Atomic cmpxchg for -O0
 //===----------------------------------
 
 // See ARMInstrInfo.td. These two thumb specific pseudos are required to
 // restrict the register class for the UXTB/UXTH ops used in the expansion.
 
 let Constraints = "@earlyclobber $Rd,@earlyclobber $temp",
     mayLoad = 1, mayStore = 1 in {
-def tCMP_SWAP_8 : PseudoInst<(outs GPR:$Rd, GPR:$temp),
+def tCMP_SWAP_8 : PseudoInst<(outs GPR:$Rd, tGPR:$temp),
                              (ins GPR:$addr, tGPR:$desired, GPR:$new),
                              NoItinerary, []>, Sched<[]>;
 
-def tCMP_SWAP_16 : PseudoInst<(outs GPR:$Rd, GPR:$temp),
+def tCMP_SWAP_16 : PseudoInst<(outs GPR:$Rd, tGPR:$temp),
                               (ins GPR:$addr, tGPR:$desired, GPR:$new),
                               NoItinerary, []>, Sched<[]>;
+
+def tCMP_SWAP_32 : PseudoInst<(outs GPR:$Rd, tGPR:$temp),
+                              (ins GPR:$addr, GPR:$desired, GPR:$new),
+                              NoItinerary, []>, Sched<[]>;
 }

llvm/test/CodeGen/ARM/atomicrmw_exclusive_monitor_ints.ll

 ; CHECK-THUMB8BASE-NEXT:    @ Parent Loop BB0_1 Depth=1
 ; CHECK-THUMB8BASE-NEXT:    @ => This Inner Loop Header: Depth=2
 ; CHECK-THUMB8BASE-NEXT:    ldrexb r0, [r3]
 ; CHECK-THUMB8BASE-NEXT:    cmp r0, r1
 ; CHECK-THUMB8BASE-NEXT:    bne .LBB0_4
 ; CHECK-THUMB8BASE-NEXT:  @ %bb.3: @ %atomicrmw.start
 ; CHECK-THUMB8BASE-NEXT:    @ in Loop: Header=BB0_2 Depth=2
 ; CHECK-THUMB8BASE-NEXT:    strexb r2, r4, [r3]
-; CHECK-THUMB8BASE-NEXT:    cmp.w r2, #0
+; CHECK-THUMB8BASE-NEXT:    cmp r2, #0
 ; CHECK-THUMB8BASE-NEXT:    bne .LBB0_2
 ; CHECK-THUMB8BASE-NEXT:  .LBB0_4: @ %atomicrmw.start
 ; CHECK-THUMB8BASE-NEXT:    @ in Loop: Header=BB0_1 Depth=1
 ; CHECK-THUMB8BASE-NEXT:    str r0, [sp] @ 4-byte Spill
 ; CHECK-THUMB8BASE-NEXT:    uxtb r1, r1
 ; CHECK-THUMB8BASE-NEXT:    subs r1, r0, r1
 ; CHECK-THUMB8BASE-NEXT:    rsbs r2, r1, #0
 ; CHECK-THUMB8BASE-NEXT:    adcs r1, r2

 ; CHECK-THUMB8BASE-NEXT:    @ Parent Loop BB1_1 Depth=1
 ; CHECK-THUMB8BASE-NEXT:    @ => This Inner Loop Header: Depth=2
 ; CHECK-THUMB8BASE-NEXT:    ldrexb r0, [r3]
 ; CHECK-THUMB8BASE-NEXT:    cmp r0, r1
 ; CHECK-THUMB8BASE-NEXT:    bne .LBB1_4
 ; CHECK-THUMB8BASE-NEXT:  @ %bb.3: @ %atomicrmw.start
 ; CHECK-THUMB8BASE-NEXT:    @ in Loop: Header=BB1_2 Depth=2
 ; CHECK-THUMB8BASE-NEXT:    strexb r2, r4, [r3]
-; CHECK-THUMB8BASE-NEXT:    cmp.w r2, #0
+; CHECK-THUMB8BASE-NEXT:    cmp r2, #0
 ; CHECK-THUMB8BASE-NEXT:    bne .LBB1_2
 ; CHECK-THUMB8BASE-NEXT:  .LBB1_4: @ %atomicrmw.start
 ; CHECK-THUMB8BASE-NEXT:    @ in Loop: Header=BB1_1 Depth=1
 ; CHECK-THUMB8BASE-NEXT:    str r0, [sp] @ 4-byte Spill
 ; CHECK-THUMB8BASE-NEXT:    uxtb r1, r1
 ; CHECK-THUMB8BASE-NEXT:    subs r1, r0, r1
 ; CHECK-THUMB8BASE-NEXT:    rsbs r2, r1, #0
 ; CHECK-THUMB8BASE-NEXT:    adcs r1, r2

 ; CHECK-THUMB8BASE-NEXT:    @ Parent Loop BB2_1 Depth=1
 ; CHECK-THUMB8BASE-NEXT:    @ => This Inner Loop Header: Depth=2
 ; CHECK-THUMB8BASE-NEXT:    ldrexb r0, [r3]
 ; CHECK-THUMB8BASE-NEXT:    cmp r0, r1
 ; CHECK-THUMB8BASE-NEXT:    bne .LBB2_4
 ; CHECK-THUMB8BASE-NEXT:  @ %bb.3: @ %atomicrmw.start
 ; CHECK-THUMB8BASE-NEXT:    @ in Loop: Header=BB2_2 Depth=2
 ; CHECK-THUMB8BASE-NEXT:    strexb r2, r4, [r3]
-; CHECK-THUMB8BASE-NEXT:    cmp.w r2, #0
+; CHECK-THUMB8BASE-NEXT:    cmp r2, #0
 ; CHECK-THUMB8BASE-NEXT:    bne .LBB2_2
 ; CHECK-THUMB8BASE-NEXT:  .LBB2_4: @ %atomicrmw.start
 ; CHECK-THUMB8BASE-NEXT:    @ in Loop: Header=BB2_1 Depth=1
 ; CHECK-THUMB8BASE-NEXT:    str r0, [sp] @ 4-byte Spill
 ; CHECK-THUMB8BASE-NEXT:    uxtb r1, r1
 ; CHECK-THUMB8BASE-NEXT:    subs r1, r0, r1
 ; CHECK-THUMB8BASE-NEXT:    rsbs r2, r1, #0
 ; CHECK-THUMB8BASE-NEXT:    adcs r1, r2

 ; CHECK-THUMB8BASE-NEXT:    @ Parent Loop BB3_1 Depth=1
 ; CHECK-THUMB8BASE-NEXT:    @ => This Inner Loop Header: Depth=2
 ; CHECK-THUMB8BASE-NEXT:    ldrexb r0, [r3]
 ; CHECK-THUMB8BASE-NEXT:    cmp r0, r1
 ; CHECK-THUMB8BASE-NEXT:    bne .LBB3_4
 ; CHECK-THUMB8BASE-NEXT:  @ %bb.3: @ %atomicrmw.start
 ; CHECK-THUMB8BASE-NEXT:    @ in Loop: Header=BB3_2 Depth=2
 ; CHECK-THUMB8BASE-NEXT:    strexb r2, r4, [r3]
-; CHECK-THUMB8BASE-NEXT:    cmp.w r2, #0
+; CHECK-THUMB8BASE-NEXT:    cmp r2, #0
 ; CHECK-THUMB8BASE-NEXT:    bne .LBB3_2
 ; CHECK-THUMB8BASE-NEXT:  .LBB3_4: @ %atomicrmw.start
 ; CHECK-THUMB8BASE-NEXT:    @ in Loop: Header=BB3_1 Depth=1
 ; CHECK-THUMB8BASE-NEXT:    str r0, [sp] @ 4-byte Spill
 ; CHECK-THUMB8BASE-NEXT:    uxtb r1, r1
 ; CHECK-THUMB8BASE-NEXT:    subs r1, r0, r1
 ; CHECK-THUMB8BASE-NEXT:    rsbs r2, r1, #0
 ; CHECK-THUMB8BASE-NEXT:    adcs r1, r2

 ; CHECK-THUMB8BASE-NEXT:    @ Parent Loop BB4_1 Depth=1
 ; CHECK-THUMB8BASE-NEXT:    @ => This Inner Loop Header: Depth=2
 ; CHECK-THUMB8BASE-NEXT:    ldrexb r0, [r3]
 ; CHECK-THUMB8BASE-NEXT:    cmp r0, r1
 ; CHECK-THUMB8BASE-NEXT:    bne .LBB4_4
 ; CHECK-THUMB8BASE-NEXT:  @ %bb.3: @ %atomicrmw.start
 ; CHECK-THUMB8BASE-NEXT:    @ in Loop: Header=BB4_2 Depth=2
 ; CHECK-THUMB8BASE-NEXT:    strexb r2, r4, [r3]
-; CHECK-THUMB8BASE-NEXT:    cmp.w r2, #0
+; CHECK-THUMB8BASE-NEXT:    cmp r2, #0
 ; CHECK-THUMB8BASE-NEXT:    bne .LBB4_2
 ; CHECK-THUMB8BASE-NEXT:  .LBB4_4: @ %atomicrmw.start
 ; CHECK-THUMB8BASE-NEXT:    @ in Loop: Header=BB4_1 Depth=1
 ; CHECK-THUMB8BASE-NEXT:    str r0, [sp] @ 4-byte Spill
 ; CHECK-THUMB8BASE-NEXT:    uxtb r1, r1
 ; CHECK-THUMB8BASE-NEXT:    subs r1, r0, r1
 ; CHECK-THUMB8BASE-NEXT:    rsbs r2, r1, #0
 ; CHECK-THUMB8BASE-NEXT:    adcs r1, r2

 ; CHECK-THUMB8BASE-NEXT:    @ Parent Loop BB5_1 Depth=1
 ; CHECK-THUMB8BASE-NEXT:    @ => This Inner Loop Header: Depth=2
 ; CHECK-THUMB8BASE-NEXT:    ldrexb r0, [r3]
 ; CHECK-THUMB8BASE-NEXT:    cmp r0, r1
 ; CHECK-THUMB8BASE-NEXT:    bne .LBB5_4
 ; CHECK-THUMB8BASE-NEXT:  @ %bb.3: @ %atomicrmw.start
 ; CHECK-THUMB8BASE-NEXT:    @ in Loop: Header=BB5_2 Depth=2
 ; CHECK-THUMB8BASE-NEXT:    strexb r2, r4, [r3]
-; CHECK-THUMB8BASE-NEXT:    cmp.w r2, #0
+; CHECK-THUMB8BASE-NEXT:    cmp r2, #0
 ; CHECK-THUMB8BASE-NEXT:    bne .LBB5_2
 ; CHECK-THUMB8BASE-NEXT:  .LBB5_4: @ %atomicrmw.start
 ; CHECK-THUMB8BASE-NEXT:    @ in Loop: Header=BB5_1 Depth=1
 ; CHECK-THUMB8BASE-NEXT:    str r0, [sp] @ 4-byte Spill
 ; CHECK-THUMB8BASE-NEXT:    uxtb r1, r1
 ; CHECK-THUMB8BASE-NEXT:    subs r1, r0, r1
 ; CHECK-THUMB8BASE-NEXT:    rsbs r2, r1, #0
 ; CHECK-THUMB8BASE-NEXT:    adcs r1, r2

 ; CHECK-THUMB8BASE-NEXT:    @ Parent Loop BB6_1 Depth=1
 ; CHECK-THUMB8BASE-NEXT:    @ => This Inner Loop Header: Depth=2
 ; CHECK-THUMB8BASE-NEXT:    ldrexb r0, [r3]
 ; CHECK-THUMB8BASE-NEXT:    cmp r0, r1
 ; CHECK-THUMB8BASE-NEXT:    bne .LBB6_4
 ; CHECK-THUMB8BASE-NEXT:  @ %bb.3: @ %atomicrmw.start
 ; CHECK-THUMB8BASE-NEXT:    @ in Loop: Header=BB6_2 Depth=2
 ; CHECK-THUMB8BASE-NEXT:    strexb r2, r4, [r3]
-; CHECK-THUMB8BASE-NEXT:    cmp.w r2, #0
+; CHECK-THUMB8BASE-NEXT:    cmp r2, #0
 ; CHECK-THUMB8BASE-NEXT:    bne .LBB6_2
 ; CHECK-THUMB8BASE-NEXT:  .LBB6_4: @ %atomicrmw.start
 ; CHECK-THUMB8BASE-NEXT:    @ in Loop: Header=BB6_1 Depth=1
 ; CHECK-THUMB8BASE-NEXT:    str r0, [sp] @ 4-byte Spill
 ; CHECK-THUMB8BASE-NEXT:    uxtb r1, r1
 ; CHECK-THUMB8BASE-NEXT:    subs r1, r0, r1
 ; CHECK-THUMB8BASE-NEXT:    rsbs r2, r1, #0
 ; CHECK-THUMB8BASE-NEXT:    adcs r1, r2

 ; CHECK-THUMB8BASE-NEXT:    @ Parent Loop BB7_1 Depth=1
 ; CHECK-THUMB8BASE-NEXT:    @ => This Inner Loop Header: Depth=2
 ; CHECK-THUMB8BASE-NEXT:    ldrexb r0, [r3]
 ; CHECK-THUMB8BASE-NEXT:    cmp r0, r1
 ; CHECK-THUMB8BASE-NEXT:    bne .LBB7_6
 ; CHECK-THUMB8BASE-NEXT:  @ %bb.5: @ %atomicrmw.start
 ; CHECK-THUMB8BASE-NEXT:    @ in Loop: Header=BB7_4 Depth=2
 ; CHECK-THUMB8BASE-NEXT:    strexb r2, r4, [r3]
-; CHECK-THUMB8BASE-NEXT:    cmp.w r2, #0
+; CHECK-THUMB8BASE-NEXT:    cmp r2, #0
 ; CHECK-THUMB8BASE-NEXT:    bne .LBB7_4
 ; CHECK-THUMB8BASE-NEXT:  .LBB7_6: @ %atomicrmw.start
 ; CHECK-THUMB8BASE-NEXT:    @ in Loop: Header=BB7_1 Depth=1
 ; CHECK-THUMB8BASE-NEXT:    str r0, [sp] @ 4-byte Spill
 ; CHECK-THUMB8BASE-NEXT:    uxtb r1, r1
 ; CHECK-THUMB8BASE-NEXT:    subs r1, r0, r1
 ; CHECK-THUMB8BASE-NEXT:    rsbs r2, r1, #0
 ; CHECK-THUMB8BASE-NEXT:    adcs r1, r2

 ; CHECK-THUMB8BASE-NEXT:    @ Parent Loop BB8_1 Depth=1
 ; CHECK-THUMB8BASE-NEXT:    @ => This Inner Loop Header: Depth=2
 ; CHECK-THUMB8BASE-NEXT:    ldrexb r0, [r3]
 ; CHECK-THUMB8BASE-NEXT:    cmp r0, r1
 ; CHECK-THUMB8BASE-NEXT:    bne .LBB8_6
 ; CHECK-THUMB8BASE-NEXT:  @ %bb.5: @ %atomicrmw.start
 ; CHECK-THUMB8BASE-NEXT:    @ in Loop: Header=BB8_4 Depth=2
 ; CHECK-THUMB8BASE-NEXT:    strexb r2, r4, [r3]
-; CHECK-THUMB8BASE-NEXT:    cmp.w r2, #0
+; CHECK-THUMB8BASE-NEXT:    cmp r2, #0
 ; CHECK-THUMB8BASE-NEXT:    bne .LBB8_4
 ; CHECK-THUMB8BASE-NEXT:  .LBB8_6: @ %atomicrmw.start
 ; CHECK-THUMB8BASE-NEXT:    @ in Loop: Header=BB8_1 Depth=1
 ; CHECK-THUMB8BASE-NEXT:    str r0, [sp] @ 4-byte Spill
 ; CHECK-THUMB8BASE-NEXT:    uxtb r1, r1
 ; CHECK-THUMB8BASE-NEXT:    subs r1, r0, r1
 ; CHECK-THUMB8BASE-NEXT:    rsbs r2, r1, #0
 ; CHECK-THUMB8BASE-NEXT:    adcs r1, r2

 ; CHECK-THUMB8BASE-NEXT:    @ Parent Loop BB9_1 Depth=1
 ; CHECK-THUMB8BASE-NEXT:    @ => This Inner Loop Header: Depth=2
 ; CHECK-THUMB8BASE-NEXT:    ldrexb r0, [r3]
 ; CHECK-THUMB8BASE-NEXT:    cmp r0, r4
 ; CHECK-THUMB8BASE-NEXT:    bne .LBB9_6
 ; CHECK-THUMB8BASE-NEXT:  @ %bb.5: @ %atomicrmw.start
 ; CHECK-THUMB8BASE-NEXT:    @ in Loop: Header=BB9_4 Depth=2
 ; CHECK-THUMB8BASE-NEXT:    strexb r2, r5, [r3]
-; CHECK-THUMB8BASE-NEXT:    cmp.w r2, #0
+; CHECK-THUMB8BASE-NEXT:    cmp r2, #0
 ; CHECK-THUMB8BASE-NEXT:    bne .LBB9_4
 ; CHECK-THUMB8BASE-NEXT:  .LBB9_6: @ %atomicrmw.start
 ; CHECK-THUMB8BASE-NEXT:    @ in Loop: Header=BB9_1 Depth=1
 ; CHECK-THUMB8BASE-NEXT:    str r0, [sp] @ 4-byte Spill
 ; CHECK-THUMB8BASE-NEXT:    subs r1, r0, r1
 ; CHECK-THUMB8BASE-NEXT:    rsbs r2, r1, #0
 ; CHECK-THUMB8BASE-NEXT:    adcs r1, r2
 ; CHECK-THUMB8BASE-NEXT:    cmp r1, #1

 ; CHECK-THUMB8BASE-NEXT:    @ Parent Loop BB10_1 Depth=1
 ; CHECK-THUMB8BASE-NEXT:    @ => This Inner Loop Header: Depth=2
 ; CHECK-THUMB8BASE-NEXT:    ldrexb r0, [r3]
 ; CHECK-THUMB8BASE-NEXT:    cmp r0, r4
 ; CHECK-THUMB8BASE-NEXT:    bne .LBB10_6
 ; CHECK-THUMB8BASE-NEXT:  @ %bb.5: @ %atomicrmw.start
 ; CHECK-THUMB8BASE-NEXT:    @ in Loop: Header=BB10_4 Depth=2
 ; CHECK-THUMB8BASE-NEXT:    strexb r2, r5, [r3]
-; CHECK-THUMB8BASE-NEXT:    cmp.w r2, #0
+; CHECK-THUMB8BASE-NEXT:    cmp r2, #0
 ; CHECK-THUMB8BASE-NEXT:    bne .LBB10_4
 ; CHECK-THUMB8BASE-NEXT:  .LBB10_6: @ %atomicrmw.start
 ; CHECK-THUMB8BASE-NEXT:    @ in Loop: Header=BB10_1 Depth=1
 ; CHECK-THUMB8BASE-NEXT:    str r0, [sp] @ 4-byte Spill
 ; CHECK-THUMB8BASE-NEXT:    subs r1, r0, r1
 ; CHECK-THUMB8BASE-NEXT:    rsbs r2, r1, #0
 ; CHECK-THUMB8BASE-NEXT:    adcs r1, r2
 ; CHECK-THUMB8BASE-NEXT:    cmp r1, #1

 ; CHECK-THUMB8BASE-NEXT:    @ Parent Loop BB11_1 Depth=1
 ; CHECK-THUMB8BASE-NEXT:    @ => This Inner Loop Header: Depth=2
 ; CHECK-THUMB8BASE-NEXT:    ldrexh r0, [r3]
 ; CHECK-THUMB8BASE-NEXT:    cmp r0, r1
 ; CHECK-THUMB8BASE-NEXT:    bne .LBB11_4
 ; CHECK-THUMB8BASE-NEXT:  @ %bb.3: @ %atomicrmw.start
 ; CHECK-THUMB8BASE-NEXT:    @ in Loop: Header=BB11_2 Depth=2
 ; CHECK-THUMB8BASE-NEXT:    strexh r2, r4, [r3]
-; CHECK-THUMB8BASE-NEXT:    cmp.w r2, #0
+; CHECK-THUMB8BASE-NEXT:    cmp r2, #0
 ; CHECK-THUMB8BASE-NEXT:    bne .LBB11_2
 ; CHECK-THUMB8BASE-NEXT:  .LBB11_4: @ %atomicrmw.start
 ; CHECK-THUMB8BASE-NEXT:    @ in Loop: Header=BB11_1 Depth=1
 ; CHECK-THUMB8BASE-NEXT:    str r0, [sp] @ 4-byte Spill
 ; CHECK-THUMB8BASE-NEXT:    uxth r1, r1
 ; CHECK-THUMB8BASE-NEXT:    subs r1, r0, r1
 ; CHECK-THUMB8BASE-NEXT:    rsbs r2, r1, #0
 ; CHECK-THUMB8BASE-NEXT:    adcs r1, r2

 ; CHECK-THUMB8BASE-NEXT:    @ Parent Loop BB12_1 Depth=1
 ; CHECK-THUMB8BASE-NEXT:    @ => This Inner Loop Header: Depth=2
 ; CHECK-THUMB8BASE-NEXT:    ldrexh r0, [r3]
 ; CHECK-THUMB8BASE-NEXT:    cmp r0, r1
 ; CHECK-THUMB8BASE-NEXT:    bne .LBB12_4
 ; CHECK-THUMB8BASE-NEXT:  @ %bb.3: @ %atomicrmw.start
 ; CHECK-THUMB8BASE-NEXT:    @ in Loop: Header=BB12_2 Depth=2
 ; CHECK-THUMB8BASE-NEXT:    strexh r2, r4, [r3]
-; CHECK-THUMB8BASE-NEXT:    cmp.w r2, #0
+; CHECK-THUMB8BASE-NEXT:    cmp r2, #0
 ; CHECK-THUMB8BASE-NEXT:    bne .LBB12_2
 ; CHECK-THUMB8BASE-NEXT:  .LBB12_4: @ %atomicrmw.start
 ; CHECK-THUMB8BASE-NEXT:    @ in Loop: Header=BB12_1 Depth=1
 ; CHECK-THUMB8BASE-NEXT:    str r0, [sp] @ 4-byte Spill
 ; CHECK-THUMB8BASE-NEXT:    uxth r1, r1
 ; CHECK-THUMB8BASE-NEXT:    subs r1, r0, r1
 ; CHECK-THUMB8BASE-NEXT:    rsbs r2, r1, #0
 ; CHECK-THUMB8BASE-NEXT:    adcs r1, r2

 ; CHECK-THUMB8BASE-NEXT:    @ Parent Loop BB13_1 Depth=1
 ; CHECK-THUMB8BASE-NEXT:    @ => This Inner Loop Header: Depth=2
 ; CHECK-THUMB8BASE-NEXT:    ldrexh r0, [r3]
 ; CHECK-THUMB8BASE-NEXT:    cmp r0, r1
 ; CHECK-THUMB8BASE-NEXT:    bne .LBB13_4
 ; CHECK-THUMB8BASE-NEXT:  @ %bb.3: @ %atomicrmw.start
 ; CHECK-THUMB8BASE-NEXT:    @ in Loop: Header=BB13_2 Depth=2
 ; CHECK-THUMB8BASE-NEXT:    strexh r2, r4, [r3]
-; CHECK-THUMB8BASE-NEXT:    cmp.w r2, #0
+; CHECK-THUMB8BASE-NEXT:    cmp r2, #0
 ; CHECK-THUMB8BASE-NEXT:    bne .LBB13_2
 ; CHECK-THUMB8BASE-NEXT:  .LBB13_4: @ %atomicrmw.start
 ; CHECK-THUMB8BASE-NEXT:    @ in Loop: Header=BB13_1 Depth=1
 ; CHECK-THUMB8BASE-NEXT:    str r0, [sp] @ 4-byte Spill
 ; CHECK-THUMB8BASE-NEXT:    uxth r1, r1
 ; CHECK-THUMB8BASE-NEXT:    subs r1, r0, r1
 ; CHECK-THUMB8BASE-NEXT:    rsbs r2, r1, #0
 ; CHECK-THUMB8BASE-NEXT:    adcs r1, r2

 ; CHECK-THUMB8BASE-NEXT:    @ Parent Loop BB14_1 Depth=1
 ; CHECK-THUMB8BASE-NEXT:    @ => This Inner Loop Header: Depth=2
 ; CHECK-THUMB8BASE-NEXT:    ldrexh r0, [r3]
 ; CHECK-THUMB8BASE-NEXT:    cmp r0, r1
 ; CHECK-THUMB8BASE-NEXT:    bne .LBB14_4
 ; CHECK-THUMB8BASE-NEXT:  @ %bb.3: @ %atomicrmw.start
 ; CHECK-THUMB8BASE-NEXT:    @ in Loop: Header=BB14_2 Depth=2
 ; CHECK-THUMB8BASE-NEXT:    strexh r2, r4, [r3]
-; CHECK-THUMB8BASE-NEXT:    cmp.w r2, #0
+; CHECK-THUMB8BASE-NEXT:    cmp r2, #0
 ; CHECK-THUMB8BASE-NEXT:    bne .LBB14_2
 ; CHECK-THUMB8BASE-NEXT:  .LBB14_4: @ %atomicrmw.start
 ; CHECK-THUMB8BASE-NEXT:    @ in Loop: Header=BB14_1 Depth=1
 ; CHECK-THUMB8BASE-NEXT:    str r0, [sp] @ 4-byte Spill
 ; CHECK-THUMB8BASE-NEXT:    uxth r1, r1
 ; CHECK-THUMB8BASE-NEXT:    subs r1, r0, r1
 ; CHECK-THUMB8BASE-NEXT:    rsbs r2, r1, #0
 ; CHECK-THUMB8BASE-NEXT:    adcs r1, r2

 ; CHECK-THUMB8BASE-NEXT:    @ Parent Loop BB15_1 Depth=1
 ; CHECK-THUMB8BASE-NEXT:    @ => This Inner Loop Header: Depth=2
 ; CHECK-THUMB8BASE-NEXT:    ldrexh r0, [r3]
 ; CHECK-THUMB8BASE-NEXT:    cmp r0, r1
 ; CHECK-THUMB8BASE-NEXT:    bne .LBB15_4
 ; CHECK-THUMB8BASE-NEXT:  @ %bb.3: @ %atomicrmw.start
 ; CHECK-THUMB8BASE-NEXT:    @ in Loop: Header=BB15_2 Depth=2
 ; CHECK-THUMB8BASE-NEXT:    strexh r2, r4, [r3]
-; CHECK-THUMB8BASE-NEXT:    cmp.w r2, #0
+; CHECK-THUMB8BASE-NEXT:    cmp r2, #0
 ; CHECK-THUMB8BASE-NEXT:    bne .LBB15_2
 ; CHECK-THUMB8BASE-NEXT:  .LBB15_4: @ %atomicrmw.start
 ; CHECK-THUMB8BASE-NEXT:    @ in Loop: Header=BB15_1 Depth=1
 ; CHECK-THUMB8BASE-NEXT:    str r0, [sp] @ 4-byte Spill
 ; CHECK-THUMB8BASE-NEXT:    uxth r1, r1
 ; CHECK-THUMB8BASE-NEXT:    subs r1, r0, r1
 ; CHECK-THUMB8BASE-NEXT:    rsbs r2, r1, #0
 ; CHECK-THUMB8BASE-NEXT:    adcs r1, r2

 ; CHECK-THUMB8BASE-NEXT:    @ Parent Loop BB16_1 Depth=1
 ; CHECK-THUMB8BASE-NEXT:    @ => This Inner Loop Header: Depth=2
 ; CHECK-THUMB8BASE-NEXT:    ldrexh r0, [r3]
 ; CHECK-THUMB8BASE-NEXT:    cmp r0, r1
 ; CHECK-THUMB8BASE-NEXT:    bne .LBB16_4
 ; CHECK-THUMB8BASE-NEXT:  @ %bb.3: @ %atomicrmw.start
 ; CHECK-THUMB8BASE-NEXT:    @ in Loop: Header=BB16_2 Depth=2
 ; CHECK-THUMB8BASE-NEXT:    strexh r2, r4, [r3]
-; CHECK-THUMB8BASE-NEXT:    cmp.w r2, #0
+; CHECK-THUMB8BASE-NEXT:    cmp r2, #0
 ; CHECK-THUMB8BASE-NEXT:    bne .LBB16_2
 ; CHECK-THUMB8BASE-NEXT:  .LBB16_4: @ %atomicrmw.start
 ; CHECK-THUMB8BASE-NEXT:    @ in Loop: Header=BB16_1 Depth=1
 ; CHECK-THUMB8BASE-NEXT:    str r0, [sp] @ 4-byte Spill
 ; CHECK-THUMB8BASE-NEXT:    uxth r1, r1
 ; CHECK-THUMB8BASE-NEXT:    subs r1, r0, r1
 ; CHECK-THUMB8BASE-NEXT:    rsbs r2, r1, #0
 ; CHECK-THUMB8BASE-NEXT:    adcs r1, r2

 ; CHECK-THUMB8BASE-NEXT:    @ Parent Loop BB17_1 Depth=1
 ; CHECK-THUMB8BASE-NEXT:    @ => This Inner Loop Header: Depth=2
 ; CHECK-THUMB8BASE-NEXT:    ldrexh r0, [r3]
 ; CHECK-THUMB8BASE-NEXT:    cmp r0, r1
 ; CHECK-THUMB8BASE-NEXT:    bne .LBB17_4
 ; CHECK-THUMB8BASE-NEXT:  @ %bb.3: @ %atomicrmw.start
 ; CHECK-THUMB8BASE-NEXT:    @ in Loop: Header=BB17_2 Depth=2
 ; CHECK-THUMB8BASE-NEXT:    strexh r2, r4, [r3]
-; CHECK-THUMB8BASE-NEXT:    cmp.w r2, #0
+; CHECK-THUMB8BASE-NEXT:    cmp r2, #0
 ; CHECK-THUMB8BASE-NEXT:    bne .LBB17_2
 ; CHECK-THUMB8BASE-NEXT:  .LBB17_4: @ %atomicrmw.start
 ; CHECK-THUMB8BASE-NEXT:    @ in Loop: Header=BB17_1 Depth=1
 ; CHECK-THUMB8BASE-NEXT:    str r0, [sp] @ 4-byte Spill
 ; CHECK-THUMB8BASE-NEXT:    uxth r1, r1
 ; CHECK-THUMB8BASE-NEXT:    subs r1, r0, r1
 ; CHECK-THUMB8BASE-NEXT:    rsbs r2, r1, #0
 ; CHECK-THUMB8BASE-NEXT:    adcs r1, r2

 ; CHECK-THUMB8BASE-NEXT:    @ Parent Loop BB18_1 Depth=1
 ; CHECK-THUMB8BASE-NEXT:    @ => This Inner Loop Header: Depth=2
 ; CHECK-THUMB8BASE-NEXT:    ldrexh r0, [r3]
 ; CHECK-THUMB8BASE-NEXT:    cmp r0, r1
 ; CHECK-THUMB8BASE-NEXT:    bne .LBB18_6
 ; CHECK-THUMB8BASE-NEXT:  @ %bb.5: @ %atomicrmw.start
 ; CHECK-THUMB8BASE-NEXT:    @ in Loop: Header=BB18_4 Depth=2
 ; CHECK-THUMB8BASE-NEXT:    strexh r2, r4, [r3]
-; CHECK-THUMB8BASE-NEXT:    cmp.w r2, #0
+; CHECK-THUMB8BASE-NEXT:    cmp r2, #0
 ; CHECK-THUMB8BASE-NEXT:    bne .LBB18_4
 ; CHECK-THUMB8BASE-NEXT:  .LBB18_6: @ %atomicrmw.start
 ; CHECK-THUMB8BASE-NEXT:    @ in Loop: Header=BB18_1 Depth=1
 ; CHECK-THUMB8BASE-NEXT:    str r0, [sp] @ 4-byte Spill
 ; CHECK-THUMB8BASE-NEXT:    uxth r1, r1
 ; CHECK-THUMB8BASE-NEXT:    subs r1, r0, r1
 ; CHECK-THUMB8BASE-NEXT:    rsbs r2, r1, #0
 ; CHECK-THUMB8BASE-NEXT:    adcs r1, r2

 ; CHECK-THUMB8BASE-NEXT:    @ Parent Loop BB19_1 Depth=1
 ; CHECK-THUMB8BASE-NEXT:    @ => This Inner Loop Header: Depth=2
 ; CHECK-THUMB8BASE-NEXT:    ldrexh r0, [r3]
 ; CHECK-THUMB8BASE-NEXT:    cmp r0, r1
 ; CHECK-THUMB8BASE-NEXT:    bne .LBB19_6
 ; CHECK-THUMB8BASE-NEXT:  @ %bb.5: @ %atomicrmw.start
 ; CHECK-THUMB8BASE-NEXT:    @ in Loop: Header=BB19_4 Depth=2
 ; CHECK-THUMB8BASE-NEXT:    strexh r2, r4, [r3]
-; CHECK-THUMB8BASE-NEXT:    cmp.w r2, #0
+; CHECK-THUMB8BASE-NEXT:    cmp r2, #0
 ; CHECK-THUMB8BASE-NEXT:    bne .LBB19_4
 ; CHECK-THUMB8BASE-NEXT:  .LBB19_6: @ %atomicrmw.start
 ; CHECK-THUMB8BASE-NEXT:    @ in Loop: Header=BB19_1 Depth=1
 ; CHECK-THUMB8BASE-NEXT:    str r0, [sp] @ 4-byte Spill
 ; CHECK-THUMB8BASE-NEXT:    uxth r1, r1
 ; CHECK-THUMB8BASE-NEXT:    subs r1, r0, r1
 ; CHECK-THUMB8BASE-NEXT:    rsbs r2, r1, #0
 ; CHECK-THUMB8BASE-NEXT:    adcs r1, r2

 ; CHECK-THUMB8BASE-NEXT:    @ Parent Loop BB20_1 Depth=1
 ; CHECK-THUMB8BASE-NEXT:    @ => This Inner Loop Header: Depth=2
 ; CHECK-THUMB8BASE-NEXT:    ldrexh r0, [r3]
 ; CHECK-THUMB8BASE-NEXT:    cmp r0, r4
 ; CHECK-THUMB8BASE-NEXT:    bne .LBB20_6
 ; CHECK-THUMB8BASE-NEXT:  @ %bb.5: @ %atomicrmw.start
 ; CHECK-THUMB8BASE-NEXT:    @ in Loop: Header=BB20_4 Depth=2
 ; CHECK-THUMB8BASE-NEXT:    strexh r2, r5, [r3]
-; CHECK-THUMB8BASE-NEXT:    cmp.w r2, #0
+; CHECK-THUMB8BASE-NEXT:    cmp r2, #0
 ; CHECK-THUMB8BASE-NEXT:    bne .LBB20_4
 ; CHECK-THUMB8BASE-NEXT:  .LBB20_6: @ %atomicrmw.start
 ; CHECK-THUMB8BASE-NEXT:    @ in Loop: Header=BB20_1 Depth=1
 ; CHECK-THUMB8BASE-NEXT:    str r0, [sp] @ 4-byte Spill
 ; CHECK-THUMB8BASE-NEXT:    subs r1, r0, r1
 ; CHECK-THUMB8BASE-NEXT:    rsbs r2, r1, #0
 ; CHECK-THUMB8BASE-NEXT:    adcs r1, r2
 ; CHECK-THUMB8BASE-NEXT:    cmp r1, #1

 ; CHECK-THUMB8BASE-NEXT:    @ Parent Loop BB21_1 Depth=1
 ; CHECK-THUMB8BASE-NEXT:    @ => This Inner Loop Header: Depth=2
 ; CHECK-THUMB8BASE-NEXT:    ldrexh r0, [r3]
 ; CHECK-THUMB8BASE-NEXT:    cmp r0, r4
 ; CHECK-THUMB8BASE-NEXT:    bne .LBB21_6
 ; CHECK-THUMB8BASE-NEXT:  @ %bb.5: @ %atomicrmw.start
 ; CHECK-THUMB8BASE-NEXT:    @ in Loop: Header=BB21_4 Depth=2
 ; CHECK-THUMB8BASE-NEXT:    strexh r2, r5, [r3]
-; CHECK-THUMB8BASE-NEXT:    cmp.w r2, #0
+; CHECK-THUMB8BASE-NEXT:    cmp r2, #0
 ; CHECK-THUMB8BASE-NEXT:    bne .LBB21_4
 ; CHECK-THUMB8BASE-NEXT:  .LBB21_6: @ %atomicrmw.start
 ; CHECK-THUMB8BASE-NEXT:    @ in Loop: Header=BB21_1 Depth=1
 ; CHECK-THUMB8BASE-NEXT:    str r0, [sp] @ 4-byte Spill
 ; CHECK-THUMB8BASE-NEXT:    subs r1, r0, r1
 ; CHECK-THUMB8BASE-NEXT:    rsbs r2, r1, #0
 ; CHECK-THUMB8BASE-NEXT:    adcs r1, r2
 ; CHECK-THUMB8BASE-NEXT:    cmp r1, #1

 ; CHECK-THUMB8BASE-NEXT:    @ Parent Loop BB22_1 Depth=1
 ; CHECK-THUMB8BASE-NEXT:    @ => This Inner Loop Header: Depth=2
 ; CHECK-THUMB8BASE-NEXT:    ldrex r0, [r3]
 ; CHECK-THUMB8BASE-NEXT:    cmp r0, r1
 ; CHECK-THUMB8BASE-NEXT:    bne .LBB22_4
 ; CHECK-THUMB8BASE-NEXT:  @ %bb.3: @ %atomicrmw.start
 ; CHECK-THUMB8BASE-NEXT:    @ in Loop: Header=BB22_2 Depth=2
 ; CHECK-THUMB8BASE-NEXT:    strex r2, r4, [r3]
-; CHECK-THUMB8BASE-NEXT:    cmp.w r2, #0
+; CHECK-THUMB8BASE-NEXT:    cmp r2, #0
 ; CHECK-THUMB8BASE-NEXT:    bne .LBB22_2
 ; CHECK-THUMB8BASE-NEXT:  .LBB22_4: @ %atomicrmw.start
 ; CHECK-THUMB8BASE-NEXT:    @ in Loop: Header=BB22_1 Depth=1
 ; CHECK-THUMB8BASE-NEXT:    str r0, [sp] @ 4-byte Spill
 ; CHECK-THUMB8BASE-NEXT:    subs r1, r0, r1
 ; CHECK-THUMB8BASE-NEXT:    rsbs r2, r1, #0
 ; CHECK-THUMB8BASE-NEXT:    adcs r1, r2
 ; CHECK-THUMB8BASE-NEXT:    cmp r1, #1

 ; CHECK-THUMB8BASE-NEXT:    @ Parent Loop BB23_1 Depth=1
 ; CHECK-THUMB8BASE-NEXT:    @ => This Inner Loop Header: Depth=2
 ; CHECK-THUMB8BASE-NEXT:    ldrex r0, [r3]
 ; CHECK-THUMB8BASE-NEXT:    cmp r0, r1
 ; CHECK-THUMB8BASE-NEXT:    bne .LBB23_4
 ; CHECK-THUMB8BASE-NEXT:  @ %bb.3: @ %atomicrmw.start
 ; CHECK-THUMB8BASE-NEXT:    @ in Loop: Header=BB23_2 Depth=2
 ; CHECK-THUMB8BASE-NEXT:    strex r2, r4, [r3]
-; CHECK-THUMB8BASE-NEXT:    cmp.w r2, #0
+; CHECK-THUMB8BASE-NEXT:    cmp r2, #0
 ; CHECK-THUMB8BASE-NEXT:    bne .LBB23_2
 ; CHECK-THUMB8BASE-NEXT:  .LBB23_4: @ %atomicrmw.start
 ; CHECK-THUMB8BASE-NEXT:    @ in Loop: Header=BB23_1 Depth=1
 ; CHECK-THUMB8BASE-NEXT:    str r0, [sp] @ 4-byte Spill
 ; CHECK-THUMB8BASE-NEXT:    subs r1, r0, r1
 ; CHECK-THUMB8BASE-NEXT:    rsbs r2, r1, #0
 ; CHECK-THUMB8BASE-NEXT:    adcs r1, r2
 ; CHECK-THUMB8BASE-NEXT:    cmp r1, #1

 ; CHECK-THUMB8BASE-NEXT:    @ Parent Loop BB24_1 Depth=1
 ; CHECK-THUMB8BASE-NEXT:    @ => This Inner Loop Header: Depth=2
 ; CHECK-THUMB8BASE-NEXT:    ldrex r0, [r3]
 ; CHECK-THUMB8BASE-NEXT:    cmp r0, r1
 ; CHECK-THUMB8BASE-NEXT:    bne .LBB24_4
 ; CHECK-THUMB8BASE-NEXT:  @ %bb.3: @ %atomicrmw.start
 ; CHECK-THUMB8BASE-NEXT:    @ in Loop: Header=BB24_2 Depth=2
 ; CHECK-THUMB8BASE-NEXT:    strex r2, r4, [r3]
-; CHECK-THUMB8BASE-NEXT:    cmp.w r2, #0
+; CHECK-THUMB8BASE-NEXT:    cmp r2, #0
 ; CHECK-THUMB8BASE-NEXT:    bne .LBB24_2
 ; CHECK-THUMB8BASE-NEXT:  .LBB24_4: @ %atomicrmw.start
 ; CHECK-THUMB8BASE-NEXT:    @ in Loop: Header=BB24_1 Depth=1
 ; CHECK-THUMB8BASE-NEXT:    str r0, [sp] @ 4-byte Spill
 ; CHECK-THUMB8BASE-NEXT:    subs r1, r0, r1
 ; CHECK-THUMB8BASE-NEXT:    rsbs r2, r1, #0
 ; CHECK-THUMB8BASE-NEXT:    adcs r1, r2
 ; CHECK-THUMB8BASE-NEXT:    cmp r1, #1

 ; CHECK-THUMB8BASE-NEXT:    @ Parent Loop BB25_1 Depth=1
 ; CHECK-THUMB8BASE-NEXT:    @ => This Inner Loop Header: Depth=2
 ; CHECK-THUMB8BASE-NEXT:    ldrex r0, [r3]
 ; CHECK-THUMB8BASE-NEXT:    cmp r0, r1
 ; CHECK-THUMB8BASE-NEXT:    bne .LBB25_4
 ; CHECK-THUMB8BASE-NEXT:  @ %bb.3: @ %atomicrmw.start
 ; CHECK-THUMB8BASE-NEXT:    @ in Loop: Header=BB25_2 Depth=2
 ; CHECK-THUMB8BASE-NEXT:    strex r2, r4, [r3]
-; CHECK-THUMB8BASE-NEXT:    cmp.w r2, #0
+; CHECK-THUMB8BASE-NEXT:    cmp r2, #0
 ; CHECK-THUMB8BASE-NEXT:    bne .LBB25_2
 ; CHECK-THUMB8BASE-NEXT:  .LBB25_4: @ %atomicrmw.start
 ; CHECK-THUMB8BASE-NEXT:    @ in Loop: Header=BB25_1 Depth=1
 ; CHECK-THUMB8BASE-NEXT:    str r0, [sp] @ 4-byte Spill
 ; CHECK-THUMB8BASE-NEXT:    subs r1, r0, r1
 ; CHECK-THUMB8BASE-NEXT:    rsbs r2, r1, #0
 ; CHECK-THUMB8BASE-NEXT:    adcs r1, r2
 ; CHECK-THUMB8BASE-NEXT:    cmp r1, #1

 ; CHECK-THUMB8BASE-NEXT:    @ Parent Loop BB26_1 Depth=1
 ; CHECK-THUMB8BASE-NEXT:    @ => This Inner Loop Header: Depth=2
 ; CHECK-THUMB8BASE-NEXT:    ldrex r0, [r3]
 ; CHECK-THUMB8BASE-NEXT:    cmp r0, r1
 ; CHECK-THUMB8BASE-NEXT:    bne .LBB26_4
 ; CHECK-THUMB8BASE-NEXT:  @ %bb.3: @ %atomicrmw.start
 ; CHECK-THUMB8BASE-NEXT:    @ in Loop: Header=BB26_2 Depth=2
 ; CHECK-THUMB8BASE-NEXT:    strex r2, r4, [r3]
-; CHECK-THUMB8BASE-NEXT:    cmp.w r2, #0
+; CHECK-THUMB8BASE-NEXT:    cmp r2, #0
 ; CHECK-THUMB8BASE-NEXT:    bne .LBB26_2
 ; CHECK-THUMB8BASE-NEXT:  .LBB26_4: @ %atomicrmw.start
 ; CHECK-THUMB8BASE-NEXT:    @ in Loop: Header=BB26_1 Depth=1
 ; CHECK-THUMB8BASE-NEXT:    str r0, [sp] @ 4-byte Spill
 ; CHECK-THUMB8BASE-NEXT:    subs r1, r0, r1
 ; CHECK-THUMB8BASE-NEXT:    rsbs r2, r1, #0
 ; CHECK-THUMB8BASE-NEXT:    adcs r1, r2
 ; CHECK-THUMB8BASE-NEXT:    cmp r1, #1

 ; CHECK-THUMB8BASE-NEXT:    @ Parent Loop BB27_1 Depth=1
 ; CHECK-THUMB8BASE-NEXT:    @ => This Inner Loop Header: Depth=2
 ; CHECK-THUMB8BASE-NEXT:    ldrex r0, [r3]
 ; CHECK-THUMB8BASE-NEXT:    cmp r0, r1
 ; CHECK-THUMB8BASE-NEXT:    bne .LBB27_4
 ; CHECK-THUMB8BASE-NEXT:  @ %bb.3: @ %atomicrmw.start
 ; CHECK-THUMB8BASE-NEXT:    @ in Loop: Header=BB27_2 Depth=2
 ; CHECK-THUMB8BASE-NEXT:    strex r2, r4, [r3]
-; CHECK-THUMB8BASE-NEXT:    cmp.w r2, #0
+; CHECK-THUMB8BASE-NEXT:    cmp r2, #0
 ; CHECK-THUMB8BASE-NEXT:    bne .LBB27_2
 ; CHECK-THUMB8BASE-NEXT:  .LBB27_4: @ %atomicrmw.start
 ; CHECK-THUMB8BASE-NEXT:    @ in Loop: Header=BB27_1 Depth=1
 ; CHECK-THUMB8BASE-NEXT:    str r0, [sp] @ 4-byte Spill
 ; CHECK-THUMB8BASE-NEXT:    subs r1, r0, r1
 ; CHECK-THUMB8BASE-NEXT:    rsbs r2, r1, #0
 ; CHECK-THUMB8BASE-NEXT:    adcs r1, r2
 ; CHECK-THUMB8BASE-NEXT:    cmp r1, #1

 ; CHECK-THUMB8BASE-NEXT:    @ Parent Loop BB28_1 Depth=1
 ; CHECK-THUMB8BASE-NEXT:    @ => This Inner Loop Header: Depth=2
 ; CHECK-THUMB8BASE-NEXT:    ldrex r0, [r3]
 ; CHECK-THUMB8BASE-NEXT:    cmp r0, r1
 ; CHECK-THUMB8BASE-NEXT:    bne .LBB28_4
 ; CHECK-THUMB8BASE-NEXT:  @ %bb.3: @ %atomicrmw.start
 ; CHECK-THUMB8BASE-NEXT:    @ in Loop: Header=BB28_2 Depth=2
 ; CHECK-THUMB8BASE-NEXT:    strex r2, r4, [r3]
-; CHECK-THUMB8BASE-NEXT:    cmp.w r2, #0
+; CHECK-THUMB8BASE-NEXT:    cmp r2, #0
 ; CHECK-THUMB8BASE-NEXT:    bne .LBB28_2
 ; CHECK-THUMB8BASE-NEXT:  .LBB28_4: @ %atomicrmw.start
 ; CHECK-THUMB8BASE-NEXT:    @ in Loop: Header=BB28_1 Depth=1
 ; CHECK-THUMB8BASE-NEXT:    str r0, [sp] @ 4-byte Spill
 ; CHECK-THUMB8BASE-NEXT:    subs r1, r0, r1
 ; CHECK-THUMB8BASE-NEXT:    rsbs r2, r1, #0
 ; CHECK-THUMB8BASE-NEXT:    adcs r1, r2
 ; CHECK-THUMB8BASE-NEXT:    cmp r1, #1

 ; CHECK-THUMB8BASE-NEXT:    @ Parent Loop BB29_1 Depth=1
 ; CHECK-THUMB8BASE-NEXT:    @ => This Inner Loop Header: Depth=2
 ; CHECK-THUMB8BASE-NEXT:    ldrex r0, [r3]
 ; CHECK-THUMB8BASE-NEXT:    cmp r0, r1
 ; CHECK-THUMB8BASE-NEXT:    bne .LBB29_6
 ; CHECK-THUMB8BASE-NEXT:  @ %bb.5: @ %atomicrmw.start
 ; CHECK-THUMB8BASE-NEXT:    @ in Loop: Header=BB29_4 Depth=2
 ; CHECK-THUMB8BASE-NEXT:    strex r2, r4, [r3]
-; CHECK-THUMB8BASE-NEXT:    cmp.w r2, #0
+; CHECK-THUMB8BASE-NEXT:    cmp r2, #0
 ; CHECK-THUMB8BASE-NEXT:    bne .LBB29_4
 ; CHECK-THUMB8BASE-NEXT:  .LBB29_6: @ %atomicrmw.start
 ; CHECK-THUMB8BASE-NEXT:    @ in Loop: Header=BB29_1 Depth=1
 ; CHECK-THUMB8BASE-NEXT:    str r0, [sp] @ 4-byte Spill
 ; CHECK-THUMB8BASE-NEXT:    subs r1, r0, r1
 ; CHECK-THUMB8BASE-NEXT:    rsbs r2, r1, #0
 ; CHECK-THUMB8BASE-NEXT:    adcs r1, r2
 ; CHECK-THUMB8BASE-NEXT:    cmp r1, #1

 ; CHECK-THUMB8BASE-NEXT:    @ Parent Loop BB30_1 Depth=1
 ; CHECK-THUMB8BASE-NEXT:    @ => This Inner Loop Header: Depth=2
 ; CHECK-THUMB8BASE-NEXT:    ldrex r0, [r3]
 ; CHECK-THUMB8BASE-NEXT:    cmp r0, r1
 ; CHECK-THUMB8BASE-NEXT:    bne .LBB30_6
 ; CHECK-THUMB8BASE-NEXT:  @ %bb.5: @ %atomicrmw.start
 ; CHECK-THUMB8BASE-NEXT:    @ in Loop: Header=BB30_4 Depth=2
 ; CHECK-THUMB8BASE-NEXT:    strex r2, r4, [r3]
-; CHECK-THUMB8BASE-NEXT:    cmp.w r2, #0
+; CHECK-THUMB8BASE-NEXT:    cmp r2, #0
 ; CHECK-THUMB8BASE-NEXT:    bne .LBB30_4
 ; CHECK-THUMB8BASE-NEXT:  .LBB30_6: @ %atomicrmw.start
 ; CHECK-THUMB8BASE-NEXT:    @ in Loop: Header=BB30_1 Depth=1
 ; CHECK-THUMB8BASE-NEXT:    str r0, [sp] @ 4-byte Spill
 ; CHECK-THUMB8BASE-NEXT:    subs r1, r0, r1
 ; CHECK-THUMB8BASE-NEXT:    rsbs r2, r1, #0
 ; CHECK-THUMB8BASE-NEXT:    adcs r1, r2
 ; CHECK-THUMB8BASE-NEXT:    cmp r1, #1

 ; CHECK-THUMB8BASE-NEXT:    @ Parent Loop BB31_1 Depth=1
 ; CHECK-THUMB8BASE-NEXT:    @ => This Inner Loop Header: Depth=2
 ; CHECK-THUMB8BASE-NEXT:    ldrex r0, [r3]
 ; CHECK-THUMB8BASE-NEXT:    cmp r0, r1
 ; CHECK-THUMB8BASE-NEXT:    bne .LBB31_6
 ; CHECK-THUMB8BASE-NEXT:  @ %bb.5: @ %atomicrmw.start
 ; CHECK-THUMB8BASE-NEXT:    @ in Loop: Header=BB31_4 Depth=2
 ; CHECK-THUMB8BASE-NEXT:    strex r2, r4, [r3]
-; CHECK-THUMB8BASE-NEXT:    cmp.w r2, #0
+; CHECK-THUMB8BASE-NEXT:    cmp r2, #0
 ; CHECK-THUMB8BASE-NEXT:    bne .LBB31_4
 ; CHECK-THUMB8BASE-NEXT:  .LBB31_6: @ %atomicrmw.start
 ; CHECK-THUMB8BASE-NEXT:    @ in Loop: Header=BB31_1 Depth=1
 ; CHECK-THUMB8BASE-NEXT:    str r0, [sp] @ 4-byte Spill
 ; CHECK-THUMB8BASE-NEXT:    subs r1, r0, r1
 ; CHECK-THUMB8BASE-NEXT:    rsbs r2, r1, #0
 ; CHECK-THUMB8BASE-NEXT:    adcs r1, r2
 ; CHECK-THUMB8BASE-NEXT:    cmp r1, #1

 ; CHECK-THUMB8BASE-NEXT:    @ Parent Loop BB32_1 Depth=1
 ; CHECK-THUMB8BASE-NEXT:    @ => This Inner Loop Header: Depth=2
 ; CHECK-THUMB8BASE-NEXT:    ldrex r0, [r3]
 ; CHECK-THUMB8BASE-NEXT:    cmp r0, r1
 ; CHECK-THUMB8BASE-NEXT:    bne .LBB32_6
 ; CHECK-THUMB8BASE-NEXT:  @ %bb.5: @ %atomicrmw.start
 ; CHECK-THUMB8BASE-NEXT:    @ in Loop: Header=BB32_4 Depth=2
 ; CHECK-THUMB8BASE-NEXT:    strex r2, r4, [r3]
-; CHECK-THUMB8BASE-NEXT:    cmp.w r2, #0
+; CHECK-THUMB8BASE-NEXT:    cmp r2, #0
 ; CHECK-THUMB8BASE-NEXT:    bne .LBB32_4
 ; CHECK-THUMB8BASE-NEXT:  .LBB32_6: @ %atomicrmw.start
 ; CHECK-THUMB8BASE-NEXT:    @ in Loop: Header=BB32_1 Depth=1
 ; CHECK-THUMB8BASE-NEXT:    str r0, [sp] @ 4-byte Spill
 ; CHECK-THUMB8BASE-NEXT:    subs r1, r0, r1
 ; CHECK-THUMB8BASE-NEXT:    rsbs r2, r1, #0
 ; CHECK-THUMB8BASE-NEXT:    adcs r1, r2
 ; CHECK-THUMB8BASE-NEXT:    cmp r1, #1

llvm/test/CodeGen/ARM/cmpxchg.mir

 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -o - %s -mtriple=armv7-unknown-linux-gnu -verify-machineinstrs -run-pass=arm-pseudo | FileCheck %s
-# RUN: llc -o - %s -mtriple=thumbv7-unknown-linux-gnu -verify-machineinstrs -run-pass=arm-pseudo | FileCheck %s --check-prefix=THUMB
 ---
 name: func
 tracksRegLiveness: true
 body: |
   bb.0:
     liveins: $r0_r1, $r4_r5, $r3, $lr
     ; CHECK-LABEL: name: func
     ; CHECK: successors: %bb.1(0x80000000)
bb.0:
     ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.3(0x40000000)
     ; CHECK-NEXT: liveins: $r4_r5, $r3
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: early-clobber $r2 = STREXD $r4_r5, $r3, 14 /* CC::al */, $noreg
     ; CHECK-NEXT: CMPri killed $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
     ; CHECK-NEXT: Bcc %bb.1, 1 /* CC::ne */, killed $cpsr
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: .3:
-    ; THUMB-LABEL: name: func
-    ; THUMB: successors: %bb.1(0x80000000)
-    ; THUMB-NEXT: liveins: $r0_r1, $r4_r5, $r3, $lr
-    ; THUMB-NEXT: {{  $}}
-    ; THUMB-NEXT: {{  $}}
-    ; THUMB-NEXT: .1:
-    ; THUMB-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
-    ; THUMB-NEXT: liveins: $r4, $r5, $r3
-    ; THUMB-NEXT: {{  $}}
-    ; THUMB-NEXT: $r0, $r1 = t2LDREXD $r3, 14 /* CC::al */, $noreg
-    ; THUMB-NEXT: tCMPhir killed $r0, $r4, 14 /* CC::al */, $noreg, implicit-def $cpsr
-    ; THUMB-NEXT: tCMPhir killed $r1, $r5, 0 /* CC::eq */, killed $cpsr, implicit-def $cpsr
-    ; THUMB-NEXT: tBcc %bb.3, 1 /* CC::ne */, killed $cpsr
-    ; THUMB-NEXT: {{  $}}
-    ; THUMB-NEXT: .2:
-    ; THUMB-NEXT: successors: %bb.1(0x40000000), %bb.3(0x40000000)
-    ; THUMB-NEXT: liveins: $r4, $r5, $r3
-    ; THUMB-NEXT: {{  $}}
-    ; THUMB-NEXT: early-clobber $r2 = t2STREXD $r4, $r5, $r3, 14 /* CC::al */, $noreg
-    ; THUMB-NEXT: t2CMPri killed $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
-    ; THUMB-NEXT: tBcc %bb.1, 1 /* CC::ne */, killed $cpsr
-    ; THUMB-NEXT: {{  $}}
-    ; THUMB-NEXT: .3:
     dead early-clobber renamable $r0_r1, dead early-clobber renamable $r2 = CMP_SWAP_64 killed renamable $r3, killed renamable $r4_r5, renamable $r4_r5 :: (volatile load store monotonic monotonic (s64))
 ...
 ---
 name: func2
 tracksRegLiveness: true
 body: |
   bb.0:
     liveins: $r1, $r2, $r3, $r12, $lr
bb.0:
     ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.3(0x40000000)
     ; CHECK-NEXT: liveins: $lr, $r3, $r12
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: early-clobber $r2 = STREX $lr, $r3, 14 /* CC::al */, $noreg
     ; CHECK-NEXT: CMPri killed $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
     ; CHECK-NEXT: Bcc %bb.1, 1 /* CC::ne */, killed $cpsr
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: .3:
-    ; THUMB-LABEL: name: func2
-    ; THUMB: successors: %bb.1(0x80000000)
-    ; THUMB-NEXT: liveins: $r1, $r2, $r3, $r12, $lr
-    ; THUMB-NEXT: {{  $}}
-    ; THUMB-NEXT: {{  $}}
-    ; THUMB-NEXT: .1:
-    ; THUMB-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
-    ; THUMB-NEXT: liveins: $lr, $r3, $r12
-    ; THUMB-NEXT: {{  $}}
-    ; THUMB-NEXT: $r1 = t2LDREX $r3, 0, 14 /* CC::al */, $noreg
-    ; THUMB-NEXT: tCMPhir killed $r1, $r12, 14 /* CC::al */, $noreg, implicit-def $cpsr
-    ; THUMB-NEXT: tBcc %bb.3, 1 /* CC::ne */, killed $cpsr
-    ; THUMB-NEXT: {{  $}}
-    ; THUMB-NEXT: .2:
-    ; THUMB-NEXT: successors: %bb.1(0x40000000), %bb.3(0x40000000)
-    ; THUMB-NEXT: liveins: $lr, $r3, $r12
-    ; THUMB-NEXT: {{  $}}
-    ; THUMB-NEXT: early-clobber $r2 = t2STREX $lr, $r3, 0, 14 /* CC::al */, $noreg
-    ; THUMB-NEXT: t2CMPri killed $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
-    ; THUMB-NEXT: tBcc %bb.1, 1 /* CC::ne */, killed $cpsr
-    ; THUMB-NEXT: {{  $}}
-    ; THUMB-NEXT: .3:
     dead early-clobber renamable $r1, dead early-clobber renamable $r2 = CMP_SWAP_32 killed renamable $r3, killed renamable $r12, killed renamable $lr
 ...

llvm/test/CodeGen/Thumb2/cmpxchg.mir

+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -o - %s -mtriple=thumbv7-unknown-linux-gnu -verify-machineinstrs -run-pass=arm-pseudo | FileCheck %s
+---
+name: func
+tracksRegLiveness: true
+body: |
+  bb.0:
+    liveins: $r0_r1, $r4_r5, $r3, $lr
+    ; CHECK-LABEL: name: func
+    ; CHECK: successors: %bb.1(0x80000000)
+    ; CHECK-NEXT: liveins: $r0_r1, $r4_r5, $r3, $lr
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: .1:
+    ; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
+    ; CHECK-NEXT: liveins: $r4, $r5, $r3
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: $r0, $r1 = t2LDREXD $r3, 14 /* CC::al */, $noreg
+    ; CHECK-NEXT: tCMPhir killed $r0, $r4, 14 /* CC::al */, $noreg, implicit-def $cpsr
+    ; CHECK-NEXT: tCMPhir killed $r1, $r5, 0 /* CC::eq */, killed $cpsr, implicit-def $cpsr
+    ; CHECK-NEXT: tBcc %bb.3, 1 /* CC::ne */, killed $cpsr
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: .2:
+    ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.3(0x40000000)
+    ; CHECK-NEXT: liveins: $r4, $r5, $r3
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: early-clobber $r2 = t2STREXD $r4, $r5, $r3, 14 /* CC::al */, $noreg
+    ; CHECK-NEXT: t2CMPri killed $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
+    ; CHECK-NEXT: tBcc %bb.1, 1 /* CC::ne */, killed $cpsr
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: .3:
+    dead early-clobber renamable $r0_r1, dead early-clobber renamable $r2 = CMP_SWAP_64 killed renamable $r3, killed renamable $r4_r5, renamable $r4_r5 :: (volatile load store monotonic monotonic (s64))
+...
+---
+name: func2
+tracksRegLiveness: true
+body: |
+  bb.0:
+    liveins: $r1, $r2, $r3, $r12, $lr
+    ; CHECK-LABEL: name: func2
+    ; CHECK: successors: %bb.1(0x80000000)
+    ; CHECK-NEXT: liveins: $r1, $r2, $r3, $r12, $lr
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: .1:
+    ; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
+    ; CHECK-NEXT: liveins: $lr, $r3, $r12
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: $r1 = t2LDREX $r3, 0, 14 /* CC::al */, $noreg
+    ; CHECK-NEXT: tCMPhir killed $r1, $r12, 14 /* CC::al */, $noreg, implicit-def $cpsr
+    ; CHECK-NEXT: tBcc %bb.3, 1 /* CC::ne */, killed $cpsr
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: .2:
+    ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.3(0x40000000)
+    ; CHECK-NEXT: liveins: $lr, $r3, $r12
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: early-clobber $r2 = t2STREX $lr, $r3, 0, 14 /* CC::al */, $noreg
+    ; CHECK-NEXT: t2CMPri killed $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
+    ; CHECK-NEXT: tBcc %bb.1, 1 /* CC::ne */, killed $cpsr
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: .3:
+    dead early-clobber renamable $r1, dead early-clobber renamable $r2 = tCMP_SWAP_32 killed renamable $r3, killed renamable $r12, killed renamable $lr
+...