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[AMDGPU] Update the mechanism used to check for cycles and add eges in power-sched mutation
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Authored by jrbyrnes on Jul 13 2022, 10:45 AM.

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Summary

Update the checking and adding of edges in power-sched dag mutation. Previously, the methods used the Preds and Succs of SUnits to determine whether or not adding an edge was feasible. An example issue of this is that the Preds and Succs vectors may not contain artificial edges added from previous DAG mutations. By using methods in the DAG to check for and add edges, we can be sure to not create cycles. Note: power-sched is now off by default in trunk, this patch is needed for cherry picking.

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Event Timeline

jrbyrnes created this revision.Jul 13 2022, 10:45 AM
Herald added a project: Restricted Project. · View Herald TranscriptJul 13 2022, 10:45 AM
jrbyrnes requested review of this revision.Jul 13 2022, 10:45 AM
Herald added a project: Restricted Project. · View Herald TranscriptJul 13 2022, 10:45 AM

Can you add a test with the bug?

jrbyrnes updated this revision to Diff 444452.Jul 13 2022, 4:41 PM

Include test which which minimally reproduces the SmallVector error reported.

kerbowa added inline comments.Jul 13 2022, 4:57 PM
llvm/test/CodeGen/AMDGPU/power-sched-no-cycle.mir
3

Remove debug-only lines and add enable-power-sched.

jrbyrnes updated this revision to Diff 444708.Jul 14 2022, 10:14 AM

Address review comments.

Additionally, add some quick checks to potentially avoid calls to DAG->canAddEdge() / handle edge case where ExitSU is treated as predecessor in DAG->canAddEdge()

arsenm accepted this revision.Jul 14 2022, 10:21 AM
This revision is now accepted and ready to land.Jul 14 2022, 10:21 AM