[greedyalloc] Return early when there is no register to allocate.

[LuoYuanke]

Summary

In X86 we split greddy register allocation into 2 passes. The 1st pass
is to allocate tile register, and the 2nd pass is to allocate the rest
of virtual register. In most cases there is no tile register, so the 1st
pass is unnecessary. To improve the compiling time, we check if there is
any register need to be allocated by invoking callback
ShouldAllocateClass. If there is no register to be allocated, just
return false in the pass. This would improve the 1st greed RA pass for
normal cases.

[LuoYuanke]

@nikic , could you help to check if this patch can fix the regression caused by D128584?

[nikic]

In D128804#3618589, @LuoYuanke wrote:

@nikic , could you help to check if this patch can fix the regression caused by D128584?

Yes, looks like it fixed the regression, or at least most of it: http://llvm-compile-time-tracker.com/compare.php?from=66a16b2848b434e937d658f15fc1849650f52185&to=67bc0ed77803965cf986e79674f16305e0c503b2&stat=instructions

[xiangzhangllvm]

llvm/lib/CodeGen/RegAllocGreedy.cpp

2536

The logic is no problem.
Do you mind move the code to a function (e.g. hasVirtRegAlloc() ) to make the RAGreedy::runOnMachineFunction clean ?

[LuoYuanke]

llvm/lib/CodeGen/RegAllocGreedy.cpp

2536

Sure, I'll update the patch.

[LuoYuanke]

Address Xiang's comments.

[xiangzhangllvm]

LGTM

llvm/lib/CodeGen/RegAllocGreedy.h

MCRegister selectOrSplitImpl(const LiveInterval &,
                                RecoloringStack &, unsigned = 0);
 
   bool LRE_CanEraseVirtReg(Register) override;
   void LRE_WillShrinkVirtReg(Register) override;
   void LRE_DidCloneVirtReg(Register, Register) override;
   void enqueue(PQueue &CurQueue, const LiveInterval *LI);
   const LiveInterval *dequeue(PQueue &CurQueue);
 
+  bool hasVirtRegAlloc();
   BlockFrequency calcSpillCost();
   bool addSplitConstraints(InterferenceCache::Cursor, BlockFrequency &);
   bool addThroughConstraints(InterferenceCache::Cursor, ArrayRef<unsigned>);
   bool growRegion(GlobalSplitCandidate &Cand);
   BlockFrequency calcGlobalSplitCost(GlobalSplitCandidate &,
                                      const AllocationOrder &Order);
   bool calcCompactRegion(GlobalSplitCandidate &);
   void splitAroundRegion(LiveRangeEdit &, ArrayRef<unsigned>);

llvm/lib/CodeGen/RegAllocGreedy.cpp

ORE->emit([&]() {
                                         &MF->front());
       Stats.report(R);
       R << "generated in function";
       return R;
     });
   }
 }
 
+bool RAGreedy::hasVirtRegAlloc() {
+  for (unsigned I = 0, E = MRI->getNumVirtRegs(); I != E; ++I) {
+    Register Reg = Register::index2VirtReg(I);
+    if (MRI->reg_nodbg_empty(Reg))
+      continue;
+    const TargetRegisterClass *RC = MRI->getRegClass(Reg);
+    if (!RC)
+      continue;
+    if (ShouldAllocateClass(*TRI, *RC))
+      return true;
+  }
+
+  return false;
+}
+
 bool RAGreedy::runOnMachineFunction(MachineFunction &mf) {
   LLVM_DEBUG(dbgs() << "********** GREEDY REGISTER ALLOCATION **********\n"
                     << "********** Function: " << mf.getName() << '\n');
 
   MF = &mf;
   TII = MF->getSubtarget().getInstrInfo();
 
   if (VerifyEnabled)
     MF->verify(this, "Before greedy register allocator");
 
   RegAllocBase::init(getAnalysis<VirtRegMap>(),
                      getAnalysis<LiveIntervals>(),
                      getAnalysis<LiveRegMatrix>());
+
+  // Early return if there is no virtual register to be allocated to a
+  // physical register.
+  if (!hasVirtRegAlloc())
+    return false;
+
   Indexes = &getAnalysis<SlotIndexes>();
   MBFI = &getAnalysis<MachineBlockFrequencyInfo>();
   DomTree = &getAnalysis<MachineDominatorTree>();
   ORE = &getAnalysis<MachineOptimizationRemarkEmitterPass>().getORE();
   Loops = &getAnalysis<MachineLoopInfo>();
   Bundles = &getAnalysis<EdgeBundles>();
   SpillPlacer = &getAnalysis<SpillPlacement>();
   DebugVars = &getAnalysis<LiveDebugVariables>();
   AA = &getAnalysis<AAResultsWrapperPass>().getAAResults();
 
   initializeCSRCost();
 
   RegCosts = TRI->getRegisterCosts(*MF);
   RegClassPriorityTrumpsGlobalness =
       GreedyRegClassPriorityTrumpsGlobalness.getNumOccurrences()
           ? GreedyRegClassPriorityTrumpsGlobalness
           : TRI->regClassPriorityTrumpsGlobalness(*MF);
 
   ExtraInfo.emplace();
   EvictAdvisor =