[AMDGPU] Use GFX11 S_PACK_HL instruction in more cases

[foad]

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-build-vector-trunc.v2s16.mir

3

@Joe_Nash mentioned offline that it might be better to pre-commit all the added RUN lines.

[Joe_Nash]

llvm/lib/Target/AMDGPU/SIInstrInfo.cpp

7090

I don't think there is any test coverage for this block.

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-build-vector-trunc.v2s16.mir

3

I think the codegen changes are reviewable by comparing with the gfx10 checks. The main reason to pre-commit tests would be separating NFC from this this change. Up to you.

[arsenm]

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-build-vector-trunc.v2s16.mir

14–16

These should be regenerated to include-NEXT first

[foad]

Rebase.

llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp

bool AMDGPUInstructionSelector::selectG_BUILD_VECTOR_TRUNC(
   Register ShiftSrc0;
   Register ShiftSrc1;
 
   // With multiple uses of the shift, this will duplicate the shift and
   // increase register pressure.
   //
   // (build_vector_trunc (lshr_oneuse $src0, 16), (lshr_oneuse $src1, 16)
   //  => (S_PACK_HH_B32_B16 $src0, $src1)
+  // (build_vector_trunc (lshr_oneuse SReg_32:$src0, 16), $src1)
+  //  => (S_PACK_HL_B32_B16 $src0, $src1)
   // (build_vector_trunc $src0, (lshr_oneuse SReg_32:$src1, 16))
   //  => (S_PACK_LH_B32_B16 $src0, $src1)
   // (build_vector_trunc $src0, $src1)
   //  => (S_PACK_LL_B32_B16 $src0, $src1)
 
   bool Shift0 = mi_match(
       Src0, *MRI, m_OneUse(m_GLShr(m_Reg(ShiftSrc0), m_SpecificICst(16))));
 
   bool Shift1 = mi_match(
       Src1, *MRI, m_OneUse(m_GLShr(m_Reg(ShiftSrc1), m_SpecificICst(16))));
 
   unsigned Opc = AMDGPU::S_PACK_LL_B32_B16;
   if (Shift0 && Shift1) {
     Opc = AMDGPU::S_PACK_HH_B32_B16;
     MI.getOperand(1).setReg(ShiftSrc0);
     MI.getOperand(2).setReg(ShiftSrc1);
   } else if (Shift1) {
     Opc = AMDGPU::S_PACK_LH_B32_B16;
     MI.getOperand(2).setReg(ShiftSrc1);
-  } else if (Shift0 && ConstSrc1 && ConstSrc1->Value == 0) {
+  } else if (Shift0) {
+    if (ConstSrc1 && ConstSrc1->Value == 0) {
       // build_vector_trunc (lshr $src0, 16), 0 -> s_lshr_b32 $src0, 16
       auto MIB = BuildMI(*BB, &MI, DL, TII.get(AMDGPU::S_LSHR_B32), Dst)
                      .addReg(ShiftSrc0)
                      .addImm(16);
 
       MI.eraseFromParent();
       return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI);
     }
+    if (STI.hasSPackHL()) {
+      Opc = AMDGPU::S_PACK_HL_B32_B16;
+      MI.getOperand(1).setReg(ShiftSrc0);
+    }
+  }
 
   MI.setDesc(TII.get(Opc));
   return constrainSelectedInstRegOperands(MI, TII, TRI, RBI);
 }
 
 bool AMDGPUInstructionSelector::selectG_PTR_ADD(MachineInstr &I) const {
   return selectG_ADD_SUB(I);
 }

llvm/lib/Target/AMDGPU/SIInstrInfo.cpp

case AMDGPU::S_CBRANCH_SCC1: {
       break;
 
     case AMDGPU::S_BFE_U64:
     case AMDGPU::S_BFM_B64:
       llvm_unreachable("Moving this op to VALU not implemented");
 
     case AMDGPU::S_PACK_LL_B32_B16:
     case AMDGPU::S_PACK_LH_B32_B16:
+    case AMDGPU::S_PACK_HL_B32_B16:
     case AMDGPU::S_PACK_HH_B32_B16:
       movePackToVALU(Worklist, MRI, Inst);
       Inst.eraseFromParent();
       continue;
 
     case AMDGPU::S_XNOR_B32:
       lowerScalarXnor(Worklist, Inst);
       Inst.eraseFromParent();
case AMDGPU::S_PACK_LH_B32_B16: {
     BuildMI(*MBB, Inst, DL, get(AMDGPU::V_MOV_B32_e32), ImmReg)
       .addImm(0xffff);
     BuildMI(*MBB, Inst, DL, get(AMDGPU::V_BFI_B32_e64), ResultReg)
       .addReg(ImmReg, RegState::Kill)
       .add(Src0)
       .add(Src1);
     break;
   }
+  case AMDGPU::S_PACK_HL_B32_B16: {
+    Register TmpReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
+    BuildMI(*MBB, Inst, DL, get(AMDGPU::V_LSHRREV_B32_e64), TmpReg)
+        .addImm(16)
+        .add(Src0);
+    BuildMI(*MBB, Inst, DL, get(AMDGPU::V_LSHL_OR_B32_e64), ResultReg)
+        .add(Src1)
+        .addImm(16)
+        .addReg(TmpReg, RegState::Kill);
+    break;
+  }
   case AMDGPU::S_PACK_HH_B32_B16: {
     Register ImmReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
     Register TmpReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
     BuildMI(*MBB, Inst, DL, get(AMDGPU::V_LSHRREV_B32_e64), TmpReg)
       .addImm(16)
       .add(Src0);
     BuildMI(*MBB, Inst, DL, get(AMDGPU::V_MOV_B32_e32), ImmReg)
       .addImm(0xffff0000);

llvm/lib/Target/AMDGPU/SIInstructions.td

 
 def : GCNPat <
   (v2f16 (is_canonicalized<build_vector> (f16 (VOP3Mods (f16 VGPR_32:$src0), i32:$src0_mods)),
                                          (f16 (VOP3Mods (f16 VGPR_32:$src1), i32:$src1_mods)))),
   (V_PACK_B32_F16_e64 $src0_mods, VGPR_32:$src0, $src1_mods, VGPR_32:$src1)
 >;
 } // End SubtargetPredicate = HasVOP3PInsts
 
+// With multiple uses of the shift, this will duplicate the shift and
+// increase register pressure.
+let SubtargetPredicate = isGFX11Plus in
+def : GCNPat <
+  (v2i16 (build_vector (i16 (trunc (srl_oneuse SReg_32:$src0, (i32 16)))), (i16 SReg_32:$src1))),
+  (v2i16 (S_PACK_HL_B32_B16 SReg_32:$src0, SReg_32:$src1))
+>;
+
+
 def : GCNPat <
   (v2f16 (scalar_to_vector f16:$src0)),
   (COPY $src0)
 >;
 
 def : GCNPat <
   (v2i16 (scalar_to_vector i16:$src0)),
   (COPY $src0)

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-build-vector-trunc.v2s16.mir

 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs  -o - %s | FileCheck -check-prefix=GFX9  %s
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefixes=GFX9PLUS,GFX9 %s
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1100 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefixes=GFX9PLUS,GFX11 %s
 
 ---
 name: test_build_vector_trunc_s_v2s16_s_s32_s_s32
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 
 body: |
   bb.0:
     liveins: $sgpr0, $sgpr1
 
-    ; GFX9-LABEL: name: test_build_vector_trunc_s_v2s16_s_s32_s_s32
-    ; GFX9: liveins: $sgpr0, $sgpr1
-    ; GFX9-NEXT: {{  $}}
-    ; GFX9-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
-    ; GFX9-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
-    ; GFX9-NEXT: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[COPY]], [[COPY1]]
-    ; GFX9-NEXT: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]]
+    ; GFX9PLUS-LABEL: name: test_build_vector_trunc_s_v2s16_s_s32_s_s32
+    ; GFX9PLUS: liveins: $sgpr0, $sgpr1
+    ; GFX9PLUS-NEXT: {{  $}}
+    ; GFX9PLUS-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+    ; GFX9PLUS-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
+    ; GFX9PLUS-NEXT: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[COPY]], [[COPY1]]
+    ; GFX9PLUS-NEXT: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]]
     %0:sgpr(s32) = COPY $sgpr0
     %1:sgpr(s32) = COPY $sgpr1
     %2:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %0, %1
     S_ENDPGM 0, implicit %2
 ...
 
 ---
 name: test_build_vector_trunc_s_pack_lh
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 
 body: |
   bb.0:
     liveins: $sgpr0, $sgpr1
 
-    ; GFX9-LABEL: name: test_build_vector_trunc_s_pack_lh
-    ; GFX9: liveins: $sgpr0, $sgpr1
-    ; GFX9-NEXT: {{  $}}
-    ; GFX9-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
-    ; GFX9-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
-    ; GFX9-NEXT: [[S_PACK_LH_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LH_B32_B16 [[COPY]], [[COPY1]]
-    ; GFX9-NEXT: S_ENDPGM 0, implicit [[S_PACK_LH_B32_B16_]]
+    ; GFX9PLUS-LABEL: name: test_build_vector_trunc_s_pack_lh
+    ; GFX9PLUS: liveins: $sgpr0, $sgpr1
+    ; GFX9PLUS-NEXT: {{  $}}
+    ; GFX9PLUS-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+    ; GFX9PLUS-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
+    ; GFX9PLUS-NEXT: [[S_PACK_LH_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LH_B32_B16 [[COPY]], [[COPY1]]
+    ; GFX9PLUS-NEXT: S_ENDPGM 0, implicit [[S_PACK_LH_B32_B16_]]
     %0:sgpr(s32) = COPY $sgpr0
     %1:sgpr(s32) = COPY $sgpr1
     %2:sgpr(s32) = G_CONSTANT i32 16
     %3:sgpr(s32) = G_LSHR %1, %2
     %4:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %0, %3
     S_ENDPGM 0, implicit %4
 ...
 
-# There is no s_pack_hl_b32
+# s_pack_hl_b32 was introduced in GFX11
 ---
-name: test_build_vector_trunc_s_pack_lh_swapped
+name: test_build_vector_trunc_s_pack_hl
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 
 body: |
   bb.0:
     liveins: $sgpr0, $sgpr1
 
-    ; GFX9-LABEL: name: test_build_vector_trunc_s_pack_lh_swapped
+    ; GFX9-LABEL: name: test_build_vector_trunc_s_pack_hl
     ; GFX9: liveins: $sgpr0, $sgpr1
     ; GFX9-NEXT: {{  $}}
     ; GFX9-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
     ; GFX9-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
     ; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 16
     ; GFX9-NEXT: [[S_LSHR_B32_:%[0-9]+]]:sreg_32 = S_LSHR_B32 [[COPY1]], [[S_MOV_B32_]], implicit-def $scc
     ; GFX9-NEXT: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[S_LSHR_B32_]], [[COPY]]
     ; GFX9-NEXT: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]]
+    ; GFX11-LABEL: name: test_build_vector_trunc_s_pack_hl
+    ; GFX11: liveins: $sgpr0, $sgpr1
+    ; GFX11-NEXT: {{  $}}
+    ; GFX11-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+    ; GFX11-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
+    ; GFX11-NEXT: [[S_PACK_HL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_HL_B32_B16 [[COPY1]], [[COPY]]
+    ; GFX11-NEXT: S_ENDPGM 0, implicit [[S_PACK_HL_B32_B16_]]
     %0:sgpr(s32) = COPY $sgpr0
     %1:sgpr(s32) = COPY $sgpr1
     %2:sgpr(s32) = G_CONSTANT i32 16
     %3:sgpr(s32) = G_LSHR %1, %2
     %4:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %3, %0
     S_ENDPGM 0, implicit %4
 ...
 
 ---
 name: test_build_vector_trunc_s_pack_hh
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 
 body: |
   bb.0:
     liveins: $sgpr0, $sgpr1
 
-    ; GFX9-LABEL: name: test_build_vector_trunc_s_pack_hh
-    ; GFX9: liveins: $sgpr0, $sgpr1
-    ; GFX9-NEXT: {{  $}}
-    ; GFX9-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
-    ; GFX9-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
-    ; GFX9-NEXT: [[S_PACK_HH_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_HH_B32_B16 [[COPY]], [[COPY1]]
-    ; GFX9-NEXT: S_ENDPGM 0, implicit [[S_PACK_HH_B32_B16_]]
+    ; GFX9PLUS-LABEL: name: test_build_vector_trunc_s_pack_hh
+    ; GFX9PLUS: liveins: $sgpr0, $sgpr1
+    ; GFX9PLUS-NEXT: {{  $}}
+    ; GFX9PLUS-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+    ; GFX9PLUS-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
+    ; GFX9PLUS-NEXT: [[S_PACK_HH_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_HH_B32_B16 [[COPY]], [[COPY1]]
+    ; GFX9PLUS-NEXT: S_ENDPGM 0, implicit [[S_PACK_HH_B32_B16_]]
     %0:sgpr(s32) = COPY $sgpr0
     %1:sgpr(s32) = COPY $sgpr1
     %2:sgpr(s32) = G_CONSTANT i32 16
     %3:sgpr(s32) = G_LSHR %0, %2
     %4:sgpr(s32) = G_LSHR %1, %2
     %5:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %3, %4
     S_ENDPGM 0, implicit %5
 ...
 
 # TODO: Should this use an and instead?
 ---
 name: test_build_vector_trunc_s_v2s16_s_s32_s_0_s32
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 
 body: |
   bb.0:
     liveins: $sgpr0
 
-    ; GFX9-LABEL: name: test_build_vector_trunc_s_v2s16_s_s32_s_0_s32
-    ; GFX9: liveins: $sgpr0
-    ; GFX9-NEXT: {{  $}}
-    ; GFX9-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
-    ; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
-    ; GFX9-NEXT: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[COPY]], [[S_MOV_B32_]]
-    ; GFX9-NEXT: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]]
+    ; GFX9PLUS-LABEL: name: test_build_vector_trunc_s_v2s16_s_s32_s_0_s32
+    ; GFX9PLUS: liveins: $sgpr0
+    ; GFX9PLUS-NEXT: {{  $}}
+    ; GFX9PLUS-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+    ; GFX9PLUS-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
+    ; GFX9PLUS-NEXT: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[COPY]], [[S_MOV_B32_]]
+    ; GFX9PLUS-NEXT: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]]
     %0:sgpr(s32) = COPY $sgpr0
     %1:sgpr(s32) = G_CONSTANT i32 0
     %2:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %0, %1
     S_ENDPGM 0, implicit %2
 ...
 
 ---
 name: test_build_vector_trunc_s_v2s16_s_0_s32_s_s32
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 
 body: |
   bb.0:
     liveins: $sgpr0
 
-    ; GFX9-LABEL: name: test_build_vector_trunc_s_v2s16_s_0_s32_s_s32
-    ; GFX9: liveins: $sgpr0
-    ; GFX9-NEXT: {{  $}}
-    ; GFX9-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
-    ; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
-    ; GFX9-NEXT: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[S_MOV_B32_]], [[COPY]]
-    ; GFX9-NEXT: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]]
+    ; GFX9PLUS-LABEL: name: test_build_vector_trunc_s_v2s16_s_0_s32_s_s32
+    ; GFX9PLUS: liveins: $sgpr0
+    ; GFX9PLUS-NEXT: {{  $}}
+    ; GFX9PLUS-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+    ; GFX9PLUS-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
+    ; GFX9PLUS-NEXT: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[S_MOV_B32_]], [[COPY]]
+    ; GFX9PLUS-NEXT: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]]
     %0:sgpr(s32) = COPY $sgpr0
     %1:sgpr(s32) = G_CONSTANT i32 0
     %2:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %1, %0
     S_ENDPGM 0, implicit %2
 ...
 
 ---
 name: test_build_vector_trunc_s_v2s16_s_s32_s_undef_s32
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 
 body: |
   bb.0:
     liveins: $sgpr0
 
-    ; GFX9-LABEL: name: test_build_vector_trunc_s_v2s16_s_s32_s_undef_s32
-    ; GFX9: liveins: $sgpr0
-    ; GFX9-NEXT: {{  $}}
-    ; GFX9-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
-    ; GFX9-NEXT: S_ENDPGM 0, implicit [[COPY]]
+    ; GFX9PLUS-LABEL: name: test_build_vector_trunc_s_v2s16_s_s32_s_undef_s32
+    ; GFX9PLUS: liveins: $sgpr0
+    ; GFX9PLUS-NEXT: {{  $}}
+    ; GFX9PLUS-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+    ; GFX9PLUS-NEXT: S_ENDPGM 0, implicit [[COPY]]
     %0:sgpr(s32) = COPY $sgpr0
     %1:sgpr(s32) = G_IMPLICIT_DEF
     %2:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %0, %1
     S_ENDPGM 0, implicit %2
 ...
 
 ---
 name: test_build_vector_trunc_s_v2s16_s_undef_s32_s_s32
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 
 body: |
   bb.0:
     liveins: $sgpr0
 
-    ; GFX9-LABEL: name: test_build_vector_trunc_s_v2s16_s_undef_s32_s_s32
-    ; GFX9: liveins: $sgpr0
-    ; GFX9-NEXT: {{  $}}
-    ; GFX9-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
-    ; GFX9-NEXT: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
-    ; GFX9-NEXT: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[DEF]], [[COPY]]
-    ; GFX9-NEXT: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]]
+    ; GFX9PLUS-LABEL: name: test_build_vector_trunc_s_v2s16_s_undef_s32_s_s32
+    ; GFX9PLUS: liveins: $sgpr0
+    ; GFX9PLUS-NEXT: {{  $}}
+    ; GFX9PLUS-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+    ; GFX9PLUS-NEXT: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
+    ; GFX9PLUS-NEXT: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[DEF]], [[COPY]]
+    ; GFX9PLUS-NEXT: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]]
     %0:sgpr(s32) = COPY $sgpr0
     %1:sgpr(s32) = G_IMPLICIT_DEF
     %2:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %1, %0
     S_ENDPGM 0, implicit %2
 ...
 
 ---
 name: test_build_vector_trunc_s_v2s16_s_undef_s_s32
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 
 body: |
   bb.0:
     liveins: $sgpr1
 
-    ; GFX9-LABEL: name: test_build_vector_trunc_s_v2s16_s_undef_s_s32
-    ; GFX9: liveins: $sgpr1
-    ; GFX9-NEXT: {{  $}}
-    ; GFX9-NEXT: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
-    ; GFX9-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr1
-    ; GFX9-NEXT: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[DEF]], [[COPY]]
-    ; GFX9-NEXT: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]]
+    ; GFX9PLUS-LABEL: name: test_build_vector_trunc_s_v2s16_s_undef_s_s32
+    ; GFX9PLUS: liveins: $sgpr1
+    ; GFX9PLUS-NEXT: {{  $}}
+    ; GFX9PLUS-NEXT: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
+    ; GFX9PLUS-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr1
+    ; GFX9PLUS-NEXT: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[DEF]], [[COPY]]
+    ; GFX9PLUS-NEXT: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]]
     %0:sgpr(s32) = G_IMPLICIT_DEF
     %1:sgpr(s32) = COPY $sgpr1
     %2:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %0, %1
     S_ENDPGM 0, implicit %2
 ...
 
 ---
 name: test_build_vector_trunc_s_v2s16_s_s32_undef
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 
 body: |
   bb.0:
     liveins: $sgpr0
 
-    ; GFX9-LABEL: name: test_build_vector_trunc_s_v2s16_s_s32_undef
-    ; GFX9: liveins: $sgpr0
-    ; GFX9-NEXT: {{  $}}
-    ; GFX9-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
-    ; GFX9-NEXT: S_ENDPGM 0, implicit [[COPY]]
+    ; GFX9PLUS-LABEL: name: test_build_vector_trunc_s_v2s16_s_s32_undef
+    ; GFX9PLUS: liveins: $sgpr0
+    ; GFX9PLUS-NEXT: {{  $}}
+    ; GFX9PLUS-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+    ; GFX9PLUS-NEXT: S_ENDPGM 0, implicit [[COPY]]
     %0:sgpr(s32) = COPY $sgpr0
     %1:sgpr(s32) = G_IMPLICIT_DEF
     %2:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %0, %1
     S_ENDPGM 0, implicit %2
 ...
 
 ---
 name: test_build_vector_trunc_s_v2s16_s_zero_s_s32
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 
 body: |
   bb.0:
     liveins: $sgpr1
 
-    ; GFX9-LABEL: name: test_build_vector_trunc_s_v2s16_s_zero_s_s32
-    ; GFX9: liveins: $sgpr1
-    ; GFX9-NEXT: {{  $}}
-    ; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
-    ; GFX9-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr1
-    ; GFX9-NEXT: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[S_MOV_B32_]], [[COPY]]
-    ; GFX9-NEXT: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]]
+    ; GFX9PLUS-LABEL: name: test_build_vector_trunc_s_v2s16_s_zero_s_s32
+    ; GFX9PLUS: liveins: $sgpr1
+    ; GFX9PLUS-NEXT: {{  $}}
+    ; GFX9PLUS-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
+    ; GFX9PLUS-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr1
+    ; GFX9PLUS-NEXT: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[S_MOV_B32_]], [[COPY]]
+    ; GFX9PLUS-NEXT: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]]
     %0:sgpr(s32) = G_CONSTANT i32 0
     %1:sgpr(s32) = COPY $sgpr1
     %2:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %0, %1
     S_ENDPGM 0, implicit %2
 ...
 
 ---
 name: test_build_vector_trunc_s_v2s16_s_s32_zero
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 
 body: |
   bb.0:
     liveins: $sgpr0
 
-    ; GFX9-LABEL: name: test_build_vector_trunc_s_v2s16_s_s32_zero
-    ; GFX9: liveins: $sgpr0
-    ; GFX9-NEXT: {{  $}}
-    ; GFX9-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
-    ; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
-    ; GFX9-NEXT: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[COPY]], [[S_MOV_B32_]]
-    ; GFX9-NEXT: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]]
+    ; GFX9PLUS-LABEL: name: test_build_vector_trunc_s_v2s16_s_s32_zero
+    ; GFX9PLUS: liveins: $sgpr0
+    ; GFX9PLUS-NEXT: {{  $}}
+    ; GFX9PLUS-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+    ; GFX9PLUS-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
+    ; GFX9PLUS-NEXT: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[COPY]], [[S_MOV_B32_]]
+    ; GFX9PLUS-NEXT: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]]
     %0:sgpr(s32) = COPY $sgpr0
     %1:sgpr(s32) = G_CONSTANT i32 0
     %2:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %0, %1
     S_ENDPGM 0, implicit %2
 ...
 
 ---
 name: test_build_vector_trunc_lshr16_zero
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 
 body: |
   bb.0:
     liveins: $sgpr0
 
-    ; GFX9-LABEL: name: test_build_vector_trunc_lshr16_zero
-    ; GFX9: liveins: $sgpr0
-    ; GFX9-NEXT: {{  $}}
-    ; GFX9-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
-    ; GFX9-NEXT: [[S_LSHR_B32_:%[0-9]+]]:sreg_32 = S_LSHR_B32 [[COPY]], 16, implicit-def $scc
-    ; GFX9-NEXT: S_ENDPGM 0, implicit [[S_LSHR_B32_]]
+    ; GFX9PLUS-LABEL: name: test_build_vector_trunc_lshr16_zero
+    ; GFX9PLUS: liveins: $sgpr0
+    ; GFX9PLUS-NEXT: {{  $}}
+    ; GFX9PLUS-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+    ; GFX9PLUS-NEXT: [[S_LSHR_B32_:%[0-9]+]]:sreg_32 = S_LSHR_B32 [[COPY]], 16, implicit-def $scc
+    ; GFX9PLUS-NEXT: S_ENDPGM 0, implicit [[S_LSHR_B32_]]
     %0:sgpr(s32) = G_CONSTANT i32 0
     %1:sgpr(s32) = COPY $sgpr0
     %2:sgpr(s32) = G_CONSTANT i32 16
     %3:sgpr(s32) = G_LSHR %1, %2
     %4:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %3, %0
     S_ENDPGM 0, implicit %4
 ...
 
 # Don't use pack since it would duplicate the shift use
 ---
 name: test_build_vector_trunc_s_pack_lh_multi_use
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 
 body: |
   bb.0:
     liveins: $sgpr0, $sgpr1
 
-    ; GFX9-LABEL: name: test_build_vector_trunc_s_pack_lh_multi_use
-    ; GFX9: liveins: $sgpr0, $sgpr1
-    ; GFX9-NEXT: {{  $}}
-    ; GFX9-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
-    ; GFX9-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
-    ; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 16
-    ; GFX9-NEXT: [[S_LSHR_B32_:%[0-9]+]]:sreg_32 = S_LSHR_B32 [[COPY1]], [[S_MOV_B32_]], implicit-def $scc
-    ; GFX9-NEXT: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[COPY]], [[S_LSHR_B32_]]
-    ; GFX9-NEXT: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]], implicit [[S_LSHR_B32_]]
+    ; GFX9PLUS-LABEL: name: test_build_vector_trunc_s_pack_lh_multi_use
+    ; GFX9PLUS: liveins: $sgpr0, $sgpr1
+    ; GFX9PLUS-NEXT: {{  $}}
+    ; GFX9PLUS-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+    ; GFX9PLUS-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
+    ; GFX9PLUS-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 16
+    ; GFX9PLUS-NEXT: [[S_LSHR_B32_:%[0-9]+]]:sreg_32 = S_LSHR_B32 [[COPY1]], [[S_MOV_B32_]], implicit-def $scc
+    ; GFX9PLUS-NEXT: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[COPY]], [[S_LSHR_B32_]]
+    ; GFX9PLUS-NEXT: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]], implicit [[S_LSHR_B32_]]
     %0:sgpr(s32) = COPY $sgpr0
     %1:sgpr(s32) = COPY $sgpr1
     %2:sgpr(s32) = G_CONSTANT i32 16
     %3:sgpr(s32) = G_LSHR %1, %2
     %4:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %0, %3
     S_ENDPGM 0, implicit %4, implicit %3
 ...
 
 ---
 name: test_build_vector_trunc_s_pack_hh_multi_use_lhs
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 
 body: |
   bb.0:
     liveins: $sgpr0, $sgpr1
 
-    ; GFX9-LABEL: name: test_build_vector_trunc_s_pack_hh_multi_use_lhs
-    ; GFX9: liveins: $sgpr0, $sgpr1
-    ; GFX9-NEXT: {{  $}}
-    ; GFX9-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
-    ; GFX9-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
-    ; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 16
-    ; GFX9-NEXT: [[S_LSHR_B32_:%[0-9]+]]:sreg_32 = S_LSHR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
-    ; GFX9-NEXT: [[S_PACK_LH_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LH_B32_B16 [[S_LSHR_B32_]], [[COPY1]]
-    ; GFX9-NEXT: S_ENDPGM 0, implicit [[S_PACK_LH_B32_B16_]], implicit [[S_LSHR_B32_]]
+    ; GFX9PLUS-LABEL: name: test_build_vector_trunc_s_pack_hh_multi_use_lhs
+    ; GFX9PLUS: liveins: $sgpr0, $sgpr1
+    ; GFX9PLUS-NEXT: {{  $}}
+    ; GFX9PLUS-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+    ; GFX9PLUS-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
+    ; GFX9PLUS-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 16
+    ; GFX9PLUS-NEXT: [[S_LSHR_B32_:%[0-9]+]]:sreg_32 = S_LSHR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
+    ; GFX9PLUS-NEXT: [[S_PACK_LH_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LH_B32_B16 [[S_LSHR_B32_]], [[COPY1]]
+    ; GFX9PLUS-NEXT: S_ENDPGM 0, implicit [[S_PACK_LH_B32_B16_]], implicit [[S_LSHR_B32_]]
     %0:sgpr(s32) = COPY $sgpr0
     %1:sgpr(s32) = COPY $sgpr1
     %2:sgpr(s32) = G_CONSTANT i32 16
     %3:sgpr(s32) = G_LSHR %0, %2
     %4:sgpr(s32) = G_LSHR %1, %2
     %5:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %3, %4
     S_ENDPGM 0, implicit %5, implicit %3
 ...
bb.0:
     ; GFX9-NEXT: {{  $}}
     ; GFX9-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
     ; GFX9-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
     ; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 16
     ; GFX9-NEXT: [[S_LSHR_B32_:%[0-9]+]]:sreg_32 = S_LSHR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
     ; GFX9-NEXT: [[S_LSHR_B32_1:%[0-9]+]]:sreg_32 = S_LSHR_B32 [[COPY1]], [[S_MOV_B32_]], implicit-def $scc
     ; GFX9-NEXT: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[S_LSHR_B32_]], [[S_LSHR_B32_1]]
     ; GFX9-NEXT: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]], implicit [[S_LSHR_B32_1]]
+    ; GFX11-LABEL: name: test_build_vector_trunc_s_pack_hh_multi_use_rhs
+    ; GFX11: liveins: $sgpr0, $sgpr1
+    ; GFX11-NEXT: {{  $}}
+    ; GFX11-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+    ; GFX11-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
+    ; GFX11-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 16
+    ; GFX11-NEXT: [[S_LSHR_B32_:%[0-9]+]]:sreg_32 = S_LSHR_B32 [[COPY1]], [[S_MOV_B32_]], implicit-def $scc
+    ; GFX11-NEXT: [[S_PACK_HL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_HL_B32_B16 [[COPY]], [[S_LSHR_B32_]]
+    ; GFX11-NEXT: S_ENDPGM 0, implicit [[S_PACK_HL_B32_B16_]], implicit [[S_LSHR_B32_]]
     %0:sgpr(s32) = COPY $sgpr0
     %1:sgpr(s32) = COPY $sgpr1
     %2:sgpr(s32) = G_CONSTANT i32 16
     %3:sgpr(s32) = G_LSHR %0, %2
     %4:sgpr(s32) = G_LSHR %1, %2
     %5:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %3, %4
     S_ENDPGM 0, implicit %5, implicit %4
 ...
 
 ---
 name: test_build_vector_trunc_s_pack_lh_wrong_shift_amt
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 
 body: |
   bb.0:
     liveins: $sgpr0, $sgpr1
 
-    ; GFX9-LABEL: name: test_build_vector_trunc_s_pack_lh_wrong_shift_amt
-    ; GFX9: liveins: $sgpr0, $sgpr1
-    ; GFX9-NEXT: {{  $}}
-    ; GFX9-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
-    ; GFX9-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
-    ; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 15
-    ; GFX9-NEXT: [[S_LSHR_B32_:%[0-9]+]]:sreg_32 = S_LSHR_B32 [[COPY1]], [[S_MOV_B32_]], implicit-def $scc
-    ; GFX9-NEXT: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[COPY]], [[S_LSHR_B32_]]
-    ; GFX9-NEXT: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]]
+    ; GFX9PLUS-LABEL: name: test_build_vector_trunc_s_pack_lh_wrong_shift_amt
+    ; GFX9PLUS: liveins: $sgpr0, $sgpr1
+    ; GFX9PLUS-NEXT: {{  $}}
+    ; GFX9PLUS-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+    ; GFX9PLUS-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
+    ; GFX9PLUS-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 15
+    ; GFX9PLUS-NEXT: [[S_LSHR_B32_:%[0-9]+]]:sreg_32 = S_LSHR_B32 [[COPY1]], [[S_MOV_B32_]], implicit-def $scc
+    ; GFX9PLUS-NEXT: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[COPY]], [[S_LSHR_B32_]]
+    ; GFX9PLUS-NEXT: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]]
     %0:sgpr(s32) = COPY $sgpr0
     %1:sgpr(s32) = COPY $sgpr1
     %2:sgpr(s32) = G_CONSTANT i32 15
     %3:sgpr(s32) = G_LSHR %1, %2
     %4:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %0, %3
     S_ENDPGM 0, implicit %4
 ...
 
 ---
 name: test_build_vector_trunc_s_pack_hh_wrong_shift_amt
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 
 body: |
   bb.0:
     liveins: $sgpr0, $sgpr1
 
-    ; GFX9-LABEL: name: test_build_vector_trunc_s_pack_hh_wrong_shift_amt
-    ; GFX9: liveins: $sgpr0, $sgpr1
-    ; GFX9-NEXT: {{  $}}
-    ; GFX9-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
-    ; GFX9-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
-    ; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 15
-    ; GFX9-NEXT: [[S_LSHR_B32_:%[0-9]+]]:sreg_32 = S_LSHR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
-    ; GFX9-NEXT: [[S_LSHR_B32_1:%[0-9]+]]:sreg_32 = S_LSHR_B32 [[COPY1]], [[S_MOV_B32_]], implicit-def $scc
-    ; GFX9-NEXT: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[S_LSHR_B32_]], [[S_LSHR_B32_1]]
-    ; GFX9-NEXT: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]]
+    ; GFX9PLUS-LABEL: name: test_build_vector_trunc_s_pack_hh_wrong_shift_amt
+    ; GFX9PLUS: liveins: $sgpr0, $sgpr1
+    ; GFX9PLUS-NEXT: {{  $}}
+    ; GFX9PLUS-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+    ; GFX9PLUS-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
+    ; GFX9PLUS-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 15
+    ; GFX9PLUS-NEXT: [[S_LSHR_B32_:%[0-9]+]]:sreg_32 = S_LSHR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
+    ; GFX9PLUS-NEXT: [[S_LSHR_B32_1:%[0-9]+]]:sreg_32 = S_LSHR_B32 [[COPY1]], [[S_MOV_B32_]], implicit-def $scc
+    ; GFX9PLUS-NEXT: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[S_LSHR_B32_]], [[S_LSHR_B32_1]]
+    ; GFX9PLUS-NEXT: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]]
     %0:sgpr(s32) = COPY $sgpr0
     %1:sgpr(s32) = COPY $sgpr1
     %2:sgpr(s32) = G_CONSTANT i32 15
     %3:sgpr(s32) = G_LSHR %0, %2
     %4:sgpr(s32) = G_LSHR %1, %2
     %5:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %3, %4
     S_ENDPGM 0, implicit %5
 ...
 
 ---
 name: test_build_vector_trunc_s_v2s16_constant_constant
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 
 body: |
   bb.0:
 
-    ; GFX9-LABEL: name: test_build_vector_trunc_s_v2s16_constant_constant
-    ; GFX9: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 29884539
-    ; GFX9-NEXT: S_ENDPGM 0, implicit [[S_MOV_B32_]]
+    ; GFX9PLUS-LABEL: name: test_build_vector_trunc_s_v2s16_constant_constant
+    ; GFX9PLUS: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 29884539
+    ; GFX9PLUS-NEXT: S_ENDPGM 0, implicit [[S_MOV_B32_]]
     %0:sgpr(s32) = G_CONSTANT i32 123
     %1:sgpr(s32) = G_CONSTANT i32 456
     %2:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %0, %1
     S_ENDPGM 0, implicit %2
 ...
 
 ---
 name: test_build_vector_trunc_s_v2s16_constant_impdef
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 
 body: |
   bb.0:
 
-    ; GFX9-LABEL: name: test_build_vector_trunc_s_v2s16_constant_impdef
-    ; GFX9: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 123
-    ; GFX9-NEXT: S_ENDPGM 0, implicit [[S_MOV_B32_]]
+    ; GFX9PLUS-LABEL: name: test_build_vector_trunc_s_v2s16_constant_impdef
+    ; GFX9PLUS: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 123
+    ; GFX9PLUS-NEXT: S_ENDPGM 0, implicit [[S_MOV_B32_]]
     %0:sgpr(s32) = G_CONSTANT i32 123
     %1:sgpr(s32) = G_IMPLICIT_DEF
     %2:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %0, %1
     S_ENDPGM 0, implicit %2
 ...
 
 ---
 name: test_build_vector_trunc_s_v2s16_impdef_constant
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 
 body: |
   bb.0:
 
-    ; GFX9-LABEL: name: test_build_vector_trunc_s_v2s16_impdef_constant
-    ; GFX9: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
-    ; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 123
-    ; GFX9-NEXT: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[DEF]], [[S_MOV_B32_]]
-    ; GFX9-NEXT: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]]
+    ; GFX9PLUS-LABEL: name: test_build_vector_trunc_s_v2s16_impdef_constant
+    ; GFX9PLUS: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
+    ; GFX9PLUS-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 123
+    ; GFX9PLUS-NEXT: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[DEF]], [[S_MOV_B32_]]
+    ; GFX9PLUS-NEXT: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]]
     %0:sgpr(s32) = G_IMPLICIT_DEF
     %1:sgpr(s32) = G_CONSTANT i32 123
     %2:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %0, %1
     S_ENDPGM 0, implicit %2
 ...
 
 ---
 name: test_build_vector_trunc_s_v2s16_impdef_impdef
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 
 body: |
   bb.0:
 
-    ; GFX9-LABEL: name: test_build_vector_trunc_s_v2s16_impdef_impdef
-    ; GFX9: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
-    ; GFX9-NEXT: S_ENDPGM 0, implicit [[DEF]]
+    ; GFX9PLUS-LABEL: name: test_build_vector_trunc_s_v2s16_impdef_impdef
+    ; GFX9PLUS: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
+    ; GFX9PLUS-NEXT: S_ENDPGM 0, implicit [[DEF]]
     %0:sgpr(s32) = G_IMPLICIT_DEF
     %1:sgpr(s32) = G_IMPLICIT_DEF
     %2:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %0, %1
     S_ENDPGM 0, implicit %2
 ...
 
 ---
 name: test_build_vector_trunc_s_v2s16_zext_constant_zext_constant
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 
 body: |
   bb.0:
 
-    ; GFX9-LABEL: name: test_build_vector_trunc_s_v2s16_zext_constant_zext_constant
-    ; GFX9: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 29884539
-    ; GFX9-NEXT: S_ENDPGM 0, implicit [[S_MOV_B32_]]
+    ; GFX9PLUS-LABEL: name: test_build_vector_trunc_s_v2s16_zext_constant_zext_constant
+    ; GFX9PLUS: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 29884539
+    ; GFX9PLUS-NEXT: S_ENDPGM 0, implicit [[S_MOV_B32_]]
     %0:sgpr(s16) = G_CONSTANT i16 123
     %1:sgpr(s16) = G_CONSTANT i16 456
     %2:sgpr(s32) = G_ZEXT %0
     %3:sgpr(s32) = G_ZEXT %1
     %4:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %2, %3
     S_ENDPGM 0, implicit %4
 ...
 
 ---
 name: test_build_vector_trunc_s_v2s16_zext_impdef_zext_constant
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 
 body: |
   bb.0:
 
-    ; GFX9-LABEL: name: test_build_vector_trunc_s_v2s16_zext_impdef_zext_constant
-    ; GFX9: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
-    ; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 123
-    ; GFX9-NEXT: [[S_BFE_U32_:%[0-9]+]]:sreg_32 = S_BFE_U32 [[DEF]], 1048576, implicit-def $scc
-    ; GFX9-NEXT: [[S_BFE_U32_1:%[0-9]+]]:sreg_32 = S_BFE_U32 [[S_MOV_B32_]], 1048576, implicit-def $scc
-    ; GFX9-NEXT: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[S_BFE_U32_]], [[S_BFE_U32_1]]
-    ; GFX9-NEXT: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]]
+    ; GFX9PLUS-LABEL: name: test_build_vector_trunc_s_v2s16_zext_impdef_zext_constant
+    ; GFX9PLUS: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
+    ; GFX9PLUS-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 123
+    ; GFX9PLUS-NEXT: [[S_BFE_U32_:%[0-9]+]]:sreg_32 = S_BFE_U32 [[DEF]], 1048576, implicit-def $scc
+    ; GFX9PLUS-NEXT: [[S_BFE_U32_1:%[0-9]+]]:sreg_32 = S_BFE_U32 [[S_MOV_B32_]], 1048576, implicit-def $scc
+    ; GFX9PLUS-NEXT: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[S_BFE_U32_]], [[S_BFE_U32_1]]
+    ; GFX9PLUS-NEXT: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]]
     %0:sgpr(s16) = G_IMPLICIT_DEF
     %1:sgpr(s16) = G_CONSTANT i16 123
     %2:sgpr(s32) = G_ZEXT %0
     %3:sgpr(s32) = G_ZEXT %1
     %4:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %2, %3
     S_ENDPGM 0, implicit %4
 ...
 
 ---
 name: test_build_vector_trunc_s_v2s16_sext_constant_sext_constant
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 
 body: |
   bb.0:
 
-    ; GFX9-LABEL: name: test_build_vector_trunc_s_v2s16_sext_constant_sext_constant
-    ; GFX9: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4294836208
-    ; GFX9-NEXT: S_ENDPGM 0, implicit [[S_MOV_B32_]]
+    ; GFX9PLUS-LABEL: name: test_build_vector_trunc_s_v2s16_sext_constant_sext_constant
+    ; GFX9PLUS: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4294836208
+    ; GFX9PLUS-NEXT: S_ENDPGM 0, implicit [[S_MOV_B32_]]
     %0:sgpr(s16) = G_CONSTANT i16 -16
     %1:sgpr(s16) = G_CONSTANT i16 -3
     %2:sgpr(s32) = G_SEXT %0
     %3:sgpr(s32) = G_SEXT %1
     %4:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %2, %3
     S_ENDPGM 0, implicit %4
 ...
 
 ---
 name: test_build_vector_trunc_s_v2s16_anyext_constant_anyext_constant
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 
 body: |
   bb.0:
 
-    ; GFX9-LABEL: name: test_build_vector_trunc_s_v2s16_anyext_constant_anyext_constant
-    ; GFX9: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 29884539
-    ; GFX9-NEXT: S_ENDPGM 0, implicit [[S_MOV_B32_]]
+    ; GFX9PLUS-LABEL: name: test_build_vector_trunc_s_v2s16_anyext_constant_anyext_constant
+    ; GFX9PLUS: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 29884539
+    ; GFX9PLUS-NEXT: S_ENDPGM 0, implicit [[S_MOV_B32_]]
     %0:sgpr(s16) = G_CONSTANT i16 123
     %1:sgpr(s16) = G_CONSTANT i16 456
     %2:sgpr(s32) = G_ANYEXT %0
     %3:sgpr(s32) = G_ANYEXT %1
     %4:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %2, %3
     S_ENDPGM 0, implicit %4
 ...
 
 ---
 name: test_build_vector_trunc_s_v2s16_anyext_impdef_anyext_constant
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 
 body: |
   bb.0:
 
-    ; GFX9-LABEL: name: test_build_vector_trunc_s_v2s16_anyext_impdef_anyext_constant
-    ; GFX9: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
-    ; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 123
-    ; GFX9-NEXT: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[DEF]], [[S_MOV_B32_]]
-    ; GFX9-NEXT: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]]
+    ; GFX9PLUS-LABEL: name: test_build_vector_trunc_s_v2s16_anyext_impdef_anyext_constant
+    ; GFX9PLUS: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
+    ; GFX9PLUS-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 123
+    ; GFX9PLUS-NEXT: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[DEF]], [[S_MOV_B32_]]
+    ; GFX9PLUS-NEXT: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]]
     %0:sgpr(s16) = G_IMPLICIT_DEF
     %1:sgpr(s16) = G_CONSTANT i16 123
     %2:sgpr(s32) = G_ANYEXT %0
     %3:sgpr(s32) = G_ANYEXT %1
     %4:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %2, %3
     S_ENDPGM 0, implicit %4
 ...
 
 ---
 name: test_build_vector_trunc_s_v2s16_var_constant
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 
 body: |
   bb.0:
     liveins: $sgpr0
 
-    ; GFX9-LABEL: name: test_build_vector_trunc_s_v2s16_var_constant
-    ; GFX9: liveins: $sgpr0
-    ; GFX9-NEXT: {{  $}}
-    ; GFX9-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
-    ; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 456
-    ; GFX9-NEXT: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[COPY]], [[S_MOV_B32_]]
-    ; GFX9-NEXT: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]]
+    ; GFX9PLUS-LABEL: name: test_build_vector_trunc_s_v2s16_var_constant
+    ; GFX9PLUS: liveins: $sgpr0
+    ; GFX9PLUS-NEXT: {{  $}}
+    ; GFX9PLUS-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+    ; GFX9PLUS-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 456
+    ; GFX9PLUS-NEXT: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[COPY]], [[S_MOV_B32_]]
+    ; GFX9PLUS-NEXT: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]]
     %0:sgpr(s32) = COPY $sgpr0
     %1:sgpr(s32) = G_CONSTANT i32 456
     %2:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %0, %1
     S_ENDPGM 0, implicit %2
 ...
 
 ---
 name: test_build_vector_trunc_s_v2s16_constant_var
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 
 body: |
   bb.0:
     liveins: $sgpr0
 
-    ; GFX9-LABEL: name: test_build_vector_trunc_s_v2s16_constant_var
-    ; GFX9: liveins: $sgpr0
-    ; GFX9-NEXT: {{  $}}
-    ; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 456
-    ; GFX9-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
-    ; GFX9-NEXT: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[S_MOV_B32_]], [[COPY]]
-    ; GFX9-NEXT: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]]
+    ; GFX9PLUS-LABEL: name: test_build_vector_trunc_s_v2s16_constant_var
+    ; GFX9PLUS: liveins: $sgpr0
+    ; GFX9PLUS-NEXT: {{  $}}
+    ; GFX9PLUS-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 456
+    ; GFX9PLUS-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+    ; GFX9PLUS-NEXT: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[S_MOV_B32_]], [[COPY]]
+    ; GFX9PLUS-NEXT: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]]
     %0:sgpr(s32) = G_CONSTANT i32 456
     %1:sgpr(s32) = COPY $sgpr0
     %2:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %0, %1
     S_ENDPGM 0, implicit %2
 ...
 
 ---
 name: test_build_vector_trunc_s_v2s16_var_0
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 
 body: |
   bb.0:
     liveins: $sgpr0
 
-    ; GFX9-LABEL: name: test_build_vector_trunc_s_v2s16_var_0
-    ; GFX9: liveins: $sgpr0
-    ; GFX9-NEXT: {{  $}}
-    ; GFX9-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
-    ; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
-    ; GFX9-NEXT: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[COPY]], [[S_MOV_B32_]]
-    ; GFX9-NEXT: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]]
+    ; GFX9PLUS-LABEL: name: test_build_vector_trunc_s_v2s16_var_0
+    ; GFX9PLUS: liveins: $sgpr0
+    ; GFX9PLUS-NEXT: {{  $}}
+    ; GFX9PLUS-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+    ; GFX9PLUS-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
+    ; GFX9PLUS-NEXT: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[COPY]], [[S_MOV_B32_]]
+    ; GFX9PLUS-NEXT: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]]
     %0:sgpr(s32) = COPY $sgpr0
     %1:sgpr(s32) = G_CONSTANT i32 0
     %2:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %0, %1
     S_ENDPGM 0, implicit %2
 ...
 
 ---
 name: test_build_vector_trunc_s_v2s16_0_var
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 
 body: |
   bb.0:
     liveins: $sgpr0
 
-    ; GFX9-LABEL: name: test_build_vector_trunc_s_v2s16_0_var
-    ; GFX9: liveins: $sgpr0
-    ; GFX9-NEXT: {{  $}}
-    ; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
-    ; GFX9-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
-    ; GFX9-NEXT: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[S_MOV_B32_]], [[COPY]]
-    ; GFX9-NEXT: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]]
+    ; GFX9PLUS-LABEL: name: test_build_vector_trunc_s_v2s16_0_var
+    ; GFX9PLUS: liveins: $sgpr0
+    ; GFX9PLUS-NEXT: {{  $}}
+    ; GFX9PLUS-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
+    ; GFX9PLUS-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+    ; GFX9PLUS-NEXT: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[S_MOV_B32_]], [[COPY]]
+    ; GFX9PLUS-NEXT: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]]
     %0:sgpr(s32) = G_CONSTANT i32 0
     %1:sgpr(s32) = COPY $sgpr0
     %2:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %0, %1
     S_ENDPGM 0, implicit %2
 ...

llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=tahiti -o - %s | FileCheck -check-prefix=GFX6 %s
 ; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=fiji -o - %s | FileCheck -check-prefix=GFX8 %s
 ; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 -o - %s | FileCheck -check-prefix=GFX9 %s
-; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx1010 -o - %s | FileCheck -check-prefix=GFX10 %s
+; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx1010 -o - %s | FileCheck -check-prefixes=GFX10PLUS,GFX10 %s
+; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx1100 -o - %s | FileCheck -check-prefixes=GFX10PLUS,GFX11 %s
 
 define i7 @v_saddsat_i7(i7 %lhs, i7 %rhs) {
 ; GFX6-LABEL: v_saddsat_i7:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX6-NEXT:    v_lshlrev_b32_e32 v0, 25, v0
 ; GFX6-NEXT:    v_min_i32_e32 v3, 0, v0
 ; GFX6-NEXT:    v_lshlrev_b32_e32 v1, 25, v1

 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    v_lshlrev_b16_e32 v0, 9, v0
 ; GFX9-NEXT:    v_lshlrev_b16_e32 v1, 9, v1
 ; GFX9-NEXT:    v_add_i16 v0, v0, v1 clamp
 ; GFX9-NEXT:    v_ashrrev_i16_e32 v0, 9, v0
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX10-LABEL: v_saddsat_i7:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_lshlrev_b16 v0, 9, v0
-; GFX10-NEXT:    v_lshlrev_b16 v1, 9, v1
-; GFX10-NEXT:    v_add_nc_i16 v0, v0, v1 clamp
-; GFX10-NEXT:    v_ashrrev_i16 v0, 9, v0
-; GFX10-NEXT:    s_setpc_b64 s[30:31]
+; GFX10PLUS-LABEL: v_saddsat_i7:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX10PLUS-NEXT:    v_lshlrev_b16 v0, 9, v0
+; GFX10PLUS-NEXT:    v_lshlrev_b16 v1, 9, v1
+; GFX10PLUS-NEXT:    v_add_nc_i16 v0, v0, v1 clamp
+; GFX10PLUS-NEXT:    v_ashrrev_i16 v0, 9, v0
+; GFX10PLUS-NEXT:    s_setpc_b64 s[30:31]
   %result = call i7 @llvm.sadd.sat.i7(i7 %lhs, i7 %rhs)
   ret i7 %result
 }
 
 define amdgpu_ps i7 @s_saddsat_i7(i7 inreg %lhs, i7 inreg %rhs) {
 ; GFX6-LABEL: s_saddsat_i7:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_lshl_b32 s0, s0, 25

 ; GFX9-NEXT:    s_lshl_b32 s1, s1, s2
 ; GFX9-NEXT:    s_lshl_b32 s0, s0, s2
 ; GFX9-NEXT:    v_mov_b32_e32 v0, s1
 ; GFX9-NEXT:    v_add_i16 v0, s0, v0 clamp
 ; GFX9-NEXT:    v_ashrrev_i16_e32 v0, 9, v0
 ; GFX9-NEXT:    v_readfirstlane_b32 s0, v0
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
-; GFX10-LABEL: s_saddsat_i7:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    s_bfe_u32 s2, 9, 0x100000
-; GFX10-NEXT:    s_lshl_b32 s0, s0, s2
-; GFX10-NEXT:    s_lshl_b32 s1, s1, s2
-; GFX10-NEXT:    v_add_nc_i16 v0, s0, s1 clamp
-; GFX10-NEXT:    v_ashrrev_i16 v0, 9, v0
-; GFX10-NEXT:    v_readfirstlane_b32 s0, v0
-; GFX10-NEXT:    ; return to shader part epilog
+; GFX10PLUS-LABEL: s_saddsat_i7:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    s_bfe_u32 s2, 9, 0x100000
+; GFX10PLUS-NEXT:    s_lshl_b32 s0, s0, s2
+; GFX10PLUS-NEXT:    s_lshl_b32 s1, s1, s2
+; GFX10PLUS-NEXT:    v_add_nc_i16 v0, s0, s1 clamp
+; GFX10PLUS-NEXT:    v_ashrrev_i16 v0, 9, v0
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s0, v0
+; GFX10PLUS-NEXT:    ; return to shader part epilog
   %result = call i7 @llvm.sadd.sat.i7(i7 %lhs, i7 %rhs)
   ret i7 %result
 }
 
 define i8 @v_saddsat_i8(i8 %lhs, i8 %rhs) {
 ; GFX6-LABEL: v_saddsat_i8:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    v_lshlrev_b16_e32 v0, 8, v0
 ; GFX9-NEXT:    v_lshlrev_b16_e32 v1, 8, v1
 ; GFX9-NEXT:    v_add_i16 v0, v0, v1 clamp
 ; GFX9-NEXT:    v_ashrrev_i16_e32 v0, 8, v0
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX10-LABEL: v_saddsat_i8:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_lshlrev_b16 v0, 8, v0
-; GFX10-NEXT:    v_lshlrev_b16 v1, 8, v1
-; GFX10-NEXT:    v_add_nc_i16 v0, v0, v1 clamp
-; GFX10-NEXT:    v_ashrrev_i16 v0, 8, v0
-; GFX10-NEXT:    s_setpc_b64 s[30:31]
+; GFX10PLUS-LABEL: v_saddsat_i8:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX10PLUS-NEXT:    v_lshlrev_b16 v0, 8, v0
+; GFX10PLUS-NEXT:    v_lshlrev_b16 v1, 8, v1
+; GFX10PLUS-NEXT:    v_add_nc_i16 v0, v0, v1 clamp
+; GFX10PLUS-NEXT:    v_ashrrev_i16 v0, 8, v0
+; GFX10PLUS-NEXT:    s_setpc_b64 s[30:31]
   %result = call i8 @llvm.sadd.sat.i8(i8 %lhs, i8 %rhs)
   ret i8 %result
 }
 
 define amdgpu_ps i8 @s_saddsat_i8(i8 inreg %lhs, i8 inreg %rhs) {
 ; GFX6-LABEL: s_saddsat_i8:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_lshl_b32 s0, s0, 24

 ; GFX9-NEXT:    s_lshl_b32 s1, s1, s2
 ; GFX9-NEXT:    s_lshl_b32 s0, s0, s2
 ; GFX9-NEXT:    v_mov_b32_e32 v0, s1
 ; GFX9-NEXT:    v_add_i16 v0, s0, v0 clamp
 ; GFX9-NEXT:    v_ashrrev_i16_e32 v0, 8, v0
 ; GFX9-NEXT:    v_readfirstlane_b32 s0, v0
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
-; GFX10-LABEL: s_saddsat_i8:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    s_bfe_u32 s2, 8, 0x100000
-; GFX10-NEXT:    s_lshl_b32 s0, s0, s2
-; GFX10-NEXT:    s_lshl_b32 s1, s1, s2
-; GFX10-NEXT:    v_add_nc_i16 v0, s0, s1 clamp
-; GFX10-NEXT:    v_ashrrev_i16 v0, 8, v0
-; GFX10-NEXT:    v_readfirstlane_b32 s0, v0
-; GFX10-NEXT:    ; return to shader part epilog
+; GFX10PLUS-LABEL: s_saddsat_i8:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    s_bfe_u32 s2, 8, 0x100000
+; GFX10PLUS-NEXT:    s_lshl_b32 s0, s0, s2
+; GFX10PLUS-NEXT:    s_lshl_b32 s1, s1, s2
+; GFX10PLUS-NEXT:    v_add_nc_i16 v0, s0, s1 clamp
+; GFX10PLUS-NEXT:    v_ashrrev_i16 v0, 8, v0
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s0, v0
+; GFX10PLUS-NEXT:    ; return to shader part epilog
   %result = call i8 @llvm.sadd.sat.i8(i8 %lhs, i8 %rhs)
   ret i8 %result
 }
 
 define i16 @v_saddsat_v2i8(i16 %lhs.arg, i16 %rhs.arg) {
 ; GFX6-LABEL: v_saddsat_v2i8:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

 ; GFX10-NEXT:    v_and_or_b32 v1, 0xffff, v1, v3
 ; GFX10-NEXT:    v_pk_lshlrev_b16 v0, 8, v0 op_sel_hi:[0,1]
 ; GFX10-NEXT:    v_pk_lshlrev_b16 v1, 8, v1 op_sel_hi:[0,1]
 ; GFX10-NEXT:    v_pk_add_i16 v0, v0, v1 clamp
 ; GFX10-NEXT:    v_pk_ashrrev_i16 v0, 8, v0 op_sel_hi:[0,1]
 ; GFX10-NEXT:    v_and_b32_sdwa v1, v0, s4 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
 ; GFX10-NEXT:    v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_saddsat_v2i8:
+; GFX11:       ; %bb.0:
+; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT:    v_lshrrev_b32_e32 v2, 8, v0
+; GFX11-NEXT:    v_lshrrev_b32_e32 v3, 8, v1
+; GFX11-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-NEXT:    v_and_or_b32 v0, 0xffff, v0, v2
+; GFX11-NEXT:    v_and_or_b32 v1, 0xffff, v1, v3
+; GFX11-NEXT:    v_pk_lshlrev_b16 v0, 8, v0 op_sel_hi:[0,1]
+; GFX11-NEXT:    v_pk_lshlrev_b16 v1, 8, v1 op_sel_hi:[0,1]
+; GFX11-NEXT:    v_pk_add_i16 v0, v0, v1 clamp
+; GFX11-NEXT:    v_pk_ashrrev_i16 v0, 8, v0 op_sel_hi:[0,1]
+; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; GFX11-NEXT:    v_lshlrev_b16 v1, 8, v1
+; GFX11-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-NEXT:    s_setpc_b64 s[30:31]
   %lhs = bitcast i16 %lhs.arg to <2 x i8>
   %rhs = bitcast i16 %rhs.arg to <2 x i8>
   %result = call <2 x i8> @llvm.sadd.sat.v2i8(<2 x i8> %lhs, <2 x i8> %rhs)
   %cast.result = bitcast <2 x i8> %result to i16
   ret i16 %cast.result
 }
 
 define amdgpu_ps i16 @s_saddsat_v2i8(i16 inreg %lhs.arg, i16 inreg %rhs.arg) {

 ; GFX10-NEXT:    s_pack_ll_b32_b16 s1, s1, s3
 ; GFX10-NEXT:    v_pk_add_i16 v0, s0, s1 clamp
 ; GFX10-NEXT:    s_movk_i32 s0, 0xff
 ; GFX10-NEXT:    v_pk_ashrrev_i16 v0, 8, v0 op_sel_hi:[0,1]
 ; GFX10-NEXT:    v_and_b32_sdwa v1, v0, s0 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
 ; GFX10-NEXT:    v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
 ; GFX10-NEXT:    v_readfirstlane_b32 s0, v0
 ; GFX10-NEXT:    ; return to shader part epilog
+;
+; GFX11-LABEL: s_saddsat_v2i8:
+; GFX11:       ; %bb.0:
+; GFX11-NEXT:    s_lshr_b32 s2, s0, 8
+; GFX11-NEXT:    s_lshr_b32 s3, s1, 8
+; GFX11-NEXT:    s_pack_ll_b32_b16 s0, s0, s2
+; GFX11-NEXT:    s_pack_ll_b32_b16 s1, s1, s3
+; GFX11-NEXT:    s_lshr_b32 s2, s0, 16
+; GFX11-NEXT:    s_lshr_b32 s3, s1, 16
+; GFX11-NEXT:    s_lshl_b32 s0, s0, 0x80008
+; GFX11-NEXT:    s_lshl_b32 s2, s2, 8
+; GFX11-NEXT:    s_lshl_b32 s1, s1, 0x80008
+; GFX11-NEXT:    s_lshl_b32 s3, s3, 8
+; GFX11-NEXT:    s_pack_ll_b32_b16 s0, s0, s2
+; GFX11-NEXT:    s_pack_ll_b32_b16 s1, s1, s3
+; GFX11-NEXT:    v_pk_add_i16 v0, s0, s1 clamp
+; GFX11-NEXT:    v_pk_ashrrev_i16 v0, 8, v0 op_sel_hi:[0,1]
+; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; GFX11-NEXT:    v_lshlrev_b16 v1, 8, v1
+; GFX11-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-NEXT:    v_readfirstlane_b32 s0, v0
+; GFX11-NEXT:    ; return to shader part epilog
   %lhs = bitcast i16 %lhs.arg to <2 x i8>
   %rhs = bitcast i16 %rhs.arg to <2 x i8>
   %result = call <2 x i8> @llvm.sadd.sat.v2i8(<2 x i8> %lhs, <2 x i8> %rhs)
   %cast.result = bitcast <2 x i8> %result to i16
   ret i16 %cast.result
 }
 
 define i32 @v_saddsat_v4i8(i32 %lhs.arg, i32 %rhs.arg) {

 ; GFX10-NEXT:    v_pk_ashrrev_i16 v1, 8, v1 op_sel_hi:[0,1]
 ; GFX10-NEXT:    v_lshlrev_b32_sdwa v2, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
 ; GFX10-NEXT:    v_and_b32_e32 v3, 0xff, v1
 ; GFX10-NEXT:    v_lshlrev_b32_sdwa v1, v4, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
 ; GFX10-NEXT:    v_and_or_b32 v0, v0, 0xff, v2
 ; GFX10-NEXT:    v_lshlrev_b32_e32 v2, 16, v3
 ; GFX10-NEXT:    v_or3_b32 v0, v0, v2, v1
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_saddsat_v4i8:
+; GFX11:       ; %bb.0:
+; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT:    v_lshrrev_b32_e32 v2, 8, v0
+; GFX11-NEXT:    v_lshrrev_b32_e32 v3, 8, v1
+; GFX11-NEXT:    v_lshrrev_b32_e32 v5, 24, v0
+; GFX11-NEXT:    v_lshrrev_b32_e32 v6, 24, v1
+; GFX11-NEXT:    v_lshrrev_b32_e32 v4, 16, v0
+; GFX11-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-NEXT:    v_lshrrev_b32_e32 v7, 16, v1
+; GFX11-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
+; GFX11-NEXT:    v_and_or_b32 v0, 0xffff, v0, v2
+; GFX11-NEXT:    v_and_or_b32 v1, 0xffff, v1, v3
+; GFX11-NEXT:    v_and_or_b32 v2, 0xffff, v4, v5
+; GFX11-NEXT:    v_and_or_b32 v3, 0xffff, v7, v6
+; GFX11-NEXT:    v_pk_lshlrev_b16 v0, 8, v0 op_sel_hi:[0,1]
+; GFX11-NEXT:    v_pk_lshlrev_b16 v1, 8, v1 op_sel_hi:[0,1]
+; GFX11-NEXT:    v_pk_lshlrev_b16 v2, 8, v2 op_sel_hi:[0,1]
+; GFX11-NEXT:    v_pk_lshlrev_b16 v3, 8, v3 op_sel_hi:[0,1]
+; GFX11-NEXT:    v_pk_add_i16 v0, v0, v1 clamp
+; GFX11-NEXT:    v_pk_add_i16 v1, v2, v3 clamp
+; GFX11-NEXT:    v_pk_ashrrev_i16 v0, 8, v0 op_sel_hi:[0,1]
+; GFX11-NEXT:    v_pk_ashrrev_i16 v1, 8, v1 op_sel_hi:[0,1]
+; GFX11-NEXT:    v_bfe_u32 v2, v0, 16, 8
+; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v1
+; GFX11-NEXT:    v_bfe_u32 v1, v1, 16, 8
+; GFX11-NEXT:    v_lshlrev_b32_e32 v2, 8, v2
+; GFX11-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-NEXT:    v_lshlrev_b32_e32 v1, 24, v1
+; GFX11-NEXT:    v_and_or_b32 v0, v0, 0xff, v2
+; GFX11-NEXT:    v_or3_b32 v0, v0, v3, v1
+; GFX11-NEXT:    s_setpc_b64 s[30:31]
   %lhs = bitcast i32 %lhs.arg to <4 x i8>
   %rhs = bitcast i32 %rhs.arg to <4 x i8>
   %result = call <4 x i8> @llvm.sadd.sat.v4i8(<4 x i8> %lhs, <4 x i8> %rhs)
   %cast.result = bitcast <4 x i8> %result to i32
   ret i32 %cast.result
 }
 
 define amdgpu_ps i32 @s_saddsat_v4i8(i32 inreg %lhs.arg, i32 inreg %rhs.arg) {

 ; GFX10-NEXT:    v_and_b32_e32 v3, 0xff, v1
 ; GFX10-NEXT:    s_mov_b32 s0, 24
 ; GFX10-NEXT:    v_lshlrev_b32_sdwa v1, s0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
 ; GFX10-NEXT:    v_and_or_b32 v0, v0, 0xff, v2
 ; GFX10-NEXT:    v_lshlrev_b32_e32 v2, 16, v3
 ; GFX10-NEXT:    v_or3_b32 v0, v0, v2, v1
 ; GFX10-NEXT:    v_readfirstlane_b32 s0, v0
 ; GFX10-NEXT:    ; return to shader part epilog
+;
+; GFX11-LABEL: s_saddsat_v4i8:
+; GFX11:       ; %bb.0:
+; GFX11-NEXT:    s_lshr_b32 s2, s0, 8
+; GFX11-NEXT:    s_lshr_b32 s4, s1, 8
+; GFX11-NEXT:    s_pack_ll_b32_b16 s2, s0, s2
+; GFX11-NEXT:    s_pack_ll_b32_b16 s4, s1, s4
+; GFX11-NEXT:    s_lshr_b32 s6, s2, 16
+; GFX11-NEXT:    s_lshl_b32 s2, s2, 0x80008
+; GFX11-NEXT:    s_lshl_b32 s6, s6, 8
+; GFX11-NEXT:    s_lshr_b32 s3, s0, 24
+; GFX11-NEXT:    s_pack_ll_b32_b16 s2, s2, s6
+; GFX11-NEXT:    s_lshr_b32 s6, s4, 16
+; GFX11-NEXT:    s_lshr_b32 s5, s1, 24
+; GFX11-NEXT:    s_lshl_b32 s4, s4, 0x80008
+; GFX11-NEXT:    s_lshl_b32 s6, s6, 8
+; GFX11-NEXT:    s_pack_hl_b32_b16 s0, s0, s3
+; GFX11-NEXT:    s_pack_hl_b32_b16 s1, s1, s5
+; GFX11-NEXT:    s_pack_ll_b32_b16 s4, s4, s6
+; GFX11-NEXT:    s_lshr_b32 s3, s0, 16
+; GFX11-NEXT:    s_lshr_b32 s5, s1, 16
+; GFX11-NEXT:    v_pk_add_i16 v0, s2, s4 clamp
+; GFX11-NEXT:    s_lshl_b32 s0, s0, 0x80008
+; GFX11-NEXT:    s_lshl_b32 s3, s3, 8
+; GFX11-NEXT:    s_lshl_b32 s1, s1, 0x80008
+; GFX11-NEXT:    s_lshl_b32 s2, s5, 8
+; GFX11-NEXT:    s_pack_ll_b32_b16 s0, s0, s3
+; GFX11-NEXT:    s_pack_ll_b32_b16 s1, s1, s2
+; GFX11-NEXT:    v_pk_ashrrev_i16 v0, 8, v0 op_sel_hi:[0,1]
+; GFX11-NEXT:    v_pk_add_i16 v1, s0, s1 clamp
+; GFX11-NEXT:    v_bfe_u32 v2, v0, 16, 8
+; GFX11-NEXT:    v_pk_ashrrev_i16 v1, 8, v1 op_sel_hi:[0,1]
+; GFX11-NEXT:    v_lshlrev_b32_e32 v2, 8, v2
+; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v1
+; GFX11-NEXT:    v_bfe_u32 v1, v1, 16, 8
+; GFX11-NEXT:    v_and_or_b32 v0, v0, 0xff, v2
+; GFX11-NEXT:    v_lshlrev_b32_e32 v2, 16, v3
+; GFX11-NEXT:    v_lshlrev_b32_e32 v1, 24, v1
+; GFX11-NEXT:    v_or3_b32 v0, v0, v2, v1
+; GFX11-NEXT:    v_readfirstlane_b32 s0, v0
+; GFX11-NEXT:    ; return to shader part epilog
   %lhs = bitcast i32 %lhs.arg to <4 x i8>
   %rhs = bitcast i32 %rhs.arg to <4 x i8>
   %result = call <4 x i8> @llvm.sadd.sat.v4i8(<4 x i8> %lhs, <4 x i8> %rhs)
   %cast.result = bitcast <4 x i8> %result to i32
   ret i32 %cast.result
 }
 
 define i24 @v_saddsat_i24(i24 %lhs, i24 %rhs) {

 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    v_lshlrev_b32_e32 v0, 8, v0
 ; GFX9-NEXT:    v_lshlrev_b32_e32 v1, 8, v1
 ; GFX9-NEXT:    v_add_i32 v0, v0, v1 clamp
 ; GFX9-NEXT:    v_ashrrev_i32_e32 v0, 8, v0
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX10-LABEL: v_saddsat_i24:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_lshlrev_b32_e32 v0, 8, v0
-; GFX10-NEXT:    v_lshlrev_b32_e32 v1, 8, v1
-; GFX10-NEXT:    v_add_nc_i32 v0, v0, v1 clamp
-; GFX10-NEXT:    v_ashrrev_i32_e32 v0, 8, v0
-; GFX10-NEXT:    s_setpc_b64 s[30:31]
+; GFX10PLUS-LABEL: v_saddsat_i24:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX10PLUS-NEXT:    v_lshlrev_b32_e32 v0, 8, v0
+; GFX10PLUS-NEXT:    v_lshlrev_b32_e32 v1, 8, v1
+; GFX10PLUS-NEXT:    v_add_nc_i32 v0, v0, v1 clamp
+; GFX10PLUS-NEXT:    v_ashrrev_i32_e32 v0, 8, v0
+; GFX10PLUS-NEXT:    s_setpc_b64 s[30:31]
   %result = call i24 @llvm.sadd.sat.i24(i24 %lhs, i24 %rhs)
   ret i24 %result
 }
 
 define amdgpu_ps i24 @s_saddsat_i24(i24 inreg %lhs, i24 inreg %rhs) {
 ; GFX6-LABEL: s_saddsat_i24:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_lshl_b32 s0, s0, 8

 ; GFX9-NEXT:    s_lshl_b32 s1, s1, 8
 ; GFX9-NEXT:    s_lshl_b32 s0, s0, 8
 ; GFX9-NEXT:    v_mov_b32_e32 v0, s1
 ; GFX9-NEXT:    v_add_i32 v0, s0, v0 clamp
 ; GFX9-NEXT:    v_ashrrev_i32_e32 v0, 8, v0
 ; GFX9-NEXT:    v_readfirstlane_b32 s0, v0
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
-; GFX10-LABEL: s_saddsat_i24:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    s_lshl_b32 s0, s0, 8
-; GFX10-NEXT:    s_lshl_b32 s1, s1, 8
-; GFX10-NEXT:    v_add_nc_i32 v0, s0, s1 clamp
-; GFX10-NEXT:    v_ashrrev_i32_e32 v0, 8, v0
-; GFX10-NEXT:    v_readfirstlane_b32 s0, v0
-; GFX10-NEXT:    ; return to shader part epilog
+; GFX10PLUS-LABEL: s_saddsat_i24:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    s_lshl_b32 s0, s0, 8
+; GFX10PLUS-NEXT:    s_lshl_b32 s1, s1, 8
+; GFX10PLUS-NEXT:    v_add_nc_i32 v0, s0, s1 clamp
+; GFX10PLUS-NEXT:    v_ashrrev_i32_e32 v0, 8, v0
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s0, v0
+; GFX10PLUS-NEXT:    ; return to shader part epilog
   %result = call i24 @llvm.sadd.sat.i24(i24 %lhs, i24 %rhs)
   ret i24 %result
 }
 
 define i32 @v_saddsat_i32(i32 %lhs, i32 %rhs) {
 ; GFX6-LABEL: v_saddsat_i32:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

 ; GFX8-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX9-LABEL: v_saddsat_i32:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    v_add_i32 v0, v0, v1 clamp
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX10-LABEL: v_saddsat_i32:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_add_nc_i32 v0, v0, v1 clamp
-; GFX10-NEXT:    s_setpc_b64 s[30:31]
+; GFX10PLUS-LABEL: v_saddsat_i32:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX10PLUS-NEXT:    v_add_nc_i32 v0, v0, v1 clamp
+; GFX10PLUS-NEXT:    s_setpc_b64 s[30:31]
   %result = call i32 @llvm.sadd.sat.i32(i32 %lhs, i32 %rhs)
   ret i32 %result
 }
 
 define amdgpu_ps i32 @s_saddsat_i32(i32 inreg %lhs, i32 inreg %rhs) {
 ; GCN-LABEL: s_saddsat_i32:
 ; GCN:       ; %bb.0:
 ; GCN-NEXT:    s_cmp_gt_i32 s0, 0

 ;
 ; GFX9-LABEL: s_saddsat_i32:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    v_mov_b32_e32 v0, s1
 ; GFX9-NEXT:    v_add_i32 v0, s0, v0 clamp
 ; GFX9-NEXT:    v_readfirstlane_b32 s0, v0
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
-; GFX10-LABEL: s_saddsat_i32:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_add_nc_i32 v0, s0, s1 clamp
-; GFX10-NEXT:    v_readfirstlane_b32 s0, v0
-; GFX10-NEXT:    ; return to shader part epilog
+; GFX10PLUS-LABEL: s_saddsat_i32:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    v_add_nc_i32 v0, s0, s1 clamp
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s0, v0
+; GFX10PLUS-NEXT:    ; return to shader part epilog
   %result = call i32 @llvm.sadd.sat.i32(i32 %lhs, i32 %rhs)
   ret i32 %result
 }
 
 define amdgpu_ps float @saddsat_i32_sv(i32 inreg %lhs, i32 %rhs) {
 ; GFX6-LABEL: saddsat_i32_sv:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_min_i32 s2, s0, 0

 ; GFX8-NEXT:    v_add_u32_e32 v0, vcc, s0, v0
 ; GFX8-NEXT:    ; return to shader part epilog
 ;
 ; GFX9-LABEL: saddsat_i32_sv:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    v_add_i32 v0, s0, v0 clamp
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
-; GFX10-LABEL: saddsat_i32_sv:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_add_nc_i32 v0, s0, v0 clamp
-; GFX10-NEXT:    ; return to shader part epilog
+; GFX10PLUS-LABEL: saddsat_i32_sv:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    v_add_nc_i32 v0, s0, v0 clamp
+; GFX10PLUS-NEXT:    ; return to shader part epilog
   %result = call i32 @llvm.sadd.sat.i32(i32 %lhs, i32 %rhs)
   %cast = bitcast i32 %result to float
   ret float %cast
 }
 
 define amdgpu_ps float @saddsat_i32_vs(i32 %lhs, i32 inreg %rhs) {
 ; GFX6-LABEL: saddsat_i32_vs:
 ; GFX6:       ; %bb.0:

 ; GFX8-NEXT:    v_add_u32_e32 v0, vcc, v0, v1
 ; GFX8-NEXT:    ; return to shader part epilog
 ;
 ; GFX9-LABEL: saddsat_i32_vs:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    v_add_i32 v0, v0, s0 clamp
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
-; GFX10-LABEL: saddsat_i32_vs:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_add_nc_i32 v0, v0, s0 clamp
-; GFX10-NEXT:    ; return to shader part epilog
+; GFX10PLUS-LABEL: saddsat_i32_vs:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    v_add_nc_i32 v0, v0, s0 clamp
+; GFX10PLUS-NEXT:    ; return to shader part epilog
   %result = call i32 @llvm.sadd.sat.i32(i32 %lhs, i32 %rhs)
   %cast = bitcast i32 %result to float
   ret float %cast
 }
 
 define <2 x i32> @v_saddsat_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) {
 ; GFX6-LABEL: v_saddsat_v2i32:
 ; GFX6:       ; %bb.0:

 ;
 ; GFX9-LABEL: v_saddsat_v2i32:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    v_add_i32 v0, v0, v2 clamp
 ; GFX9-NEXT:    v_add_i32 v1, v1, v3 clamp
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX10-LABEL: v_saddsat_v2i32:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_add_nc_i32 v0, v0, v2 clamp
-; GFX10-NEXT:    v_add_nc_i32 v1, v1, v3 clamp
-; GFX10-NEXT:    s_setpc_b64 s[30:31]
+; GFX10PLUS-LABEL: v_saddsat_v2i32:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX10PLUS-NEXT:    v_add_nc_i32 v0, v0, v2 clamp
+; GFX10PLUS-NEXT:    v_add_nc_i32 v1, v1, v3 clamp
+; GFX10PLUS-NEXT:    s_setpc_b64 s[30:31]
   %result = call <2 x i32> @llvm.sadd.sat.v2i32(<2 x i32> %lhs, <2 x i32> %rhs)
   ret <2 x i32> %result
 }
 
 define amdgpu_ps <2 x i32> @s_saddsat_v2i32(<2 x i32> inreg %lhs, <2 x i32> inreg %rhs) {
 ; GFX6-LABEL: s_saddsat_v2i32:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_min_i32 s5, s0, 0

 ; GFX9-NEXT:    v_mov_b32_e32 v0, s2
 ; GFX9-NEXT:    v_mov_b32_e32 v1, s3
 ; GFX9-NEXT:    v_add_i32 v0, s0, v0 clamp
 ; GFX9-NEXT:    v_add_i32 v1, s1, v1 clamp
 ; GFX9-NEXT:    v_readfirstlane_b32 s0, v0
 ; GFX9-NEXT:    v_readfirstlane_b32 s1, v1
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
-; GFX10-LABEL: s_saddsat_v2i32:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_add_nc_i32 v0, s0, s2 clamp
-; GFX10-NEXT:    v_add_nc_i32 v1, s1, s3 clamp
-; GFX10-NEXT:    v_readfirstlane_b32 s0, v0
-; GFX10-NEXT:    v_readfirstlane_b32 s1, v1
-; GFX10-NEXT:    ; return to shader part epilog
+; GFX10PLUS-LABEL: s_saddsat_v2i32:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    v_add_nc_i32 v0, s0, s2 clamp
+; GFX10PLUS-NEXT:    v_add_nc_i32 v1, s1, s3 clamp
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s0, v0
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s1, v1
+; GFX10PLUS-NEXT:    ; return to shader part epilog
   %result = call <2 x i32> @llvm.sadd.sat.v2i32(<2 x i32> %lhs, <2 x i32> %rhs)
   ret <2 x i32> %result
 }
 
 define <3 x i32> @v_saddsat_v3i32(<3 x i32> %lhs, <3 x i32> %rhs) {
 ; GFX6-LABEL: v_saddsat_v3i32:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

 ; GFX9-LABEL: v_saddsat_v3i32:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    v_add_i32 v0, v0, v3 clamp
 ; GFX9-NEXT:    v_add_i32 v1, v1, v4 clamp
 ; GFX9-NEXT:    v_add_i32 v2, v2, v5 clamp
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX10-LABEL: v_saddsat_v3i32:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_add_nc_i32 v0, v0, v3 clamp
-; GFX10-NEXT:    v_add_nc_i32 v1, v1, v4 clamp
-; GFX10-NEXT:    v_add_nc_i32 v2, v2, v5 clamp
-; GFX10-NEXT:    s_setpc_b64 s[30:31]
+; GFX10PLUS-LABEL: v_saddsat_v3i32:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX10PLUS-NEXT:    v_add_nc_i32 v0, v0, v3 clamp
+; GFX10PLUS-NEXT:    v_add_nc_i32 v1, v1, v4 clamp
+; GFX10PLUS-NEXT:    v_add_nc_i32 v2, v2, v5 clamp
+; GFX10PLUS-NEXT:    s_setpc_b64 s[30:31]
   %result = call <3 x i32> @llvm.sadd.sat.v3i32(<3 x i32> %lhs, <3 x i32> %rhs)
   ret <3 x i32> %result
 }
 
 define amdgpu_ps <3 x i32> @s_saddsat_v3i32(<3 x i32> inreg %lhs, <3 x i32> inreg %rhs) {
 ; GFX6-LABEL: s_saddsat_v3i32:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_min_i32 s7, s0, 0

 ; GFX9-NEXT:    v_add_i32 v0, s0, v0 clamp
 ; GFX9-NEXT:    v_add_i32 v1, s1, v1 clamp
 ; GFX9-NEXT:    v_add_i32 v2, s2, v2 clamp
 ; GFX9-NEXT:    v_readfirstlane_b32 s0, v0
 ; GFX9-NEXT:    v_readfirstlane_b32 s1, v1
 ; GFX9-NEXT:    v_readfirstlane_b32 s2, v2
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
-; GFX10-LABEL: s_saddsat_v3i32:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_add_nc_i32 v0, s0, s3 clamp
-; GFX10-NEXT:    v_add_nc_i32 v1, s1, s4 clamp
-; GFX10-NEXT:    v_add_nc_i32 v2, s2, s5 clamp
-; GFX10-NEXT:    v_readfirstlane_b32 s0, v0
-; GFX10-NEXT:    v_readfirstlane_b32 s1, v1
-; GFX10-NEXT:    v_readfirstlane_b32 s2, v2
-; GFX10-NEXT:    ; return to shader part epilog
+; GFX10PLUS-LABEL: s_saddsat_v3i32:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    v_add_nc_i32 v0, s0, s3 clamp
+; GFX10PLUS-NEXT:    v_add_nc_i32 v1, s1, s4 clamp
+; GFX10PLUS-NEXT:    v_add_nc_i32 v2, s2, s5 clamp
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s0, v0
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s1, v1
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s2, v2
+; GFX10PLUS-NEXT:    ; return to shader part epilog
   %result = call <3 x i32> @llvm.sadd.sat.v3i32(<3 x i32> %lhs, <3 x i32> %rhs)
   ret <3 x i32> %result
 }
 
 define <4 x i32> @v_saddsat_v4i32(<4 x i32> %lhs, <4 x i32> %rhs) {
 ; GFX6-LABEL: v_saddsat_v4i32:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    v_add_i32 v0, v0, v4 clamp
 ; GFX9-NEXT:    v_add_i32 v1, v1, v5 clamp
 ; GFX9-NEXT:    v_add_i32 v2, v2, v6 clamp
 ; GFX9-NEXT:    v_add_i32 v3, v3, v7 clamp
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX10-LABEL: v_saddsat_v4i32:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_add_nc_i32 v0, v0, v4 clamp
-; GFX10-NEXT:    v_add_nc_i32 v1, v1, v5 clamp
-; GFX10-NEXT:    v_add_nc_i32 v2, v2, v6 clamp
-; GFX10-NEXT:    v_add_nc_i32 v3, v3, v7 clamp
-; GFX10-NEXT:    s_setpc_b64 s[30:31]
+; GFX10PLUS-LABEL: v_saddsat_v4i32:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX10PLUS-NEXT:    v_add_nc_i32 v0, v0, v4 clamp
+; GFX10PLUS-NEXT:    v_add_nc_i32 v1, v1, v5 clamp
+; GFX10PLUS-NEXT:    v_add_nc_i32 v2, v2, v6 clamp
+; GFX10PLUS-NEXT:    v_add_nc_i32 v3, v3, v7 clamp
+; GFX10PLUS-NEXT:    s_setpc_b64 s[30:31]
   %result = call <4 x i32> @llvm.sadd.sat.v4i32(<4 x i32> %lhs, <4 x i32> %rhs)
   ret <4 x i32> %result
 }
 
 define amdgpu_ps <4 x i32> @s_saddsat_v4i32(<4 x i32> inreg %lhs, <4 x i32> inreg %rhs) {
 ; GFX6-LABEL: s_saddsat_v4i32:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_min_i32 s9, s0, 0

 ; GFX9-NEXT:    v_add_i32 v2, s2, v2 clamp
 ; GFX9-NEXT:    v_add_i32 v3, s3, v3 clamp
 ; GFX9-NEXT:    v_readfirstlane_b32 s0, v0
 ; GFX9-NEXT:    v_readfirstlane_b32 s1, v1
 ; GFX9-NEXT:    v_readfirstlane_b32 s2, v2
 ; GFX9-NEXT:    v_readfirstlane_b32 s3, v3
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
-; GFX10-LABEL: s_saddsat_v4i32:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_add_nc_i32 v0, s0, s4 clamp
-; GFX10-NEXT:    v_add_nc_i32 v1, s1, s5 clamp
-; GFX10-NEXT:    v_add_nc_i32 v2, s2, s6 clamp
-; GFX10-NEXT:    v_add_nc_i32 v3, s3, s7 clamp
-; GFX10-NEXT:    v_readfirstlane_b32 s0, v0
-; GFX10-NEXT:    v_readfirstlane_b32 s1, v1
-; GFX10-NEXT:    v_readfirstlane_b32 s2, v2
-; GFX10-NEXT:    v_readfirstlane_b32 s3, v3
-; GFX10-NEXT:    ; return to shader part epilog
+; GFX10PLUS-LABEL: s_saddsat_v4i32:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    v_add_nc_i32 v0, s0, s4 clamp
+; GFX10PLUS-NEXT:    v_add_nc_i32 v1, s1, s5 clamp
+; GFX10PLUS-NEXT:    v_add_nc_i32 v2, s2, s6 clamp
+; GFX10PLUS-NEXT:    v_add_nc_i32 v3, s3, s7 clamp
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s0, v0
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s1, v1
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s2, v2
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s3, v3
+; GFX10PLUS-NEXT:    ; return to shader part epilog
   %result = call <4 x i32> @llvm.sadd.sat.v4i32(<4 x i32> %lhs, <4 x i32> %rhs)
   ret <4 x i32> %result
 }
 
 define <5 x i32> @v_saddsat_v5i32(<5 x i32> %lhs, <5 x i32> %rhs) {
 ; GFX6-LABEL: v_saddsat_v5i32:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    v_add_i32 v0, v0, v5 clamp
 ; GFX9-NEXT:    v_add_i32 v1, v1, v6 clamp
 ; GFX9-NEXT:    v_add_i32 v2, v2, v7 clamp
 ; GFX9-NEXT:    v_add_i32 v3, v3, v8 clamp
 ; GFX9-NEXT:    v_add_i32 v4, v4, v9 clamp
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX10-LABEL: v_saddsat_v5i32:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_add_nc_i32 v0, v0, v5 clamp
-; GFX10-NEXT:    v_add_nc_i32 v1, v1, v6 clamp
-; GFX10-NEXT:    v_add_nc_i32 v2, v2, v7 clamp
-; GFX10-NEXT:    v_add_nc_i32 v3, v3, v8 clamp
-; GFX10-NEXT:    v_add_nc_i32 v4, v4, v9 clamp
-; GFX10-NEXT:    s_setpc_b64 s[30:31]
+; GFX10PLUS-LABEL: v_saddsat_v5i32:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX10PLUS-NEXT:    v_add_nc_i32 v0, v0, v5 clamp
+; GFX10PLUS-NEXT:    v_add_nc_i32 v1, v1, v6 clamp
+; GFX10PLUS-NEXT:    v_add_nc_i32 v2, v2, v7 clamp
+; GFX10PLUS-NEXT:    v_add_nc_i32 v3, v3, v8 clamp
+; GFX10PLUS-NEXT:    v_add_nc_i32 v4, v4, v9 clamp
+; GFX10PLUS-NEXT:    s_setpc_b64 s[30:31]
   %result = call <5 x i32> @llvm.sadd.sat.v5i32(<5 x i32> %lhs, <5 x i32> %rhs)
   ret <5 x i32> %result
 }
 
 define amdgpu_ps <5 x i32> @s_saddsat_v5i32(<5 x i32> inreg %lhs, <5 x i32> inreg %rhs) {
 ; GFX6-LABEL: s_saddsat_v5i32:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_min_i32 s11, s0, 0

 ; GFX9-NEXT:    v_add_i32 v4, s4, v4 clamp
 ; GFX9-NEXT:    v_readfirstlane_b32 s0, v0
 ; GFX9-NEXT:    v_readfirstlane_b32 s1, v1
 ; GFX9-NEXT:    v_readfirstlane_b32 s2, v2
 ; GFX9-NEXT:    v_readfirstlane_b32 s3, v3
 ; GFX9-NEXT:    v_readfirstlane_b32 s4, v4
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
-; GFX10-LABEL: s_saddsat_v5i32:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_add_nc_i32 v0, s0, s5 clamp
-; GFX10-NEXT:    v_add_nc_i32 v1, s1, s6 clamp
-; GFX10-NEXT:    v_add_nc_i32 v2, s2, s7 clamp
-; GFX10-NEXT:    v_add_nc_i32 v3, s3, s8 clamp
-; GFX10-NEXT:    v_add_nc_i32 v4, s4, s9 clamp
-; GFX10-NEXT:    v_readfirstlane_b32 s0, v0
-; GFX10-NEXT:    v_readfirstlane_b32 s1, v1
-; GFX10-NEXT:    v_readfirstlane_b32 s2, v2
-; GFX10-NEXT:    v_readfirstlane_b32 s3, v3
-; GFX10-NEXT:    v_readfirstlane_b32 s4, v4
-; GFX10-NEXT:    ; return to shader part epilog
+; GFX10PLUS-LABEL: s_saddsat_v5i32:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    v_add_nc_i32 v0, s0, s5 clamp
+; GFX10PLUS-NEXT:    v_add_nc_i32 v1, s1, s6 clamp
+; GFX10PLUS-NEXT:    v_add_nc_i32 v2, s2, s7 clamp
+; GFX10PLUS-NEXT:    v_add_nc_i32 v3, s3, s8 clamp
+; GFX10PLUS-NEXT:    v_add_nc_i32 v4, s4, s9 clamp
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s0, v0
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s1, v1
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s2, v2
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s3, v3
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s4, v4
+; GFX10PLUS-NEXT:    ; return to shader part epilog
   %result = call <5 x i32> @llvm.sadd.sat.v5i32(<5 x i32> %lhs, <5 x i32> %rhs)
   ret <5 x i32> %result
 }
 
 define <16 x i32> @v_saddsat_v16i32(<16 x i32> %lhs, <16 x i32> %rhs) {
 ; GFX6-LABEL: v_saddsat_v16i32:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

 ; GFX10-NEXT:    v_add_nc_i32 v10, v10, v26 clamp
 ; GFX10-NEXT:    v_add_nc_i32 v11, v11, v27 clamp
 ; GFX10-NEXT:    v_add_nc_i32 v12, v12, v28 clamp
 ; GFX10-NEXT:    v_add_nc_i32 v13, v13, v29 clamp
 ; GFX10-NEXT:    v_add_nc_i32 v14, v14, v30 clamp
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    v_add_nc_i32 v15, v15, v31 clamp
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_saddsat_v16i32:
+; GFX11:       ; %bb.0:
+; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT:    scratch_load_b32 v31, off, s32
+; GFX11-NEXT:    v_add_nc_i32 v0, v0, v16 clamp
+; GFX11-NEXT:    v_add_nc_i32 v1, v1, v17 clamp
+; GFX11-NEXT:    v_add_nc_i32 v2, v2, v18 clamp
+; GFX11-NEXT:    v_add_nc_i32 v3, v3, v19 clamp
+; GFX11-NEXT:    v_add_nc_i32 v4, v4, v20 clamp
+; GFX11-NEXT:    v_add_nc_i32 v5, v5, v21 clamp
+; GFX11-NEXT:    v_add_nc_i32 v6, v6, v22 clamp
+; GFX11-NEXT:    v_add_nc_i32 v7, v7, v23 clamp
+; GFX11-NEXT:    v_add_nc_i32 v8, v8, v24 clamp
+; GFX11-NEXT:    v_add_nc_i32 v9, v9, v25 clamp
+; GFX11-NEXT:    v_add_nc_i32 v10, v10, v26 clamp
+; GFX11-NEXT:    v_add_nc_i32 v11, v11, v27 clamp
+; GFX11-NEXT:    v_add_nc_i32 v12, v12, v28 clamp
+; GFX11-NEXT:    v_add_nc_i32 v13, v13, v29 clamp
+; GFX11-NEXT:    v_add_nc_i32 v14, v14, v30 clamp
+; GFX11-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-NEXT:    v_add_nc_i32 v15, v15, v31 clamp
+; GFX11-NEXT:    s_setpc_b64 s[30:31]
   %result = call <16 x i32> @llvm.sadd.sat.v16i32(<16 x i32> %lhs, <16 x i32> %rhs)
   ret <16 x i32> %result
 }
 
 define amdgpu_ps <16 x i32> @s_saddsat_v16i32(<16 x i32> inreg %lhs, <16 x i32> inreg %rhs) {
 ; GFX6-LABEL: s_saddsat_v16i32:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_min_i32 s33, s0, 0

 ; GFX9-NEXT:    v_readfirstlane_b32 s10, v10
 ; GFX9-NEXT:    v_readfirstlane_b32 s11, v11
 ; GFX9-NEXT:    v_readfirstlane_b32 s12, v12
 ; GFX9-NEXT:    v_readfirstlane_b32 s13, v13
 ; GFX9-NEXT:    v_readfirstlane_b32 s14, v14
 ; GFX9-NEXT:    v_readfirstlane_b32 s15, v15
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
-; GFX10-LABEL: s_saddsat_v16i32:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_add_nc_i32 v0, s0, s16 clamp
-; GFX10-NEXT:    v_add_nc_i32 v1, s1, s17 clamp
-; GFX10-NEXT:    v_add_nc_i32 v2, s2, s18 clamp
-; GFX10-NEXT:    v_add_nc_i32 v3, s3, s19 clamp
-; GFX10-NEXT:    v_add_nc_i32 v4, s4, s20 clamp
-; GFX10-NEXT:    v_add_nc_i32 v5, s5, s21 clamp
-; GFX10-NEXT:    v_add_nc_i32 v6, s6, s22 clamp
-; GFX10-NEXT:    v_add_nc_i32 v7, s7, s23 clamp
-; GFX10-NEXT:    v_add_nc_i32 v8, s8, s24 clamp
-; GFX10-NEXT:    v_add_nc_i32 v9, s9, s25 clamp
-; GFX10-NEXT:    v_add_nc_i32 v10, s10, s26 clamp
-; GFX10-NEXT:    v_add_nc_i32 v11, s11, s27 clamp
-; GFX10-NEXT:    v_add_nc_i32 v12, s12, s28 clamp
-; GFX10-NEXT:    v_add_nc_i32 v13, s13, s29 clamp
-; GFX10-NEXT:    v_add_nc_i32 v14, s14, s30 clamp
-; GFX10-NEXT:    v_add_nc_i32 v15, s15, s31 clamp
-; GFX10-NEXT:    v_readfirstlane_b32 s0, v0
-; GFX10-NEXT:    v_readfirstlane_b32 s1, v1
-; GFX10-NEXT:    v_readfirstlane_b32 s2, v2
-; GFX10-NEXT:    v_readfirstlane_b32 s3, v3
-; GFX10-NEXT:    v_readfirstlane_b32 s4, v4
-; GFX10-NEXT:    v_readfirstlane_b32 s5, v5
-; GFX10-NEXT:    v_readfirstlane_b32 s6, v6
-; GFX10-NEXT:    v_readfirstlane_b32 s7, v7
-; GFX10-NEXT:    v_readfirstlane_b32 s8, v8
-; GFX10-NEXT:    v_readfirstlane_b32 s9, v9
-; GFX10-NEXT:    v_readfirstlane_b32 s10, v10
-; GFX10-NEXT:    v_readfirstlane_b32 s11, v11
-; GFX10-NEXT:    v_readfirstlane_b32 s12, v12
-; GFX10-NEXT:    v_readfirstlane_b32 s13, v13
-; GFX10-NEXT:    v_readfirstlane_b32 s14, v14
-; GFX10-NEXT:    v_readfirstlane_b32 s15, v15
-; GFX10-NEXT:    ; return to shader part epilog
+; GFX10PLUS-LABEL: s_saddsat_v16i32:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    v_add_nc_i32 v0, s0, s16 clamp
+; GFX10PLUS-NEXT:    v_add_nc_i32 v1, s1, s17 clamp
+; GFX10PLUS-NEXT:    v_add_nc_i32 v2, s2, s18 clamp
+; GFX10PLUS-NEXT:    v_add_nc_i32 v3, s3, s19 clamp
+; GFX10PLUS-NEXT:    v_add_nc_i32 v4, s4, s20 clamp
+; GFX10PLUS-NEXT:    v_add_nc_i32 v5, s5, s21 clamp
+; GFX10PLUS-NEXT:    v_add_nc_i32 v6, s6, s22 clamp
+; GFX10PLUS-NEXT:    v_add_nc_i32 v7, s7, s23 clamp
+; GFX10PLUS-NEXT:    v_add_nc_i32 v8, s8, s24 clamp
+; GFX10PLUS-NEXT:    v_add_nc_i32 v9, s9, s25 clamp
+; GFX10PLUS-NEXT:    v_add_nc_i32 v10, s10, s26 clamp
+; GFX10PLUS-NEXT:    v_add_nc_i32 v11, s11, s27 clamp
+; GFX10PLUS-NEXT:    v_add_nc_i32 v12, s12, s28 clamp
+; GFX10PLUS-NEXT:    v_add_nc_i32 v13, s13, s29 clamp
+; GFX10PLUS-NEXT:    v_add_nc_i32 v14, s14, s30 clamp
+; GFX10PLUS-NEXT:    v_add_nc_i32 v15, s15, s31 clamp
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s0, v0
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s1, v1
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s2, v2
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s3, v3
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s4, v4
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s5, v5
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s6, v6
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s7, v7
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s8, v8
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s9, v9
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s10, v10
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s11, v11
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s12, v12
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s13, v13
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s14, v14
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s15, v15
+; GFX10PLUS-NEXT:    ; return to shader part epilog
   %result = call <16 x i32> @llvm.sadd.sat.v16i32(<16 x i32> %lhs, <16 x i32> %rhs)
   ret <16 x i32> %result
 }
 
 define i16 @v_saddsat_i16(i16 %lhs, i16 %rhs) {
 ; GFX6-LABEL: v_saddsat_i16:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

 ; GFX8-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX9-LABEL: v_saddsat_i16:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    v_add_i16 v0, v0, v1 clamp
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX10-LABEL: v_saddsat_i16:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_add_nc_i16 v0, v0, v1 clamp
-; GFX10-NEXT:    s_setpc_b64 s[30:31]
+; GFX10PLUS-LABEL: v_saddsat_i16:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX10PLUS-NEXT:    v_add_nc_i16 v0, v0, v1 clamp
+; GFX10PLUS-NEXT:    s_setpc_b64 s[30:31]
   %result = call i16 @llvm.sadd.sat.i16(i16 %lhs, i16 %rhs)
   ret i16 %result
 }
 
 define amdgpu_ps i16 @s_saddsat_i16(i16 inreg %lhs, i16 inreg %rhs) {
 ; GFX6-LABEL: s_saddsat_i16:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_lshl_b32 s0, s0, 16

 ;
 ; GFX9-LABEL: s_saddsat_i16:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    v_mov_b32_e32 v0, s1
 ; GFX9-NEXT:    v_add_i16 v0, s0, v0 clamp
 ; GFX9-NEXT:    v_readfirstlane_b32 s0, v0
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
-; GFX10-LABEL: s_saddsat_i16:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_add_nc_i16 v0, s0, s1 clamp
-; GFX10-NEXT:    v_readfirstlane_b32 s0, v0
-; GFX10-NEXT:    ; return to shader part epilog
+; GFX10PLUS-LABEL: s_saddsat_i16:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    v_add_nc_i16 v0, s0, s1 clamp
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s0, v0
+; GFX10PLUS-NEXT:    ; return to shader part epilog
   %result = call i16 @llvm.sadd.sat.i16(i16 %lhs, i16 %rhs)
   ret i16 %result
 }
 
 define amdgpu_ps half @saddsat_i16_sv(i16 inreg %lhs, i16 %rhs) {
 ; GFX6-LABEL: saddsat_i16_sv:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_lshl_b32 s0, s0, 16

 ; GFX8-NEXT:    v_add_u16_e32 v0, s0, v0
 ; GFX8-NEXT:    ; return to shader part epilog
 ;
 ; GFX9-LABEL: saddsat_i16_sv:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    v_add_i16 v0, s0, v0 clamp
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
-; GFX10-LABEL: saddsat_i16_sv:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_add_nc_i16 v0, s0, v0 clamp
-; GFX10-NEXT:    ; return to shader part epilog
+; GFX10PLUS-LABEL: saddsat_i16_sv:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    v_add_nc_i16 v0, s0, v0 clamp
+; GFX10PLUS-NEXT:    ; return to shader part epilog
   %result = call i16 @llvm.sadd.sat.i16(i16 %lhs, i16 %rhs)
   %cast = bitcast i16 %result to half
   ret half %cast
 }
 
 define amdgpu_ps half @saddsat_i16_vs(i16 %lhs, i16 inreg %rhs) {
 ; GFX6-LABEL: saddsat_i16_vs:
 ; GFX6:       ; %bb.0:

 ; GFX8-NEXT:    v_add_u16_e32 v0, v0, v1
 ; GFX8-NEXT:    ; return to shader part epilog
 ;
 ; GFX9-LABEL: saddsat_i16_vs:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    v_add_i16 v0, v0, s0 clamp
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
-; GFX10-LABEL: saddsat_i16_vs:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_add_nc_i16 v0, v0, s0 clamp
-; GFX10-NEXT:    ; return to shader part epilog
+; GFX10PLUS-LABEL: saddsat_i16_vs:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    v_add_nc_i16 v0, v0, s0 clamp
+; GFX10PLUS-NEXT:    ; return to shader part epilog
   %result = call i16 @llvm.sadd.sat.i16(i16 %lhs, i16 %rhs)
   %cast = bitcast i16 %result to half
   ret half %cast
 }
 
 define <2 x i16> @v_saddsat_v2i16(<2 x i16> %lhs, <2 x i16> %rhs) {
 ; GFX6-LABEL: v_saddsat_v2i16:
 ; GFX6:       ; %bb.0:

 ; GFX8-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX9-LABEL: v_saddsat_v2i16:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    v_pk_add_i16 v0, v0, v1 clamp
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX10-LABEL: v_saddsat_v2i16:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_pk_add_i16 v0, v0, v1 clamp
-; GFX10-NEXT:    s_setpc_b64 s[30:31]
+; GFX10PLUS-LABEL: v_saddsat_v2i16:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX10PLUS-NEXT:    v_pk_add_i16 v0, v0, v1 clamp
+; GFX10PLUS-NEXT:    s_setpc_b64 s[30:31]
   %result = call <2 x i16> @llvm.sadd.sat.v2i16(<2 x i16> %lhs, <2 x i16> %rhs)
   ret <2 x i16> %result
 }
 
 define amdgpu_ps i32 @s_saddsat_v2i16(<2 x i16> inreg %lhs, <2 x i16> inreg %rhs) {
 ; GFX6-LABEL: s_saddsat_v2i16:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_lshl_b32 s0, s0, 16

 ;
 ; GFX9-LABEL: s_saddsat_v2i16:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    v_mov_b32_e32 v0, s1
 ; GFX9-NEXT:    v_pk_add_i16 v0, s0, v0 clamp
 ; GFX9-NEXT:    v_readfirstlane_b32 s0, v0
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
-; GFX10-LABEL: s_saddsat_v2i16:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_pk_add_i16 v0, s0, s1 clamp
-; GFX10-NEXT:    v_readfirstlane_b32 s0, v0
-; GFX10-NEXT:    ; return to shader part epilog
+; GFX10PLUS-LABEL: s_saddsat_v2i16:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    v_pk_add_i16 v0, s0, s1 clamp
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s0, v0
+; GFX10PLUS-NEXT:    ; return to shader part epilog
   %result = call <2 x i16> @llvm.sadd.sat.v2i16(<2 x i16> %lhs, <2 x i16> %rhs)
   %cast = bitcast <2 x i16> %result to i32
   ret i32 %cast
 }
 
 define amdgpu_ps float @saddsat_v2i16_sv(<2 x i16> inreg %lhs, <2 x i16> %rhs) {
 ; GFX6-LABEL: saddsat_v2i16_sv:
 ; GFX6:       ; %bb.0:

 ; GFX8-NEXT:    v_or_b32_e32 v0, v1, v0
 ; GFX8-NEXT:    ; return to shader part epilog
 ;
 ; GFX9-LABEL: saddsat_v2i16_sv:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    v_pk_add_i16 v0, s0, v0 clamp
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
-; GFX10-LABEL: saddsat_v2i16_sv:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_pk_add_i16 v0, s0, v0 clamp
-; GFX10-NEXT:    ; return to shader part epilog
+; GFX10PLUS-LABEL: saddsat_v2i16_sv:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    v_pk_add_i16 v0, s0, v0 clamp
+; GFX10PLUS-NEXT:    ; return to shader part epilog
   %result = call <2 x i16> @llvm.sadd.sat.v2i16(<2 x i16> %lhs, <2 x i16> %rhs)
   %cast = bitcast <2 x i16> %result to float
   ret float %cast
 }
 
 define amdgpu_ps float @saddsat_v2i16_vs(<2 x i16> %lhs, <2 x i16> inreg %rhs) {
 ; GFX6-LABEL: saddsat_v2i16_vs:
 ; GFX6:       ; %bb.0:

 ; GFX8-NEXT:    v_or_b32_e32 v0, v0, v1
 ; GFX8-NEXT:    ; return to shader part epilog
 ;
 ; GFX9-LABEL: saddsat_v2i16_vs:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    v_pk_add_i16 v0, v0, s0 clamp
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
-; GFX10-LABEL: saddsat_v2i16_vs:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_pk_add_i16 v0, v0, s0 clamp
-; GFX10-NEXT:    ; return to shader part epilog
+; GFX10PLUS-LABEL: saddsat_v2i16_vs:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    v_pk_add_i16 v0, v0, s0 clamp
+; GFX10PLUS-NEXT:    ; return to shader part epilog
   %result = call <2 x i16> @llvm.sadd.sat.v2i16(<2 x i16> %lhs, <2 x i16> %rhs)
   %cast = bitcast <2 x i16> %result to float
   ret float %cast
 }
 
 ; FIXME: v3i16 insert/extract
 ; define <3 x i16> @v_saddsat_v3i16(<3 x i16> %lhs, <3 x i16> %rhs) {
 ;   %result = call <3 x i16> @llvm.sadd.sat.v3i16(<3 x i16> %lhs, <3 x i16> %rhs)

 ;
 ; GFX9-LABEL: v_saddsat_v4i16:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    v_pk_add_i16 v0, v0, v2 clamp
 ; GFX9-NEXT:    v_pk_add_i16 v1, v1, v3 clamp
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX10-LABEL: v_saddsat_v4i16:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_pk_add_i16 v0, v0, v2 clamp
-; GFX10-NEXT:    v_pk_add_i16 v1, v1, v3 clamp
-; GFX10-NEXT:    s_setpc_b64 s[30:31]
+; GFX10PLUS-LABEL: v_saddsat_v4i16:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX10PLUS-NEXT:    v_pk_add_i16 v0, v0, v2 clamp
+; GFX10PLUS-NEXT:    v_pk_add_i16 v1, v1, v3 clamp
+; GFX10PLUS-NEXT:    s_setpc_b64 s[30:31]
   %result = call <4 x i16> @llvm.sadd.sat.v4i16(<4 x i16> %lhs, <4 x i16> %rhs)
   %cast = bitcast <4 x i16> %result to <2 x float>
   ret <2 x float> %cast
 }
 
 define amdgpu_ps <2 x i32> @s_saddsat_v4i16(<4 x i16> inreg %lhs, <4 x i16> inreg %rhs) {
 ; GFX6-LABEL: s_saddsat_v4i16:
 ; GFX6:       ; %bb.0:

 ; GFX9-NEXT:    v_mov_b32_e32 v0, s2
 ; GFX9-NEXT:    v_mov_b32_e32 v1, s3
 ; GFX9-NEXT:    v_pk_add_i16 v0, s0, v0 clamp
 ; GFX9-NEXT:    v_pk_add_i16 v1, s1, v1 clamp
 ; GFX9-NEXT:    v_readfirstlane_b32 s0, v0
 ; GFX9-NEXT:    v_readfirstlane_b32 s1, v1
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
-; GFX10-LABEL: s_saddsat_v4i16:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_pk_add_i16 v0, s0, s2 clamp
-; GFX10-NEXT:    v_pk_add_i16 v1, s1, s3 clamp
-; GFX10-NEXT:    v_readfirstlane_b32 s0, v0
-; GFX10-NEXT:    v_readfirstlane_b32 s1, v1
-; GFX10-NEXT:    ; return to shader part epilog
+; GFX10PLUS-LABEL: s_saddsat_v4i16:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    v_pk_add_i16 v0, s0, s2 clamp
+; GFX10PLUS-NEXT:    v_pk_add_i16 v1, s1, s3 clamp
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s0, v0
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s1, v1
+; GFX10PLUS-NEXT:    ; return to shader part epilog
   %result = call <4 x i16> @llvm.sadd.sat.v4i16(<4 x i16> %lhs, <4 x i16> %rhs)
   %cast = bitcast <4 x i16> %result to <2 x i32>
   ret <2 x i32> %cast
 }
 
 ; FIXME
 ; define <5 x i16> @v_saddsat_v5i16(<5 x i16> %lhs, <5 x i16> %rhs) {
 ;   %result = call <5 x i16> @llvm.sadd.sat.v5i16(<5 x i16> %lhs, <5 x i16> %rhs)

 ; GFX9-LABEL: v_saddsat_v6i16:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    v_pk_add_i16 v0, v0, v3 clamp
 ; GFX9-NEXT:    v_pk_add_i16 v1, v1, v4 clamp
 ; GFX9-NEXT:    v_pk_add_i16 v2, v2, v5 clamp
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX10-LABEL: v_saddsat_v6i16:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_pk_add_i16 v0, v0, v3 clamp
-; GFX10-NEXT:    v_pk_add_i16 v1, v1, v4 clamp
-; GFX10-NEXT:    v_pk_add_i16 v2, v2, v5 clamp
-; GFX10-NEXT:    s_setpc_b64 s[30:31]
+; GFX10PLUS-LABEL: v_saddsat_v6i16:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX10PLUS-NEXT:    v_pk_add_i16 v0, v0, v3 clamp
+; GFX10PLUS-NEXT:    v_pk_add_i16 v1, v1, v4 clamp
+; GFX10PLUS-NEXT:    v_pk_add_i16 v2, v2, v5 clamp
+; GFX10PLUS-NEXT:    s_setpc_b64 s[30:31]
   %result = call <6 x i16> @llvm.sadd.sat.v6i16(<6 x i16> %lhs, <6 x i16> %rhs)
   %cast = bitcast <6 x i16> %result to <3 x float>
   ret <3 x float> %cast
 }
 
 define amdgpu_ps <3 x i32> @s_saddsat_v6i16(<6 x i16> inreg %lhs, <6 x i16> inreg %rhs) {
 ; GFX6-LABEL: s_saddsat_v6i16:
 ; GFX6:       ; %bb.0:

 ; GFX9-NEXT:    v_pk_add_i16 v0, s0, v0 clamp
 ; GFX9-NEXT:    v_pk_add_i16 v1, s1, v1 clamp
 ; GFX9-NEXT:    v_pk_add_i16 v2, s2, v2 clamp
 ; GFX9-NEXT:    v_readfirstlane_b32 s0, v0
 ; GFX9-NEXT:    v_readfirstlane_b32 s1, v1
 ; GFX9-NEXT:    v_readfirstlane_b32 s2, v2
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
-; GFX10-LABEL: s_saddsat_v6i16:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_pk_add_i16 v0, s0, s3 clamp
-; GFX10-NEXT:    v_pk_add_i16 v1, s1, s4 clamp
-; GFX10-NEXT:    v_pk_add_i16 v2, s2, s5 clamp
-; GFX10-NEXT:    v_readfirstlane_b32 s0, v0
-; GFX10-NEXT:    v_readfirstlane_b32 s1, v1
-; GFX10-NEXT:    v_readfirstlane_b32 s2, v2
-; GFX10-NEXT:    ; return to shader part epilog
+; GFX10PLUS-LABEL: s_saddsat_v6i16:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    v_pk_add_i16 v0, s0, s3 clamp
+; GFX10PLUS-NEXT:    v_pk_add_i16 v1, s1, s4 clamp
+; GFX10PLUS-NEXT:    v_pk_add_i16 v2, s2, s5 clamp
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s0, v0
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s1, v1
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s2, v2
+; GFX10PLUS-NEXT:    ; return to shader part epilog
   %result = call <6 x i16> @llvm.sadd.sat.v6i16(<6 x i16> %lhs, <6 x i16> %rhs)
   %cast = bitcast <6 x i16> %result to <3 x i32>
   ret <3 x i32> %cast
 }
 
 define <4 x float> @v_saddsat_v8i16(<8 x i16> %lhs, <8 x i16> %rhs) {
 ; GFX6-LABEL: v_saddsat_v8i16:
 ; GFX6:       ; %bb.0:

 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    v_pk_add_i16 v0, v0, v4 clamp
 ; GFX9-NEXT:    v_pk_add_i16 v1, v1, v5 clamp
 ; GFX9-NEXT:    v_pk_add_i16 v2, v2, v6 clamp
 ; GFX9-NEXT:    v_pk_add_i16 v3, v3, v7 clamp
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX10-LABEL: v_saddsat_v8i16:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_pk_add_i16 v0, v0, v4 clamp
-; GFX10-NEXT:    v_pk_add_i16 v1, v1, v5 clamp
-; GFX10-NEXT:    v_pk_add_i16 v2, v2, v6 clamp
-; GFX10-NEXT:    v_pk_add_i16 v3, v3, v7 clamp
-; GFX10-NEXT:    s_setpc_b64 s[30:31]
+; GFX10PLUS-LABEL: v_saddsat_v8i16:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX10PLUS-NEXT:    v_pk_add_i16 v0, v0, v4 clamp
+; GFX10PLUS-NEXT:    v_pk_add_i16 v1, v1, v5 clamp
+; GFX10PLUS-NEXT:    v_pk_add_i16 v2, v2, v6 clamp
+; GFX10PLUS-NEXT:    v_pk_add_i16 v3, v3, v7 clamp
+; GFX10PLUS-NEXT:    s_setpc_b64 s[30:31]
   %result = call <8 x i16> @llvm.sadd.sat.v8i16(<8 x i16> %lhs, <8 x i16> %rhs)
   %cast = bitcast <8 x i16> %result to <4 x float>
   ret <4 x float> %cast
 }
 
 define amdgpu_ps <4 x i32> @s_saddsat_v8i16(<8 x i16> inreg %lhs, <8 x i16> inreg %rhs) {
 ; GFX6-LABEL: s_saddsat_v8i16:
 ; GFX6:       ; %bb.0:

 ; GFX9-NEXT:    v_pk_add_i16 v2, s2, v2 clamp
 ; GFX9-NEXT:    v_pk_add_i16 v3, s3, v3 clamp
 ; GFX9-NEXT:    v_readfirstlane_b32 s0, v0
 ; GFX9-NEXT:    v_readfirstlane_b32 s1, v1
 ; GFX9-NEXT:    v_readfirstlane_b32 s2, v2
 ; GFX9-NEXT:    v_readfirstlane_b32 s3, v3
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
-; GFX10-LABEL: s_saddsat_v8i16:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_pk_add_i16 v0, s0, s4 clamp
-; GFX10-NEXT:    v_pk_add_i16 v1, s1, s5 clamp
-; GFX10-NEXT:    v_pk_add_i16 v2, s2, s6 clamp
-; GFX10-NEXT:    v_pk_add_i16 v3, s3, s7 clamp
-; GFX10-NEXT:    v_readfirstlane_b32 s0, v0
-; GFX10-NEXT:    v_readfirstlane_b32 s1, v1
-; GFX10-NEXT:    v_readfirstlane_b32 s2, v2
-; GFX10-NEXT:    v_readfirstlane_b32 s3, v3
-; GFX10-NEXT:    ; return to shader part epilog
+; GFX10PLUS-LABEL: s_saddsat_v8i16:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    v_pk_add_i16 v0, s0, s4 clamp
+; GFX10PLUS-NEXT:    v_pk_add_i16 v1, s1, s5 clamp
+; GFX10PLUS-NEXT:    v_pk_add_i16 v2, s2, s6 clamp
+; GFX10PLUS-NEXT:    v_pk_add_i16 v3, s3, s7 clamp
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s0, v0
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s1, v1
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s2, v2
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s3, v3
+; GFX10PLUS-NEXT:    ; return to shader part epilog
   %result = call <8 x i16> @llvm.sadd.sat.v8i16(<8 x i16> %lhs, <8 x i16> %rhs)
   %cast = bitcast <8 x i16> %result to <4 x i32>
   ret <4 x i32> %cast
 }
 
 ; FIXME: i48 broken because i48 add broken
 ; define i48 @v_saddsat_i48(i48 %lhs, i48 %rhs) {
 ;   %result = call i48 @llvm.sadd.sat.i48(i48 %lhs, i48 %rhs)

 ; GFX10-NEXT:    s_mov_b32 s5, 0
 ; GFX10-NEXT:    v_ashrrev_i32_e32 v6, 31, v5
 ; GFX10-NEXT:    v_cmp_lt_i64_e32 vcc_lo, v[4:5], v[0:1]
 ; GFX10-NEXT:    v_add_co_ci_u32_e64 v1, s5, 0x80000000, v6, s5
 ; GFX10-NEXT:    s_xor_b32 vcc_lo, s4, vcc_lo
 ; GFX10-NEXT:    v_cndmask_b32_e32 v0, v4, v6, vcc_lo
 ; GFX10-NEXT:    v_cndmask_b32_e32 v1, v5, v1, vcc_lo
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_saddsat_i64:
+; GFX11:       ; %bb.0:
+; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT:    v_add_co_u32 v4, vcc_lo, v0, v2
+; GFX11-NEXT:    v_add_co_ci_u32_e32 v5, vcc_lo, v1, v3, vcc_lo
+; GFX11-NEXT:    v_cmp_gt_i64_e64 s0, 0, v[2:3]
+; GFX11-NEXT:    s_mov_b32 s1, 0
+; GFX11-NEXT:    v_ashrrev_i32_e32 v6, 31, v5
+; GFX11-NEXT:    v_cmp_lt_i64_e32 vcc_lo, v[4:5], v[0:1]
+; GFX11-NEXT:    v_add_co_ci_u32_e64 v1, s1, 0x80000000, v6, s1
+; GFX11-NEXT:    s_xor_b32 vcc_lo, s0, vcc_lo
+; GFX11-NEXT:    v_cndmask_b32_e32 v0, v4, v6, vcc_lo
+; GFX11-NEXT:    v_cndmask_b32_e32 v1, v5, v1, vcc_lo
+; GFX11-NEXT:    s_setpc_b64 s[30:31]
   %result = call i64 @llvm.sadd.sat.i64(i64 %lhs, i64 %rhs)
   ret i64 %result
 }
 
 define amdgpu_ps i64 @s_saddsat_i64(i64 inreg %lhs, i64 inreg %rhs) {
 ; GFX6-LABEL: s_saddsat_i64:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_add_u32 s4, s0, s2

 ; GFX9-NEXT:    v_mov_b32_e32 v2, s1
 ; GFX9-NEXT:    v_mov_b32_e32 v3, s5
 ; GFX9-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc
 ; GFX9-NEXT:    v_cndmask_b32_e32 v1, v3, v2, vcc
 ; GFX9-NEXT:    v_readfirstlane_b32 s0, v0
 ; GFX9-NEXT:    v_readfirstlane_b32 s1, v1
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
-; GFX10-LABEL: s_saddsat_i64:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    s_add_u32 s4, s0, s2
-; GFX10-NEXT:    s_addc_u32 s5, s1, s3
-; GFX10-NEXT:    v_cmp_lt_i64_e64 s2, s[2:3], 0
-; GFX10-NEXT:    v_cmp_lt_i64_e64 s1, s[4:5], s[0:1]
-; GFX10-NEXT:    s_mov_b32 s3, 0
-; GFX10-NEXT:    s_ashr_i32 s0, s5, 31
-; GFX10-NEXT:    v_mov_b32_e32 v0, s4
-; GFX10-NEXT:    v_mov_b32_e32 v1, s5
-; GFX10-NEXT:    s_xor_b32 s2, s2, s1
-; GFX10-NEXT:    s_cmp_lg_u32 s3, 0
-; GFX10-NEXT:    v_cndmask_b32_e64 v0, v0, s0, s2
-; GFX10-NEXT:    s_addc_u32 s1, s0, 0x80000000
-; GFX10-NEXT:    v_cndmask_b32_e64 v1, v1, s1, s2
-; GFX10-NEXT:    v_readfirstlane_b32 s0, v0
-; GFX10-NEXT:    v_readfirstlane_b32 s1, v1
-; GFX10-NEXT:    ; return to shader part epilog
+; GFX10PLUS-LABEL: s_saddsat_i64:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    s_add_u32 s4, s0, s2
+; GFX10PLUS-NEXT:    s_addc_u32 s5, s1, s3
+; GFX10PLUS-NEXT:    v_cmp_lt_i64_e64 s2, s[2:3], 0
+; GFX10PLUS-NEXT:    v_cmp_lt_i64_e64 s1, s[4:5], s[0:1]
+; GFX10PLUS-NEXT:    s_mov_b32 s3, 0
+; GFX10PLUS-NEXT:    s_ashr_i32 s0, s5, 31
+; GFX10PLUS-NEXT:    v_mov_b32_e32 v0, s4
+; GFX10PLUS-NEXT:    v_mov_b32_e32 v1, s5
+; GFX10PLUS-NEXT:    s_xor_b32 s2, s2, s1
+; GFX10PLUS-NEXT:    s_cmp_lg_u32 s3, 0
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v0, v0, s0, s2
+; GFX10PLUS-NEXT:    s_addc_u32 s1, s0, 0x80000000
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v1, v1, s1, s2
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s0, v0
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s1, v1
+; GFX10PLUS-NEXT:    ; return to shader part epilog
   %result = call i64 @llvm.sadd.sat.i64(i64 %lhs, i64 %rhs)
   ret i64 %result
 }
 
 define amdgpu_ps <2 x float> @saddsat_i64_sv(i64 inreg %lhs, i64 %rhs) {
 ; GFX6-LABEL: saddsat_i64_sv:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    v_mov_b32_e32 v3, s1

 ; GFX9-NEXT:    v_bfrev_b32_e32 v1, 1
 ; GFX9-NEXT:    s_mov_b64 s[2:3], 0
 ; GFX9-NEXT:    v_addc_co_u32_e64 v1, s[2:3], v0, v1, s[2:3]
 ; GFX9-NEXT:    s_xor_b64 vcc, s[0:1], vcc
 ; GFX9-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc
 ; GFX9-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
-; GFX10-LABEL: saddsat_i64_sv:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_add_co_u32 v2, vcc_lo, s0, v0
-; GFX10-NEXT:    v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
-; GFX10-NEXT:    v_ashrrev_i32_e32 v4, 31, v3
-; GFX10-NEXT:    v_cmp_gt_i64_e32 vcc_lo, s[0:1], v[2:3]
-; GFX10-NEXT:    v_cmp_gt_i64_e64 s0, 0, v[0:1]
-; GFX10-NEXT:    s_mov_b32 s1, 0
-; GFX10-NEXT:    v_add_co_ci_u32_e64 v1, s1, 0x80000000, v4, s1
-; GFX10-NEXT:    s_xor_b32 vcc_lo, s0, vcc_lo
-; GFX10-NEXT:    v_cndmask_b32_e32 v0, v2, v4, vcc_lo
-; GFX10-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc_lo
-; GFX10-NEXT:    ; return to shader part epilog
+; GFX10PLUS-LABEL: saddsat_i64_sv:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    v_add_co_u32 v2, vcc_lo, s0, v0
+; GFX10PLUS-NEXT:    v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
+; GFX10PLUS-NEXT:    v_ashrrev_i32_e32 v4, 31, v3
+; GFX10PLUS-NEXT:    v_cmp_gt_i64_e32 vcc_lo, s[0:1], v[2:3]
+; GFX10PLUS-NEXT:    v_cmp_gt_i64_e64 s0, 0, v[0:1]
+; GFX10PLUS-NEXT:    s_mov_b32 s1, 0
+; GFX10PLUS-NEXT:    v_add_co_ci_u32_e64 v1, s1, 0x80000000, v4, s1
+; GFX10PLUS-NEXT:    s_xor_b32 vcc_lo, s0, vcc_lo
+; GFX10PLUS-NEXT:    v_cndmask_b32_e32 v0, v2, v4, vcc_lo
+; GFX10PLUS-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc_lo
+; GFX10PLUS-NEXT:    ; return to shader part epilog
   %result = call i64 @llvm.sadd.sat.i64(i64 %lhs, i64 %rhs)
   %cast = bitcast i64 %result to <2 x float>
   ret <2 x float> %cast
 }
 
 define amdgpu_ps <2 x float> @saddsat_i64_vs(i64 %lhs, i64 inreg %rhs) {
 ; GFX6-LABEL: saddsat_i64_vs:
 ; GFX6:       ; %bb.0:

 ; GFX9-NEXT:    v_bfrev_b32_e32 v1, 1
 ; GFX9-NEXT:    s_mov_b64 s[0:1], 0
 ; GFX9-NEXT:    v_addc_co_u32_e64 v1, s[0:1], v0, v1, s[0:1]
 ; GFX9-NEXT:    s_xor_b64 vcc, s[2:3], vcc
 ; GFX9-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc
 ; GFX9-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
-; GFX10-LABEL: saddsat_i64_vs:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_add_co_u32 v2, vcc_lo, v0, s0
-; GFX10-NEXT:    v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
-; GFX10-NEXT:    v_cmp_lt_i64_e64 s1, s[0:1], 0
-; GFX10-NEXT:    s_mov_b32 s0, 0
-; GFX10-NEXT:    v_ashrrev_i32_e32 v4, 31, v3
-; GFX10-NEXT:    v_cmp_lt_i64_e32 vcc_lo, v[2:3], v[0:1]
-; GFX10-NEXT:    v_add_co_ci_u32_e64 v1, s0, 0x80000000, v4, s0
-; GFX10-NEXT:    s_xor_b32 vcc_lo, s1, vcc_lo
-; GFX10-NEXT:    v_cndmask_b32_e32 v0, v2, v4, vcc_lo
-; GFX10-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc_lo
-; GFX10-NEXT:    ; return to shader part epilog
+; GFX10PLUS-LABEL: saddsat_i64_vs:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    v_add_co_u32 v2, vcc_lo, v0, s0
+; GFX10PLUS-NEXT:    v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
+; GFX10PLUS-NEXT:    v_cmp_lt_i64_e64 s1, s[0:1], 0
+; GFX10PLUS-NEXT:    s_mov_b32 s0, 0
+; GFX10PLUS-NEXT:    v_ashrrev_i32_e32 v4, 31, v3
+; GFX10PLUS-NEXT:    v_cmp_lt_i64_e32 vcc_lo, v[2:3], v[0:1]
+; GFX10PLUS-NEXT:    v_add_co_ci_u32_e64 v1, s0, 0x80000000, v4, s0
+; GFX10PLUS-NEXT:    s_xor_b32 vcc_lo, s1, vcc_lo
+; GFX10PLUS-NEXT:    v_cndmask_b32_e32 v0, v2, v4, vcc_lo
+; GFX10PLUS-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc_lo
+; GFX10PLUS-NEXT:    ; return to shader part epilog
   %result = call i64 @llvm.sadd.sat.i64(i64 %lhs, i64 %rhs)
   %cast = bitcast i64 %result to <2 x float>
   ret <2 x float> %cast
 }
 
 define <2 x i64> @v_saddsat_v2i64(<2 x i64> %lhs, <2 x i64> %rhs) {
 ; GFX6-LABEL: v_saddsat_v2i64:
 ; GFX6:       ; %bb.0:

 ; GFX10-NEXT:    v_add_co_ci_u32_e64 v3, s5, 0x80000000, v4, s5
 ; GFX10-NEXT:    s_xor_b32 vcc_lo, s4, vcc_lo
 ; GFX10-NEXT:    v_cndmask_b32_e32 v0, v8, v0, vcc_lo
 ; GFX10-NEXT:    v_cndmask_b32_e32 v1, v9, v1, vcc_lo
 ; GFX10-NEXT:    s_xor_b32 vcc_lo, s7, s6
 ; GFX10-NEXT:    v_cndmask_b32_e32 v2, v10, v4, vcc_lo
 ; GFX10-NEXT:    v_cndmask_b32_e32 v3, v11, v3, vcc_lo
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_saddsat_v2i64:
+; GFX11:       ; %bb.0:
+; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT:    v_add_co_u32 v8, vcc_lo, v0, v4
+; GFX11-NEXT:    v_add_co_ci_u32_e32 v9, vcc_lo, v1, v5, vcc_lo
+; GFX11-NEXT:    v_add_co_u32 v10, vcc_lo, v2, v6
+; GFX11-NEXT:    v_add_co_ci_u32_e32 v11, vcc_lo, v3, v7, vcc_lo
+; GFX11-NEXT:    v_cmp_lt_i64_e32 vcc_lo, v[8:9], v[0:1]
+; GFX11-NEXT:    v_ashrrev_i32_e32 v0, 31, v9
+; GFX11-NEXT:    s_mov_b32 s1, 0
+; GFX11-NEXT:    v_cmp_gt_i64_e64 s0, 0, v[4:5]
+; GFX11-NEXT:    v_ashrrev_i32_e32 v4, 31, v11
+; GFX11-NEXT:    v_cmp_gt_i64_e64 s3, 0, v[6:7]
+; GFX11-NEXT:    v_add_co_ci_u32_e64 v1, s2, 0x80000000, v0, s1
+; GFX11-NEXT:    v_cmp_lt_i64_e64 s2, v[10:11], v[2:3]
+; GFX11-NEXT:    v_add_co_ci_u32_e64 v3, s1, 0x80000000, v4, s1
+; GFX11-NEXT:    s_xor_b32 vcc_lo, s0, vcc_lo
+; GFX11-NEXT:    v_cndmask_b32_e32 v0, v8, v0, vcc_lo
+; GFX11-NEXT:    v_cndmask_b32_e32 v1, v9, v1, vcc_lo
+; GFX11-NEXT:    s_xor_b32 vcc_lo, s3, s2
+; GFX11-NEXT:    v_cndmask_b32_e32 v2, v10, v4, vcc_lo
+; GFX11-NEXT:    v_cndmask_b32_e32 v3, v11, v3, vcc_lo
+; GFX11-NEXT:    s_setpc_b64 s[30:31]
   %result = call <2 x i64> @llvm.sadd.sat.v2i64(<2 x i64> %lhs, <2 x i64> %rhs)
   ret <2 x i64> %result
 }
 
 define amdgpu_ps <2 x i64> @s_saddsat_v2i64(<2 x i64> inreg %lhs, <2 x i64> inreg %rhs) {
 ; GFX6-LABEL: s_saddsat_v2i64:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_add_u32 s8, s0, s4

 ; GFX9-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc
 ; GFX9-NEXT:    v_cndmask_b32_e32 v1, v5, v3, vcc
 ; GFX9-NEXT:    v_readfirstlane_b32 s0, v4
 ; GFX9-NEXT:    v_readfirstlane_b32 s1, v2
 ; GFX9-NEXT:    v_readfirstlane_b32 s2, v0
 ; GFX9-NEXT:    v_readfirstlane_b32 s3, v1
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
-; GFX10-LABEL: s_saddsat_v2i64:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    s_add_u32 s8, s0, s4
-; GFX10-NEXT:    s_addc_u32 s9, s1, s5
-; GFX10-NEXT:    v_cmp_lt_i64_e64 s4, s[4:5], 0
-; GFX10-NEXT:    v_cmp_lt_i64_e64 s1, s[8:9], s[0:1]
-; GFX10-NEXT:    s_mov_b32 s10, 0
-; GFX10-NEXT:    s_ashr_i32 s0, s9, 31
-; GFX10-NEXT:    v_mov_b32_e32 v0, s8
-; GFX10-NEXT:    v_mov_b32_e32 v1, s9
-; GFX10-NEXT:    s_xor_b32 s8, s4, s1
-; GFX10-NEXT:    s_cmp_lg_u32 s10, 0
-; GFX10-NEXT:    v_cndmask_b32_e64 v0, v0, s0, s8
-; GFX10-NEXT:    s_addc_u32 s1, s0, 0x80000000
-; GFX10-NEXT:    s_add_u32 s4, s2, s6
-; GFX10-NEXT:    s_addc_u32 s5, s3, s7
-; GFX10-NEXT:    v_mov_b32_e32 v2, s4
-; GFX10-NEXT:    v_cmp_lt_i64_e64 s2, s[4:5], s[2:3]
-; GFX10-NEXT:    v_cmp_lt_i64_e64 s3, s[6:7], 0
-; GFX10-NEXT:    s_ashr_i32 s0, s5, 31
-; GFX10-NEXT:    v_mov_b32_e32 v3, s5
-; GFX10-NEXT:    v_cndmask_b32_e64 v1, v1, s1, s8
-; GFX10-NEXT:    s_xor_b32 s2, s3, s2
-; GFX10-NEXT:    s_cmp_lg_u32 s10, 0
-; GFX10-NEXT:    v_cndmask_b32_e64 v2, v2, s0, s2
-; GFX10-NEXT:    s_addc_u32 s1, s0, 0x80000000
-; GFX10-NEXT:    v_readfirstlane_b32 s0, v0
-; GFX10-NEXT:    v_cndmask_b32_e64 v3, v3, s1, s2
-; GFX10-NEXT:    v_readfirstlane_b32 s1, v1
-; GFX10-NEXT:    v_readfirstlane_b32 s2, v2
-; GFX10-NEXT:    v_readfirstlane_b32 s3, v3
-; GFX10-NEXT:    ; return to shader part epilog
+; GFX10PLUS-LABEL: s_saddsat_v2i64:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    s_add_u32 s8, s0, s4
+; GFX10PLUS-NEXT:    s_addc_u32 s9, s1, s5
+; GFX10PLUS-NEXT:    v_cmp_lt_i64_e64 s4, s[4:5], 0
+; GFX10PLUS-NEXT:    v_cmp_lt_i64_e64 s1, s[8:9], s[0:1]
+; GFX10PLUS-NEXT:    s_mov_b32 s10, 0
+; GFX10PLUS-NEXT:    s_ashr_i32 s0, s9, 31
+; GFX10PLUS-NEXT:    v_mov_b32_e32 v0, s8
+; GFX10PLUS-NEXT:    v_mov_b32_e32 v1, s9
+; GFX10PLUS-NEXT:    s_xor_b32 s8, s4, s1
+; GFX10PLUS-NEXT:    s_cmp_lg_u32 s10, 0
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v0, v0, s0, s8
+; GFX10PLUS-NEXT:    s_addc_u32 s1, s0, 0x80000000
+; GFX10PLUS-NEXT:    s_add_u32 s4, s2, s6
+; GFX10PLUS-NEXT:    s_addc_u32 s5, s3, s7
+; GFX10PLUS-NEXT:    v_mov_b32_e32 v2, s4
+; GFX10PLUS-NEXT:    v_cmp_lt_i64_e64 s2, s[4:5], s[2:3]
+; GFX10PLUS-NEXT:    v_cmp_lt_i64_e64 s3, s[6:7], 0
+; GFX10PLUS-NEXT:    s_ashr_i32 s0, s5, 31
+; GFX10PLUS-NEXT:    v_mov_b32_e32 v3, s5
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v1, v1, s1, s8
+; GFX10PLUS-NEXT:    s_xor_b32 s2, s3, s2
+; GFX10PLUS-NEXT:    s_cmp_lg_u32 s10, 0
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v2, v2, s0, s2
+; GFX10PLUS-NEXT:    s_addc_u32 s1, s0, 0x80000000
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s0, v0
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v3, v3, s1, s2
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s1, v1
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s2, v2
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s3, v3
+; GFX10PLUS-NEXT:    ; return to shader part epilog
   %result = call <2 x i64> @llvm.sadd.sat.v2i64(<2 x i64> %lhs, <2 x i64> %rhs)
   ret <2 x i64> %result
 }
 
 define amdgpu_ps i128 @s_saddsat_i128(i128 inreg %lhs, i128 inreg %rhs) {
 ; GFX6-LABEL: s_saddsat_i128:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_add_u32 s4, s0, s4

 ; GFX9-NEXT:    v_cndmask_b32_e32 v2, v4, v2, vcc
 ; GFX9-NEXT:    v_cndmask_b32_e32 v3, v5, v3, vcc
 ; GFX9-NEXT:    v_readfirstlane_b32 s0, v0
 ; GFX9-NEXT:    v_readfirstlane_b32 s1, v1
 ; GFX9-NEXT:    v_readfirstlane_b32 s2, v2
 ; GFX9-NEXT:    v_readfirstlane_b32 s3, v3
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
-; GFX10-LABEL: s_saddsat_i128:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    s_add_u32 s4, s0, s4
-; GFX10-NEXT:    s_addc_u32 s5, s1, s5
-; GFX10-NEXT:    s_addc_u32 s8, s2, s6
-; GFX10-NEXT:    v_cmp_lt_u64_e64 s0, s[4:5], s[0:1]
-; GFX10-NEXT:    s_addc_u32 s9, s3, s7
-; GFX10-NEXT:    s_cmp_eq_u64 s[8:9], s[2:3]
-; GFX10-NEXT:    v_mov_b32_e32 v3, s9
-; GFX10-NEXT:    s_cselect_b32 s10, 1, 0
-; GFX10-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
-; GFX10-NEXT:    v_cmp_lt_i64_e64 s0, s[8:9], s[2:3]
-; GFX10-NEXT:    v_cmp_lt_i64_e64 s2, s[6:7], 0
-; GFX10-NEXT:    v_cndmask_b32_e64 v1, 0, 1, s0
-; GFX10-NEXT:    s_and_b32 s0, 1, s10
-; GFX10-NEXT:    s_cmp_eq_u64 s[6:7], 0
-; GFX10-NEXT:    v_cndmask_b32_e64 v2, 0, 1, s2
-; GFX10-NEXT:    s_cselect_b32 s1, 1, 0
-; GFX10-NEXT:    v_cmp_ne_u32_e64 vcc_lo, 0, s0
-; GFX10-NEXT:    s_and_b32 s1, 1, s1
-; GFX10-NEXT:    v_cmp_ne_u32_e64 s0, 0, s1
-; GFX10-NEXT:    s_mov_b32 s1, 0
-; GFX10-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc_lo
-; GFX10-NEXT:    v_cndmask_b32_e64 v1, v2, 0, s0
-; GFX10-NEXT:    s_ashr_i32 s0, s9, 31
-; GFX10-NEXT:    s_cmp_lg_u32 s1, 0
-; GFX10-NEXT:    v_mov_b32_e32 v2, s5
-; GFX10-NEXT:    s_addc_u32 s1, s0, 0
-; GFX10-NEXT:    v_xor_b32_e32 v0, v1, v0
-; GFX10-NEXT:    v_mov_b32_e32 v1, s4
-; GFX10-NEXT:    s_addc_u32 s2, s0, 0
-; GFX10-NEXT:    s_addc_u32 s3, s0, 0x80000000
-; GFX10-NEXT:    v_and_b32_e32 v0, 1, v0
-; GFX10-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v0
-; GFX10-NEXT:    v_mov_b32_e32 v0, s8
-; GFX10-NEXT:    v_cndmask_b32_e64 v1, v1, s0, vcc_lo
-; GFX10-NEXT:    v_cndmask_b32_e64 v2, v2, s1, vcc_lo
-; GFX10-NEXT:    v_cndmask_b32_e64 v0, v0, s2, vcc_lo
-; GFX10-NEXT:    v_cndmask_b32_e64 v3, v3, s3, vcc_lo
-; GFX10-NEXT:    v_readfirstlane_b32 s0, v1
-; GFX10-NEXT:    v_readfirstlane_b32 s1, v2
-; GFX10-NEXT:    v_readfirstlane_b32 s2, v0
-; GFX10-NEXT:    v_readfirstlane_b32 s3, v3
-; GFX10-NEXT:    ; return to shader part epilog
+; GFX10PLUS-LABEL: s_saddsat_i128:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    s_add_u32 s4, s0, s4
+; GFX10PLUS-NEXT:    s_addc_u32 s5, s1, s5
+; GFX10PLUS-NEXT:    s_addc_u32 s8, s2, s6
+; GFX10PLUS-NEXT:    v_cmp_lt_u64_e64 s0, s[4:5], s[0:1]
+; GFX10PLUS-NEXT:    s_addc_u32 s9, s3, s7
+; GFX10PLUS-NEXT:    s_cmp_eq_u64 s[8:9], s[2:3]
+; GFX10PLUS-NEXT:    v_mov_b32_e32 v3, s9
+; GFX10PLUS-NEXT:    s_cselect_b32 s10, 1, 0
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; GFX10PLUS-NEXT:    v_cmp_lt_i64_e64 s0, s[8:9], s[2:3]
+; GFX10PLUS-NEXT:    v_cmp_lt_i64_e64 s2, s[6:7], 0
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v1, 0, 1, s0
+; GFX10PLUS-NEXT:    s_and_b32 s0, 1, s10
+; GFX10PLUS-NEXT:    s_cmp_eq_u64 s[6:7], 0
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v2, 0, 1, s2
+; GFX10PLUS-NEXT:    s_cselect_b32 s1, 1, 0
+; GFX10PLUS-NEXT:    v_cmp_ne_u32_e64 vcc_lo, 0, s0
+; GFX10PLUS-NEXT:    s_and_b32 s1, 1, s1
+; GFX10PLUS-NEXT:    v_cmp_ne_u32_e64 s0, 0, s1
+; GFX10PLUS-NEXT:    s_mov_b32 s1, 0
+; GFX10PLUS-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc_lo
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v1, v2, 0, s0
+; GFX10PLUS-NEXT:    s_ashr_i32 s0, s9, 31
+; GFX10PLUS-NEXT:    s_cmp_lg_u32 s1, 0
+; GFX10PLUS-NEXT:    v_mov_b32_e32 v2, s5
+; GFX10PLUS-NEXT:    s_addc_u32 s1, s0, 0
+; GFX10PLUS-NEXT:    v_xor_b32_e32 v0, v1, v0
+; GFX10PLUS-NEXT:    v_mov_b32_e32 v1, s4
+; GFX10PLUS-NEXT:    s_addc_u32 s2, s0, 0
+; GFX10PLUS-NEXT:    s_addc_u32 s3, s0, 0x80000000
+; GFX10PLUS-NEXT:    v_and_b32_e32 v0, 1, v0
+; GFX10PLUS-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v0
+; GFX10PLUS-NEXT:    v_mov_b32_e32 v0, s8
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v1, v1, s0, vcc_lo
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v2, v2, s1, vcc_lo
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v0, v0, s2, vcc_lo
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v3, v3, s3, vcc_lo
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s0, v1
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s1, v2
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s2, v0
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s3, v3
+; GFX10PLUS-NEXT:    ; return to shader part epilog
   %result = call i128 @llvm.sadd.sat.i128(i128 %lhs, i128 %rhs)
   ret i128 %result
 }
 
 define amdgpu_ps <4 x float> @saddsat_i128_sv(i128 inreg %lhs, i128 %rhs) {
 ; GFX6-LABEL: saddsat_i128_sv:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    v_mov_b32_e32 v4, s1

 ; GFX9-NEXT:    v_and_b32_e32 v2, 1, v2
 ; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v2
 ; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
 ; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v6, vcc
 ; GFX9-NEXT:    v_cndmask_b32_e32 v2, v4, v8, vcc
 ; GFX9-NEXT:    v_cndmask_b32_e32 v3, v5, v7, vcc
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
-; GFX10-LABEL: saddsat_i128_sv:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_add_co_u32 v0, vcc_lo, s0, v0
-; GFX10-NEXT:    v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
-; GFX10-NEXT:    v_add_co_ci_u32_e32 v4, vcc_lo, s2, v2, vcc_lo
-; GFX10-NEXT:    v_add_co_ci_u32_e32 v5, vcc_lo, s3, v3, vcc_lo
-; GFX10-NEXT:    v_cmp_gt_u64_e32 vcc_lo, s[0:1], v[0:1]
-; GFX10-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc_lo
-; GFX10-NEXT:    v_cmp_gt_i64_e32 vcc_lo, s[2:3], v[4:5]
-; GFX10-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc_lo
-; GFX10-NEXT:    v_cmp_gt_i64_e32 vcc_lo, 0, v[2:3]
-; GFX10-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc_lo
-; GFX10-NEXT:    v_cmp_eq_u64_e32 vcc_lo, s[2:3], v[4:5]
-; GFX10-NEXT:    v_cndmask_b32_e32 v6, v7, v6, vcc_lo
-; GFX10-NEXT:    v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
-; GFX10-NEXT:    v_ashrrev_i32_e32 v3, 31, v5
-; GFX10-NEXT:    v_cndmask_b32_e64 v2, v8, 0, vcc_lo
-; GFX10-NEXT:    s_mov_b32 vcc_lo, 0
-; GFX10-NEXT:    v_xor_b32_e32 v2, v2, v6
-; GFX10-NEXT:    v_add_co_ci_u32_e32 v6, vcc_lo, 0, v3, vcc_lo
-; GFX10-NEXT:    v_and_b32_e32 v2, 1, v2
-; GFX10-NEXT:    v_cmp_ne_u32_e64 s0, 0, v2
-; GFX10-NEXT:    v_add_co_ci_u32_e32 v2, vcc_lo, 0, v3, vcc_lo
-; GFX10-NEXT:    v_add_co_ci_u32_e32 v7, vcc_lo, 0x80000000, v3, vcc_lo
-; GFX10-NEXT:    v_cndmask_b32_e64 v0, v0, v3, s0
-; GFX10-NEXT:    v_cndmask_b32_e64 v1, v1, v6, s0
-; GFX10-NEXT:    v_cndmask_b32_e64 v2, v4, v2, s0
-; GFX10-NEXT:    v_cndmask_b32_e64 v3, v5, v7, s0
-; GFX10-NEXT:    ; return to shader part epilog
+; GFX10PLUS-LABEL: saddsat_i128_sv:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    v_add_co_u32 v0, vcc_lo, s0, v0
+; GFX10PLUS-NEXT:    v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
+; GFX10PLUS-NEXT:    v_add_co_ci_u32_e32 v4, vcc_lo, s2, v2, vcc_lo
+; GFX10PLUS-NEXT:    v_add_co_ci_u32_e32 v5, vcc_lo, s3, v3, vcc_lo
+; GFX10PLUS-NEXT:    v_cmp_gt_u64_e32 vcc_lo, s[0:1], v[0:1]
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc_lo
+; GFX10PLUS-NEXT:    v_cmp_gt_i64_e32 vcc_lo, s[2:3], v[4:5]
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc_lo
+; GFX10PLUS-NEXT:    v_cmp_gt_i64_e32 vcc_lo, 0, v[2:3]
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc_lo
+; GFX10PLUS-NEXT:    v_cmp_eq_u64_e32 vcc_lo, s[2:3], v[4:5]
+; GFX10PLUS-NEXT:    v_cndmask_b32_e32 v6, v7, v6, vcc_lo
+; GFX10PLUS-NEXT:    v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
+; GFX10PLUS-NEXT:    v_ashrrev_i32_e32 v3, 31, v5
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v2, v8, 0, vcc_lo
+; GFX10PLUS-NEXT:    s_mov_b32 vcc_lo, 0
+; GFX10PLUS-NEXT:    v_xor_b32_e32 v2, v2, v6
+; GFX10PLUS-NEXT:    v_add_co_ci_u32_e32 v6, vcc_lo, 0, v3, vcc_lo
+; GFX10PLUS-NEXT:    v_and_b32_e32 v2, 1, v2
+; GFX10PLUS-NEXT:    v_cmp_ne_u32_e64 s0, 0, v2
+; GFX10PLUS-NEXT:    v_add_co_ci_u32_e32 v2, vcc_lo, 0, v3, vcc_lo
+; GFX10PLUS-NEXT:    v_add_co_ci_u32_e32 v7, vcc_lo, 0x80000000, v3, vcc_lo
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v0, v0, v3, s0
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v1, v1, v6, s0
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v2, v4, v2, s0
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v3, v5, v7, s0
+; GFX10PLUS-NEXT:    ; return to shader part epilog
   %result = call i128 @llvm.sadd.sat.i128(i128 %lhs, i128 %rhs)
   %cast = bitcast i128 %result to <4 x float>
   ret <4 x float> %cast
 }
 
 define amdgpu_ps <4 x float> @saddsat_i128_vs(i128 %lhs, i128 inreg %rhs) {
 ; GFX6-LABEL: saddsat_i128_vs:
 ; GFX6:       ; %bb.0:

 ; GFX9-NEXT:    v_and_b32_e32 v0, 1, v0
 ; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
 ; GFX9-NEXT:    v_cndmask_b32_e32 v0, v4, v1, vcc
 ; GFX9-NEXT:    v_cndmask_b32_e32 v1, v5, v2, vcc
 ; GFX9-NEXT:    v_cndmask_b32_e32 v2, v6, v8, vcc
 ; GFX9-NEXT:    v_cndmask_b32_e32 v3, v7, v3, vcc
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
-; GFX10-LABEL: saddsat_i128_vs:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_add_co_u32 v4, vcc_lo, v0, s0
-; GFX10-NEXT:    v_add_co_ci_u32_e32 v5, vcc_lo, s1, v1, vcc_lo
-; GFX10-NEXT:    v_add_co_ci_u32_e32 v6, vcc_lo, s2, v2, vcc_lo
-; GFX10-NEXT:    v_add_co_ci_u32_e32 v7, vcc_lo, s3, v3, vcc_lo
-; GFX10-NEXT:    v_cmp_lt_u64_e32 vcc_lo, v[4:5], v[0:1]
-; GFX10-NEXT:    s_cmp_eq_u64 s[2:3], 0
-; GFX10-NEXT:    v_cmp_lt_i64_e64 s1, s[2:3], 0
-; GFX10-NEXT:    s_cselect_b32 s0, 1, 0
-; GFX10-NEXT:    s_and_b32 s0, 1, s0
-; GFX10-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX10-NEXT:    v_cmp_lt_i64_e32 vcc_lo, v[6:7], v[2:3]
-; GFX10-NEXT:    v_cndmask_b32_e64 v8, 0, 1, s1
-; GFX10-NEXT:    v_cmp_ne_u32_e64 s0, 0, s0
-; GFX10-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc_lo
-; GFX10-NEXT:    v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[2:3]
-; GFX10-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc_lo
-; GFX10-NEXT:    v_cndmask_b32_e64 v1, v8, 0, s0
-; GFX10-NEXT:    s_mov_b32 vcc_lo, 0
-; GFX10-NEXT:    v_xor_b32_e32 v0, v1, v0
-; GFX10-NEXT:    v_ashrrev_i32_e32 v1, 31, v7
-; GFX10-NEXT:    v_and_b32_e32 v0, 1, v0
-; GFX10-NEXT:    v_add_co_ci_u32_e32 v2, vcc_lo, 0, v1, vcc_lo
-; GFX10-NEXT:    v_add_co_ci_u32_e32 v3, vcc_lo, 0, v1, vcc_lo
-; GFX10-NEXT:    v_cmp_ne_u32_e64 s0, 0, v0
-; GFX10-NEXT:    v_add_co_ci_u32_e32 v8, vcc_lo, 0x80000000, v1, vcc_lo
-; GFX10-NEXT:    v_cndmask_b32_e64 v0, v4, v1, s0
-; GFX10-NEXT:    v_cndmask_b32_e64 v1, v5, v2, s0
-; GFX10-NEXT:    v_cndmask_b32_e64 v2, v6, v3, s0
-; GFX10-NEXT:    v_cndmask_b32_e64 v3, v7, v8, s0
-; GFX10-NEXT:    ; return to shader part epilog
+; GFX10PLUS-LABEL: saddsat_i128_vs:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    v_add_co_u32 v4, vcc_lo, v0, s0
+; GFX10PLUS-NEXT:    v_add_co_ci_u32_e32 v5, vcc_lo, s1, v1, vcc_lo
+; GFX10PLUS-NEXT:    v_add_co_ci_u32_e32 v6, vcc_lo, s2, v2, vcc_lo
+; GFX10PLUS-NEXT:    v_add_co_ci_u32_e32 v7, vcc_lo, s3, v3, vcc_lo
+; GFX10PLUS-NEXT:    v_cmp_lt_u64_e32 vcc_lo, v[4:5], v[0:1]
+; GFX10PLUS-NEXT:    s_cmp_eq_u64 s[2:3], 0
+; GFX10PLUS-NEXT:    v_cmp_lt_i64_e64 s1, s[2:3], 0
+; GFX10PLUS-NEXT:    s_cselect_b32 s0, 1, 0
+; GFX10PLUS-NEXT:    s_and_b32 s0, 1, s0
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX10PLUS-NEXT:    v_cmp_lt_i64_e32 vcc_lo, v[6:7], v[2:3]
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v8, 0, 1, s1
+; GFX10PLUS-NEXT:    v_cmp_ne_u32_e64 s0, 0, s0
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; GFX10PLUS-NEXT:    v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[2:3]
+; GFX10PLUS-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc_lo
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v1, v8, 0, s0
+; GFX10PLUS-NEXT:    s_mov_b32 vcc_lo, 0
+; GFX10PLUS-NEXT:    v_xor_b32_e32 v0, v1, v0
+; GFX10PLUS-NEXT:    v_ashrrev_i32_e32 v1, 31, v7
+; GFX10PLUS-NEXT:    v_and_b32_e32 v0, 1, v0
+; GFX10PLUS-NEXT:    v_add_co_ci_u32_e32 v2, vcc_lo, 0, v1, vcc_lo
+; GFX10PLUS-NEXT:    v_add_co_ci_u32_e32 v3, vcc_lo, 0, v1, vcc_lo
+; GFX10PLUS-NEXT:    v_cmp_ne_u32_e64 s0, 0, v0
+; GFX10PLUS-NEXT:    v_add_co_ci_u32_e32 v8, vcc_lo, 0x80000000, v1, vcc_lo
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v0, v4, v1, s0
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v1, v5, v2, s0
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v2, v6, v3, s0
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v3, v7, v8, s0
+; GFX10PLUS-NEXT:    ; return to shader part epilog
   %result = call i128 @llvm.sadd.sat.i128(i128 %lhs, i128 %rhs)
   %cast = bitcast i128 %result to <4 x float>
   ret <4 x float> %cast
 }
 
 define <2 x i128> @v_saddsat_v2i128(<2 x i128> %lhs, <2 x i128> %rhs) {
 ; GFX6-LABEL: v_saddsat_v2i128:
 ; GFX6:       ; %bb.0:

 ; GFX10-NEXT:    v_cndmask_b32_e64 v2, v16, v4, s5
 ; GFX10-NEXT:    v_cmp_ne_u32_e64 s4, 0, v3
 ; GFX10-NEXT:    v_cndmask_b32_e64 v3, v17, v5, s5
 ; GFX10-NEXT:    v_cndmask_b32_e64 v4, v10, v6, s4
 ; GFX10-NEXT:    v_cndmask_b32_e64 v5, v11, v7, s4
 ; GFX10-NEXT:    v_cndmask_b32_e64 v6, v12, v8, s4
 ; GFX10-NEXT:    v_cndmask_b32_e64 v7, v13, v9, s4
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_saddsat_v2i128:
+; GFX11:       ; %bb.0:
+; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT:    v_add_co_u32 v8, vcc_lo, v0, v8
+; GFX11-NEXT:    v_add_co_ci_u32_e32 v9, vcc_lo, v1, v9, vcc_lo
+; GFX11-NEXT:    v_add_co_ci_u32_e32 v16, vcc_lo, v2, v10, vcc_lo
+; GFX11-NEXT:    v_add_co_ci_u32_e32 v17, vcc_lo, v3, v11, vcc_lo
+; GFX11-NEXT:    v_cmp_lt_u64_e32 vcc_lo, v[8:9], v[0:1]
+; GFX11-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX11-NEXT:    v_cmp_lt_i64_e32 vcc_lo, v[16:17], v[2:3]
+; GFX11-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; GFX11-NEXT:    v_cmp_gt_i64_e32 vcc_lo, 0, v[10:11]
+; GFX11-NEXT:    v_cndmask_b32_e64 v18, 0, 1, vcc_lo
+; GFX11-NEXT:    v_cmp_eq_u64_e32 vcc_lo, v[16:17], v[2:3]
+; GFX11-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc_lo
+; GFX11-NEXT:    v_cmp_eq_u64_e32 vcc_lo, 0, v[10:11]
+; GFX11-NEXT:    v_cndmask_b32_e64 v1, v18, 0, vcc_lo
+; GFX11-NEXT:    v_add_co_u32 v10, vcc_lo, v4, v12
+; GFX11-NEXT:    v_add_co_ci_u32_e32 v11, vcc_lo, v5, v13, vcc_lo
+; GFX11-NEXT:    v_add_co_ci_u32_e32 v12, vcc_lo, v6, v14, vcc_lo
+; GFX11-NEXT:    v_add_co_ci_u32_e32 v13, vcc_lo, v7, v15, vcc_lo
+; GFX11-NEXT:    v_cmp_lt_u64_e64 s1, v[10:11], v[4:5]
+; GFX11-NEXT:    v_xor_b32_e32 v0, v1, v0
+; GFX11-NEXT:    v_ashrrev_i32_e32 v1, 31, v17
+; GFX11-NEXT:    v_cmp_eq_u64_e64 s2, v[12:13], v[6:7]
+; GFX11-NEXT:    s_mov_b32 vcc_lo, 0
+; GFX11-NEXT:    v_cndmask_b32_e64 v3, 0, 1, s1
+; GFX11-NEXT:    v_cmp_lt_i64_e64 s1, v[12:13], v[6:7]
+; GFX11-NEXT:    v_and_b32_e32 v0, 1, v0
+; GFX11-NEXT:    v_ashrrev_i32_e32 v6, 31, v13
+; GFX11-NEXT:    v_add_co_ci_u32_e64 v2, s0, 0, v1, vcc_lo
+; GFX11-NEXT:    v_cndmask_b32_e64 v4, 0, 1, s1
+; GFX11-NEXT:    v_cmp_gt_i64_e64 s1, 0, v[14:15]
+; GFX11-NEXT:    v_add_co_ci_u32_e32 v7, vcc_lo, 0, v6, vcc_lo
+; GFX11-NEXT:    v_cndmask_b32_e64 v5, 0, 1, s1
+; GFX11-NEXT:    v_cmp_ne_u32_e64 s1, 0, v0
+; GFX11-NEXT:    v_cndmask_b32_e64 v0, v4, v3, s2
+; GFX11-NEXT:    v_cmp_eq_u64_e64 s2, 0, v[14:15]
+; GFX11-NEXT:    v_add_co_ci_u32_e64 v4, s0, 0, v1, s0
+; GFX11-NEXT:    v_cndmask_b32_e64 v3, v5, 0, s2
+; GFX11-NEXT:    v_add_co_ci_u32_e64 v5, s0, 0x80000000, v1, s0
+; GFX11-NEXT:    v_xor_b32_e32 v3, v3, v0
+; GFX11-NEXT:    v_cndmask_b32_e64 v0, v8, v1, s1
+; GFX11-NEXT:    v_add_co_ci_u32_e32 v8, vcc_lo, 0, v6, vcc_lo
+; GFX11-NEXT:    v_cndmask_b32_e64 v1, v9, v2, s1
+; GFX11-NEXT:    v_and_b32_e32 v3, 1, v3
+; GFX11-NEXT:    v_add_co_ci_u32_e32 v9, vcc_lo, 0x80000000, v6, vcc_lo
+; GFX11-NEXT:    v_cndmask_b32_e64 v2, v16, v4, s1
+; GFX11-NEXT:    v_cmp_ne_u32_e64 s0, 0, v3
+; GFX11-NEXT:    v_cndmask_b32_e64 v3, v17, v5, s1
+; GFX11-NEXT:    v_cndmask_b32_e64 v4, v10, v6, s0
+; GFX11-NEXT:    v_cndmask_b32_e64 v5, v11, v7, s0
+; GFX11-NEXT:    v_cndmask_b32_e64 v6, v12, v8, s0
+; GFX11-NEXT:    v_cndmask_b32_e64 v7, v13, v9, s0
+; GFX11-NEXT:    s_setpc_b64 s[30:31]
   %result = call <2 x i128> @llvm.sadd.sat.v2i128(<2 x i128> %lhs, <2 x i128> %rhs)
   ret <2 x i128> %result
 }
 
 define amdgpu_ps <2 x i128> @s_saddsat_v2i128(<2 x i128> inreg %lhs, <2 x i128> inreg %rhs) {
 ; GFX6-LABEL: s_saddsat_v2i128:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_add_u32 s8, s0, s8

 ; GFX9-NEXT:    v_readfirstlane_b32 s2, v6
 ; GFX9-NEXT:    v_readfirstlane_b32 s3, v7
 ; GFX9-NEXT:    v_readfirstlane_b32 s4, v0
 ; GFX9-NEXT:    v_readfirstlane_b32 s5, v1
 ; GFX9-NEXT:    v_readfirstlane_b32 s6, v2
 ; GFX9-NEXT:    v_readfirstlane_b32 s7, v3
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
-; GFX10-LABEL: s_saddsat_v2i128:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    s_add_u32 s8, s0, s8
-; GFX10-NEXT:    s_addc_u32 s9, s1, s9
-; GFX10-NEXT:    s_addc_u32 s16, s2, s10
-; GFX10-NEXT:    v_cmp_lt_u64_e64 s0, s[8:9], s[0:1]
-; GFX10-NEXT:    s_addc_u32 s17, s3, s11
-; GFX10-NEXT:    s_cmp_eq_u64 s[16:17], s[2:3]
-; GFX10-NEXT:    v_mov_b32_e32 v5, s17
-; GFX10-NEXT:    s_cselect_b32 s18, 1, 0
-; GFX10-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
-; GFX10-NEXT:    v_cmp_lt_i64_e64 s0, s[16:17], s[2:3]
-; GFX10-NEXT:    v_cmp_lt_i64_e64 s2, s[10:11], 0
-; GFX10-NEXT:    v_cndmask_b32_e64 v1, 0, 1, s0
-; GFX10-NEXT:    s_and_b32 s0, 1, s18
-; GFX10-NEXT:    s_cmp_eq_u64 s[10:11], 0
-; GFX10-NEXT:    v_cndmask_b32_e64 v2, 0, 1, s2
-; GFX10-NEXT:    s_cselect_b32 s1, 1, 0
-; GFX10-NEXT:    v_cmp_ne_u32_e64 vcc_lo, 0, s0
-; GFX10-NEXT:    s_and_b32 s1, 1, s1
-; GFX10-NEXT:    s_ashr_i32 s2, s17, 31
-; GFX10-NEXT:    v_cmp_ne_u32_e64 s0, 0, s1
-; GFX10-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc_lo
-; GFX10-NEXT:    v_cndmask_b32_e64 v1, v2, 0, s0
-; GFX10-NEXT:    s_mov_b32 s0, 0
-; GFX10-NEXT:    s_cmp_lg_u32 s0, 0
-; GFX10-NEXT:    s_addc_u32 s1, s2, 0
-; GFX10-NEXT:    s_addc_u32 s10, s2, 0
-; GFX10-NEXT:    s_addc_u32 s3, s2, 0x80000000
-; GFX10-NEXT:    s_add_u32 s12, s4, s12
-; GFX10-NEXT:    s_addc_u32 s13, s5, s13
-; GFX10-NEXT:    s_addc_u32 s18, s6, s14
-; GFX10-NEXT:    v_cmp_lt_u64_e64 s4, s[12:13], s[4:5]
-; GFX10-NEXT:    s_addc_u32 s19, s7, s15
-; GFX10-NEXT:    v_cmp_lt_i64_e64 s5, s[14:15], 0
-; GFX10-NEXT:    s_cmp_eq_u64 s[18:19], s[6:7]
-; GFX10-NEXT:    v_xor_b32_e32 v0, v1, v0
-; GFX10-NEXT:    s_cselect_b32 s0, 1, 0
-; GFX10-NEXT:    v_cndmask_b32_e64 v2, 0, 1, s4
-; GFX10-NEXT:    v_cmp_lt_i64_e64 s4, s[18:19], s[6:7]
-; GFX10-NEXT:    s_and_b32 s0, 1, s0
-; GFX10-NEXT:    s_cmp_eq_u64 s[14:15], 0
-; GFX10-NEXT:    v_cmp_ne_u32_e64 s0, 0, s0
-; GFX10-NEXT:    v_cndmask_b32_e64 v4, 0, 1, s5
-; GFX10-NEXT:    v_and_b32_e32 v0, 1, v0
-; GFX10-NEXT:    v_cndmask_b32_e64 v3, 0, 1, s4
-; GFX10-NEXT:    s_cselect_b32 s4, 1, 0
-; GFX10-NEXT:    v_mov_b32_e32 v1, s8
-; GFX10-NEXT:    s_and_b32 s4, 1, s4
-; GFX10-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v0
-; GFX10-NEXT:    v_cndmask_b32_e64 v2, v3, v2, s0
-; GFX10-NEXT:    v_cmp_ne_u32_e64 s0, 0, s4
-; GFX10-NEXT:    v_mov_b32_e32 v0, s9
-; GFX10-NEXT:    v_mov_b32_e32 v6, s13
-; GFX10-NEXT:    v_cndmask_b32_e64 v1, v1, s2, vcc_lo
-; GFX10-NEXT:    v_mov_b32_e32 v7, s19
-; GFX10-NEXT:    v_cndmask_b32_e64 v3, v4, 0, s0
-; GFX10-NEXT:    v_mov_b32_e32 v4, s16
-; GFX10-NEXT:    v_cndmask_b32_e64 v0, v0, s1, vcc_lo
-; GFX10-NEXT:    s_mov_b32 s1, 0
-; GFX10-NEXT:    s_ashr_i32 s0, s19, 31
-; GFX10-NEXT:    v_xor_b32_e32 v2, v3, v2
-; GFX10-NEXT:    s_cmp_lg_u32 s1, 0
-; GFX10-NEXT:    v_cndmask_b32_e64 v3, v4, s10, vcc_lo
-; GFX10-NEXT:    v_cndmask_b32_e64 v4, v5, s3, vcc_lo
-; GFX10-NEXT:    v_mov_b32_e32 v5, s12
-; GFX10-NEXT:    v_and_b32_e32 v2, 1, v2
-; GFX10-NEXT:    s_addc_u32 s1, s0, 0
-; GFX10-NEXT:    s_addc_u32 s2, s0, 0
-; GFX10-NEXT:    s_addc_u32 s3, s0, 0x80000000
-; GFX10-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v2
-; GFX10-NEXT:    v_mov_b32_e32 v2, s18
-; GFX10-NEXT:    v_cndmask_b32_e64 v5, v5, s0, vcc_lo
-; GFX10-NEXT:    v_cndmask_b32_e64 v6, v6, s1, vcc_lo
-; GFX10-NEXT:    v_cndmask_b32_e64 v2, v2, s2, vcc_lo
-; GFX10-NEXT:    v_cndmask_b32_e64 v7, v7, s3, vcc_lo
-; GFX10-NEXT:    v_readfirstlane_b32 s0, v1
-; GFX10-NEXT:    v_readfirstlane_b32 s1, v0
-; GFX10-NEXT:    v_readfirstlane_b32 s2, v3
-; GFX10-NEXT:    v_readfirstlane_b32 s3, v4
-; GFX10-NEXT:    v_readfirstlane_b32 s4, v5
-; GFX10-NEXT:    v_readfirstlane_b32 s5, v6
-; GFX10-NEXT:    v_readfirstlane_b32 s6, v2
-; GFX10-NEXT:    v_readfirstlane_b32 s7, v7
-; GFX10-NEXT:    ; return to shader part epilog
+; GFX10PLUS-LABEL: s_saddsat_v2i128:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    s_add_u32 s8, s0, s8
+; GFX10PLUS-NEXT:    s_addc_u32 s9, s1, s9
+; GFX10PLUS-NEXT:    s_addc_u32 s16, s2, s10
+; GFX10PLUS-NEXT:    v_cmp_lt_u64_e64 s0, s[8:9], s[0:1]
+; GFX10PLUS-NEXT:    s_addc_u32 s17, s3, s11
+; GFX10PLUS-NEXT:    s_cmp_eq_u64 s[16:17], s[2:3]
+; GFX10PLUS-NEXT:    v_mov_b32_e32 v5, s17
+; GFX10PLUS-NEXT:    s_cselect_b32 s18, 1, 0
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; GFX10PLUS-NEXT:    v_cmp_lt_i64_e64 s0, s[16:17], s[2:3]
+; GFX10PLUS-NEXT:    v_cmp_lt_i64_e64 s2, s[10:11], 0
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v1, 0, 1, s0
+; GFX10PLUS-NEXT:    s_and_b32 s0, 1, s18
+; GFX10PLUS-NEXT:    s_cmp_eq_u64 s[10:11], 0
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v2, 0, 1, s2
+; GFX10PLUS-NEXT:    s_cselect_b32 s1, 1, 0
+; GFX10PLUS-NEXT:    v_cmp_ne_u32_e64 vcc_lo, 0, s0
+; GFX10PLUS-NEXT:    s_and_b32 s1, 1, s1
+; GFX10PLUS-NEXT:    s_ashr_i32 s2, s17, 31
+; GFX10PLUS-NEXT:    v_cmp_ne_u32_e64 s0, 0, s1
+; GFX10PLUS-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc_lo
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v1, v2, 0, s0
+; GFX10PLUS-NEXT:    s_mov_b32 s0, 0
+; GFX10PLUS-NEXT:    s_cmp_lg_u32 s0, 0
+; GFX10PLUS-NEXT:    s_addc_u32 s1, s2, 0
+; GFX10PLUS-NEXT:    s_addc_u32 s10, s2, 0
+; GFX10PLUS-NEXT:    s_addc_u32 s3, s2, 0x80000000
+; GFX10PLUS-NEXT:    s_add_u32 s12, s4, s12
+; GFX10PLUS-NEXT:    s_addc_u32 s13, s5, s13
+; GFX10PLUS-NEXT:    s_addc_u32 s18, s6, s14
+; GFX10PLUS-NEXT:    v_cmp_lt_u64_e64 s4, s[12:13], s[4:5]
+; GFX10PLUS-NEXT:    s_addc_u32 s19, s7, s15
+; GFX10PLUS-NEXT:    v_cmp_lt_i64_e64 s5, s[14:15], 0
+; GFX10PLUS-NEXT:    s_cmp_eq_u64 s[18:19], s[6:7]
+; GFX10PLUS-NEXT:    v_xor_b32_e32 v0, v1, v0
+; GFX10PLUS-NEXT:    s_cselect_b32 s0, 1, 0
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v2, 0, 1, s4
+; GFX10PLUS-NEXT:    v_cmp_lt_i64_e64 s4, s[18:19], s[6:7]
+; GFX10PLUS-NEXT:    s_and_b32 s0, 1, s0
+; GFX10PLUS-NEXT:    s_cmp_eq_u64 s[14:15], 0
+; GFX10PLUS-NEXT:    v_cmp_ne_u32_e64 s0, 0, s0
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v4, 0, 1, s5
+; GFX10PLUS-NEXT:    v_and_b32_e32 v0, 1, v0
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v3, 0, 1, s4
+; GFX10PLUS-NEXT:    s_cselect_b32 s4, 1, 0
+; GFX10PLUS-NEXT:    v_mov_b32_e32 v1, s8
+; GFX10PLUS-NEXT:    s_and_b32 s4, 1, s4
+; GFX10PLUS-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v0
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v2, v3, v2, s0
+; GFX10PLUS-NEXT:    v_cmp_ne_u32_e64 s0, 0, s4
+; GFX10PLUS-NEXT:    v_mov_b32_e32 v0, s9
+; GFX10PLUS-NEXT:    v_mov_b32_e32 v6, s13
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v1, v1, s2, vcc_lo
+; GFX10PLUS-NEXT:    v_mov_b32_e32 v7, s19
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v3, v4, 0, s0
+; GFX10PLUS-NEXT:    v_mov_b32_e32 v4, s16
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v0, v0, s1, vcc_lo
+; GFX10PLUS-NEXT:    s_mov_b32 s1, 0
+; GFX10PLUS-NEXT:    s_ashr_i32 s0, s19, 31
+; GFX10PLUS-NEXT:    v_xor_b32_e32 v2, v3, v2
+; GFX10PLUS-NEXT:    s_cmp_lg_u32 s1, 0
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v3, v4, s10, vcc_lo
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v4, v5, s3, vcc_lo
+; GFX10PLUS-NEXT:    v_mov_b32_e32 v5, s12
+; GFX10PLUS-NEXT:    v_and_b32_e32 v2, 1, v2
+; GFX10PLUS-NEXT:    s_addc_u32 s1, s0, 0
+; GFX10PLUS-NEXT:    s_addc_u32 s2, s0, 0
+; GFX10PLUS-NEXT:    s_addc_u32 s3, s0, 0x80000000
+; GFX10PLUS-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v2
+; GFX10PLUS-NEXT:    v_mov_b32_e32 v2, s18
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v5, v5, s0, vcc_lo
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v6, v6, s1, vcc_lo
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v2, v2, s2, vcc_lo
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v7, v7, s3, vcc_lo
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s0, v1
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s1, v0
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s2, v3
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s3, v4
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s4, v5
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s5, v6
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s6, v2
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s7, v7
+; GFX10PLUS-NEXT:    ; return to shader part epilog
   %result = call <2 x i128> @llvm.sadd.sat.v2i128(<2 x i128> %lhs, <2 x i128> %rhs)
   ret <2 x i128> %result
 }
 
 declare i7 @llvm.sadd.sat.i7(i7, i7) #0
 declare i8 @llvm.sadd.sat.i8(i8, i8) #0
 declare <2 x i8> @llvm.sadd.sat.v2i8(<2 x i8>, <2 x i8>) #0
 declare <4 x i8> @llvm.sadd.sat.v4i8(<4 x i8>, <4 x i8>) #0

llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=tahiti -o - %s | FileCheck -check-prefix=GFX6 %s
 ; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=fiji -o - %s | FileCheck -check-prefix=GFX8 %s
 ; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 -o - %s | FileCheck -check-prefix=GFX9 %s
-; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx1010 -o - %s | FileCheck -check-prefix=GFX10 %s
+; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx1010 -o - %s | FileCheck -check-prefixes=GFX10PLUS,GFX10 %s
+; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx1100 -o - %s | FileCheck -check-prefixes=GFX10PLUS,GFX11 %s
 
 define i7 @v_ssubsat_i7(i7 %lhs, i7 %rhs) {
 ; GFX6-LABEL: v_ssubsat_i7:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX6-NEXT:    v_lshlrev_b32_e32 v0, 25, v0
 ; GFX6-NEXT:    v_max_i32_e32 v2, -1, v0
 ; GFX6-NEXT:    v_lshlrev_b32_e32 v1, 25, v1

 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    v_lshlrev_b16_e32 v0, 9, v0
 ; GFX9-NEXT:    v_lshlrev_b16_e32 v1, 9, v1
 ; GFX9-NEXT:    v_sub_i16 v0, v0, v1 clamp
 ; GFX9-NEXT:    v_ashrrev_i16_e32 v0, 9, v0
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX10-LABEL: v_ssubsat_i7:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_lshlrev_b16 v0, 9, v0
-; GFX10-NEXT:    v_lshlrev_b16 v1, 9, v1
-; GFX10-NEXT:    v_sub_nc_i16 v0, v0, v1 clamp
-; GFX10-NEXT:    v_ashrrev_i16 v0, 9, v0
-; GFX10-NEXT:    s_setpc_b64 s[30:31]
+; GFX10PLUS-LABEL: v_ssubsat_i7:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX10PLUS-NEXT:    v_lshlrev_b16 v0, 9, v0
+; GFX10PLUS-NEXT:    v_lshlrev_b16 v1, 9, v1
+; GFX10PLUS-NEXT:    v_sub_nc_i16 v0, v0, v1 clamp
+; GFX10PLUS-NEXT:    v_ashrrev_i16 v0, 9, v0
+; GFX10PLUS-NEXT:    s_setpc_b64 s[30:31]
   %result = call i7 @llvm.ssub.sat.i7(i7 %lhs, i7 %rhs)
   ret i7 %result
 }
 
 define amdgpu_ps i7 @s_ssubsat_i7(i7 inreg %lhs, i7 inreg %rhs) {
 ; GFX6-LABEL: s_ssubsat_i7:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_lshl_b32 s0, s0, 25

 ; GFX9-NEXT:    s_lshl_b32 s1, s1, s2
 ; GFX9-NEXT:    s_lshl_b32 s0, s0, s2
 ; GFX9-NEXT:    v_mov_b32_e32 v0, s1
 ; GFX9-NEXT:    v_sub_i16 v0, s0, v0 clamp
 ; GFX9-NEXT:    v_ashrrev_i16_e32 v0, 9, v0
 ; GFX9-NEXT:    v_readfirstlane_b32 s0, v0
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
-; GFX10-LABEL: s_ssubsat_i7:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    s_bfe_u32 s2, 9, 0x100000
-; GFX10-NEXT:    s_lshl_b32 s0, s0, s2
-; GFX10-NEXT:    s_lshl_b32 s1, s1, s2
-; GFX10-NEXT:    v_sub_nc_i16 v0, s0, s1 clamp
-; GFX10-NEXT:    v_ashrrev_i16 v0, 9, v0
-; GFX10-NEXT:    v_readfirstlane_b32 s0, v0
-; GFX10-NEXT:    ; return to shader part epilog
+; GFX10PLUS-LABEL: s_ssubsat_i7:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    s_bfe_u32 s2, 9, 0x100000
+; GFX10PLUS-NEXT:    s_lshl_b32 s0, s0, s2
+; GFX10PLUS-NEXT:    s_lshl_b32 s1, s1, s2
+; GFX10PLUS-NEXT:    v_sub_nc_i16 v0, s0, s1 clamp
+; GFX10PLUS-NEXT:    v_ashrrev_i16 v0, 9, v0
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s0, v0
+; GFX10PLUS-NEXT:    ; return to shader part epilog
   %result = call i7 @llvm.ssub.sat.i7(i7 %lhs, i7 %rhs)
   ret i7 %result
 }
 
 define i8 @v_ssubsat_i8(i8 %lhs, i8 %rhs) {
 ; GFX6-LABEL: v_ssubsat_i8:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    v_lshlrev_b16_e32 v0, 8, v0
 ; GFX9-NEXT:    v_lshlrev_b16_e32 v1, 8, v1
 ; GFX9-NEXT:    v_sub_i16 v0, v0, v1 clamp
 ; GFX9-NEXT:    v_ashrrev_i16_e32 v0, 8, v0
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX10-LABEL: v_ssubsat_i8:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_lshlrev_b16 v0, 8, v0
-; GFX10-NEXT:    v_lshlrev_b16 v1, 8, v1
-; GFX10-NEXT:    v_sub_nc_i16 v0, v0, v1 clamp
-; GFX10-NEXT:    v_ashrrev_i16 v0, 8, v0
-; GFX10-NEXT:    s_setpc_b64 s[30:31]
+; GFX10PLUS-LABEL: v_ssubsat_i8:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX10PLUS-NEXT:    v_lshlrev_b16 v0, 8, v0
+; GFX10PLUS-NEXT:    v_lshlrev_b16 v1, 8, v1
+; GFX10PLUS-NEXT:    v_sub_nc_i16 v0, v0, v1 clamp
+; GFX10PLUS-NEXT:    v_ashrrev_i16 v0, 8, v0
+; GFX10PLUS-NEXT:    s_setpc_b64 s[30:31]
   %result = call i8 @llvm.ssub.sat.i8(i8 %lhs, i8 %rhs)
   ret i8 %result
 }
 
 define amdgpu_ps i8 @s_ssubsat_i8(i8 inreg %lhs, i8 inreg %rhs) {
 ; GFX6-LABEL: s_ssubsat_i8:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_lshl_b32 s0, s0, 24

 ; GFX9-NEXT:    s_lshl_b32 s1, s1, s2
 ; GFX9-NEXT:    s_lshl_b32 s0, s0, s2
 ; GFX9-NEXT:    v_mov_b32_e32 v0, s1
 ; GFX9-NEXT:    v_sub_i16 v0, s0, v0 clamp
 ; GFX9-NEXT:    v_ashrrev_i16_e32 v0, 8, v0
 ; GFX9-NEXT:    v_readfirstlane_b32 s0, v0
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
-; GFX10-LABEL: s_ssubsat_i8:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    s_bfe_u32 s2, 8, 0x100000
-; GFX10-NEXT:    s_lshl_b32 s0, s0, s2
-; GFX10-NEXT:    s_lshl_b32 s1, s1, s2
-; GFX10-NEXT:    v_sub_nc_i16 v0, s0, s1 clamp
-; GFX10-NEXT:    v_ashrrev_i16 v0, 8, v0
-; GFX10-NEXT:    v_readfirstlane_b32 s0, v0
-; GFX10-NEXT:    ; return to shader part epilog
+; GFX10PLUS-LABEL: s_ssubsat_i8:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    s_bfe_u32 s2, 8, 0x100000
+; GFX10PLUS-NEXT:    s_lshl_b32 s0, s0, s2
+; GFX10PLUS-NEXT:    s_lshl_b32 s1, s1, s2
+; GFX10PLUS-NEXT:    v_sub_nc_i16 v0, s0, s1 clamp
+; GFX10PLUS-NEXT:    v_ashrrev_i16 v0, 8, v0
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s0, v0
+; GFX10PLUS-NEXT:    ; return to shader part epilog
   %result = call i8 @llvm.ssub.sat.i8(i8 %lhs, i8 %rhs)
   ret i8 %result
 }
 
 define i16 @v_ssubsat_v2i8(i16 %lhs.arg, i16 %rhs.arg) {
 ; GFX6-LABEL: v_ssubsat_v2i8:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

 ; GFX10-NEXT:    v_and_or_b32 v1, 0xffff, v1, v3
 ; GFX10-NEXT:    v_pk_lshlrev_b16 v0, 8, v0 op_sel_hi:[0,1]
 ; GFX10-NEXT:    v_pk_lshlrev_b16 v1, 8, v1 op_sel_hi:[0,1]
 ; GFX10-NEXT:    v_pk_sub_i16 v0, v0, v1 clamp
 ; GFX10-NEXT:    v_pk_ashrrev_i16 v0, 8, v0 op_sel_hi:[0,1]
 ; GFX10-NEXT:    v_and_b32_sdwa v1, v0, s4 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
 ; GFX10-NEXT:    v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_ssubsat_v2i8:
+; GFX11:       ; %bb.0:
+; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT:    v_lshrrev_b32_e32 v2, 8, v0
+; GFX11-NEXT:    v_lshrrev_b32_e32 v3, 8, v1
+; GFX11-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-NEXT:    v_and_or_b32 v0, 0xffff, v0, v2
+; GFX11-NEXT:    v_and_or_b32 v1, 0xffff, v1, v3
+; GFX11-NEXT:    v_pk_lshlrev_b16 v0, 8, v0 op_sel_hi:[0,1]
+; GFX11-NEXT:    v_pk_lshlrev_b16 v1, 8, v1 op_sel_hi:[0,1]
+; GFX11-NEXT:    v_pk_sub_i16 v0, v0, v1 clamp
+; GFX11-NEXT:    v_pk_ashrrev_i16 v0, 8, v0 op_sel_hi:[0,1]
+; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; GFX11-NEXT:    v_lshlrev_b16 v1, 8, v1
+; GFX11-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-NEXT:    s_setpc_b64 s[30:31]
   %lhs = bitcast i16 %lhs.arg to <2 x i8>
   %rhs = bitcast i16 %rhs.arg to <2 x i8>
   %result = call <2 x i8> @llvm.ssub.sat.v2i8(<2 x i8> %lhs, <2 x i8> %rhs)
   %cast.result = bitcast <2 x i8> %result to i16
   ret i16 %cast.result
 }
 
 define amdgpu_ps i16 @s_ssubsat_v2i8(i16 inreg %lhs.arg, i16 inreg %rhs.arg) {

 ; GFX10-NEXT:    s_pack_ll_b32_b16 s1, s1, s3
 ; GFX10-NEXT:    v_pk_sub_i16 v0, s0, s1 clamp
 ; GFX10-NEXT:    s_movk_i32 s0, 0xff
 ; GFX10-NEXT:    v_pk_ashrrev_i16 v0, 8, v0 op_sel_hi:[0,1]
 ; GFX10-NEXT:    v_and_b32_sdwa v1, v0, s0 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
 ; GFX10-NEXT:    v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
 ; GFX10-NEXT:    v_readfirstlane_b32 s0, v0
 ; GFX10-NEXT:    ; return to shader part epilog
+;
+; GFX11-LABEL: s_ssubsat_v2i8:
+; GFX11:       ; %bb.0:
+; GFX11-NEXT:    s_lshr_b32 s2, s0, 8
+; GFX11-NEXT:    s_lshr_b32 s3, s1, 8
+; GFX11-NEXT:    s_pack_ll_b32_b16 s0, s0, s2
+; GFX11-NEXT:    s_pack_ll_b32_b16 s1, s1, s3
+; GFX11-NEXT:    s_lshr_b32 s2, s0, 16
+; GFX11-NEXT:    s_lshr_b32 s3, s1, 16
+; GFX11-NEXT:    s_lshl_b32 s0, s0, 0x80008
+; GFX11-NEXT:    s_lshl_b32 s2, s2, 8
+; GFX11-NEXT:    s_lshl_b32 s1, s1, 0x80008
+; GFX11-NEXT:    s_lshl_b32 s3, s3, 8
+; GFX11-NEXT:    s_pack_ll_b32_b16 s0, s0, s2
+; GFX11-NEXT:    s_pack_ll_b32_b16 s1, s1, s3
+; GFX11-NEXT:    v_pk_sub_i16 v0, s0, s1 clamp
+; GFX11-NEXT:    v_pk_ashrrev_i16 v0, 8, v0 op_sel_hi:[0,1]
+; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; GFX11-NEXT:    v_lshlrev_b16 v1, 8, v1
+; GFX11-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-NEXT:    v_readfirstlane_b32 s0, v0
+; GFX11-NEXT:    ; return to shader part epilog
   %lhs = bitcast i16 %lhs.arg to <2 x i8>
   %rhs = bitcast i16 %rhs.arg to <2 x i8>
   %result = call <2 x i8> @llvm.ssub.sat.v2i8(<2 x i8> %lhs, <2 x i8> %rhs)
   %cast.result = bitcast <2 x i8> %result to i16
   ret i16 %cast.result
 }
 
 define i32 @v_ssubsat_v4i8(i32 %lhs.arg, i32 %rhs.arg) {

 ; GFX10-NEXT:    v_pk_ashrrev_i16 v1, 8, v1 op_sel_hi:[0,1]
 ; GFX10-NEXT:    v_lshlrev_b32_sdwa v2, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
 ; GFX10-NEXT:    v_and_b32_e32 v3, 0xff, v1
 ; GFX10-NEXT:    v_lshlrev_b32_sdwa v1, v4, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
 ; GFX10-NEXT:    v_and_or_b32 v0, v0, 0xff, v2
 ; GFX10-NEXT:    v_lshlrev_b32_e32 v2, 16, v3
 ; GFX10-NEXT:    v_or3_b32 v0, v0, v2, v1
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_ssubsat_v4i8:
+; GFX11:       ; %bb.0:
+; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT:    v_lshrrev_b32_e32 v2, 8, v0
+; GFX11-NEXT:    v_lshrrev_b32_e32 v3, 8, v1
+; GFX11-NEXT:    v_lshrrev_b32_e32 v5, 24, v0
+; GFX11-NEXT:    v_lshrrev_b32_e32 v6, 24, v1
+; GFX11-NEXT:    v_lshrrev_b32_e32 v4, 16, v0
+; GFX11-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-NEXT:    v_lshrrev_b32_e32 v7, 16, v1
+; GFX11-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
+; GFX11-NEXT:    v_and_or_b32 v0, 0xffff, v0, v2
+; GFX11-NEXT:    v_and_or_b32 v1, 0xffff, v1, v3
+; GFX11-NEXT:    v_and_or_b32 v2, 0xffff, v4, v5
+; GFX11-NEXT:    v_and_or_b32 v3, 0xffff, v7, v6
+; GFX11-NEXT:    v_pk_lshlrev_b16 v0, 8, v0 op_sel_hi:[0,1]
+; GFX11-NEXT:    v_pk_lshlrev_b16 v1, 8, v1 op_sel_hi:[0,1]
+; GFX11-NEXT:    v_pk_lshlrev_b16 v2, 8, v2 op_sel_hi:[0,1]
+; GFX11-NEXT:    v_pk_lshlrev_b16 v3, 8, v3 op_sel_hi:[0,1]
+; GFX11-NEXT:    v_pk_sub_i16 v0, v0, v1 clamp
+; GFX11-NEXT:    v_pk_sub_i16 v1, v2, v3 clamp
+; GFX11-NEXT:    v_pk_ashrrev_i16 v0, 8, v0 op_sel_hi:[0,1]
+; GFX11-NEXT:    v_pk_ashrrev_i16 v1, 8, v1 op_sel_hi:[0,1]
+; GFX11-NEXT:    v_bfe_u32 v2, v0, 16, 8
+; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v1
+; GFX11-NEXT:    v_bfe_u32 v1, v1, 16, 8
+; GFX11-NEXT:    v_lshlrev_b32_e32 v2, 8, v2
+; GFX11-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-NEXT:    v_lshlrev_b32_e32 v1, 24, v1
+; GFX11-NEXT:    v_and_or_b32 v0, v0, 0xff, v2
+; GFX11-NEXT:    v_or3_b32 v0, v0, v3, v1
+; GFX11-NEXT:    s_setpc_b64 s[30:31]
   %lhs = bitcast i32 %lhs.arg to <4 x i8>
   %rhs = bitcast i32 %rhs.arg to <4 x i8>
   %result = call <4 x i8> @llvm.ssub.sat.v4i8(<4 x i8> %lhs, <4 x i8> %rhs)
   %cast.result = bitcast <4 x i8> %result to i32
   ret i32 %cast.result
 }
 
 define amdgpu_ps i32 @s_ssubsat_v4i8(i32 inreg %lhs.arg, i32 inreg %rhs.arg) {

 ; GFX10-NEXT:    v_and_b32_e32 v3, 0xff, v1
 ; GFX10-NEXT:    s_mov_b32 s0, 24
 ; GFX10-NEXT:    v_lshlrev_b32_sdwa v1, s0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
 ; GFX10-NEXT:    v_and_or_b32 v0, v0, 0xff, v2
 ; GFX10-NEXT:    v_lshlrev_b32_e32 v2, 16, v3
 ; GFX10-NEXT:    v_or3_b32 v0, v0, v2, v1
 ; GFX10-NEXT:    v_readfirstlane_b32 s0, v0
 ; GFX10-NEXT:    ; return to shader part epilog
+;
+; GFX11-LABEL: s_ssubsat_v4i8:
+; GFX11:       ; %bb.0:
+; GFX11-NEXT:    s_lshr_b32 s2, s0, 8
+; GFX11-NEXT:    s_lshr_b32 s4, s1, 8
+; GFX11-NEXT:    s_pack_ll_b32_b16 s2, s0, s2
+; GFX11-NEXT:    s_pack_ll_b32_b16 s4, s1, s4
+; GFX11-NEXT:    s_lshr_b32 s6, s2, 16
+; GFX11-NEXT:    s_lshl_b32 s2, s2, 0x80008
+; GFX11-NEXT:    s_lshl_b32 s6, s6, 8
+; GFX11-NEXT:    s_lshr_b32 s3, s0, 24
+; GFX11-NEXT:    s_pack_ll_b32_b16 s2, s2, s6
+; GFX11-NEXT:    s_lshr_b32 s6, s4, 16
+; GFX11-NEXT:    s_lshr_b32 s5, s1, 24
+; GFX11-NEXT:    s_lshl_b32 s4, s4, 0x80008
+; GFX11-NEXT:    s_lshl_b32 s6, s6, 8
+; GFX11-NEXT:    s_pack_hl_b32_b16 s0, s0, s3
+; GFX11-NEXT:    s_pack_hl_b32_b16 s1, s1, s5
+; GFX11-NEXT:    s_pack_ll_b32_b16 s4, s4, s6
+; GFX11-NEXT:    s_lshr_b32 s3, s0, 16
+; GFX11-NEXT:    s_lshr_b32 s5, s1, 16
+; GFX11-NEXT:    v_pk_sub_i16 v0, s2, s4 clamp
+; GFX11-NEXT:    s_lshl_b32 s0, s0, 0x80008
+; GFX11-NEXT:    s_lshl_b32 s3, s3, 8
+; GFX11-NEXT:    s_lshl_b32 s1, s1, 0x80008
+; GFX11-NEXT:    s_lshl_b32 s2, s5, 8
+; GFX11-NEXT:    s_pack_ll_b32_b16 s0, s0, s3
+; GFX11-NEXT:    s_pack_ll_b32_b16 s1, s1, s2
+; GFX11-NEXT:    v_pk_ashrrev_i16 v0, 8, v0 op_sel_hi:[0,1]
+; GFX11-NEXT:    v_pk_sub_i16 v1, s0, s1 clamp
+; GFX11-NEXT:    v_bfe_u32 v2, v0, 16, 8
+; GFX11-NEXT:    v_pk_ashrrev_i16 v1, 8, v1 op_sel_hi:[0,1]
+; GFX11-NEXT:    v_lshlrev_b32_e32 v2, 8, v2
+; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v1
+; GFX11-NEXT:    v_bfe_u32 v1, v1, 16, 8
+; GFX11-NEXT:    v_and_or_b32 v0, v0, 0xff, v2
+; GFX11-NEXT:    v_lshlrev_b32_e32 v2, 16, v3
+; GFX11-NEXT:    v_lshlrev_b32_e32 v1, 24, v1
+; GFX11-NEXT:    v_or3_b32 v0, v0, v2, v1
+; GFX11-NEXT:    v_readfirstlane_b32 s0, v0
+; GFX11-NEXT:    ; return to shader part epilog
   %lhs = bitcast i32 %lhs.arg to <4 x i8>
   %rhs = bitcast i32 %rhs.arg to <4 x i8>
   %result = call <4 x i8> @llvm.ssub.sat.v4i8(<4 x i8> %lhs, <4 x i8> %rhs)
   %cast.result = bitcast <4 x i8> %result to i32
   ret i32 %cast.result
 }
 
 define i24 @v_ssubsat_i24(i24 %lhs, i24 %rhs) {

 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    v_lshlrev_b32_e32 v0, 8, v0
 ; GFX9-NEXT:    v_lshlrev_b32_e32 v1, 8, v1
 ; GFX9-NEXT:    v_sub_i32 v0, v0, v1 clamp
 ; GFX9-NEXT:    v_ashrrev_i32_e32 v0, 8, v0
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX10-LABEL: v_ssubsat_i24:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_lshlrev_b32_e32 v0, 8, v0
-; GFX10-NEXT:    v_lshlrev_b32_e32 v1, 8, v1
-; GFX10-NEXT:    v_sub_nc_i32 v0, v0, v1 clamp
-; GFX10-NEXT:    v_ashrrev_i32_e32 v0, 8, v0
-; GFX10-NEXT:    s_setpc_b64 s[30:31]
+; GFX10PLUS-LABEL: v_ssubsat_i24:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX10PLUS-NEXT:    v_lshlrev_b32_e32 v0, 8, v0
+; GFX10PLUS-NEXT:    v_lshlrev_b32_e32 v1, 8, v1
+; GFX10PLUS-NEXT:    v_sub_nc_i32 v0, v0, v1 clamp
+; GFX10PLUS-NEXT:    v_ashrrev_i32_e32 v0, 8, v0
+; GFX10PLUS-NEXT:    s_setpc_b64 s[30:31]
   %result = call i24 @llvm.ssub.sat.i24(i24 %lhs, i24 %rhs)
   ret i24 %result
 }
 
 define amdgpu_ps i24 @s_ssubsat_i24(i24 inreg %lhs, i24 inreg %rhs) {
 ; GFX6-LABEL: s_ssubsat_i24:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_lshl_b32 s0, s0, 8

 ; GFX9-NEXT:    s_lshl_b32 s1, s1, 8
 ; GFX9-NEXT:    s_lshl_b32 s0, s0, 8
 ; GFX9-NEXT:    v_mov_b32_e32 v0, s1
 ; GFX9-NEXT:    v_sub_i32 v0, s0, v0 clamp
 ; GFX9-NEXT:    v_ashrrev_i32_e32 v0, 8, v0
 ; GFX9-NEXT:    v_readfirstlane_b32 s0, v0
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
-; GFX10-LABEL: s_ssubsat_i24:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    s_lshl_b32 s0, s0, 8
-; GFX10-NEXT:    s_lshl_b32 s1, s1, 8
-; GFX10-NEXT:    v_sub_nc_i32 v0, s0, s1 clamp
-; GFX10-NEXT:    v_ashrrev_i32_e32 v0, 8, v0
-; GFX10-NEXT:    v_readfirstlane_b32 s0, v0
-; GFX10-NEXT:    ; return to shader part epilog
+; GFX10PLUS-LABEL: s_ssubsat_i24:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    s_lshl_b32 s0, s0, 8
+; GFX10PLUS-NEXT:    s_lshl_b32 s1, s1, 8
+; GFX10PLUS-NEXT:    v_sub_nc_i32 v0, s0, s1 clamp
+; GFX10PLUS-NEXT:    v_ashrrev_i32_e32 v0, 8, v0
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s0, v0
+; GFX10PLUS-NEXT:    ; return to shader part epilog
   %result = call i24 @llvm.ssub.sat.i24(i24 %lhs, i24 %rhs)
   ret i24 %result
 }
 
 define i32 @v_ssubsat_i32(i32 %lhs, i32 %rhs) {
 ; GFX6-LABEL: v_ssubsat_i32:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

 ; GFX8-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX9-LABEL: v_ssubsat_i32:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    v_sub_i32 v0, v0, v1 clamp
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX10-LABEL: v_ssubsat_i32:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_sub_nc_i32 v0, v0, v1 clamp
-; GFX10-NEXT:    s_setpc_b64 s[30:31]
+; GFX10PLUS-LABEL: v_ssubsat_i32:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX10PLUS-NEXT:    v_sub_nc_i32 v0, v0, v1 clamp
+; GFX10PLUS-NEXT:    s_setpc_b64 s[30:31]
   %result = call i32 @llvm.ssub.sat.i32(i32 %lhs, i32 %rhs)
   ret i32 %result
 }
 
 define amdgpu_ps i32 @s_ssubsat_i32(i32 inreg %lhs, i32 inreg %rhs) {
 ; GFX6-LABEL: s_ssubsat_i32:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_max_i32 s2, s0, -1

 ;
 ; GFX9-LABEL: s_ssubsat_i32:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    v_mov_b32_e32 v0, s1
 ; GFX9-NEXT:    v_sub_i32 v0, s0, v0 clamp
 ; GFX9-NEXT:    v_readfirstlane_b32 s0, v0
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
-; GFX10-LABEL: s_ssubsat_i32:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_sub_nc_i32 v0, s0, s1 clamp
-; GFX10-NEXT:    v_readfirstlane_b32 s0, v0
-; GFX10-NEXT:    ; return to shader part epilog
+; GFX10PLUS-LABEL: s_ssubsat_i32:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    v_sub_nc_i32 v0, s0, s1 clamp
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s0, v0
+; GFX10PLUS-NEXT:    ; return to shader part epilog
   %result = call i32 @llvm.ssub.sat.i32(i32 %lhs, i32 %rhs)
   ret i32 %result
 }
 
 define amdgpu_ps float @ssubsat_i32_sv(i32 inreg %lhs, i32 %rhs) {
 ; GFX6-LABEL: ssubsat_i32_sv:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_max_i32 s1, s0, -1

 ; GFX8-NEXT:    v_sub_u32_e32 v0, vcc, s0, v0
 ; GFX8-NEXT:    ; return to shader part epilog
 ;
 ; GFX9-LABEL: ssubsat_i32_sv:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    v_sub_i32 v0, s0, v0 clamp
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
-; GFX10-LABEL: ssubsat_i32_sv:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_sub_nc_i32 v0, s0, v0 clamp
-; GFX10-NEXT:    ; return to shader part epilog
+; GFX10PLUS-LABEL: ssubsat_i32_sv:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    v_sub_nc_i32 v0, s0, v0 clamp
+; GFX10PLUS-NEXT:    ; return to shader part epilog
   %result = call i32 @llvm.ssub.sat.i32(i32 %lhs, i32 %rhs)
   %cast = bitcast i32 %result to float
   ret float %cast
 }
 
 define amdgpu_ps float @ssubsat_i32_vs(i32 %lhs, i32 inreg %rhs) {
 ; GFX6-LABEL: ssubsat_i32_vs:
 ; GFX6:       ; %bb.0:

 ; GFX8-NEXT:    v_sub_u32_e32 v0, vcc, v0, v1
 ; GFX8-NEXT:    ; return to shader part epilog
 ;
 ; GFX9-LABEL: ssubsat_i32_vs:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    v_sub_i32 v0, v0, s0 clamp
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
-; GFX10-LABEL: ssubsat_i32_vs:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_sub_nc_i32 v0, v0, s0 clamp
-; GFX10-NEXT:    ; return to shader part epilog
+; GFX10PLUS-LABEL: ssubsat_i32_vs:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    v_sub_nc_i32 v0, v0, s0 clamp
+; GFX10PLUS-NEXT:    ; return to shader part epilog
   %result = call i32 @llvm.ssub.sat.i32(i32 %lhs, i32 %rhs)
   %cast = bitcast i32 %result to float
   ret float %cast
 }
 
 define <2 x i32> @v_ssubsat_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) {
 ; GFX6-LABEL: v_ssubsat_v2i32:
 ; GFX6:       ; %bb.0:

 ;
 ; GFX9-LABEL: v_ssubsat_v2i32:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    v_sub_i32 v0, v0, v2 clamp
 ; GFX9-NEXT:    v_sub_i32 v1, v1, v3 clamp
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX10-LABEL: v_ssubsat_v2i32:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_sub_nc_i32 v0, v0, v2 clamp
-; GFX10-NEXT:    v_sub_nc_i32 v1, v1, v3 clamp
-; GFX10-NEXT:    s_setpc_b64 s[30:31]
+; GFX10PLUS-LABEL: v_ssubsat_v2i32:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX10PLUS-NEXT:    v_sub_nc_i32 v0, v0, v2 clamp
+; GFX10PLUS-NEXT:    v_sub_nc_i32 v1, v1, v3 clamp
+; GFX10PLUS-NEXT:    s_setpc_b64 s[30:31]
   %result = call <2 x i32> @llvm.ssub.sat.v2i32(<2 x i32> %lhs, <2 x i32> %rhs)
   ret <2 x i32> %result
 }
 
 define amdgpu_ps <2 x i32> @s_ssubsat_v2i32(<2 x i32> inreg %lhs, <2 x i32> inreg %rhs) {
 ; GFX6-LABEL: s_ssubsat_v2i32:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_max_i32 s4, s0, -1

 ; GFX9-NEXT:    v_mov_b32_e32 v0, s2
 ; GFX9-NEXT:    v_mov_b32_e32 v1, s3
 ; GFX9-NEXT:    v_sub_i32 v0, s0, v0 clamp
 ; GFX9-NEXT:    v_sub_i32 v1, s1, v1 clamp
 ; GFX9-NEXT:    v_readfirstlane_b32 s0, v0
 ; GFX9-NEXT:    v_readfirstlane_b32 s1, v1
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
-; GFX10-LABEL: s_ssubsat_v2i32:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_sub_nc_i32 v0, s0, s2 clamp
-; GFX10-NEXT:    v_sub_nc_i32 v1, s1, s3 clamp
-; GFX10-NEXT:    v_readfirstlane_b32 s0, v0
-; GFX10-NEXT:    v_readfirstlane_b32 s1, v1
-; GFX10-NEXT:    ; return to shader part epilog
+; GFX10PLUS-LABEL: s_ssubsat_v2i32:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    v_sub_nc_i32 v0, s0, s2 clamp
+; GFX10PLUS-NEXT:    v_sub_nc_i32 v1, s1, s3 clamp
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s0, v0
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s1, v1
+; GFX10PLUS-NEXT:    ; return to shader part epilog
   %result = call <2 x i32> @llvm.ssub.sat.v2i32(<2 x i32> %lhs, <2 x i32> %rhs)
   ret <2 x i32> %result
 }
 
 define <3 x i32> @v_ssubsat_v3i32(<3 x i32> %lhs, <3 x i32> %rhs) {
 ; GFX6-LABEL: v_ssubsat_v3i32:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

 ; GFX9-LABEL: v_ssubsat_v3i32:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    v_sub_i32 v0, v0, v3 clamp
 ; GFX9-NEXT:    v_sub_i32 v1, v1, v4 clamp
 ; GFX9-NEXT:    v_sub_i32 v2, v2, v5 clamp
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX10-LABEL: v_ssubsat_v3i32:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_sub_nc_i32 v0, v0, v3 clamp
-; GFX10-NEXT:    v_sub_nc_i32 v1, v1, v4 clamp
-; GFX10-NEXT:    v_sub_nc_i32 v2, v2, v5 clamp
-; GFX10-NEXT:    s_setpc_b64 s[30:31]
+; GFX10PLUS-LABEL: v_ssubsat_v3i32:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX10PLUS-NEXT:    v_sub_nc_i32 v0, v0, v3 clamp
+; GFX10PLUS-NEXT:    v_sub_nc_i32 v1, v1, v4 clamp
+; GFX10PLUS-NEXT:    v_sub_nc_i32 v2, v2, v5 clamp
+; GFX10PLUS-NEXT:    s_setpc_b64 s[30:31]
   %result = call <3 x i32> @llvm.ssub.sat.v3i32(<3 x i32> %lhs, <3 x i32> %rhs)
   ret <3 x i32> %result
 }
 
 define amdgpu_ps <3 x i32> @s_ssubsat_v3i32(<3 x i32> inreg %lhs, <3 x i32> inreg %rhs) {
 ; GFX6-LABEL: s_ssubsat_v3i32:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_max_i32 s6, s0, -1

 ; GFX9-NEXT:    v_sub_i32 v0, s0, v0 clamp
 ; GFX9-NEXT:    v_sub_i32 v1, s1, v1 clamp
 ; GFX9-NEXT:    v_sub_i32 v2, s2, v2 clamp
 ; GFX9-NEXT:    v_readfirstlane_b32 s0, v0
 ; GFX9-NEXT:    v_readfirstlane_b32 s1, v1
 ; GFX9-NEXT:    v_readfirstlane_b32 s2, v2
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
-; GFX10-LABEL: s_ssubsat_v3i32:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_sub_nc_i32 v0, s0, s3 clamp
-; GFX10-NEXT:    v_sub_nc_i32 v1, s1, s4 clamp
-; GFX10-NEXT:    v_sub_nc_i32 v2, s2, s5 clamp
-; GFX10-NEXT:    v_readfirstlane_b32 s0, v0
-; GFX10-NEXT:    v_readfirstlane_b32 s1, v1
-; GFX10-NEXT:    v_readfirstlane_b32 s2, v2
-; GFX10-NEXT:    ; return to shader part epilog
+; GFX10PLUS-LABEL: s_ssubsat_v3i32:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    v_sub_nc_i32 v0, s0, s3 clamp
+; GFX10PLUS-NEXT:    v_sub_nc_i32 v1, s1, s4 clamp
+; GFX10PLUS-NEXT:    v_sub_nc_i32 v2, s2, s5 clamp
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s0, v0
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s1, v1
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s2, v2
+; GFX10PLUS-NEXT:    ; return to shader part epilog
   %result = call <3 x i32> @llvm.ssub.sat.v3i32(<3 x i32> %lhs, <3 x i32> %rhs)
   ret <3 x i32> %result
 }
 
 define <4 x i32> @v_ssubsat_v4i32(<4 x i32> %lhs, <4 x i32> %rhs) {
 ; GFX6-LABEL: v_ssubsat_v4i32:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    v_sub_i32 v0, v0, v4 clamp
 ; GFX9-NEXT:    v_sub_i32 v1, v1, v5 clamp
 ; GFX9-NEXT:    v_sub_i32 v2, v2, v6 clamp
 ; GFX9-NEXT:    v_sub_i32 v3, v3, v7 clamp
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX10-LABEL: v_ssubsat_v4i32:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_sub_nc_i32 v0, v0, v4 clamp
-; GFX10-NEXT:    v_sub_nc_i32 v1, v1, v5 clamp
-; GFX10-NEXT:    v_sub_nc_i32 v2, v2, v6 clamp
-; GFX10-NEXT:    v_sub_nc_i32 v3, v3, v7 clamp
-; GFX10-NEXT:    s_setpc_b64 s[30:31]
+; GFX10PLUS-LABEL: v_ssubsat_v4i32:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX10PLUS-NEXT:    v_sub_nc_i32 v0, v0, v4 clamp
+; GFX10PLUS-NEXT:    v_sub_nc_i32 v1, v1, v5 clamp
+; GFX10PLUS-NEXT:    v_sub_nc_i32 v2, v2, v6 clamp
+; GFX10PLUS-NEXT:    v_sub_nc_i32 v3, v3, v7 clamp
+; GFX10PLUS-NEXT:    s_setpc_b64 s[30:31]
   %result = call <4 x i32> @llvm.ssub.sat.v4i32(<4 x i32> %lhs, <4 x i32> %rhs)
   ret <4 x i32> %result
 }
 
 define amdgpu_ps <4 x i32> @s_ssubsat_v4i32(<4 x i32> inreg %lhs, <4 x i32> inreg %rhs) {
 ; GFX6-LABEL: s_ssubsat_v4i32:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_max_i32 s8, s0, -1

 ; GFX9-NEXT:    v_sub_i32 v2, s2, v2 clamp
 ; GFX9-NEXT:    v_sub_i32 v3, s3, v3 clamp
 ; GFX9-NEXT:    v_readfirstlane_b32 s0, v0
 ; GFX9-NEXT:    v_readfirstlane_b32 s1, v1
 ; GFX9-NEXT:    v_readfirstlane_b32 s2, v2
 ; GFX9-NEXT:    v_readfirstlane_b32 s3, v3
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
-; GFX10-LABEL: s_ssubsat_v4i32:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_sub_nc_i32 v0, s0, s4 clamp
-; GFX10-NEXT:    v_sub_nc_i32 v1, s1, s5 clamp
-; GFX10-NEXT:    v_sub_nc_i32 v2, s2, s6 clamp
-; GFX10-NEXT:    v_sub_nc_i32 v3, s3, s7 clamp
-; GFX10-NEXT:    v_readfirstlane_b32 s0, v0
-; GFX10-NEXT:    v_readfirstlane_b32 s1, v1
-; GFX10-NEXT:    v_readfirstlane_b32 s2, v2
-; GFX10-NEXT:    v_readfirstlane_b32 s3, v3
-; GFX10-NEXT:    ; return to shader part epilog
+; GFX10PLUS-LABEL: s_ssubsat_v4i32:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    v_sub_nc_i32 v0, s0, s4 clamp
+; GFX10PLUS-NEXT:    v_sub_nc_i32 v1, s1, s5 clamp
+; GFX10PLUS-NEXT:    v_sub_nc_i32 v2, s2, s6 clamp
+; GFX10PLUS-NEXT:    v_sub_nc_i32 v3, s3, s7 clamp
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s0, v0
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s1, v1
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s2, v2
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s3, v3
+; GFX10PLUS-NEXT:    ; return to shader part epilog
   %result = call <4 x i32> @llvm.ssub.sat.v4i32(<4 x i32> %lhs, <4 x i32> %rhs)
   ret <4 x i32> %result
 }
 
 define <5 x i32> @v_ssubsat_v5i32(<5 x i32> %lhs, <5 x i32> %rhs) {
 ; GFX6-LABEL: v_ssubsat_v5i32:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    v_sub_i32 v0, v0, v5 clamp
 ; GFX9-NEXT:    v_sub_i32 v1, v1, v6 clamp
 ; GFX9-NEXT:    v_sub_i32 v2, v2, v7 clamp
 ; GFX9-NEXT:    v_sub_i32 v3, v3, v8 clamp
 ; GFX9-NEXT:    v_sub_i32 v4, v4, v9 clamp
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX10-LABEL: v_ssubsat_v5i32:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_sub_nc_i32 v0, v0, v5 clamp
-; GFX10-NEXT:    v_sub_nc_i32 v1, v1, v6 clamp
-; GFX10-NEXT:    v_sub_nc_i32 v2, v2, v7 clamp
-; GFX10-NEXT:    v_sub_nc_i32 v3, v3, v8 clamp
-; GFX10-NEXT:    v_sub_nc_i32 v4, v4, v9 clamp
-; GFX10-NEXT:    s_setpc_b64 s[30:31]
+; GFX10PLUS-LABEL: v_ssubsat_v5i32:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX10PLUS-NEXT:    v_sub_nc_i32 v0, v0, v5 clamp
+; GFX10PLUS-NEXT:    v_sub_nc_i32 v1, v1, v6 clamp
+; GFX10PLUS-NEXT:    v_sub_nc_i32 v2, v2, v7 clamp
+; GFX10PLUS-NEXT:    v_sub_nc_i32 v3, v3, v8 clamp
+; GFX10PLUS-NEXT:    v_sub_nc_i32 v4, v4, v9 clamp
+; GFX10PLUS-NEXT:    s_setpc_b64 s[30:31]
   %result = call <5 x i32> @llvm.ssub.sat.v5i32(<5 x i32> %lhs, <5 x i32> %rhs)
   ret <5 x i32> %result
 }
 
 define amdgpu_ps <5 x i32> @s_ssubsat_v5i32(<5 x i32> inreg %lhs, <5 x i32> inreg %rhs) {
 ; GFX6-LABEL: s_ssubsat_v5i32:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_max_i32 s10, s0, -1

 ; GFX9-NEXT:    v_sub_i32 v4, s4, v4 clamp
 ; GFX9-NEXT:    v_readfirstlane_b32 s0, v0
 ; GFX9-NEXT:    v_readfirstlane_b32 s1, v1
 ; GFX9-NEXT:    v_readfirstlane_b32 s2, v2
 ; GFX9-NEXT:    v_readfirstlane_b32 s3, v3
 ; GFX9-NEXT:    v_readfirstlane_b32 s4, v4
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
-; GFX10-LABEL: s_ssubsat_v5i32:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_sub_nc_i32 v0, s0, s5 clamp
-; GFX10-NEXT:    v_sub_nc_i32 v1, s1, s6 clamp
-; GFX10-NEXT:    v_sub_nc_i32 v2, s2, s7 clamp
-; GFX10-NEXT:    v_sub_nc_i32 v3, s3, s8 clamp
-; GFX10-NEXT:    v_sub_nc_i32 v4, s4, s9 clamp
-; GFX10-NEXT:    v_readfirstlane_b32 s0, v0
-; GFX10-NEXT:    v_readfirstlane_b32 s1, v1
-; GFX10-NEXT:    v_readfirstlane_b32 s2, v2
-; GFX10-NEXT:    v_readfirstlane_b32 s3, v3
-; GFX10-NEXT:    v_readfirstlane_b32 s4, v4
-; GFX10-NEXT:    ; return to shader part epilog
+; GFX10PLUS-LABEL: s_ssubsat_v5i32:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    v_sub_nc_i32 v0, s0, s5 clamp
+; GFX10PLUS-NEXT:    v_sub_nc_i32 v1, s1, s6 clamp
+; GFX10PLUS-NEXT:    v_sub_nc_i32 v2, s2, s7 clamp
+; GFX10PLUS-NEXT:    v_sub_nc_i32 v3, s3, s8 clamp
+; GFX10PLUS-NEXT:    v_sub_nc_i32 v4, s4, s9 clamp
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s0, v0
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s1, v1
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s2, v2
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s3, v3
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s4, v4
+; GFX10PLUS-NEXT:    ; return to shader part epilog
   %result = call <5 x i32> @llvm.ssub.sat.v5i32(<5 x i32> %lhs, <5 x i32> %rhs)
   ret <5 x i32> %result
 }
 
 define <16 x i32> @v_ssubsat_v16i32(<16 x i32> %lhs, <16 x i32> %rhs) {
 ; GFX6-LABEL: v_ssubsat_v16i32:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

 ; GFX10-NEXT:    v_sub_nc_i32 v10, v10, v26 clamp
 ; GFX10-NEXT:    v_sub_nc_i32 v11, v11, v27 clamp
 ; GFX10-NEXT:    v_sub_nc_i32 v12, v12, v28 clamp
 ; GFX10-NEXT:    v_sub_nc_i32 v13, v13, v29 clamp
 ; GFX10-NEXT:    v_sub_nc_i32 v14, v14, v30 clamp
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    v_sub_nc_i32 v15, v15, v31 clamp
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_ssubsat_v16i32:
+; GFX11:       ; %bb.0:
+; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT:    scratch_load_b32 v31, off, s32
+; GFX11-NEXT:    v_sub_nc_i32 v0, v0, v16 clamp
+; GFX11-NEXT:    v_sub_nc_i32 v1, v1, v17 clamp
+; GFX11-NEXT:    v_sub_nc_i32 v2, v2, v18 clamp
+; GFX11-NEXT:    v_sub_nc_i32 v3, v3, v19 clamp
+; GFX11-NEXT:    v_sub_nc_i32 v4, v4, v20 clamp
+; GFX11-NEXT:    v_sub_nc_i32 v5, v5, v21 clamp
+; GFX11-NEXT:    v_sub_nc_i32 v6, v6, v22 clamp
+; GFX11-NEXT:    v_sub_nc_i32 v7, v7, v23 clamp
+; GFX11-NEXT:    v_sub_nc_i32 v8, v8, v24 clamp
+; GFX11-NEXT:    v_sub_nc_i32 v9, v9, v25 clamp
+; GFX11-NEXT:    v_sub_nc_i32 v10, v10, v26 clamp
+; GFX11-NEXT:    v_sub_nc_i32 v11, v11, v27 clamp
+; GFX11-NEXT:    v_sub_nc_i32 v12, v12, v28 clamp
+; GFX11-NEXT:    v_sub_nc_i32 v13, v13, v29 clamp
+; GFX11-NEXT:    v_sub_nc_i32 v14, v14, v30 clamp
+; GFX11-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-NEXT:    v_sub_nc_i32 v15, v15, v31 clamp
+; GFX11-NEXT:    s_setpc_b64 s[30:31]
   %result = call <16 x i32> @llvm.ssub.sat.v16i32(<16 x i32> %lhs, <16 x i32> %rhs)
   ret <16 x i32> %result
 }
 
 define amdgpu_ps <16 x i32> @s_ssubsat_v16i32(<16 x i32> inreg %lhs, <16 x i32> inreg %rhs) {
 ; GFX6-LABEL: s_ssubsat_v16i32:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_max_i32 s32, s0, -1

 ; GFX9-NEXT:    v_readfirstlane_b32 s10, v10
 ; GFX9-NEXT:    v_readfirstlane_b32 s11, v11
 ; GFX9-NEXT:    v_readfirstlane_b32 s12, v12
 ; GFX9-NEXT:    v_readfirstlane_b32 s13, v13
 ; GFX9-NEXT:    v_readfirstlane_b32 s14, v14
 ; GFX9-NEXT:    v_readfirstlane_b32 s15, v15
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
-; GFX10-LABEL: s_ssubsat_v16i32:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_sub_nc_i32 v0, s0, s16 clamp
-; GFX10-NEXT:    v_sub_nc_i32 v1, s1, s17 clamp
-; GFX10-NEXT:    v_sub_nc_i32 v2, s2, s18 clamp
-; GFX10-NEXT:    v_sub_nc_i32 v3, s3, s19 clamp
-; GFX10-NEXT:    v_sub_nc_i32 v4, s4, s20 clamp
-; GFX10-NEXT:    v_sub_nc_i32 v5, s5, s21 clamp
-; GFX10-NEXT:    v_sub_nc_i32 v6, s6, s22 clamp
-; GFX10-NEXT:    v_sub_nc_i32 v7, s7, s23 clamp
-; GFX10-NEXT:    v_sub_nc_i32 v8, s8, s24 clamp
-; GFX10-NEXT:    v_sub_nc_i32 v9, s9, s25 clamp
-; GFX10-NEXT:    v_sub_nc_i32 v10, s10, s26 clamp
-; GFX10-NEXT:    v_sub_nc_i32 v11, s11, s27 clamp
-; GFX10-NEXT:    v_sub_nc_i32 v12, s12, s28 clamp
-; GFX10-NEXT:    v_sub_nc_i32 v13, s13, s29 clamp
-; GFX10-NEXT:    v_sub_nc_i32 v14, s14, s30 clamp
-; GFX10-NEXT:    v_sub_nc_i32 v15, s15, s31 clamp
-; GFX10-NEXT:    v_readfirstlane_b32 s0, v0
-; GFX10-NEXT:    v_readfirstlane_b32 s1, v1
-; GFX10-NEXT:    v_readfirstlane_b32 s2, v2
-; GFX10-NEXT:    v_readfirstlane_b32 s3, v3
-; GFX10-NEXT:    v_readfirstlane_b32 s4, v4
-; GFX10-NEXT:    v_readfirstlane_b32 s5, v5
-; GFX10-NEXT:    v_readfirstlane_b32 s6, v6
-; GFX10-NEXT:    v_readfirstlane_b32 s7, v7
-; GFX10-NEXT:    v_readfirstlane_b32 s8, v8
-; GFX10-NEXT:    v_readfirstlane_b32 s9, v9
-; GFX10-NEXT:    v_readfirstlane_b32 s10, v10
-; GFX10-NEXT:    v_readfirstlane_b32 s11, v11
-; GFX10-NEXT:    v_readfirstlane_b32 s12, v12
-; GFX10-NEXT:    v_readfirstlane_b32 s13, v13
-; GFX10-NEXT:    v_readfirstlane_b32 s14, v14
-; GFX10-NEXT:    v_readfirstlane_b32 s15, v15
-; GFX10-NEXT:    ; return to shader part epilog
+; GFX10PLUS-LABEL: s_ssubsat_v16i32:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    v_sub_nc_i32 v0, s0, s16 clamp
+; GFX10PLUS-NEXT:    v_sub_nc_i32 v1, s1, s17 clamp
+; GFX10PLUS-NEXT:    v_sub_nc_i32 v2, s2, s18 clamp
+; GFX10PLUS-NEXT:    v_sub_nc_i32 v3, s3, s19 clamp
+; GFX10PLUS-NEXT:    v_sub_nc_i32 v4, s4, s20 clamp
+; GFX10PLUS-NEXT:    v_sub_nc_i32 v5, s5, s21 clamp
+; GFX10PLUS-NEXT:    v_sub_nc_i32 v6, s6, s22 clamp
+; GFX10PLUS-NEXT:    v_sub_nc_i32 v7, s7, s23 clamp
+; GFX10PLUS-NEXT:    v_sub_nc_i32 v8, s8, s24 clamp
+; GFX10PLUS-NEXT:    v_sub_nc_i32 v9, s9, s25 clamp
+; GFX10PLUS-NEXT:    v_sub_nc_i32 v10, s10, s26 clamp
+; GFX10PLUS-NEXT:    v_sub_nc_i32 v11, s11, s27 clamp
+; GFX10PLUS-NEXT:    v_sub_nc_i32 v12, s12, s28 clamp
+; GFX10PLUS-NEXT:    v_sub_nc_i32 v13, s13, s29 clamp
+; GFX10PLUS-NEXT:    v_sub_nc_i32 v14, s14, s30 clamp
+; GFX10PLUS-NEXT:    v_sub_nc_i32 v15, s15, s31 clamp
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s0, v0
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s1, v1
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s2, v2
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s3, v3
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s4, v4
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s5, v5
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s6, v6
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s7, v7
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s8, v8
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s9, v9
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s10, v10
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s11, v11
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s12, v12
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s13, v13
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s14, v14
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s15, v15
+; GFX10PLUS-NEXT:    ; return to shader part epilog
   %result = call <16 x i32> @llvm.ssub.sat.v16i32(<16 x i32> %lhs, <16 x i32> %rhs)
   ret <16 x i32> %result
 }
 
 define i16 @v_ssubsat_i16(i16 %lhs, i16 %rhs) {
 ; GFX6-LABEL: v_ssubsat_i16:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

 ; GFX8-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX9-LABEL: v_ssubsat_i16:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    v_sub_i16 v0, v0, v1 clamp
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX10-LABEL: v_ssubsat_i16:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_sub_nc_i16 v0, v0, v1 clamp
-; GFX10-NEXT:    s_setpc_b64 s[30:31]
+; GFX10PLUS-LABEL: v_ssubsat_i16:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX10PLUS-NEXT:    v_sub_nc_i16 v0, v0, v1 clamp
+; GFX10PLUS-NEXT:    s_setpc_b64 s[30:31]
   %result = call i16 @llvm.ssub.sat.i16(i16 %lhs, i16 %rhs)
   ret i16 %result
 }
 
 define amdgpu_ps i16 @s_ssubsat_i16(i16 inreg %lhs, i16 inreg %rhs) {
 ; GFX6-LABEL: s_ssubsat_i16:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_lshl_b32 s0, s0, 16

 ;
 ; GFX9-LABEL: s_ssubsat_i16:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    v_mov_b32_e32 v0, s1
 ; GFX9-NEXT:    v_sub_i16 v0, s0, v0 clamp
 ; GFX9-NEXT:    v_readfirstlane_b32 s0, v0
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
-; GFX10-LABEL: s_ssubsat_i16:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_sub_nc_i16 v0, s0, s1 clamp
-; GFX10-NEXT:    v_readfirstlane_b32 s0, v0
-; GFX10-NEXT:    ; return to shader part epilog
+; GFX10PLUS-LABEL: s_ssubsat_i16:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    v_sub_nc_i16 v0, s0, s1 clamp
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s0, v0
+; GFX10PLUS-NEXT:    ; return to shader part epilog
   %result = call i16 @llvm.ssub.sat.i16(i16 %lhs, i16 %rhs)
   ret i16 %result
 }
 
 define amdgpu_ps half @ssubsat_i16_sv(i16 inreg %lhs, i16 %rhs) {
 ; GFX6-LABEL: ssubsat_i16_sv:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_lshl_b32 s0, s0, 16

 ; GFX8-NEXT:    v_sub_u16_e32 v0, s0, v0
 ; GFX8-NEXT:    ; return to shader part epilog
 ;
 ; GFX9-LABEL: ssubsat_i16_sv:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    v_sub_i16 v0, s0, v0 clamp
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
-; GFX10-LABEL: ssubsat_i16_sv:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_sub_nc_i16 v0, s0, v0 clamp
-; GFX10-NEXT:    ; return to shader part epilog
+; GFX10PLUS-LABEL: ssubsat_i16_sv:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    v_sub_nc_i16 v0, s0, v0 clamp
+; GFX10PLUS-NEXT:    ; return to shader part epilog
   %result = call i16 @llvm.ssub.sat.i16(i16 %lhs, i16 %rhs)
   %cast = bitcast i16 %result to half
   ret half %cast
 }
 
 define amdgpu_ps half @ssubsat_i16_vs(i16 %lhs, i16 inreg %rhs) {
 ; GFX6-LABEL: ssubsat_i16_vs:
 ; GFX6:       ; %bb.0:

 ; GFX8-NEXT:    v_sub_u16_e32 v0, v0, v1
 ; GFX8-NEXT:    ; return to shader part epilog
 ;
 ; GFX9-LABEL: ssubsat_i16_vs:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    v_sub_i16 v0, v0, s0 clamp
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
-; GFX10-LABEL: ssubsat_i16_vs:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_sub_nc_i16 v0, v0, s0 clamp
-; GFX10-NEXT:    ; return to shader part epilog
+; GFX10PLUS-LABEL: ssubsat_i16_vs:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    v_sub_nc_i16 v0, v0, s0 clamp
+; GFX10PLUS-NEXT:    ; return to shader part epilog
   %result = call i16 @llvm.ssub.sat.i16(i16 %lhs, i16 %rhs)
   %cast = bitcast i16 %result to half
   ret half %cast
 }
 
 define <2 x i16> @v_ssubsat_v2i16(<2 x i16> %lhs, <2 x i16> %rhs) {
 ; GFX6-LABEL: v_ssubsat_v2i16:
 ; GFX6:       ; %bb.0:

 ; GFX8-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX9-LABEL: v_ssubsat_v2i16:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    v_pk_sub_i16 v0, v0, v1 clamp
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX10-LABEL: v_ssubsat_v2i16:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_pk_sub_i16 v0, v0, v1 clamp
-; GFX10-NEXT:    s_setpc_b64 s[30:31]
+; GFX10PLUS-LABEL: v_ssubsat_v2i16:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX10PLUS-NEXT:    v_pk_sub_i16 v0, v0, v1 clamp
+; GFX10PLUS-NEXT:    s_setpc_b64 s[30:31]
   %result = call <2 x i16> @llvm.ssub.sat.v2i16(<2 x i16> %lhs, <2 x i16> %rhs)
   ret <2 x i16> %result
 }
 
 define amdgpu_ps i32 @s_ssubsat_v2i16(<2 x i16> inreg %lhs, <2 x i16> inreg %rhs) {
 ; GFX6-LABEL: s_ssubsat_v2i16:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_lshl_b32 s0, s0, 16

 ;
 ; GFX9-LABEL: s_ssubsat_v2i16:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    v_mov_b32_e32 v0, s1
 ; GFX9-NEXT:    v_pk_sub_i16 v0, s0, v0 clamp
 ; GFX9-NEXT:    v_readfirstlane_b32 s0, v0
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
-; GFX10-LABEL: s_ssubsat_v2i16:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_pk_sub_i16 v0, s0, s1 clamp
-; GFX10-NEXT:    v_readfirstlane_b32 s0, v0
-; GFX10-NEXT:    ; return to shader part epilog
+; GFX10PLUS-LABEL: s_ssubsat_v2i16:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    v_pk_sub_i16 v0, s0, s1 clamp
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s0, v0
+; GFX10PLUS-NEXT:    ; return to shader part epilog
   %result = call <2 x i16> @llvm.ssub.sat.v2i16(<2 x i16> %lhs, <2 x i16> %rhs)
   %cast = bitcast <2 x i16> %result to i32
   ret i32 %cast
 }
 
 define amdgpu_ps float @ssubsat_v2i16_sv(<2 x i16> inreg %lhs, <2 x i16> %rhs) {
 ; GFX6-LABEL: ssubsat_v2i16_sv:
 ; GFX6:       ; %bb.0:

 ; GFX8-NEXT:    v_or_b32_e32 v0, v1, v0
 ; GFX8-NEXT:    ; return to shader part epilog
 ;
 ; GFX9-LABEL: ssubsat_v2i16_sv:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    v_pk_sub_i16 v0, s0, v0 clamp
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
-; GFX10-LABEL: ssubsat_v2i16_sv:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_pk_sub_i16 v0, s0, v0 clamp
-; GFX10-NEXT:    ; return to shader part epilog
+; GFX10PLUS-LABEL: ssubsat_v2i16_sv:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    v_pk_sub_i16 v0, s0, v0 clamp
+; GFX10PLUS-NEXT:    ; return to shader part epilog
   %result = call <2 x i16> @llvm.ssub.sat.v2i16(<2 x i16> %lhs, <2 x i16> %rhs)
   %cast = bitcast <2 x i16> %result to float
   ret float %cast
 }
 
 define amdgpu_ps float @ssubsat_v2i16_vs(<2 x i16> %lhs, <2 x i16> inreg %rhs) {
 ; GFX6-LABEL: ssubsat_v2i16_vs:
 ; GFX6:       ; %bb.0:

 ; GFX8-NEXT:    v_or_b32_e32 v0, v0, v1
 ; GFX8-NEXT:    ; return to shader part epilog
 ;
 ; GFX9-LABEL: ssubsat_v2i16_vs:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    v_pk_sub_i16 v0, v0, s0 clamp
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
-; GFX10-LABEL: ssubsat_v2i16_vs:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_pk_sub_i16 v0, v0, s0 clamp
-; GFX10-NEXT:    ; return to shader part epilog
+; GFX10PLUS-LABEL: ssubsat_v2i16_vs:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    v_pk_sub_i16 v0, v0, s0 clamp
+; GFX10PLUS-NEXT:    ; return to shader part epilog
   %result = call <2 x i16> @llvm.ssub.sat.v2i16(<2 x i16> %lhs, <2 x i16> %rhs)
   %cast = bitcast <2 x i16> %result to float
   ret float %cast
 }
 
 ; FIXME: v3i16 insert/extract
 ; define <3 x i16> @v_ssubsat_v3i16(<3 x i16> %lhs, <3 x i16> %rhs) {
 ;   %result = call <3 x i16> @llvm.ssub.sat.v3i16(<3 x i16> %lhs, <3 x i16> %rhs)

 ;
 ; GFX9-LABEL: v_ssubsat_v4i16:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    v_pk_sub_i16 v0, v0, v2 clamp
 ; GFX9-NEXT:    v_pk_sub_i16 v1, v1, v3 clamp
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX10-LABEL: v_ssubsat_v4i16:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_pk_sub_i16 v0, v0, v2 clamp
-; GFX10-NEXT:    v_pk_sub_i16 v1, v1, v3 clamp
-; GFX10-NEXT:    s_setpc_b64 s[30:31]
+; GFX10PLUS-LABEL: v_ssubsat_v4i16:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX10PLUS-NEXT:    v_pk_sub_i16 v0, v0, v2 clamp
+; GFX10PLUS-NEXT:    v_pk_sub_i16 v1, v1, v3 clamp
+; GFX10PLUS-NEXT:    s_setpc_b64 s[30:31]
   %result = call <4 x i16> @llvm.ssub.sat.v4i16(<4 x i16> %lhs, <4 x i16> %rhs)
   %cast = bitcast <4 x i16> %result to <2 x float>
   ret <2 x float> %cast
 }
 
 define amdgpu_ps <2 x i32> @s_ssubsat_v4i16(<4 x i16> inreg %lhs, <4 x i16> inreg %rhs) {
 ; GFX6-LABEL: s_ssubsat_v4i16:
 ; GFX6:       ; %bb.0:

 ; GFX9-NEXT:    v_mov_b32_e32 v0, s2
 ; GFX9-NEXT:    v_mov_b32_e32 v1, s3
 ; GFX9-NEXT:    v_pk_sub_i16 v0, s0, v0 clamp
 ; GFX9-NEXT:    v_pk_sub_i16 v1, s1, v1 clamp
 ; GFX9-NEXT:    v_readfirstlane_b32 s0, v0
 ; GFX9-NEXT:    v_readfirstlane_b32 s1, v1
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
-; GFX10-LABEL: s_ssubsat_v4i16:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_pk_sub_i16 v0, s0, s2 clamp
-; GFX10-NEXT:    v_pk_sub_i16 v1, s1, s3 clamp
-; GFX10-NEXT:    v_readfirstlane_b32 s0, v0
-; GFX10-NEXT:    v_readfirstlane_b32 s1, v1
-; GFX10-NEXT:    ; return to shader part epilog
+; GFX10PLUS-LABEL: s_ssubsat_v4i16:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    v_pk_sub_i16 v0, s0, s2 clamp
+; GFX10PLUS-NEXT:    v_pk_sub_i16 v1, s1, s3 clamp
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s0, v0
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s1, v1
+; GFX10PLUS-NEXT:    ; return to shader part epilog
   %result = call <4 x i16> @llvm.ssub.sat.v4i16(<4 x i16> %lhs, <4 x i16> %rhs)
   %cast = bitcast <4 x i16> %result to <2 x i32>
   ret <2 x i32> %cast
 }
 
 ; FIXME
 ; define <5 x i16> @v_ssubsat_v5i16(<5 x i16> %lhs, <5 x i16> %rhs) {
 ;   %result = call <5 x i16> @llvm.ssub.sat.v5i16(<5 x i16> %lhs, <5 x i16> %rhs)

 ; GFX9-LABEL: v_ssubsat_v6i16:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    v_pk_sub_i16 v0, v0, v3 clamp
 ; GFX9-NEXT:    v_pk_sub_i16 v1, v1, v4 clamp
 ; GFX9-NEXT:    v_pk_sub_i16 v2, v2, v5 clamp
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX10-LABEL: v_ssubsat_v6i16:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_pk_sub_i16 v0, v0, v3 clamp
-; GFX10-NEXT:    v_pk_sub_i16 v1, v1, v4 clamp
-; GFX10-NEXT:    v_pk_sub_i16 v2, v2, v5 clamp
-; GFX10-NEXT:    s_setpc_b64 s[30:31]
+; GFX10PLUS-LABEL: v_ssubsat_v6i16:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX10PLUS-NEXT:    v_pk_sub_i16 v0, v0, v3 clamp
+; GFX10PLUS-NEXT:    v_pk_sub_i16 v1, v1, v4 clamp
+; GFX10PLUS-NEXT:    v_pk_sub_i16 v2, v2, v5 clamp
+; GFX10PLUS-NEXT:    s_setpc_b64 s[30:31]
   %result = call <6 x i16> @llvm.ssub.sat.v6i16(<6 x i16> %lhs, <6 x i16> %rhs)
   %cast = bitcast <6 x i16> %result to <3 x float>
   ret <3 x float> %cast
 }
 
 define amdgpu_ps <3 x i32> @s_ssubsat_v6i16(<6 x i16> inreg %lhs, <6 x i16> inreg %rhs) {
 ; GFX6-LABEL: s_ssubsat_v6i16:
 ; GFX6:       ; %bb.0:

 ; GFX9-NEXT:    v_pk_sub_i16 v0, s0, v0 clamp
 ; GFX9-NEXT:    v_pk_sub_i16 v1, s1, v1 clamp
 ; GFX9-NEXT:    v_pk_sub_i16 v2, s2, v2 clamp
 ; GFX9-NEXT:    v_readfirstlane_b32 s0, v0
 ; GFX9-NEXT:    v_readfirstlane_b32 s1, v1
 ; GFX9-NEXT:    v_readfirstlane_b32 s2, v2
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
-; GFX10-LABEL: s_ssubsat_v6i16:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_pk_sub_i16 v0, s0, s3 clamp
-; GFX10-NEXT:    v_pk_sub_i16 v1, s1, s4 clamp
-; GFX10-NEXT:    v_pk_sub_i16 v2, s2, s5 clamp
-; GFX10-NEXT:    v_readfirstlane_b32 s0, v0
-; GFX10-NEXT:    v_readfirstlane_b32 s1, v1
-; GFX10-NEXT:    v_readfirstlane_b32 s2, v2
-; GFX10-NEXT:    ; return to shader part epilog
+; GFX10PLUS-LABEL: s_ssubsat_v6i16:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    v_pk_sub_i16 v0, s0, s3 clamp
+; GFX10PLUS-NEXT:    v_pk_sub_i16 v1, s1, s4 clamp
+; GFX10PLUS-NEXT:    v_pk_sub_i16 v2, s2, s5 clamp
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s0, v0
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s1, v1
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s2, v2
+; GFX10PLUS-NEXT:    ; return to shader part epilog
   %result = call <6 x i16> @llvm.ssub.sat.v6i16(<6 x i16> %lhs, <6 x i16> %rhs)
   %cast = bitcast <6 x i16> %result to <3 x i32>
   ret <3 x i32> %cast
 }
 
 define <4 x float> @v_ssubsat_v8i16(<8 x i16> %lhs, <8 x i16> %rhs) {
 ; GFX6-LABEL: v_ssubsat_v8i16:
 ; GFX6:       ; %bb.0:

 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    v_pk_sub_i16 v0, v0, v4 clamp
 ; GFX9-NEXT:    v_pk_sub_i16 v1, v1, v5 clamp
 ; GFX9-NEXT:    v_pk_sub_i16 v2, v2, v6 clamp
 ; GFX9-NEXT:    v_pk_sub_i16 v3, v3, v7 clamp
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX10-LABEL: v_ssubsat_v8i16:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_pk_sub_i16 v0, v0, v4 clamp
-; GFX10-NEXT:    v_pk_sub_i16 v1, v1, v5 clamp
-; GFX10-NEXT:    v_pk_sub_i16 v2, v2, v6 clamp
-; GFX10-NEXT:    v_pk_sub_i16 v3, v3, v7 clamp
-; GFX10-NEXT:    s_setpc_b64 s[30:31]
+; GFX10PLUS-LABEL: v_ssubsat_v8i16:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX10PLUS-NEXT:    v_pk_sub_i16 v0, v0, v4 clamp
+; GFX10PLUS-NEXT:    v_pk_sub_i16 v1, v1, v5 clamp
+; GFX10PLUS-NEXT:    v_pk_sub_i16 v2, v2, v6 clamp
+; GFX10PLUS-NEXT:    v_pk_sub_i16 v3, v3, v7 clamp
+; GFX10PLUS-NEXT:    s_setpc_b64 s[30:31]
   %result = call <8 x i16> @llvm.ssub.sat.v8i16(<8 x i16> %lhs, <8 x i16> %rhs)
   %cast = bitcast <8 x i16> %result to <4 x float>
   ret <4 x float> %cast
 }
 
 define amdgpu_ps <4 x i32> @s_ssubsat_v8i16(<8 x i16> inreg %lhs, <8 x i16> inreg %rhs) {
 ; GFX6-LABEL: s_ssubsat_v8i16:
 ; GFX6:       ; %bb.0:

 ; GFX9-NEXT:    v_pk_sub_i16 v2, s2, v2 clamp
 ; GFX9-NEXT:    v_pk_sub_i16 v3, s3, v3 clamp
 ; GFX9-NEXT:    v_readfirstlane_b32 s0, v0
 ; GFX9-NEXT:    v_readfirstlane_b32 s1, v1
 ; GFX9-NEXT:    v_readfirstlane_b32 s2, v2
 ; GFX9-NEXT:    v_readfirstlane_b32 s3, v3
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
-; GFX10-LABEL: s_ssubsat_v8i16:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_pk_sub_i16 v0, s0, s4 clamp
-; GFX10-NEXT:    v_pk_sub_i16 v1, s1, s5 clamp
-; GFX10-NEXT:    v_pk_sub_i16 v2, s2, s6 clamp
-; GFX10-NEXT:    v_pk_sub_i16 v3, s3, s7 clamp
-; GFX10-NEXT:    v_readfirstlane_b32 s0, v0
-; GFX10-NEXT:    v_readfirstlane_b32 s1, v1
-; GFX10-NEXT:    v_readfirstlane_b32 s2, v2
-; GFX10-NEXT:    v_readfirstlane_b32 s3, v3
-; GFX10-NEXT:    ; return to shader part epilog
+; GFX10PLUS-LABEL: s_ssubsat_v8i16:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    v_pk_sub_i16 v0, s0, s4 clamp
+; GFX10PLUS-NEXT:    v_pk_sub_i16 v1, s1, s5 clamp
+; GFX10PLUS-NEXT:    v_pk_sub_i16 v2, s2, s6 clamp
+; GFX10PLUS-NEXT:    v_pk_sub_i16 v3, s3, s7 clamp
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s0, v0
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s1, v1
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s2, v2
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s3, v3
+; GFX10PLUS-NEXT:    ; return to shader part epilog
   %result = call <8 x i16> @llvm.ssub.sat.v8i16(<8 x i16> %lhs, <8 x i16> %rhs)
   %cast = bitcast <8 x i16> %result to <4 x i32>
   ret <4 x i32> %cast
 }
 
 ; FIXME: i48 broken because i48 add broken
 ; define i48 @v_ssubsat_i48(i48 %lhs, i48 %rhs) {
 ;   %result = call i48 @llvm.ssub.sat.i48(i48 %lhs, i48 %rhs)

 ; GFX10-NEXT:    s_mov_b32 s5, 0
 ; GFX10-NEXT:    v_ashrrev_i32_e32 v6, 31, v5
 ; GFX10-NEXT:    v_cmp_lt_i64_e32 vcc_lo, v[4:5], v[0:1]
 ; GFX10-NEXT:    v_add_co_ci_u32_e64 v1, s5, 0x80000000, v6, s5
 ; GFX10-NEXT:    s_xor_b32 vcc_lo, s4, vcc_lo
 ; GFX10-NEXT:    v_cndmask_b32_e32 v0, v4, v6, vcc_lo
 ; GFX10-NEXT:    v_cndmask_b32_e32 v1, v5, v1, vcc_lo
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_ssubsat_i64:
+; GFX11:       ; %bb.0:
+; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT:    v_sub_co_u32 v4, vcc_lo, v0, v2
+; GFX11-NEXT:    v_sub_co_ci_u32_e32 v5, vcc_lo, v1, v3, vcc_lo
+; GFX11-NEXT:    v_cmp_lt_i64_e64 s0, 0, v[2:3]
+; GFX11-NEXT:    s_mov_b32 s1, 0
+; GFX11-NEXT:    v_ashrrev_i32_e32 v6, 31, v5
+; GFX11-NEXT:    v_cmp_lt_i64_e32 vcc_lo, v[4:5], v[0:1]
+; GFX11-NEXT:    v_add_co_ci_u32_e64 v1, s1, 0x80000000, v6, s1
+; GFX11-NEXT:    s_xor_b32 vcc_lo, s0, vcc_lo
+; GFX11-NEXT:    v_cndmask_b32_e32 v0, v4, v6, vcc_lo
+; GFX11-NEXT:    v_cndmask_b32_e32 v1, v5, v1, vcc_lo
+; GFX11-NEXT:    s_setpc_b64 s[30:31]
   %result = call i64 @llvm.ssub.sat.i64(i64 %lhs, i64 %rhs)
   ret i64 %result
 }
 
 define amdgpu_ps i64 @s_ssubsat_i64(i64 inreg %lhs, i64 inreg %rhs) {
 ; GFX6-LABEL: s_ssubsat_i64:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_sub_u32 s4, s0, s2

 ; GFX9-NEXT:    v_mov_b32_e32 v2, s1
 ; GFX9-NEXT:    v_mov_b32_e32 v3, s5
 ; GFX9-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc
 ; GFX9-NEXT:    v_cndmask_b32_e32 v1, v3, v2, vcc
 ; GFX9-NEXT:    v_readfirstlane_b32 s0, v0
 ; GFX9-NEXT:    v_readfirstlane_b32 s1, v1
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
-; GFX10-LABEL: s_ssubsat_i64:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    s_sub_u32 s4, s0, s2
-; GFX10-NEXT:    s_subb_u32 s5, s1, s3
-; GFX10-NEXT:    v_cmp_gt_i64_e64 s2, s[2:3], 0
-; GFX10-NEXT:    v_cmp_lt_i64_e64 s1, s[4:5], s[0:1]
-; GFX10-NEXT:    s_mov_b32 s3, 0
-; GFX10-NEXT:    s_ashr_i32 s0, s5, 31
-; GFX10-NEXT:    v_mov_b32_e32 v0, s4
-; GFX10-NEXT:    v_mov_b32_e32 v1, s5
-; GFX10-NEXT:    s_xor_b32 s2, s2, s1
-; GFX10-NEXT:    s_cmp_lg_u32 s3, 0
-; GFX10-NEXT:    v_cndmask_b32_e64 v0, v0, s0, s2
-; GFX10-NEXT:    s_addc_u32 s1, s0, 0x80000000
-; GFX10-NEXT:    v_cndmask_b32_e64 v1, v1, s1, s2
-; GFX10-NEXT:    v_readfirstlane_b32 s0, v0
-; GFX10-NEXT:    v_readfirstlane_b32 s1, v1
-; GFX10-NEXT:    ; return to shader part epilog
+; GFX10PLUS-LABEL: s_ssubsat_i64:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    s_sub_u32 s4, s0, s2
+; GFX10PLUS-NEXT:    s_subb_u32 s5, s1, s3
+; GFX10PLUS-NEXT:    v_cmp_gt_i64_e64 s2, s[2:3], 0
+; GFX10PLUS-NEXT:    v_cmp_lt_i64_e64 s1, s[4:5], s[0:1]
+; GFX10PLUS-NEXT:    s_mov_b32 s3, 0
+; GFX10PLUS-NEXT:    s_ashr_i32 s0, s5, 31
+; GFX10PLUS-NEXT:    v_mov_b32_e32 v0, s4
+; GFX10PLUS-NEXT:    v_mov_b32_e32 v1, s5
+; GFX10PLUS-NEXT:    s_xor_b32 s2, s2, s1
+; GFX10PLUS-NEXT:    s_cmp_lg_u32 s3, 0
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v0, v0, s0, s2
+; GFX10PLUS-NEXT:    s_addc_u32 s1, s0, 0x80000000
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v1, v1, s1, s2
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s0, v0
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s1, v1
+; GFX10PLUS-NEXT:    ; return to shader part epilog
   %result = call i64 @llvm.ssub.sat.i64(i64 %lhs, i64 %rhs)
   ret i64 %result
 }
 
 define amdgpu_ps <2 x float> @ssubsat_i64_sv(i64 inreg %lhs, i64 %rhs) {
 ; GFX6-LABEL: ssubsat_i64_sv:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    v_mov_b32_e32 v3, s1

 ; GFX9-NEXT:    v_bfrev_b32_e32 v1, 1
 ; GFX9-NEXT:    s_mov_b64 s[2:3], 0
 ; GFX9-NEXT:    v_addc_co_u32_e64 v1, s[2:3], v0, v1, s[2:3]
 ; GFX9-NEXT:    s_xor_b64 vcc, s[0:1], vcc
 ; GFX9-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc
 ; GFX9-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
-; GFX10-LABEL: ssubsat_i64_sv:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_sub_co_u32 v2, vcc_lo, s0, v0
-; GFX10-NEXT:    v_sub_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
-; GFX10-NEXT:    v_ashrrev_i32_e32 v4, 31, v3
-; GFX10-NEXT:    v_cmp_gt_i64_e32 vcc_lo, s[0:1], v[2:3]
-; GFX10-NEXT:    v_cmp_lt_i64_e64 s0, 0, v[0:1]
-; GFX10-NEXT:    s_mov_b32 s1, 0
-; GFX10-NEXT:    v_add_co_ci_u32_e64 v1, s1, 0x80000000, v4, s1
-; GFX10-NEXT:    s_xor_b32 vcc_lo, s0, vcc_lo
-; GFX10-NEXT:    v_cndmask_b32_e32 v0, v2, v4, vcc_lo
-; GFX10-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc_lo
-; GFX10-NEXT:    ; return to shader part epilog
+; GFX10PLUS-LABEL: ssubsat_i64_sv:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    v_sub_co_u32 v2, vcc_lo, s0, v0
+; GFX10PLUS-NEXT:    v_sub_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
+; GFX10PLUS-NEXT:    v_ashrrev_i32_e32 v4, 31, v3
+; GFX10PLUS-NEXT:    v_cmp_gt_i64_e32 vcc_lo, s[0:1], v[2:3]
+; GFX10PLUS-NEXT:    v_cmp_lt_i64_e64 s0, 0, v[0:1]
+; GFX10PLUS-NEXT:    s_mov_b32 s1, 0
+; GFX10PLUS-NEXT:    v_add_co_ci_u32_e64 v1, s1, 0x80000000, v4, s1
+; GFX10PLUS-NEXT:    s_xor_b32 vcc_lo, s0, vcc_lo
+; GFX10PLUS-NEXT:    v_cndmask_b32_e32 v0, v2, v4, vcc_lo
+; GFX10PLUS-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc_lo
+; GFX10PLUS-NEXT:    ; return to shader part epilog
   %result = call i64 @llvm.ssub.sat.i64(i64 %lhs, i64 %rhs)
   %cast = bitcast i64 %result to <2 x float>
   ret <2 x float> %cast
 }
 
 define amdgpu_ps <2 x float> @ssubsat_i64_vs(i64 %lhs, i64 inreg %rhs) {
 ; GFX6-LABEL: ssubsat_i64_vs:
 ; GFX6:       ; %bb.0:

 ; GFX9-NEXT:    v_bfrev_b32_e32 v1, 1
 ; GFX9-NEXT:    s_mov_b64 s[0:1], 0
 ; GFX9-NEXT:    v_addc_co_u32_e64 v1, s[0:1], v0, v1, s[0:1]
 ; GFX9-NEXT:    s_xor_b64 vcc, s[2:3], vcc
 ; GFX9-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc
 ; GFX9-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
-; GFX10-LABEL: ssubsat_i64_vs:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_sub_co_u32 v2, vcc_lo, v0, s0
-; GFX10-NEXT:    v_subrev_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
-; GFX10-NEXT:    v_cmp_gt_i64_e64 s1, s[0:1], 0
-; GFX10-NEXT:    s_mov_b32 s0, 0
-; GFX10-NEXT:    v_ashrrev_i32_e32 v4, 31, v3
-; GFX10-NEXT:    v_cmp_lt_i64_e32 vcc_lo, v[2:3], v[0:1]
-; GFX10-NEXT:    v_add_co_ci_u32_e64 v1, s0, 0x80000000, v4, s0
-; GFX10-NEXT:    s_xor_b32 vcc_lo, s1, vcc_lo
-; GFX10-NEXT:    v_cndmask_b32_e32 v0, v2, v4, vcc_lo
-; GFX10-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc_lo
-; GFX10-NEXT:    ; return to shader part epilog
+; GFX10PLUS-LABEL: ssubsat_i64_vs:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    v_sub_co_u32 v2, vcc_lo, v0, s0
+; GFX10PLUS-NEXT:    v_subrev_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
+; GFX10PLUS-NEXT:    v_cmp_gt_i64_e64 s1, s[0:1], 0
+; GFX10PLUS-NEXT:    s_mov_b32 s0, 0
+; GFX10PLUS-NEXT:    v_ashrrev_i32_e32 v4, 31, v3
+; GFX10PLUS-NEXT:    v_cmp_lt_i64_e32 vcc_lo, v[2:3], v[0:1]
+; GFX10PLUS-NEXT:    v_add_co_ci_u32_e64 v1, s0, 0x80000000, v4, s0
+; GFX10PLUS-NEXT:    s_xor_b32 vcc_lo, s1, vcc_lo
+; GFX10PLUS-NEXT:    v_cndmask_b32_e32 v0, v2, v4, vcc_lo
+; GFX10PLUS-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc_lo
+; GFX10PLUS-NEXT:    ; return to shader part epilog
   %result = call i64 @llvm.ssub.sat.i64(i64 %lhs, i64 %rhs)
   %cast = bitcast i64 %result to <2 x float>
   ret <2 x float> %cast
 }
 
 define <2 x i64> @v_ssubsat_v2i64(<2 x i64> %lhs, <2 x i64> %rhs) {
 ; GFX6-LABEL: v_ssubsat_v2i64:
 ; GFX6:       ; %bb.0:

 ; GFX10-NEXT:    v_add_co_ci_u32_e64 v3, s5, 0x80000000, v4, s5
 ; GFX10-NEXT:    s_xor_b32 vcc_lo, s4, vcc_lo
 ; GFX10-NEXT:    v_cndmask_b32_e32 v0, v8, v0, vcc_lo
 ; GFX10-NEXT:    v_cndmask_b32_e32 v1, v9, v1, vcc_lo
 ; GFX10-NEXT:    s_xor_b32 vcc_lo, s7, s6
 ; GFX10-NEXT:    v_cndmask_b32_e32 v2, v10, v4, vcc_lo
 ; GFX10-NEXT:    v_cndmask_b32_e32 v3, v11, v3, vcc_lo
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_ssubsat_v2i64:
+; GFX11:       ; %bb.0:
+; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT:    v_sub_co_u32 v8, vcc_lo, v0, v4
+; GFX11-NEXT:    v_sub_co_ci_u32_e32 v9, vcc_lo, v1, v5, vcc_lo
+; GFX11-NEXT:    v_sub_co_u32 v10, vcc_lo, v2, v6
+; GFX11-NEXT:    v_sub_co_ci_u32_e32 v11, vcc_lo, v3, v7, vcc_lo
+; GFX11-NEXT:    v_cmp_lt_i64_e32 vcc_lo, v[8:9], v[0:1]
+; GFX11-NEXT:    v_ashrrev_i32_e32 v0, 31, v9
+; GFX11-NEXT:    s_mov_b32 s1, 0
+; GFX11-NEXT:    v_cmp_lt_i64_e64 s0, 0, v[4:5]
+; GFX11-NEXT:    v_ashrrev_i32_e32 v4, 31, v11
+; GFX11-NEXT:    v_cmp_lt_i64_e64 s3, 0, v[6:7]
+; GFX11-NEXT:    v_add_co_ci_u32_e64 v1, s2, 0x80000000, v0, s1
+; GFX11-NEXT:    v_cmp_lt_i64_e64 s2, v[10:11], v[2:3]
+; GFX11-NEXT:    v_add_co_ci_u32_e64 v3, s1, 0x80000000, v4, s1
+; GFX11-NEXT:    s_xor_b32 vcc_lo, s0, vcc_lo
+; GFX11-NEXT:    v_cndmask_b32_e32 v0, v8, v0, vcc_lo
+; GFX11-NEXT:    v_cndmask_b32_e32 v1, v9, v1, vcc_lo
+; GFX11-NEXT:    s_xor_b32 vcc_lo, s3, s2
+; GFX11-NEXT:    v_cndmask_b32_e32 v2, v10, v4, vcc_lo
+; GFX11-NEXT:    v_cndmask_b32_e32 v3, v11, v3, vcc_lo
+; GFX11-NEXT:    s_setpc_b64 s[30:31]
   %result = call <2 x i64> @llvm.ssub.sat.v2i64(<2 x i64> %lhs, <2 x i64> %rhs)
   ret <2 x i64> %result
 }
 
 define amdgpu_ps <2 x i64> @s_ssubsat_v2i64(<2 x i64> inreg %lhs, <2 x i64> inreg %rhs) {
 ; GFX6-LABEL: s_ssubsat_v2i64:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_sub_u32 s8, s0, s4

 ; GFX9-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc
 ; GFX9-NEXT:    v_cndmask_b32_e32 v1, v5, v3, vcc
 ; GFX9-NEXT:    v_readfirstlane_b32 s0, v4
 ; GFX9-NEXT:    v_readfirstlane_b32 s1, v2
 ; GFX9-NEXT:    v_readfirstlane_b32 s2, v0
 ; GFX9-NEXT:    v_readfirstlane_b32 s3, v1
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
-; GFX10-LABEL: s_ssubsat_v2i64:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    s_sub_u32 s8, s0, s4
-; GFX10-NEXT:    s_subb_u32 s9, s1, s5
-; GFX10-NEXT:    v_cmp_gt_i64_e64 s4, s[4:5], 0
-; GFX10-NEXT:    v_cmp_lt_i64_e64 s1, s[8:9], s[0:1]
-; GFX10-NEXT:    s_mov_b32 s10, 0
-; GFX10-NEXT:    s_ashr_i32 s0, s9, 31
-; GFX10-NEXT:    v_mov_b32_e32 v0, s8
-; GFX10-NEXT:    v_mov_b32_e32 v1, s9
-; GFX10-NEXT:    s_xor_b32 s8, s4, s1
-; GFX10-NEXT:    s_cmp_lg_u32 s10, 0
-; GFX10-NEXT:    v_cndmask_b32_e64 v0, v0, s0, s8
-; GFX10-NEXT:    s_addc_u32 s1, s0, 0x80000000
-; GFX10-NEXT:    s_sub_u32 s4, s2, s6
-; GFX10-NEXT:    s_subb_u32 s5, s3, s7
-; GFX10-NEXT:    v_mov_b32_e32 v2, s4
-; GFX10-NEXT:    v_cmp_lt_i64_e64 s2, s[4:5], s[2:3]
-; GFX10-NEXT:    v_cmp_gt_i64_e64 s3, s[6:7], 0
-; GFX10-NEXT:    s_ashr_i32 s0, s5, 31
-; GFX10-NEXT:    v_mov_b32_e32 v3, s5
-; GFX10-NEXT:    v_cndmask_b32_e64 v1, v1, s1, s8
-; GFX10-NEXT:    s_xor_b32 s2, s3, s2
-; GFX10-NEXT:    s_cmp_lg_u32 s10, 0
-; GFX10-NEXT:    v_cndmask_b32_e64 v2, v2, s0, s2
-; GFX10-NEXT:    s_addc_u32 s1, s0, 0x80000000
-; GFX10-NEXT:    v_readfirstlane_b32 s0, v0
-; GFX10-NEXT:    v_cndmask_b32_e64 v3, v3, s1, s2
-; GFX10-NEXT:    v_readfirstlane_b32 s1, v1
-; GFX10-NEXT:    v_readfirstlane_b32 s2, v2
-; GFX10-NEXT:    v_readfirstlane_b32 s3, v3
-; GFX10-NEXT:    ; return to shader part epilog
+; GFX10PLUS-LABEL: s_ssubsat_v2i64:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    s_sub_u32 s8, s0, s4
+; GFX10PLUS-NEXT:    s_subb_u32 s9, s1, s5
+; GFX10PLUS-NEXT:    v_cmp_gt_i64_e64 s4, s[4:5], 0
+; GFX10PLUS-NEXT:    v_cmp_lt_i64_e64 s1, s[8:9], s[0:1]
+; GFX10PLUS-NEXT:    s_mov_b32 s10, 0
+; GFX10PLUS-NEXT:    s_ashr_i32 s0, s9, 31
+; GFX10PLUS-NEXT:    v_mov_b32_e32 v0, s8
+; GFX10PLUS-NEXT:    v_mov_b32_e32 v1, s9
+; GFX10PLUS-NEXT:    s_xor_b32 s8, s4, s1
+; GFX10PLUS-NEXT:    s_cmp_lg_u32 s10, 0
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v0, v0, s0, s8
+; GFX10PLUS-NEXT:    s_addc_u32 s1, s0, 0x80000000
+; GFX10PLUS-NEXT:    s_sub_u32 s4, s2, s6
+; GFX10PLUS-NEXT:    s_subb_u32 s5, s3, s7
+; GFX10PLUS-NEXT:    v_mov_b32_e32 v2, s4
+; GFX10PLUS-NEXT:    v_cmp_lt_i64_e64 s2, s[4:5], s[2:3]
+; GFX10PLUS-NEXT:    v_cmp_gt_i64_e64 s3, s[6:7], 0
+; GFX10PLUS-NEXT:    s_ashr_i32 s0, s5, 31
+; GFX10PLUS-NEXT:    v_mov_b32_e32 v3, s5
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v1, v1, s1, s8
+; GFX10PLUS-NEXT:    s_xor_b32 s2, s3, s2
+; GFX10PLUS-NEXT:    s_cmp_lg_u32 s10, 0
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v2, v2, s0, s2
+; GFX10PLUS-NEXT:    s_addc_u32 s1, s0, 0x80000000
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s0, v0
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v3, v3, s1, s2
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s1, v1
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s2, v2
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s3, v3
+; GFX10PLUS-NEXT:    ; return to shader part epilog
   %result = call <2 x i64> @llvm.ssub.sat.v2i64(<2 x i64> %lhs, <2 x i64> %rhs)
   ret <2 x i64> %result
 }
 
 define amdgpu_ps i128 @s_ssubsat_i128(i128 inreg %lhs, i128 inreg %rhs) {
 ; GFX6-LABEL: s_ssubsat_i128:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_sub_u32 s8, s0, s4

 ; GFX9-NEXT:    v_cndmask_b32_e32 v2, v4, v2, vcc
 ; GFX9-NEXT:    v_cndmask_b32_e32 v3, v5, v3, vcc
 ; GFX9-NEXT:    v_readfirstlane_b32 s0, v0
 ; GFX9-NEXT:    v_readfirstlane_b32 s1, v1
 ; GFX9-NEXT:    v_readfirstlane_b32 s2, v2
 ; GFX9-NEXT:    v_readfirstlane_b32 s3, v3
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
-; GFX10-LABEL: s_ssubsat_i128:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    s_sub_u32 s8, s0, s4
-; GFX10-NEXT:    s_subb_u32 s9, s1, s5
-; GFX10-NEXT:    s_subb_u32 s10, s2, s6
-; GFX10-NEXT:    v_cmp_lt_u64_e64 s0, s[8:9], s[0:1]
-; GFX10-NEXT:    s_subb_u32 s11, s3, s7
-; GFX10-NEXT:    s_cmp_eq_u64 s[10:11], s[2:3]
-; GFX10-NEXT:    s_cselect_b32 s12, 1, 0
-; GFX10-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
-; GFX10-NEXT:    v_cmp_lt_i64_e64 s0, s[10:11], s[2:3]
-; GFX10-NEXT:    v_cmp_gt_u64_e64 s2, s[4:5], 0
-; GFX10-NEXT:    v_cndmask_b32_e64 v1, 0, 1, s0
-; GFX10-NEXT:    s_and_b32 s0, 1, s12
-; GFX10-NEXT:    s_cmp_eq_u64 s[6:7], 0
-; GFX10-NEXT:    v_cndmask_b32_e64 v2, 0, 1, s2
-; GFX10-NEXT:    v_cmp_gt_i64_e64 s2, s[6:7], 0
-; GFX10-NEXT:    v_cmp_ne_u32_e64 vcc_lo, 0, s0
-; GFX10-NEXT:    s_cselect_b32 s1, 1, 0
-; GFX10-NEXT:    s_ashr_i32 s0, s11, 31
-; GFX10-NEXT:    s_and_b32 s1, 1, s1
-; GFX10-NEXT:    v_cndmask_b32_e64 v3, 0, 1, s2
-; GFX10-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc_lo
-; GFX10-NEXT:    v_cmp_ne_u32_e64 vcc_lo, 0, s1
-; GFX10-NEXT:    s_mov_b32 s1, 0
-; GFX10-NEXT:    s_cmp_lg_u32 s1, 0
-; GFX10-NEXT:    v_cndmask_b32_e32 v1, v3, v2, vcc_lo
-; GFX10-NEXT:    v_mov_b32_e32 v2, s9
-; GFX10-NEXT:    v_mov_b32_e32 v3, s11
-; GFX10-NEXT:    s_addc_u32 s1, s0, 0
-; GFX10-NEXT:    s_addc_u32 s2, s0, 0
-; GFX10-NEXT:    v_xor_b32_e32 v0, v1, v0
-; GFX10-NEXT:    v_mov_b32_e32 v1, s8
-; GFX10-NEXT:    s_addc_u32 s3, s0, 0x80000000
-; GFX10-NEXT:    v_and_b32_e32 v0, 1, v0
-; GFX10-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v0
-; GFX10-NEXT:    v_mov_b32_e32 v0, s10
-; GFX10-NEXT:    v_cndmask_b32_e64 v1, v1, s0, vcc_lo
-; GFX10-NEXT:    v_cndmask_b32_e64 v2, v2, s1, vcc_lo
-; GFX10-NEXT:    v_cndmask_b32_e64 v0, v0, s2, vcc_lo
-; GFX10-NEXT:    v_cndmask_b32_e64 v3, v3, s3, vcc_lo
-; GFX10-NEXT:    v_readfirstlane_b32 s0, v1
-; GFX10-NEXT:    v_readfirstlane_b32 s1, v2
-; GFX10-NEXT:    v_readfirstlane_b32 s2, v0
-; GFX10-NEXT:    v_readfirstlane_b32 s3, v3
-; GFX10-NEXT:    ; return to shader part epilog
+; GFX10PLUS-LABEL: s_ssubsat_i128:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    s_sub_u32 s8, s0, s4
+; GFX10PLUS-NEXT:    s_subb_u32 s9, s1, s5
+; GFX10PLUS-NEXT:    s_subb_u32 s10, s2, s6
+; GFX10PLUS-NEXT:    v_cmp_lt_u64_e64 s0, s[8:9], s[0:1]
+; GFX10PLUS-NEXT:    s_subb_u32 s11, s3, s7
+; GFX10PLUS-NEXT:    s_cmp_eq_u64 s[10:11], s[2:3]
+; GFX10PLUS-NEXT:    s_cselect_b32 s12, 1, 0
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; GFX10PLUS-NEXT:    v_cmp_lt_i64_e64 s0, s[10:11], s[2:3]
+; GFX10PLUS-NEXT:    v_cmp_gt_u64_e64 s2, s[4:5], 0
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v1, 0, 1, s0
+; GFX10PLUS-NEXT:    s_and_b32 s0, 1, s12
+; GFX10PLUS-NEXT:    s_cmp_eq_u64 s[6:7], 0
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v2, 0, 1, s2
+; GFX10PLUS-NEXT:    v_cmp_gt_i64_e64 s2, s[6:7], 0
+; GFX10PLUS-NEXT:    v_cmp_ne_u32_e64 vcc_lo, 0, s0
+; GFX10PLUS-NEXT:    s_cselect_b32 s1, 1, 0
+; GFX10PLUS-NEXT:    s_ashr_i32 s0, s11, 31
+; GFX10PLUS-NEXT:    s_and_b32 s1, 1, s1
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v3, 0, 1, s2
+; GFX10PLUS-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc_lo
+; GFX10PLUS-NEXT:    v_cmp_ne_u32_e64 vcc_lo, 0, s1
+; GFX10PLUS-NEXT:    s_mov_b32 s1, 0
+; GFX10PLUS-NEXT:    s_cmp_lg_u32 s1, 0
+; GFX10PLUS-NEXT:    v_cndmask_b32_e32 v1, v3, v2, vcc_lo
+; GFX10PLUS-NEXT:    v_mov_b32_e32 v2, s9
+; GFX10PLUS-NEXT:    v_mov_b32_e32 v3, s11
+; GFX10PLUS-NEXT:    s_addc_u32 s1, s0, 0
+; GFX10PLUS-NEXT:    s_addc_u32 s2, s0, 0
+; GFX10PLUS-NEXT:    v_xor_b32_e32 v0, v1, v0
+; GFX10PLUS-NEXT:    v_mov_b32_e32 v1, s8
+; GFX10PLUS-NEXT:    s_addc_u32 s3, s0, 0x80000000
+; GFX10PLUS-NEXT:    v_and_b32_e32 v0, 1, v0
+; GFX10PLUS-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v0
+; GFX10PLUS-NEXT:    v_mov_b32_e32 v0, s10
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v1, v1, s0, vcc_lo
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v2, v2, s1, vcc_lo
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v0, v0, s2, vcc_lo
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v3, v3, s3, vcc_lo
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s0, v1
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s1, v2
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s2, v0
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s3, v3
+; GFX10PLUS-NEXT:    ; return to shader part epilog
   %result = call i128 @llvm.ssub.sat.i128(i128 %lhs, i128 %rhs)
   ret i128 %result
 }
 
 define amdgpu_ps <4 x float> @ssubsat_i128_sv(i128 inreg %lhs, i128 %rhs) {
 ; GFX6-LABEL: ssubsat_i128_sv:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    v_mov_b32_e32 v5, s1

 ; GFX9-NEXT:    v_and_b32_e32 v0, 1, v0
 ; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
 ; GFX9-NEXT:    v_cndmask_b32_e32 v0, v4, v1, vcc
 ; GFX9-NEXT:    v_cndmask_b32_e32 v1, v5, v2, vcc
 ; GFX9-NEXT:    v_cndmask_b32_e32 v2, v6, v8, vcc
 ; GFX9-NEXT:    v_cndmask_b32_e32 v3, v7, v3, vcc
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
-; GFX10-LABEL: ssubsat_i128_sv:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_sub_co_u32 v4, vcc_lo, s0, v0
-; GFX10-NEXT:    v_sub_co_ci_u32_e32 v5, vcc_lo, s1, v1, vcc_lo
-; GFX10-NEXT:    v_sub_co_ci_u32_e32 v6, vcc_lo, s2, v2, vcc_lo
-; GFX10-NEXT:    v_sub_co_ci_u32_e32 v7, vcc_lo, s3, v3, vcc_lo
-; GFX10-NEXT:    v_cmp_gt_u64_e32 vcc_lo, s[0:1], v[4:5]
-; GFX10-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc_lo
-; GFX10-NEXT:    v_cmp_gt_i64_e32 vcc_lo, s[2:3], v[6:7]
-; GFX10-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc_lo
-; GFX10-NEXT:    v_cmp_lt_u64_e32 vcc_lo, 0, v[0:1]
-; GFX10-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX10-NEXT:    v_cmp_lt_i64_e32 vcc_lo, 0, v[2:3]
-; GFX10-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc_lo
-; GFX10-NEXT:    v_cmp_eq_u64_e32 vcc_lo, s[2:3], v[6:7]
-; GFX10-NEXT:    v_cndmask_b32_e32 v8, v9, v8, vcc_lo
-; GFX10-NEXT:    v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
-; GFX10-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc_lo
-; GFX10-NEXT:    v_ashrrev_i32_e32 v1, 31, v7
-; GFX10-NEXT:    s_mov_b32 vcc_lo, 0
-; GFX10-NEXT:    v_xor_b32_e32 v0, v0, v8
-; GFX10-NEXT:    v_add_co_ci_u32_e32 v2, vcc_lo, 0, v1, vcc_lo
-; GFX10-NEXT:    v_add_co_ci_u32_e32 v3, vcc_lo, 0, v1, vcc_lo
-; GFX10-NEXT:    v_and_b32_e32 v0, 1, v0
-; GFX10-NEXT:    v_add_co_ci_u32_e32 v8, vcc_lo, 0x80000000, v1, vcc_lo
-; GFX10-NEXT:    v_cmp_ne_u32_e64 s0, 0, v0
-; GFX10-NEXT:    v_cndmask_b32_e64 v0, v4, v1, s0
-; GFX10-NEXT:    v_cndmask_b32_e64 v1, v5, v2, s0
-; GFX10-NEXT:    v_cndmask_b32_e64 v2, v6, v3, s0
-; GFX10-NEXT:    v_cndmask_b32_e64 v3, v7, v8, s0
-; GFX10-NEXT:    ; return to shader part epilog
+; GFX10PLUS-LABEL: ssubsat_i128_sv:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    v_sub_co_u32 v4, vcc_lo, s0, v0
+; GFX10PLUS-NEXT:    v_sub_co_ci_u32_e32 v5, vcc_lo, s1, v1, vcc_lo
+; GFX10PLUS-NEXT:    v_sub_co_ci_u32_e32 v6, vcc_lo, s2, v2, vcc_lo
+; GFX10PLUS-NEXT:    v_sub_co_ci_u32_e32 v7, vcc_lo, s3, v3, vcc_lo
+; GFX10PLUS-NEXT:    v_cmp_gt_u64_e32 vcc_lo, s[0:1], v[4:5]
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc_lo
+; GFX10PLUS-NEXT:    v_cmp_gt_i64_e32 vcc_lo, s[2:3], v[6:7]
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc_lo
+; GFX10PLUS-NEXT:    v_cmp_lt_u64_e32 vcc_lo, 0, v[0:1]
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX10PLUS-NEXT:    v_cmp_lt_i64_e32 vcc_lo, 0, v[2:3]
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; GFX10PLUS-NEXT:    v_cmp_eq_u64_e32 vcc_lo, s[2:3], v[6:7]
+; GFX10PLUS-NEXT:    v_cndmask_b32_e32 v8, v9, v8, vcc_lo
+; GFX10PLUS-NEXT:    v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
+; GFX10PLUS-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc_lo
+; GFX10PLUS-NEXT:    v_ashrrev_i32_e32 v1, 31, v7
+; GFX10PLUS-NEXT:    s_mov_b32 vcc_lo, 0
+; GFX10PLUS-NEXT:    v_xor_b32_e32 v0, v0, v8
+; GFX10PLUS-NEXT:    v_add_co_ci_u32_e32 v2, vcc_lo, 0, v1, vcc_lo
+; GFX10PLUS-NEXT:    v_add_co_ci_u32_e32 v3, vcc_lo, 0, v1, vcc_lo
+; GFX10PLUS-NEXT:    v_and_b32_e32 v0, 1, v0
+; GFX10PLUS-NEXT:    v_add_co_ci_u32_e32 v8, vcc_lo, 0x80000000, v1, vcc_lo
+; GFX10PLUS-NEXT:    v_cmp_ne_u32_e64 s0, 0, v0
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v0, v4, v1, s0
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v1, v5, v2, s0
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v2, v6, v3, s0
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v3, v7, v8, s0
+; GFX10PLUS-NEXT:    ; return to shader part epilog
   %result = call i128 @llvm.ssub.sat.i128(i128 %lhs, i128 %rhs)
   %cast = bitcast i128 %result to <4 x float>
   ret <4 x float> %cast
 }
 
 define amdgpu_ps <4 x float> @ssubsat_i128_vs(i128 %lhs, i128 inreg %rhs) {
 ; GFX6-LABEL: ssubsat_i128_vs:
 ; GFX6:       ; %bb.0:

 ; GFX9-NEXT:    v_and_b32_e32 v0, 1, v0
 ; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
 ; GFX9-NEXT:    v_cndmask_b32_e32 v0, v4, v1, vcc
 ; GFX9-NEXT:    v_cndmask_b32_e32 v1, v5, v2, vcc
 ; GFX9-NEXT:    v_cndmask_b32_e32 v2, v6, v8, vcc
 ; GFX9-NEXT:    v_cndmask_b32_e32 v3, v7, v3, vcc
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
-; GFX10-LABEL: ssubsat_i128_vs:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_sub_co_u32 v4, vcc_lo, v0, s0
-; GFX10-NEXT:    v_subrev_co_ci_u32_e32 v5, vcc_lo, s1, v1, vcc_lo
-; GFX10-NEXT:    v_subrev_co_ci_u32_e32 v6, vcc_lo, s2, v2, vcc_lo
-; GFX10-NEXT:    v_subrev_co_ci_u32_e32 v7, vcc_lo, s3, v3, vcc_lo
-; GFX10-NEXT:    v_cmp_lt_u64_e32 vcc_lo, v[4:5], v[0:1]
-; GFX10-NEXT:    v_cmp_gt_u64_e64 s0, s[0:1], 0
-; GFX10-NEXT:    s_cmp_eq_u64 s[2:3], 0
-; GFX10-NEXT:    s_cselect_b32 s4, 1, 0
-; GFX10-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX10-NEXT:    v_cmp_lt_i64_e32 vcc_lo, v[6:7], v[2:3]
-; GFX10-NEXT:    v_cndmask_b32_e64 v8, 0, 1, s0
-; GFX10-NEXT:    v_cmp_gt_i64_e64 s0, s[2:3], 0
-; GFX10-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc_lo
-; GFX10-NEXT:    v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[2:3]
-; GFX10-NEXT:    v_cndmask_b32_e64 v9, 0, 1, s0
-; GFX10-NEXT:    s_and_b32 s0, 1, s4
-; GFX10-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc_lo
-; GFX10-NEXT:    v_cmp_ne_u32_e64 vcc_lo, 0, s0
-; GFX10-NEXT:    v_cndmask_b32_e32 v1, v9, v8, vcc_lo
-; GFX10-NEXT:    s_mov_b32 vcc_lo, 0
-; GFX10-NEXT:    v_xor_b32_e32 v0, v1, v0
-; GFX10-NEXT:    v_ashrrev_i32_e32 v1, 31, v7
-; GFX10-NEXT:    v_and_b32_e32 v0, 1, v0
-; GFX10-NEXT:    v_add_co_ci_u32_e32 v2, vcc_lo, 0, v1, vcc_lo
-; GFX10-NEXT:    v_add_co_ci_u32_e32 v3, vcc_lo, 0, v1, vcc_lo
-; GFX10-NEXT:    v_cmp_ne_u32_e64 s0, 0, v0
-; GFX10-NEXT:    v_add_co_ci_u32_e32 v8, vcc_lo, 0x80000000, v1, vcc_lo
-; GFX10-NEXT:    v_cndmask_b32_e64 v0, v4, v1, s0
-; GFX10-NEXT:    v_cndmask_b32_e64 v1, v5, v2, s0
-; GFX10-NEXT:    v_cndmask_b32_e64 v2, v6, v3, s0
-; GFX10-NEXT:    v_cndmask_b32_e64 v3, v7, v8, s0
-; GFX10-NEXT:    ; return to shader part epilog
+; GFX10PLUS-LABEL: ssubsat_i128_vs:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    v_sub_co_u32 v4, vcc_lo, v0, s0
+; GFX10PLUS-NEXT:    v_subrev_co_ci_u32_e32 v5, vcc_lo, s1, v1, vcc_lo
+; GFX10PLUS-NEXT:    v_subrev_co_ci_u32_e32 v6, vcc_lo, s2, v2, vcc_lo
+; GFX10PLUS-NEXT:    v_subrev_co_ci_u32_e32 v7, vcc_lo, s3, v3, vcc_lo
+; GFX10PLUS-NEXT:    v_cmp_lt_u64_e32 vcc_lo, v[4:5], v[0:1]
+; GFX10PLUS-NEXT:    v_cmp_gt_u64_e64 s0, s[0:1], 0
+; GFX10PLUS-NEXT:    s_cmp_eq_u64 s[2:3], 0
+; GFX10PLUS-NEXT:    s_cselect_b32 s4, 1, 0
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX10PLUS-NEXT:    v_cmp_lt_i64_e32 vcc_lo, v[6:7], v[2:3]
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v8, 0, 1, s0
+; GFX10PLUS-NEXT:    v_cmp_gt_i64_e64 s0, s[2:3], 0
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; GFX10PLUS-NEXT:    v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[2:3]
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v9, 0, 1, s0
+; GFX10PLUS-NEXT:    s_and_b32 s0, 1, s4
+; GFX10PLUS-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc_lo
+; GFX10PLUS-NEXT:    v_cmp_ne_u32_e64 vcc_lo, 0, s0
+; GFX10PLUS-NEXT:    v_cndmask_b32_e32 v1, v9, v8, vcc_lo
+; GFX10PLUS-NEXT:    s_mov_b32 vcc_lo, 0
+; GFX10PLUS-NEXT:    v_xor_b32_e32 v0, v1, v0
+; GFX10PLUS-NEXT:    v_ashrrev_i32_e32 v1, 31, v7
+; GFX10PLUS-NEXT:    v_and_b32_e32 v0, 1, v0
+; GFX10PLUS-NEXT:    v_add_co_ci_u32_e32 v2, vcc_lo, 0, v1, vcc_lo
+; GFX10PLUS-NEXT:    v_add_co_ci_u32_e32 v3, vcc_lo, 0, v1, vcc_lo
+; GFX10PLUS-NEXT:    v_cmp_ne_u32_e64 s0, 0, v0
+; GFX10PLUS-NEXT:    v_add_co_ci_u32_e32 v8, vcc_lo, 0x80000000, v1, vcc_lo
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v0, v4, v1, s0
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v1, v5, v2, s0
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v2, v6, v3, s0
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v3, v7, v8, s0
+; GFX10PLUS-NEXT:    ; return to shader part epilog
   %result = call i128 @llvm.ssub.sat.i128(i128 %lhs, i128 %rhs)
   %cast = bitcast i128 %result to <4 x float>
   ret <4 x float> %cast
 }
 
 define <2 x i128> @v_ssubsat_v2i128(<2 x i128> %lhs, <2 x i128> %rhs) {
 ; GFX6-LABEL: v_ssubsat_v2i128:
 ; GFX6:       ; %bb.0:

 ; GFX10-NEXT:    v_cndmask_b32_e64 v2, v18, v4, s5
 ; GFX10-NEXT:    v_cmp_ne_u32_e64 s4, 0, v3
 ; GFX10-NEXT:    v_cndmask_b32_e64 v3, v19, v5, s5
 ; GFX10-NEXT:    v_cndmask_b32_e64 v4, v8, v6, s4
 ; GFX10-NEXT:    v_cndmask_b32_e64 v5, v9, v7, s4
 ; GFX10-NEXT:    v_cndmask_b32_e64 v6, v10, v12, s4
 ; GFX10-NEXT:    v_cndmask_b32_e64 v7, v11, v13, s4
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_ssubsat_v2i128:
+; GFX11:       ; %bb.0:
+; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT:    v_sub_co_u32 v16, vcc_lo, v0, v8
+; GFX11-NEXT:    v_sub_co_ci_u32_e32 v17, vcc_lo, v1, v9, vcc_lo
+; GFX11-NEXT:    v_sub_co_ci_u32_e32 v18, vcc_lo, v2, v10, vcc_lo
+; GFX11-NEXT:    v_sub_co_ci_u32_e32 v19, vcc_lo, v3, v11, vcc_lo
+; GFX11-NEXT:    v_cmp_lt_u64_e32 vcc_lo, v[16:17], v[0:1]
+; GFX11-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX11-NEXT:    v_cmp_lt_i64_e32 vcc_lo, v[18:19], v[2:3]
+; GFX11-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; GFX11-NEXT:    v_cmp_lt_u64_e32 vcc_lo, 0, v[8:9]
+; GFX11-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc_lo
+; GFX11-NEXT:    v_cmp_lt_i64_e32 vcc_lo, 0, v[10:11]
+; GFX11-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc_lo
+; GFX11-NEXT:    v_cmp_eq_u64_e32 vcc_lo, v[18:19], v[2:3]
+; GFX11-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc_lo
+; GFX11-NEXT:    v_cmp_eq_u64_e32 vcc_lo, 0, v[10:11]
+; GFX11-NEXT:    v_cndmask_b32_e32 v1, v9, v8, vcc_lo
+; GFX11-NEXT:    v_sub_co_u32 v8, vcc_lo, v4, v12
+; GFX11-NEXT:    v_sub_co_ci_u32_e32 v9, vcc_lo, v5, v13, vcc_lo
+; GFX11-NEXT:    v_sub_co_ci_u32_e32 v10, vcc_lo, v6, v14, vcc_lo
+; GFX11-NEXT:    v_sub_co_ci_u32_e32 v11, vcc_lo, v7, v15, vcc_lo
+; GFX11-NEXT:    v_cmp_lt_u64_e64 s1, v[8:9], v[4:5]
+; GFX11-NEXT:    v_xor_b32_e32 v0, v1, v0
+; GFX11-NEXT:    v_ashrrev_i32_e32 v1, 31, v19
+; GFX11-NEXT:    v_cmp_eq_u64_e64 s2, v[10:11], v[6:7]
+; GFX11-NEXT:    s_mov_b32 vcc_lo, 0
+; GFX11-NEXT:    v_cndmask_b32_e64 v3, 0, 1, s1
+; GFX11-NEXT:    v_cmp_lt_i64_e64 s1, v[10:11], v[6:7]
+; GFX11-NEXT:    v_and_b32_e32 v0, 1, v0
+; GFX11-NEXT:    v_ashrrev_i32_e32 v6, 31, v11
+; GFX11-NEXT:    v_add_co_ci_u32_e64 v2, s0, 0, v1, vcc_lo
+; GFX11-NEXT:    v_cndmask_b32_e64 v4, 0, 1, s1
+; GFX11-NEXT:    v_cmp_lt_u64_e64 s1, 0, v[12:13]
+; GFX11-NEXT:    v_add_co_ci_u32_e32 v7, vcc_lo, 0, v6, vcc_lo
+; GFX11-NEXT:    v_cndmask_b32_e64 v5, 0, 1, s1
+; GFX11-NEXT:    v_cmp_lt_i64_e64 s1, 0, v[14:15]
+; GFX11-NEXT:    v_cndmask_b32_e64 v12, 0, 1, s1
+; GFX11-NEXT:    v_cmp_ne_u32_e64 s1, 0, v0
+; GFX11-NEXT:    v_cndmask_b32_e64 v0, v4, v3, s2
+; GFX11-NEXT:    v_cmp_eq_u64_e64 s2, 0, v[14:15]
+; GFX11-NEXT:    v_add_co_ci_u32_e64 v4, s0, 0, v1, s0
+; GFX11-NEXT:    v_cndmask_b32_e64 v3, v12, v5, s2
+; GFX11-NEXT:    v_add_co_ci_u32_e32 v12, vcc_lo, 0, v6, vcc_lo
+; GFX11-NEXT:    v_add_co_ci_u32_e64 v5, s0, 0x80000000, v1, s0
+; GFX11-NEXT:    v_xor_b32_e32 v3, v3, v0
+; GFX11-NEXT:    v_add_co_ci_u32_e32 v13, vcc_lo, 0x80000000, v6, vcc_lo
+; GFX11-NEXT:    v_cndmask_b32_e64 v0, v16, v1, s1
+; GFX11-NEXT:    v_cndmask_b32_e64 v1, v17, v2, s1
+; GFX11-NEXT:    v_and_b32_e32 v3, 1, v3
+; GFX11-NEXT:    v_cndmask_b32_e64 v2, v18, v4, s1
+; GFX11-NEXT:    v_cmp_ne_u32_e64 s0, 0, v3
+; GFX11-NEXT:    v_cndmask_b32_e64 v3, v19, v5, s1
+; GFX11-NEXT:    v_cndmask_b32_e64 v4, v8, v6, s0
+; GFX11-NEXT:    v_cndmask_b32_e64 v5, v9, v7, s0
+; GFX11-NEXT:    v_cndmask_b32_e64 v6, v10, v12, s0
+; GFX11-NEXT:    v_cndmask_b32_e64 v7, v11, v13, s0
+; GFX11-NEXT:    s_setpc_b64 s[30:31]
   %result = call <2 x i128> @llvm.ssub.sat.v2i128(<2 x i128> %lhs, <2 x i128> %rhs)
   ret <2 x i128> %result
 }
 
 define amdgpu_ps <2 x i128> @s_ssubsat_v2i128(<2 x i128> inreg %lhs, <2 x i128> inreg %rhs) {
 ; GFX6-LABEL: s_ssubsat_v2i128:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_sub_u32 s16, s0, s8

 ; GFX9-NEXT:    v_readfirstlane_b32 s2, v6
 ; GFX9-NEXT:    v_readfirstlane_b32 s3, v7
 ; GFX9-NEXT:    v_readfirstlane_b32 s4, v0
 ; GFX9-NEXT:    v_readfirstlane_b32 s5, v1
 ; GFX9-NEXT:    v_readfirstlane_b32 s6, v2
 ; GFX9-NEXT:    v_readfirstlane_b32 s7, v3
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
-; GFX10-LABEL: s_ssubsat_v2i128:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    s_sub_u32 s16, s0, s8
-; GFX10-NEXT:    s_subb_u32 s17, s1, s9
-; GFX10-NEXT:    s_subb_u32 s18, s2, s10
-; GFX10-NEXT:    v_cmp_lt_u64_e64 s0, s[16:17], s[0:1]
-; GFX10-NEXT:    s_subb_u32 s19, s3, s11
-; GFX10-NEXT:    s_cmp_eq_u64 s[18:19], s[2:3]
-; GFX10-NEXT:    s_cselect_b32 s20, 1, 0
-; GFX10-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
-; GFX10-NEXT:    v_cmp_lt_i64_e64 s0, s[18:19], s[2:3]
-; GFX10-NEXT:    v_cmp_gt_u64_e64 s2, s[8:9], 0
-; GFX10-NEXT:    v_cndmask_b32_e64 v1, 0, 1, s0
-; GFX10-NEXT:    s_and_b32 s0, 1, s20
-; GFX10-NEXT:    s_cmp_eq_u64 s[10:11], 0
-; GFX10-NEXT:    v_cndmask_b32_e64 v2, 0, 1, s2
-; GFX10-NEXT:    s_cselect_b32 s1, 1, 0
-; GFX10-NEXT:    v_cmp_gt_i64_e64 s2, s[10:11], 0
-; GFX10-NEXT:    v_cmp_ne_u32_e64 vcc_lo, 0, s0
-; GFX10-NEXT:    s_mov_b32 s20, 0
-; GFX10-NEXT:    s_and_b32 s1, 1, s1
-; GFX10-NEXT:    s_ashr_i32 s0, s19, 31
-; GFX10-NEXT:    s_cmp_lg_u32 s20, 0
-; GFX10-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc_lo
-; GFX10-NEXT:    v_cmp_ne_u32_e64 vcc_lo, 0, s1
-; GFX10-NEXT:    s_addc_u32 s1, s0, 0
-; GFX10-NEXT:    v_cndmask_b32_e64 v3, 0, 1, s2
-; GFX10-NEXT:    s_addc_u32 s2, s0, 0
-; GFX10-NEXT:    s_addc_u32 s3, s0, 0x80000000
-; GFX10-NEXT:    s_sub_u32 s8, s4, s12
-; GFX10-NEXT:    s_subb_u32 s9, s5, s13
-; GFX10-NEXT:    s_subb_u32 s10, s6, s14
-; GFX10-NEXT:    v_cmp_lt_u64_e64 s4, s[8:9], s[4:5]
-; GFX10-NEXT:    s_subb_u32 s11, s7, s15
-; GFX10-NEXT:    v_cndmask_b32_e32 v1, v3, v2, vcc_lo
-; GFX10-NEXT:    s_cmp_eq_u64 s[10:11], s[6:7]
-; GFX10-NEXT:    v_mov_b32_e32 v2, s17
-; GFX10-NEXT:    v_mov_b32_e32 v7, s11
-; GFX10-NEXT:    v_cndmask_b32_e64 v3, 0, 1, s4
-; GFX10-NEXT:    v_cmp_lt_i64_e64 s4, s[10:11], s[6:7]
-; GFX10-NEXT:    v_cmp_gt_u64_e64 s6, s[12:13], 0
-; GFX10-NEXT:    v_xor_b32_e32 v0, v1, v0
-; GFX10-NEXT:    v_mov_b32_e32 v1, s16
-; GFX10-NEXT:    s_cselect_b32 s16, 1, 0
-; GFX10-NEXT:    v_cndmask_b32_e64 v4, 0, 1, s4
-; GFX10-NEXT:    s_and_b32 s4, 1, s16
-; GFX10-NEXT:    s_cmp_eq_u64 s[14:15], 0
-; GFX10-NEXT:    v_cndmask_b32_e64 v5, 0, 1, s6
-; GFX10-NEXT:    v_cmp_gt_i64_e64 s6, s[14:15], 0
-; GFX10-NEXT:    v_cmp_ne_u32_e64 vcc_lo, 0, s4
-; GFX10-NEXT:    s_cselect_b32 s5, 1, 0
-; GFX10-NEXT:    v_and_b32_e32 v0, 1, v0
-; GFX10-NEXT:    s_and_b32 s5, 1, s5
-; GFX10-NEXT:    v_cndmask_b32_e64 v6, 0, 1, s6
-; GFX10-NEXT:    v_cndmask_b32_e32 v3, v4, v3, vcc_lo
-; GFX10-NEXT:    v_cmp_ne_u32_e64 vcc_lo, 0, s5
-; GFX10-NEXT:    v_cndmask_b32_e32 v4, v6, v5, vcc_lo
-; GFX10-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v0
-; GFX10-NEXT:    v_mov_b32_e32 v0, s18
-; GFX10-NEXT:    v_mov_b32_e32 v5, s19
-; GFX10-NEXT:    v_mov_b32_e32 v6, s9
-; GFX10-NEXT:    v_xor_b32_e32 v3, v4, v3
-; GFX10-NEXT:    v_cndmask_b32_e64 v1, v1, s0, vcc_lo
-; GFX10-NEXT:    s_ashr_i32 s0, s11, 31
-; GFX10-NEXT:    s_cmp_lg_u32 s20, 0
-; GFX10-NEXT:    v_cndmask_b32_e64 v2, v2, s1, vcc_lo
-; GFX10-NEXT:    v_and_b32_e32 v3, 1, v3
-; GFX10-NEXT:    v_cndmask_b32_e64 v0, v0, s2, vcc_lo
-; GFX10-NEXT:    v_cndmask_b32_e64 v4, v5, s3, vcc_lo
-; GFX10-NEXT:    v_mov_b32_e32 v5, s8
-; GFX10-NEXT:    s_addc_u32 s1, s0, 0
-; GFX10-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v3
-; GFX10-NEXT:    v_mov_b32_e32 v3, s10
-; GFX10-NEXT:    s_addc_u32 s2, s0, 0
-; GFX10-NEXT:    s_addc_u32 s3, s0, 0x80000000
-; GFX10-NEXT:    v_cndmask_b32_e64 v5, v5, s0, vcc_lo
-; GFX10-NEXT:    v_cndmask_b32_e64 v6, v6, s1, vcc_lo
-; GFX10-NEXT:    v_cndmask_b32_e64 v3, v3, s2, vcc_lo
-; GFX10-NEXT:    v_cndmask_b32_e64 v7, v7, s3, vcc_lo
-; GFX10-NEXT:    v_readfirstlane_b32 s0, v1
-; GFX10-NEXT:    v_readfirstlane_b32 s1, v2
-; GFX10-NEXT:    v_readfirstlane_b32 s2, v0
-; GFX10-NEXT:    v_readfirstlane_b32 s3, v4
-; GFX10-NEXT:    v_readfirstlane_b32 s4, v5
-; GFX10-NEXT:    v_readfirstlane_b32 s5, v6
-; GFX10-NEXT:    v_readfirstlane_b32 s6, v3
-; GFX10-NEXT:    v_readfirstlane_b32 s7, v7
-; GFX10-NEXT:    ; return to shader part epilog
+; GFX10PLUS-LABEL: s_ssubsat_v2i128:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    s_sub_u32 s16, s0, s8
+; GFX10PLUS-NEXT:    s_subb_u32 s17, s1, s9
+; GFX10PLUS-NEXT:    s_subb_u32 s18, s2, s10
+; GFX10PLUS-NEXT:    v_cmp_lt_u64_e64 s0, s[16:17], s[0:1]
+; GFX10PLUS-NEXT:    s_subb_u32 s19, s3, s11
+; GFX10PLUS-NEXT:    s_cmp_eq_u64 s[18:19], s[2:3]
+; GFX10PLUS-NEXT:    s_cselect_b32 s20, 1, 0
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; GFX10PLUS-NEXT:    v_cmp_lt_i64_e64 s0, s[18:19], s[2:3]
+; GFX10PLUS-NEXT:    v_cmp_gt_u64_e64 s2, s[8:9], 0
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v1, 0, 1, s0
+; GFX10PLUS-NEXT:    s_and_b32 s0, 1, s20
+; GFX10PLUS-NEXT:    s_cmp_eq_u64 s[10:11], 0
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v2, 0, 1, s2
+; GFX10PLUS-NEXT:    s_cselect_b32 s1, 1, 0
+; GFX10PLUS-NEXT:    v_cmp_gt_i64_e64 s2, s[10:11], 0
+; GFX10PLUS-NEXT:    v_cmp_ne_u32_e64 vcc_lo, 0, s0
+; GFX10PLUS-NEXT:    s_mov_b32 s20, 0
+; GFX10PLUS-NEXT:    s_and_b32 s1, 1, s1
+; GFX10PLUS-NEXT:    s_ashr_i32 s0, s19, 31
+; GFX10PLUS-NEXT:    s_cmp_lg_u32 s20, 0
+; GFX10PLUS-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc_lo
+; GFX10PLUS-NEXT:    v_cmp_ne_u32_e64 vcc_lo, 0, s1
+; GFX10PLUS-NEXT:    s_addc_u32 s1, s0, 0
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v3, 0, 1, s2
+; GFX10PLUS-NEXT:    s_addc_u32 s2, s0, 0
+; GFX10PLUS-NEXT:    s_addc_u32 s3, s0, 0x80000000
+; GFX10PLUS-NEXT:    s_sub_u32 s8, s4, s12
+; GFX10PLUS-NEXT:    s_subb_u32 s9, s5, s13
+; GFX10PLUS-NEXT:    s_subb_u32 s10, s6, s14
+; GFX10PLUS-NEXT:    v_cmp_lt_u64_e64 s4, s[8:9], s[4:5]
+; GFX10PLUS-NEXT:    s_subb_u32 s11, s7, s15
+; GFX10PLUS-NEXT:    v_cndmask_b32_e32 v1, v3, v2, vcc_lo
+; GFX10PLUS-NEXT:    s_cmp_eq_u64 s[10:11], s[6:7]
+; GFX10PLUS-NEXT:    v_mov_b32_e32 v2, s17
+; GFX10PLUS-NEXT:    v_mov_b32_e32 v7, s11
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v3, 0, 1, s4
+; GFX10PLUS-NEXT:    v_cmp_lt_i64_e64 s4, s[10:11], s[6:7]
+; GFX10PLUS-NEXT:    v_cmp_gt_u64_e64 s6, s[12:13], 0
+; GFX10PLUS-NEXT:    v_xor_b32_e32 v0, v1, v0
+; GFX10PLUS-NEXT:    v_mov_b32_e32 v1, s16
+; GFX10PLUS-NEXT:    s_cselect_b32 s16, 1, 0
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v4, 0, 1, s4
+; GFX10PLUS-NEXT:    s_and_b32 s4, 1, s16
+; GFX10PLUS-NEXT:    s_cmp_eq_u64 s[14:15], 0
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v5, 0, 1, s6
+; GFX10PLUS-NEXT:    v_cmp_gt_i64_e64 s6, s[14:15], 0
+; GFX10PLUS-NEXT:    v_cmp_ne_u32_e64 vcc_lo, 0, s4
+; GFX10PLUS-NEXT:    s_cselect_b32 s5, 1, 0
+; GFX10PLUS-NEXT:    v_and_b32_e32 v0, 1, v0
+; GFX10PLUS-NEXT:    s_and_b32 s5, 1, s5
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v6, 0, 1, s6
+; GFX10PLUS-NEXT:    v_cndmask_b32_e32 v3, v4, v3, vcc_lo
+; GFX10PLUS-NEXT:    v_cmp_ne_u32_e64 vcc_lo, 0, s5
+; GFX10PLUS-NEXT:    v_cndmask_b32_e32 v4, v6, v5, vcc_lo
+; GFX10PLUS-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v0
+; GFX10PLUS-NEXT:    v_mov_b32_e32 v0, s18
+; GFX10PLUS-NEXT:    v_mov_b32_e32 v5, s19
+; GFX10PLUS-NEXT:    v_mov_b32_e32 v6, s9
+; GFX10PLUS-NEXT:    v_xor_b32_e32 v3, v4, v3
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v1, v1, s0, vcc_lo
+; GFX10PLUS-NEXT:    s_ashr_i32 s0, s11, 31
+; GFX10PLUS-NEXT:    s_cmp_lg_u32 s20, 0
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v2, v2, s1, vcc_lo
+; GFX10PLUS-NEXT:    v_and_b32_e32 v3, 1, v3
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v0, v0, s2, vcc_lo
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v4, v5, s3, vcc_lo
+; GFX10PLUS-NEXT:    v_mov_b32_e32 v5, s8
+; GFX10PLUS-NEXT:    s_addc_u32 s1, s0, 0
+; GFX10PLUS-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v3
+; GFX10PLUS-NEXT:    v_mov_b32_e32 v3, s10
+; GFX10PLUS-NEXT:    s_addc_u32 s2, s0, 0
+; GFX10PLUS-NEXT:    s_addc_u32 s3, s0, 0x80000000
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v5, v5, s0, vcc_lo
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v6, v6, s1, vcc_lo
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v3, v3, s2, vcc_lo
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v7, v7, s3, vcc_lo
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s0, v1
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s1, v2
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s2, v0
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s3, v4
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s4, v5
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s5, v6
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s6, v3
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s7, v7
+; GFX10PLUS-NEXT:    ; return to shader part epilog
   %result = call <2 x i128> @llvm.ssub.sat.v2i128(<2 x i128> %lhs, <2 x i128> %rhs)
   ret <2 x i128> %result
 }
 
 declare i7 @llvm.ssub.sat.i7(i7, i7) #0
 declare i8 @llvm.ssub.sat.i8(i8, i8) #0
 declare <2 x i8> @llvm.ssub.sat.v2i8(<2 x i8>, <2 x i8>) #0
 declare <4 x i8> @llvm.ssub.sat.v4i8(<4 x i8>, <4 x i8>) #0

llvm/test/CodeGen/AMDGPU/GlobalISel/uaddsat.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=tahiti -o - %s | FileCheck -check-prefix=GFX6 %s
 ; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=fiji -o - %s | FileCheck -check-prefix=GFX8 %s
 ; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 -o - %s | FileCheck -check-prefix=GFX9 %s
-; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx1010 -o - %s | FileCheck -check-prefix=GFX10 %s
+; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx1010 -o - %s | FileCheck -check-prefixes=GFX10PLUS,GFX10 %s
+; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx1100 -o - %s | FileCheck -check-prefixes=GFX10PLUS,GFX11 %s
 
 define i7 @v_uaddsat_i7(i7 %lhs, i7 %rhs) {
 ; GFX6-LABEL: v_uaddsat_i7:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX6-NEXT:    v_lshlrev_b32_e32 v0, 25, v0
 ; GFX6-NEXT:    v_lshlrev_b32_e32 v1, 25, v1
 ; GFX6-NEXT:    v_xor_b32_e32 v2, -1, v0

 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    v_lshlrev_b16_e32 v0, 9, v0
 ; GFX9-NEXT:    v_lshlrev_b16_e32 v1, 9, v1
 ; GFX9-NEXT:    v_add_u16_e64 v0, v0, v1 clamp
 ; GFX9-NEXT:    v_lshrrev_b16_e32 v0, 9, v0
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX10-LABEL: v_uaddsat_i7:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_lshlrev_b16 v0, 9, v0
-; GFX10-NEXT:    v_lshlrev_b16 v1, 9, v1
-; GFX10-NEXT:    v_add_nc_u16 v0, v0, v1 clamp
-; GFX10-NEXT:    v_lshrrev_b16 v0, 9, v0
-; GFX10-NEXT:    s_setpc_b64 s[30:31]
+; GFX10PLUS-LABEL: v_uaddsat_i7:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX10PLUS-NEXT:    v_lshlrev_b16 v0, 9, v0
+; GFX10PLUS-NEXT:    v_lshlrev_b16 v1, 9, v1
+; GFX10PLUS-NEXT:    v_add_nc_u16 v0, v0, v1 clamp
+; GFX10PLUS-NEXT:    v_lshrrev_b16 v0, 9, v0
+; GFX10PLUS-NEXT:    s_setpc_b64 s[30:31]
   %result = call i7 @llvm.uadd.sat.i7(i7 %lhs, i7 %rhs)
   ret i7 %result
 }
 
 define amdgpu_ps i7 @s_uaddsat_i7(i7 inreg %lhs, i7 inreg %rhs) {
 ; GFX6-LABEL: s_uaddsat_i7:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_lshl_b32 s0, s0, 25

 ; GFX9-NEXT:    s_lshl_b32 s1, s1, s2
 ; GFX9-NEXT:    s_lshl_b32 s0, s0, s2
 ; GFX9-NEXT:    v_mov_b32_e32 v0, s1
 ; GFX9-NEXT:    v_add_u16_e64 v0, s0, v0 clamp
 ; GFX9-NEXT:    v_lshrrev_b16_e32 v0, 9, v0
 ; GFX9-NEXT:    v_readfirstlane_b32 s0, v0
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
-; GFX10-LABEL: s_uaddsat_i7:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    s_bfe_u32 s2, 9, 0x100000
-; GFX10-NEXT:    s_lshl_b32 s0, s0, s2
-; GFX10-NEXT:    s_lshl_b32 s1, s1, s2
-; GFX10-NEXT:    v_add_nc_u16 v0, s0, s1 clamp
-; GFX10-NEXT:    v_lshrrev_b16 v0, 9, v0
-; GFX10-NEXT:    v_readfirstlane_b32 s0, v0
-; GFX10-NEXT:    ; return to shader part epilog
+; GFX10PLUS-LABEL: s_uaddsat_i7:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    s_bfe_u32 s2, 9, 0x100000
+; GFX10PLUS-NEXT:    s_lshl_b32 s0, s0, s2
+; GFX10PLUS-NEXT:    s_lshl_b32 s1, s1, s2
+; GFX10PLUS-NEXT:    v_add_nc_u16 v0, s0, s1 clamp
+; GFX10PLUS-NEXT:    v_lshrrev_b16 v0, 9, v0
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s0, v0
+; GFX10PLUS-NEXT:    ; return to shader part epilog
   %result = call i7 @llvm.uadd.sat.i7(i7 %lhs, i7 %rhs)
   ret i7 %result
 }
 
 define i8 @v_uaddsat_i8(i8 %lhs, i8 %rhs) {
 ; GFX6-LABEL: v_uaddsat_i8:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    v_lshlrev_b16_e32 v0, 8, v0
 ; GFX9-NEXT:    v_lshlrev_b16_e32 v1, 8, v1
 ; GFX9-NEXT:    v_add_u16_e64 v0, v0, v1 clamp
 ; GFX9-NEXT:    v_lshrrev_b16_e32 v0, 8, v0
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX10-LABEL: v_uaddsat_i8:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_lshlrev_b16 v0, 8, v0
-; GFX10-NEXT:    v_lshlrev_b16 v1, 8, v1
-; GFX10-NEXT:    v_add_nc_u16 v0, v0, v1 clamp
-; GFX10-NEXT:    v_lshrrev_b16 v0, 8, v0
-; GFX10-NEXT:    s_setpc_b64 s[30:31]
+; GFX10PLUS-LABEL: v_uaddsat_i8:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX10PLUS-NEXT:    v_lshlrev_b16 v0, 8, v0
+; GFX10PLUS-NEXT:    v_lshlrev_b16 v1, 8, v1
+; GFX10PLUS-NEXT:    v_add_nc_u16 v0, v0, v1 clamp
+; GFX10PLUS-NEXT:    v_lshrrev_b16 v0, 8, v0
+; GFX10PLUS-NEXT:    s_setpc_b64 s[30:31]
   %result = call i8 @llvm.uadd.sat.i8(i8 %lhs, i8 %rhs)
   ret i8 %result
 }
 
 define amdgpu_ps i8 @s_uaddsat_i8(i8 inreg %lhs, i8 inreg %rhs) {
 ; GFX6-LABEL: s_uaddsat_i8:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_lshl_b32 s0, s0, 24

 ; GFX9-NEXT:    s_lshl_b32 s1, s1, s2
 ; GFX9-NEXT:    s_lshl_b32 s0, s0, s2
 ; GFX9-NEXT:    v_mov_b32_e32 v0, s1
 ; GFX9-NEXT:    v_add_u16_e64 v0, s0, v0 clamp
 ; GFX9-NEXT:    v_lshrrev_b16_e32 v0, 8, v0
 ; GFX9-NEXT:    v_readfirstlane_b32 s0, v0
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
-; GFX10-LABEL: s_uaddsat_i8:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    s_bfe_u32 s2, 8, 0x100000
-; GFX10-NEXT:    s_lshl_b32 s0, s0, s2
-; GFX10-NEXT:    s_lshl_b32 s1, s1, s2
-; GFX10-NEXT:    v_add_nc_u16 v0, s0, s1 clamp
-; GFX10-NEXT:    v_lshrrev_b16 v0, 8, v0
-; GFX10-NEXT:    v_readfirstlane_b32 s0, v0
-; GFX10-NEXT:    ; return to shader part epilog
+; GFX10PLUS-LABEL: s_uaddsat_i8:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    s_bfe_u32 s2, 8, 0x100000
+; GFX10PLUS-NEXT:    s_lshl_b32 s0, s0, s2
+; GFX10PLUS-NEXT:    s_lshl_b32 s1, s1, s2
+; GFX10PLUS-NEXT:    v_add_nc_u16 v0, s0, s1 clamp
+; GFX10PLUS-NEXT:    v_lshrrev_b16 v0, 8, v0
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s0, v0
+; GFX10PLUS-NEXT:    ; return to shader part epilog
   %result = call i8 @llvm.uadd.sat.i8(i8 %lhs, i8 %rhs)
   ret i8 %result
 }
 
 define i16 @v_uaddsat_v2i8(i16 %lhs.arg, i16 %rhs.arg) {
 ; GFX6-LABEL: v_uaddsat_v2i8:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

 ; GFX10-NEXT:    v_and_or_b32 v1, 0xffff, v1, v3
 ; GFX10-NEXT:    v_pk_lshlrev_b16 v0, 8, v0 op_sel_hi:[0,1]
 ; GFX10-NEXT:    v_pk_lshlrev_b16 v1, 8, v1 op_sel_hi:[0,1]
 ; GFX10-NEXT:    v_pk_add_u16 v0, v0, v1 clamp
 ; GFX10-NEXT:    v_pk_lshrrev_b16 v0, 8, v0 op_sel_hi:[0,1]
 ; GFX10-NEXT:    v_and_b32_sdwa v1, v0, s4 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
 ; GFX10-NEXT:    v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_uaddsat_v2i8:
+; GFX11:       ; %bb.0:
+; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT:    v_lshrrev_b32_e32 v2, 8, v0
+; GFX11-NEXT:    v_lshrrev_b32_e32 v3, 8, v1
+; GFX11-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-NEXT:    v_and_or_b32 v0, 0xffff, v0, v2
+; GFX11-NEXT:    v_and_or_b32 v1, 0xffff, v1, v3
+; GFX11-NEXT:    v_pk_lshlrev_b16 v0, 8, v0 op_sel_hi:[0,1]
+; GFX11-NEXT:    v_pk_lshlrev_b16 v1, 8, v1 op_sel_hi:[0,1]
+; GFX11-NEXT:    v_pk_add_u16 v0, v0, v1 clamp
+; GFX11-NEXT:    v_pk_lshrrev_b16 v0, 8, v0 op_sel_hi:[0,1]
+; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; GFX11-NEXT:    v_lshlrev_b16 v1, 8, v1
+; GFX11-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-NEXT:    s_setpc_b64 s[30:31]
   %lhs = bitcast i16 %lhs.arg to <2 x i8>
   %rhs = bitcast i16 %rhs.arg to <2 x i8>
   %result = call <2 x i8> @llvm.uadd.sat.v2i8(<2 x i8> %lhs, <2 x i8> %rhs)
   %cast.result = bitcast <2 x i8> %result to i16
   ret i16 %cast.result
 }
 
 define amdgpu_ps i16 @s_uaddsat_v2i8(i16 inreg %lhs.arg, i16 inreg %rhs.arg) {

 ; GFX10-NEXT:    s_pack_ll_b32_b16 s1, s1, s3
 ; GFX10-NEXT:    v_pk_add_u16 v0, s0, s1 clamp
 ; GFX10-NEXT:    s_movk_i32 s0, 0xff
 ; GFX10-NEXT:    v_pk_lshrrev_b16 v0, 8, v0 op_sel_hi:[0,1]
 ; GFX10-NEXT:    v_and_b32_sdwa v1, v0, s0 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
 ; GFX10-NEXT:    v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
 ; GFX10-NEXT:    v_readfirstlane_b32 s0, v0
 ; GFX10-NEXT:    ; return to shader part epilog
+;
+; GFX11-LABEL: s_uaddsat_v2i8:
+; GFX11:       ; %bb.0:
+; GFX11-NEXT:    s_lshr_b32 s2, s0, 8
+; GFX11-NEXT:    s_lshr_b32 s3, s1, 8
+; GFX11-NEXT:    s_pack_ll_b32_b16 s0, s0, s2
+; GFX11-NEXT:    s_pack_ll_b32_b16 s1, s1, s3
+; GFX11-NEXT:    s_lshr_b32 s2, s0, 16
+; GFX11-NEXT:    s_lshr_b32 s3, s1, 16
+; GFX11-NEXT:    s_lshl_b32 s0, s0, 0x80008
+; GFX11-NEXT:    s_lshl_b32 s2, s2, 8
+; GFX11-NEXT:    s_lshl_b32 s1, s1, 0x80008
+; GFX11-NEXT:    s_lshl_b32 s3, s3, 8
+; GFX11-NEXT:    s_pack_ll_b32_b16 s0, s0, s2
+; GFX11-NEXT:    s_pack_ll_b32_b16 s1, s1, s3
+; GFX11-NEXT:    v_pk_add_u16 v0, s0, s1 clamp
+; GFX11-NEXT:    v_pk_lshrrev_b16 v0, 8, v0 op_sel_hi:[0,1]
+; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; GFX11-NEXT:    v_lshlrev_b16 v1, 8, v1
+; GFX11-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-NEXT:    v_readfirstlane_b32 s0, v0
+; GFX11-NEXT:    ; return to shader part epilog
   %lhs = bitcast i16 %lhs.arg to <2 x i8>
   %rhs = bitcast i16 %rhs.arg to <2 x i8>
   %result = call <2 x i8> @llvm.uadd.sat.v2i8(<2 x i8> %lhs, <2 x i8> %rhs)
   %cast.result = bitcast <2 x i8> %result to i16
   ret i16 %cast.result
 }
 
 define i32 @v_uaddsat_v4i8(i32 %lhs.arg, i32 %rhs.arg) {

 ; GFX10-NEXT:    v_pk_lshrrev_b16 v1, 8, v1 op_sel_hi:[0,1]
 ; GFX10-NEXT:    v_lshlrev_b32_sdwa v2, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
 ; GFX10-NEXT:    v_and_b32_e32 v3, 0xff, v1
 ; GFX10-NEXT:    v_lshlrev_b32_sdwa v1, v4, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
 ; GFX10-NEXT:    v_and_or_b32 v0, v0, 0xff, v2
 ; GFX10-NEXT:    v_lshlrev_b32_e32 v2, 16, v3
 ; GFX10-NEXT:    v_or3_b32 v0, v0, v2, v1
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_uaddsat_v4i8:
+; GFX11:       ; %bb.0:
+; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT:    v_lshrrev_b32_e32 v2, 8, v0
+; GFX11-NEXT:    v_lshrrev_b32_e32 v3, 8, v1
+; GFX11-NEXT:    v_lshrrev_b32_e32 v5, 24, v0
+; GFX11-NEXT:    v_lshrrev_b32_e32 v6, 24, v1
+; GFX11-NEXT:    v_lshrrev_b32_e32 v4, 16, v0
+; GFX11-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-NEXT:    v_lshrrev_b32_e32 v7, 16, v1
+; GFX11-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
+; GFX11-NEXT:    v_and_or_b32 v0, 0xffff, v0, v2
+; GFX11-NEXT:    v_and_or_b32 v1, 0xffff, v1, v3
+; GFX11-NEXT:    v_and_or_b32 v2, 0xffff, v4, v5
+; GFX11-NEXT:    v_and_or_b32 v3, 0xffff, v7, v6
+; GFX11-NEXT:    v_pk_lshlrev_b16 v0, 8, v0 op_sel_hi:[0,1]
+; GFX11-NEXT:    v_pk_lshlrev_b16 v1, 8, v1 op_sel_hi:[0,1]
+; GFX11-NEXT:    v_pk_lshlrev_b16 v2, 8, v2 op_sel_hi:[0,1]
+; GFX11-NEXT:    v_pk_lshlrev_b16 v3, 8, v3 op_sel_hi:[0,1]
+; GFX11-NEXT:    v_pk_add_u16 v0, v0, v1 clamp
+; GFX11-NEXT:    v_pk_add_u16 v1, v2, v3 clamp
+; GFX11-NEXT:    v_pk_lshrrev_b16 v0, 8, v0 op_sel_hi:[0,1]
+; GFX11-NEXT:    v_pk_lshrrev_b16 v1, 8, v1 op_sel_hi:[0,1]
+; GFX11-NEXT:    v_bfe_u32 v2, v0, 16, 8
+; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v1
+; GFX11-NEXT:    v_bfe_u32 v1, v1, 16, 8
+; GFX11-NEXT:    v_lshlrev_b32_e32 v2, 8, v2
+; GFX11-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-NEXT:    v_lshlrev_b32_e32 v1, 24, v1
+; GFX11-NEXT:    v_and_or_b32 v0, v0, 0xff, v2
+; GFX11-NEXT:    v_or3_b32 v0, v0, v3, v1
+; GFX11-NEXT:    s_setpc_b64 s[30:31]
   %lhs = bitcast i32 %lhs.arg to <4 x i8>
   %rhs = bitcast i32 %rhs.arg to <4 x i8>
   %result = call <4 x i8> @llvm.uadd.sat.v4i8(<4 x i8> %lhs, <4 x i8> %rhs)
   %cast.result = bitcast <4 x i8> %result to i32
   ret i32 %cast.result
 }
 
 define amdgpu_ps i32 @s_uaddsat_v4i8(i32 inreg %lhs.arg, i32 inreg %rhs.arg) {

 ; GFX10-NEXT:    v_and_b32_e32 v3, 0xff, v1
 ; GFX10-NEXT:    s_mov_b32 s0, 24
 ; GFX10-NEXT:    v_lshlrev_b32_sdwa v1, s0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
 ; GFX10-NEXT:    v_and_or_b32 v0, v0, 0xff, v2
 ; GFX10-NEXT:    v_lshlrev_b32_e32 v2, 16, v3
 ; GFX10-NEXT:    v_or3_b32 v0, v0, v2, v1
 ; GFX10-NEXT:    v_readfirstlane_b32 s0, v0
 ; GFX10-NEXT:    ; return to shader part epilog
+;
+; GFX11-LABEL: s_uaddsat_v4i8:
+; GFX11:       ; %bb.0:
+; GFX11-NEXT:    s_lshr_b32 s2, s0, 8
+; GFX11-NEXT:    s_lshr_b32 s4, s1, 8
+; GFX11-NEXT:    s_pack_ll_b32_b16 s2, s0, s2
+; GFX11-NEXT:    s_pack_ll_b32_b16 s4, s1, s4
+; GFX11-NEXT:    s_lshr_b32 s6, s2, 16
+; GFX11-NEXT:    s_lshl_b32 s2, s2, 0x80008
+; GFX11-NEXT:    s_lshl_b32 s6, s6, 8
+; GFX11-NEXT:    s_lshr_b32 s3, s0, 24
+; GFX11-NEXT:    s_pack_ll_b32_b16 s2, s2, s6
+; GFX11-NEXT:    s_lshr_b32 s6, s4, 16
+; GFX11-NEXT:    s_lshr_b32 s5, s1, 24
+; GFX11-NEXT:    s_lshl_b32 s4, s4, 0x80008
+; GFX11-NEXT:    s_lshl_b32 s6, s6, 8
+; GFX11-NEXT:    s_pack_hl_b32_b16 s0, s0, s3
+; GFX11-NEXT:    s_pack_hl_b32_b16 s1, s1, s5
+; GFX11-NEXT:    s_pack_ll_b32_b16 s4, s4, s6
+; GFX11-NEXT:    s_lshr_b32 s3, s0, 16
+; GFX11-NEXT:    s_lshr_b32 s5, s1, 16
+; GFX11-NEXT:    v_pk_add_u16 v0, s2, s4 clamp
+; GFX11-NEXT:    s_lshl_b32 s0, s0, 0x80008
+; GFX11-NEXT:    s_lshl_b32 s3, s3, 8
+; GFX11-NEXT:    s_lshl_b32 s1, s1, 0x80008
+; GFX11-NEXT:    s_lshl_b32 s2, s5, 8
+; GFX11-NEXT:    s_pack_ll_b32_b16 s0, s0, s3
+; GFX11-NEXT:    s_pack_ll_b32_b16 s1, s1, s2
+; GFX11-NEXT:    v_pk_lshrrev_b16 v0, 8, v0 op_sel_hi:[0,1]
+; GFX11-NEXT:    v_pk_add_u16 v1, s0, s1 clamp
+; GFX11-NEXT:    v_bfe_u32 v2, v0, 16, 8
+; GFX11-NEXT:    v_pk_lshrrev_b16 v1, 8, v1 op_sel_hi:[0,1]
+; GFX11-NEXT:    v_lshlrev_b32_e32 v2, 8, v2
+; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v1
+; GFX11-NEXT:    v_bfe_u32 v1, v1, 16, 8
+; GFX11-NEXT:    v_and_or_b32 v0, v0, 0xff, v2
+; GFX11-NEXT:    v_lshlrev_b32_e32 v2, 16, v3
+; GFX11-NEXT:    v_lshlrev_b32_e32 v1, 24, v1
+; GFX11-NEXT:    v_or3_b32 v0, v0, v2, v1
+; GFX11-NEXT:    v_readfirstlane_b32 s0, v0
+; GFX11-NEXT:    ; return to shader part epilog
   %lhs = bitcast i32 %lhs.arg to <4 x i8>
   %rhs = bitcast i32 %rhs.arg to <4 x i8>
   %result = call <4 x i8> @llvm.uadd.sat.v4i8(<4 x i8> %lhs, <4 x i8> %rhs)
   %cast.result = bitcast <4 x i8> %result to i32
   ret i32 %cast.result
 }
 
 define i24 @v_uaddsat_i24(i24 %lhs, i24 %rhs) {

 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    v_lshlrev_b32_e32 v0, 8, v0
 ; GFX9-NEXT:    v_lshlrev_b32_e32 v1, 8, v1
 ; GFX9-NEXT:    v_add_u32_e64 v0, v0, v1 clamp
 ; GFX9-NEXT:    v_lshrrev_b32_e32 v0, 8, v0
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX10-LABEL: v_uaddsat_i24:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_lshlrev_b32_e32 v0, 8, v0
-; GFX10-NEXT:    v_lshlrev_b32_e32 v1, 8, v1
-; GFX10-NEXT:    v_add_nc_u32_e64 v0, v0, v1 clamp
-; GFX10-NEXT:    v_lshrrev_b32_e32 v0, 8, v0
-; GFX10-NEXT:    s_setpc_b64 s[30:31]
+; GFX10PLUS-LABEL: v_uaddsat_i24:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX10PLUS-NEXT:    v_lshlrev_b32_e32 v0, 8, v0
+; GFX10PLUS-NEXT:    v_lshlrev_b32_e32 v1, 8, v1
+; GFX10PLUS-NEXT:    v_add_nc_u32_e64 v0, v0, v1 clamp
+; GFX10PLUS-NEXT:    v_lshrrev_b32_e32 v0, 8, v0
+; GFX10PLUS-NEXT:    s_setpc_b64 s[30:31]
   %result = call i24 @llvm.uadd.sat.i24(i24 %lhs, i24 %rhs)
   ret i24 %result
 }
 
 define amdgpu_ps i24 @s_uaddsat_i24(i24 inreg %lhs, i24 inreg %rhs) {
 ; GFX6-LABEL: s_uaddsat_i24:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_lshl_b32 s0, s0, 8

 ; GFX9-NEXT:    s_lshl_b32 s1, s1, 8
 ; GFX9-NEXT:    s_lshl_b32 s0, s0, 8
 ; GFX9-NEXT:    v_mov_b32_e32 v0, s1
 ; GFX9-NEXT:    v_add_u32_e64 v0, s0, v0 clamp
 ; GFX9-NEXT:    v_lshrrev_b32_e32 v0, 8, v0
 ; GFX9-NEXT:    v_readfirstlane_b32 s0, v0
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
-; GFX10-LABEL: s_uaddsat_i24:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    s_lshl_b32 s0, s0, 8
-; GFX10-NEXT:    s_lshl_b32 s1, s1, 8
-; GFX10-NEXT:    v_add_nc_u32_e64 v0, s0, s1 clamp
-; GFX10-NEXT:    v_lshrrev_b32_e32 v0, 8, v0
-; GFX10-NEXT:    v_readfirstlane_b32 s0, v0
-; GFX10-NEXT:    ; return to shader part epilog
+; GFX10PLUS-LABEL: s_uaddsat_i24:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    s_lshl_b32 s0, s0, 8
+; GFX10PLUS-NEXT:    s_lshl_b32 s1, s1, 8
+; GFX10PLUS-NEXT:    v_add_nc_u32_e64 v0, s0, s1 clamp
+; GFX10PLUS-NEXT:    v_lshrrev_b32_e32 v0, 8, v0
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s0, v0
+; GFX10PLUS-NEXT:    ; return to shader part epilog
   %result = call i24 @llvm.uadd.sat.i24(i24 %lhs, i24 %rhs)
   ret i24 %result
 }
 
 define i32 @v_uaddsat_i32(i32 %lhs, i32 %rhs) {
 ; GFX6-LABEL: v_uaddsat_i32:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

 ; GFX8-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX9-LABEL: v_uaddsat_i32:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    v_add_u32_e64 v0, v0, v1 clamp
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX10-LABEL: v_uaddsat_i32:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_add_nc_u32_e64 v0, v0, v1 clamp
-; GFX10-NEXT:    s_setpc_b64 s[30:31]
+; GFX10PLUS-LABEL: v_uaddsat_i32:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX10PLUS-NEXT:    v_add_nc_u32_e64 v0, v0, v1 clamp
+; GFX10PLUS-NEXT:    s_setpc_b64 s[30:31]
   %result = call i32 @llvm.uadd.sat.i32(i32 %lhs, i32 %rhs)
   ret i32 %result
 }
 
 define amdgpu_ps i32 @s_uaddsat_i32(i32 inreg %lhs, i32 inreg %rhs) {
 ; GFX6-LABEL: s_uaddsat_i32:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_not_b32 s2, s0

 ;
 ; GFX9-LABEL: s_uaddsat_i32:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    v_mov_b32_e32 v0, s1
 ; GFX9-NEXT:    v_add_u32_e64 v0, s0, v0 clamp
 ; GFX9-NEXT:    v_readfirstlane_b32 s0, v0
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
-; GFX10-LABEL: s_uaddsat_i32:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_add_nc_u32_e64 v0, s0, s1 clamp
-; GFX10-NEXT:    v_readfirstlane_b32 s0, v0
-; GFX10-NEXT:    ; return to shader part epilog
+; GFX10PLUS-LABEL: s_uaddsat_i32:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    v_add_nc_u32_e64 v0, s0, s1 clamp
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s0, v0
+; GFX10PLUS-NEXT:    ; return to shader part epilog
   %result = call i32 @llvm.uadd.sat.i32(i32 %lhs, i32 %rhs)
   ret i32 %result
 }
 
 define amdgpu_ps float @uaddsat_i32_sv(i32 inreg %lhs, i32 %rhs) {
 ; GFX6-LABEL: uaddsat_i32_sv:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_not_b32 s1, s0
 ; GFX6-NEXT:    v_min_u32_e32 v0, s1, v0
 ; GFX6-NEXT:    v_add_i32_e32 v0, vcc, s0, v0
 ; GFX6-NEXT:    ; return to shader part epilog
 ;
 ; GFX8-LABEL: uaddsat_i32_sv:
 ; GFX8:       ; %bb.0:
 ; GFX8-NEXT:    v_add_u32_e64 v0, s[0:1], s0, v0 clamp
 ; GFX8-NEXT:    ; return to shader part epilog
 ;
 ; GFX9-LABEL: uaddsat_i32_sv:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    v_add_u32_e64 v0, s0, v0 clamp
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
-; GFX10-LABEL: uaddsat_i32_sv:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_add_nc_u32_e64 v0, s0, v0 clamp
-; GFX10-NEXT:    ; return to shader part epilog
+; GFX10PLUS-LABEL: uaddsat_i32_sv:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    v_add_nc_u32_e64 v0, s0, v0 clamp
+; GFX10PLUS-NEXT:    ; return to shader part epilog
   %result = call i32 @llvm.uadd.sat.i32(i32 %lhs, i32 %rhs)
   %cast = bitcast i32 %result to float
   ret float %cast
 }
 
 define amdgpu_ps float @uaddsat_i32_vs(i32 %lhs, i32 inreg %rhs) {
 ; GFX6-LABEL: uaddsat_i32_vs:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    v_xor_b32_e32 v1, -1, v0
 ; GFX6-NEXT:    v_min_u32_e32 v1, s0, v1
 ; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
 ; GFX6-NEXT:    ; return to shader part epilog
 ;
 ; GFX8-LABEL: uaddsat_i32_vs:
 ; GFX8:       ; %bb.0:
 ; GFX8-NEXT:    v_add_u32_e64 v0, s[0:1], v0, s0 clamp
 ; GFX8-NEXT:    ; return to shader part epilog
 ;
 ; GFX9-LABEL: uaddsat_i32_vs:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    v_add_u32_e64 v0, v0, s0 clamp
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
-; GFX10-LABEL: uaddsat_i32_vs:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_add_nc_u32_e64 v0, v0, s0 clamp
-; GFX10-NEXT:    ; return to shader part epilog
+; GFX10PLUS-LABEL: uaddsat_i32_vs:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    v_add_nc_u32_e64 v0, v0, s0 clamp
+; GFX10PLUS-NEXT:    ; return to shader part epilog
   %result = call i32 @llvm.uadd.sat.i32(i32 %lhs, i32 %rhs)
   %cast = bitcast i32 %result to float
   ret float %cast
 }
 
 define <2 x i32> @v_uaddsat_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) {
 ; GFX6-LABEL: v_uaddsat_v2i32:
 ; GFX6:       ; %bb.0:

 ;
 ; GFX9-LABEL: v_uaddsat_v2i32:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    v_add_u32_e64 v0, v0, v2 clamp
 ; GFX9-NEXT:    v_add_u32_e64 v1, v1, v3 clamp
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX10-LABEL: v_uaddsat_v2i32:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_add_nc_u32_e64 v0, v0, v2 clamp
-; GFX10-NEXT:    v_add_nc_u32_e64 v1, v1, v3 clamp
-; GFX10-NEXT:    s_setpc_b64 s[30:31]
+; GFX10PLUS-LABEL: v_uaddsat_v2i32:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX10PLUS-NEXT:    v_add_nc_u32_e64 v0, v0, v2 clamp
+; GFX10PLUS-NEXT:    v_add_nc_u32_e64 v1, v1, v3 clamp
+; GFX10PLUS-NEXT:    s_setpc_b64 s[30:31]
   %result = call <2 x i32> @llvm.uadd.sat.v2i32(<2 x i32> %lhs, <2 x i32> %rhs)
   ret <2 x i32> %result
 }
 
 define amdgpu_ps <2 x i32> @s_uaddsat_v2i32(<2 x i32> inreg %lhs, <2 x i32> inreg %rhs) {
 ; GFX6-LABEL: s_uaddsat_v2i32:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_not_b32 s4, s0

 ; GFX9-NEXT:    v_mov_b32_e32 v0, s2
 ; GFX9-NEXT:    v_mov_b32_e32 v1, s3
 ; GFX9-NEXT:    v_add_u32_e64 v0, s0, v0 clamp
 ; GFX9-NEXT:    v_add_u32_e64 v1, s1, v1 clamp
 ; GFX9-NEXT:    v_readfirstlane_b32 s0, v0
 ; GFX9-NEXT:    v_readfirstlane_b32 s1, v1
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
-; GFX10-LABEL: s_uaddsat_v2i32:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_add_nc_u32_e64 v0, s0, s2 clamp
-; GFX10-NEXT:    v_add_nc_u32_e64 v1, s1, s3 clamp
-; GFX10-NEXT:    v_readfirstlane_b32 s0, v0
-; GFX10-NEXT:    v_readfirstlane_b32 s1, v1
-; GFX10-NEXT:    ; return to shader part epilog
+; GFX10PLUS-LABEL: s_uaddsat_v2i32:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    v_add_nc_u32_e64 v0, s0, s2 clamp
+; GFX10PLUS-NEXT:    v_add_nc_u32_e64 v1, s1, s3 clamp
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s0, v0
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s1, v1
+; GFX10PLUS-NEXT:    ; return to shader part epilog
   %result = call <2 x i32> @llvm.uadd.sat.v2i32(<2 x i32> %lhs, <2 x i32> %rhs)
   ret <2 x i32> %result
 }
 
 define <3 x i32> @v_uaddsat_v3i32(<3 x i32> %lhs, <3 x i32> %rhs) {
 ; GFX6-LABEL: v_uaddsat_v3i32:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

 ; GFX9-LABEL: v_uaddsat_v3i32:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    v_add_u32_e64 v0, v0, v3 clamp
 ; GFX9-NEXT:    v_add_u32_e64 v1, v1, v4 clamp
 ; GFX9-NEXT:    v_add_u32_e64 v2, v2, v5 clamp
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX10-LABEL: v_uaddsat_v3i32:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_add_nc_u32_e64 v0, v0, v3 clamp
-; GFX10-NEXT:    v_add_nc_u32_e64 v1, v1, v4 clamp
-; GFX10-NEXT:    v_add_nc_u32_e64 v2, v2, v5 clamp
-; GFX10-NEXT:    s_setpc_b64 s[30:31]
+; GFX10PLUS-LABEL: v_uaddsat_v3i32:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX10PLUS-NEXT:    v_add_nc_u32_e64 v0, v0, v3 clamp
+; GFX10PLUS-NEXT:    v_add_nc_u32_e64 v1, v1, v4 clamp
+; GFX10PLUS-NEXT:    v_add_nc_u32_e64 v2, v2, v5 clamp
+; GFX10PLUS-NEXT:    s_setpc_b64 s[30:31]
   %result = call <3 x i32> @llvm.uadd.sat.v3i32(<3 x i32> %lhs, <3 x i32> %rhs)
   ret <3 x i32> %result
 }
 
 define amdgpu_ps <3 x i32> @s_uaddsat_v3i32(<3 x i32> inreg %lhs, <3 x i32> inreg %rhs) {
 ; GFX6-LABEL: s_uaddsat_v3i32:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_not_b32 s6, s0

 ; GFX9-NEXT:    v_add_u32_e64 v0, s0, v0 clamp
 ; GFX9-NEXT:    v_add_u32_e64 v1, s1, v1 clamp
 ; GFX9-NEXT:    v_add_u32_e64 v2, s2, v2 clamp
 ; GFX9-NEXT:    v_readfirstlane_b32 s0, v0
 ; GFX9-NEXT:    v_readfirstlane_b32 s1, v1
 ; GFX9-NEXT:    v_readfirstlane_b32 s2, v2
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
-; GFX10-LABEL: s_uaddsat_v3i32:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_add_nc_u32_e64 v0, s0, s3 clamp
-; GFX10-NEXT:    v_add_nc_u32_e64 v1, s1, s4 clamp
-; GFX10-NEXT:    v_add_nc_u32_e64 v2, s2, s5 clamp
-; GFX10-NEXT:    v_readfirstlane_b32 s0, v0
-; GFX10-NEXT:    v_readfirstlane_b32 s1, v1
-; GFX10-NEXT:    v_readfirstlane_b32 s2, v2
-; GFX10-NEXT:    ; return to shader part epilog
+; GFX10PLUS-LABEL: s_uaddsat_v3i32:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    v_add_nc_u32_e64 v0, s0, s3 clamp
+; GFX10PLUS-NEXT:    v_add_nc_u32_e64 v1, s1, s4 clamp
+; GFX10PLUS-NEXT:    v_add_nc_u32_e64 v2, s2, s5 clamp
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s0, v0
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s1, v1
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s2, v2
+; GFX10PLUS-NEXT:    ; return to shader part epilog
   %result = call <3 x i32> @llvm.uadd.sat.v3i32(<3 x i32> %lhs, <3 x i32> %rhs)
   ret <3 x i32> %result
 }
 
 define <4 x i32> @v_uaddsat_v4i32(<4 x i32> %lhs, <4 x i32> %rhs) {
 ; GFX6-LABEL: v_uaddsat_v4i32:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    v_add_u32_e64 v0, v0, v4 clamp
 ; GFX9-NEXT:    v_add_u32_e64 v1, v1, v5 clamp
 ; GFX9-NEXT:    v_add_u32_e64 v2, v2, v6 clamp
 ; GFX9-NEXT:    v_add_u32_e64 v3, v3, v7 clamp
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX10-LABEL: v_uaddsat_v4i32:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_add_nc_u32_e64 v0, v0, v4 clamp
-; GFX10-NEXT:    v_add_nc_u32_e64 v1, v1, v5 clamp
-; GFX10-NEXT:    v_add_nc_u32_e64 v2, v2, v6 clamp
-; GFX10-NEXT:    v_add_nc_u32_e64 v3, v3, v7 clamp
-; GFX10-NEXT:    s_setpc_b64 s[30:31]
+; GFX10PLUS-LABEL: v_uaddsat_v4i32:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX10PLUS-NEXT:    v_add_nc_u32_e64 v0, v0, v4 clamp
+; GFX10PLUS-NEXT:    v_add_nc_u32_e64 v1, v1, v5 clamp
+; GFX10PLUS-NEXT:    v_add_nc_u32_e64 v2, v2, v6 clamp
+; GFX10PLUS-NEXT:    v_add_nc_u32_e64 v3, v3, v7 clamp
+; GFX10PLUS-NEXT:    s_setpc_b64 s[30:31]
   %result = call <4 x i32> @llvm.uadd.sat.v4i32(<4 x i32> %lhs, <4 x i32> %rhs)
   ret <4 x i32> %result
 }
 
 define amdgpu_ps <4 x i32> @s_uaddsat_v4i32(<4 x i32> inreg %lhs, <4 x i32> inreg %rhs) {
 ; GFX6-LABEL: s_uaddsat_v4i32:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_not_b32 s8, s0

 ; GFX9-NEXT:    v_add_u32_e64 v2, s2, v2 clamp
 ; GFX9-NEXT:    v_add_u32_e64 v3, s3, v3 clamp
 ; GFX9-NEXT:    v_readfirstlane_b32 s0, v0
 ; GFX9-NEXT:    v_readfirstlane_b32 s1, v1
 ; GFX9-NEXT:    v_readfirstlane_b32 s2, v2
 ; GFX9-NEXT:    v_readfirstlane_b32 s3, v3
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
-; GFX10-LABEL: s_uaddsat_v4i32:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_add_nc_u32_e64 v0, s0, s4 clamp
-; GFX10-NEXT:    v_add_nc_u32_e64 v1, s1, s5 clamp
-; GFX10-NEXT:    v_add_nc_u32_e64 v2, s2, s6 clamp
-; GFX10-NEXT:    v_add_nc_u32_e64 v3, s3, s7 clamp
-; GFX10-NEXT:    v_readfirstlane_b32 s0, v0
-; GFX10-NEXT:    v_readfirstlane_b32 s1, v1
-; GFX10-NEXT:    v_readfirstlane_b32 s2, v2
-; GFX10-NEXT:    v_readfirstlane_b32 s3, v3
-; GFX10-NEXT:    ; return to shader part epilog
+; GFX10PLUS-LABEL: s_uaddsat_v4i32:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    v_add_nc_u32_e64 v0, s0, s4 clamp
+; GFX10PLUS-NEXT:    v_add_nc_u32_e64 v1, s1, s5 clamp
+; GFX10PLUS-NEXT:    v_add_nc_u32_e64 v2, s2, s6 clamp
+; GFX10PLUS-NEXT:    v_add_nc_u32_e64 v3, s3, s7 clamp
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s0, v0
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s1, v1
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s2, v2
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s3, v3
+; GFX10PLUS-NEXT:    ; return to shader part epilog
   %result = call <4 x i32> @llvm.uadd.sat.v4i32(<4 x i32> %lhs, <4 x i32> %rhs)
   ret <4 x i32> %result
 }
 
 define <5 x i32> @v_uaddsat_v5i32(<5 x i32> %lhs, <5 x i32> %rhs) {
 ; GFX6-LABEL: v_uaddsat_v5i32:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    v_add_u32_e64 v0, v0, v5 clamp
 ; GFX9-NEXT:    v_add_u32_e64 v1, v1, v6 clamp
 ; GFX9-NEXT:    v_add_u32_e64 v2, v2, v7 clamp
 ; GFX9-NEXT:    v_add_u32_e64 v3, v3, v8 clamp
 ; GFX9-NEXT:    v_add_u32_e64 v4, v4, v9 clamp
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX10-LABEL: v_uaddsat_v5i32:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_add_nc_u32_e64 v0, v0, v5 clamp
-; GFX10-NEXT:    v_add_nc_u32_e64 v1, v1, v6 clamp
-; GFX10-NEXT:    v_add_nc_u32_e64 v2, v2, v7 clamp
-; GFX10-NEXT:    v_add_nc_u32_e64 v3, v3, v8 clamp
-; GFX10-NEXT:    v_add_nc_u32_e64 v4, v4, v9 clamp
-; GFX10-NEXT:    s_setpc_b64 s[30:31]
+; GFX10PLUS-LABEL: v_uaddsat_v5i32:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX10PLUS-NEXT:    v_add_nc_u32_e64 v0, v0, v5 clamp
+; GFX10PLUS-NEXT:    v_add_nc_u32_e64 v1, v1, v6 clamp
+; GFX10PLUS-NEXT:    v_add_nc_u32_e64 v2, v2, v7 clamp
+; GFX10PLUS-NEXT:    v_add_nc_u32_e64 v3, v3, v8 clamp
+; GFX10PLUS-NEXT:    v_add_nc_u32_e64 v4, v4, v9 clamp
+; GFX10PLUS-NEXT:    s_setpc_b64 s[30:31]
   %result = call <5 x i32> @llvm.uadd.sat.v5i32(<5 x i32> %lhs, <5 x i32> %rhs)
   ret <5 x i32> %result
 }
 
 define amdgpu_ps <5 x i32> @s_uaddsat_v5i32(<5 x i32> inreg %lhs, <5 x i32> inreg %rhs) {
 ; GFX6-LABEL: s_uaddsat_v5i32:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_not_b32 s10, s0

 ; GFX9-NEXT:    v_add_u32_e64 v4, s4, v4 clamp
 ; GFX9-NEXT:    v_readfirstlane_b32 s0, v0
 ; GFX9-NEXT:    v_readfirstlane_b32 s1, v1
 ; GFX9-NEXT:    v_readfirstlane_b32 s2, v2
 ; GFX9-NEXT:    v_readfirstlane_b32 s3, v3
 ; GFX9-NEXT:    v_readfirstlane_b32 s4, v4
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
-; GFX10-LABEL: s_uaddsat_v5i32:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_add_nc_u32_e64 v0, s0, s5 clamp
-; GFX10-NEXT:    v_add_nc_u32_e64 v1, s1, s6 clamp
-; GFX10-NEXT:    v_add_nc_u32_e64 v2, s2, s7 clamp
-; GFX10-NEXT:    v_add_nc_u32_e64 v3, s3, s8 clamp
-; GFX10-NEXT:    v_add_nc_u32_e64 v4, s4, s9 clamp
-; GFX10-NEXT:    v_readfirstlane_b32 s0, v0
-; GFX10-NEXT:    v_readfirstlane_b32 s1, v1
-; GFX10-NEXT:    v_readfirstlane_b32 s2, v2
-; GFX10-NEXT:    v_readfirstlane_b32 s3, v3
-; GFX10-NEXT:    v_readfirstlane_b32 s4, v4
-; GFX10-NEXT:    ; return to shader part epilog
+; GFX10PLUS-LABEL: s_uaddsat_v5i32:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    v_add_nc_u32_e64 v0, s0, s5 clamp
+; GFX10PLUS-NEXT:    v_add_nc_u32_e64 v1, s1, s6 clamp
+; GFX10PLUS-NEXT:    v_add_nc_u32_e64 v2, s2, s7 clamp
+; GFX10PLUS-NEXT:    v_add_nc_u32_e64 v3, s3, s8 clamp
+; GFX10PLUS-NEXT:    v_add_nc_u32_e64 v4, s4, s9 clamp
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s0, v0
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s1, v1
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s2, v2
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s3, v3
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s4, v4
+; GFX10PLUS-NEXT:    ; return to shader part epilog
   %result = call <5 x i32> @llvm.uadd.sat.v5i32(<5 x i32> %lhs, <5 x i32> %rhs)
   ret <5 x i32> %result
 }
 
 define <16 x i32> @v_uaddsat_v16i32(<16 x i32> %lhs, <16 x i32> %rhs) {
 ; GFX6-LABEL: v_uaddsat_v16i32:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

 ; GFX10-NEXT:    v_add_nc_u32_e64 v10, v10, v26 clamp
 ; GFX10-NEXT:    v_add_nc_u32_e64 v11, v11, v27 clamp
 ; GFX10-NEXT:    v_add_nc_u32_e64 v12, v12, v28 clamp
 ; GFX10-NEXT:    v_add_nc_u32_e64 v13, v13, v29 clamp
 ; GFX10-NEXT:    v_add_nc_u32_e64 v14, v14, v30 clamp
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    v_add_nc_u32_e64 v15, v15, v31 clamp
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_uaddsat_v16i32:
+; GFX11:       ; %bb.0:
+; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT:    scratch_load_b32 v31, off, s32
+; GFX11-NEXT:    v_add_nc_u32_e64 v0, v0, v16 clamp
+; GFX11-NEXT:    v_add_nc_u32_e64 v1, v1, v17 clamp
+; GFX11-NEXT:    v_add_nc_u32_e64 v2, v2, v18 clamp
+; GFX11-NEXT:    v_add_nc_u32_e64 v3, v3, v19 clamp
+; GFX11-NEXT:    v_add_nc_u32_e64 v4, v4, v20 clamp
+; GFX11-NEXT:    v_add_nc_u32_e64 v5, v5, v21 clamp
+; GFX11-NEXT:    v_add_nc_u32_e64 v6, v6, v22 clamp
+; GFX11-NEXT:    v_add_nc_u32_e64 v7, v7, v23 clamp
+; GFX11-NEXT:    v_add_nc_u32_e64 v8, v8, v24 clamp
+; GFX11-NEXT:    v_add_nc_u32_e64 v9, v9, v25 clamp
+; GFX11-NEXT:    v_add_nc_u32_e64 v10, v10, v26 clamp
+; GFX11-NEXT:    v_add_nc_u32_e64 v11, v11, v27 clamp
+; GFX11-NEXT:    v_add_nc_u32_e64 v12, v12, v28 clamp
+; GFX11-NEXT:    v_add_nc_u32_e64 v13, v13, v29 clamp
+; GFX11-NEXT:    v_add_nc_u32_e64 v14, v14, v30 clamp
+; GFX11-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-NEXT:    v_add_nc_u32_e64 v15, v15, v31 clamp
+; GFX11-NEXT:    s_setpc_b64 s[30:31]
   %result = call <16 x i32> @llvm.uadd.sat.v16i32(<16 x i32> %lhs, <16 x i32> %rhs)
   ret <16 x i32> %result
 }
 
 define amdgpu_ps <16 x i32> @s_uaddsat_v16i32(<16 x i32> inreg %lhs, <16 x i32> inreg %rhs) {
 ; GFX6-LABEL: s_uaddsat_v16i32:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_not_b32 s32, s0

 ; GFX9-NEXT:    v_readfirstlane_b32 s10, v10
 ; GFX9-NEXT:    v_readfirstlane_b32 s11, v11
 ; GFX9-NEXT:    v_readfirstlane_b32 s12, v12
 ; GFX9-NEXT:    v_readfirstlane_b32 s13, v13
 ; GFX9-NEXT:    v_readfirstlane_b32 s14, v14
 ; GFX9-NEXT:    v_readfirstlane_b32 s15, v15
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
-; GFX10-LABEL: s_uaddsat_v16i32:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_add_nc_u32_e64 v0, s0, s16 clamp
-; GFX10-NEXT:    v_add_nc_u32_e64 v1, s1, s17 clamp
-; GFX10-NEXT:    v_add_nc_u32_e64 v2, s2, s18 clamp
-; GFX10-NEXT:    v_add_nc_u32_e64 v3, s3, s19 clamp
-; GFX10-NEXT:    v_add_nc_u32_e64 v4, s4, s20 clamp
-; GFX10-NEXT:    v_add_nc_u32_e64 v5, s5, s21 clamp
-; GFX10-NEXT:    v_add_nc_u32_e64 v6, s6, s22 clamp
-; GFX10-NEXT:    v_add_nc_u32_e64 v7, s7, s23 clamp
-; GFX10-NEXT:    v_add_nc_u32_e64 v8, s8, s24 clamp
-; GFX10-NEXT:    v_add_nc_u32_e64 v9, s9, s25 clamp
-; GFX10-NEXT:    v_add_nc_u32_e64 v10, s10, s26 clamp
-; GFX10-NEXT:    v_add_nc_u32_e64 v11, s11, s27 clamp
-; GFX10-NEXT:    v_add_nc_u32_e64 v12, s12, s28 clamp
-; GFX10-NEXT:    v_add_nc_u32_e64 v13, s13, s29 clamp
-; GFX10-NEXT:    v_add_nc_u32_e64 v14, s14, s30 clamp
-; GFX10-NEXT:    v_add_nc_u32_e64 v15, s15, s31 clamp
-; GFX10-NEXT:    v_readfirstlane_b32 s0, v0
-; GFX10-NEXT:    v_readfirstlane_b32 s1, v1
-; GFX10-NEXT:    v_readfirstlane_b32 s2, v2
-; GFX10-NEXT:    v_readfirstlane_b32 s3, v3
-; GFX10-NEXT:    v_readfirstlane_b32 s4, v4
-; GFX10-NEXT:    v_readfirstlane_b32 s5, v5
-; GFX10-NEXT:    v_readfirstlane_b32 s6, v6
-; GFX10-NEXT:    v_readfirstlane_b32 s7, v7
-; GFX10-NEXT:    v_readfirstlane_b32 s8, v8
-; GFX10-NEXT:    v_readfirstlane_b32 s9, v9
-; GFX10-NEXT:    v_readfirstlane_b32 s10, v10
-; GFX10-NEXT:    v_readfirstlane_b32 s11, v11
-; GFX10-NEXT:    v_readfirstlane_b32 s12, v12
-; GFX10-NEXT:    v_readfirstlane_b32 s13, v13
-; GFX10-NEXT:    v_readfirstlane_b32 s14, v14
-; GFX10-NEXT:    v_readfirstlane_b32 s15, v15
-; GFX10-NEXT:    ; return to shader part epilog
+; GFX10PLUS-LABEL: s_uaddsat_v16i32:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    v_add_nc_u32_e64 v0, s0, s16 clamp
+; GFX10PLUS-NEXT:    v_add_nc_u32_e64 v1, s1, s17 clamp
+; GFX10PLUS-NEXT:    v_add_nc_u32_e64 v2, s2, s18 clamp
+; GFX10PLUS-NEXT:    v_add_nc_u32_e64 v3, s3, s19 clamp
+; GFX10PLUS-NEXT:    v_add_nc_u32_e64 v4, s4, s20 clamp
+; GFX10PLUS-NEXT:    v_add_nc_u32_e64 v5, s5, s21 clamp
+; GFX10PLUS-NEXT:    v_add_nc_u32_e64 v6, s6, s22 clamp
+; GFX10PLUS-NEXT:    v_add_nc_u32_e64 v7, s7, s23 clamp
+; GFX10PLUS-NEXT:    v_add_nc_u32_e64 v8, s8, s24 clamp
+; GFX10PLUS-NEXT:    v_add_nc_u32_e64 v9, s9, s25 clamp
+; GFX10PLUS-NEXT:    v_add_nc_u32_e64 v10, s10, s26 clamp
+; GFX10PLUS-NEXT:    v_add_nc_u32_e64 v11, s11, s27 clamp
+; GFX10PLUS-NEXT:    v_add_nc_u32_e64 v12, s12, s28 clamp
+; GFX10PLUS-NEXT:    v_add_nc_u32_e64 v13, s13, s29 clamp
+; GFX10PLUS-NEXT:    v_add_nc_u32_e64 v14, s14, s30 clamp
+; GFX10PLUS-NEXT:    v_add_nc_u32_e64 v15, s15, s31 clamp
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s0, v0
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s1, v1
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s2, v2
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s3, v3
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s4, v4
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s5, v5
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s6, v6
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s7, v7
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s8, v8
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s9, v9
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s10, v10
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s11, v11
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s12, v12
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s13, v13
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s14, v14
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s15, v15
+; GFX10PLUS-NEXT:    ; return to shader part epilog
   %result = call <16 x i32> @llvm.uadd.sat.v16i32(<16 x i32> %lhs, <16 x i32> %rhs)
   ret <16 x i32> %result
 }
 
 define i16 @v_uaddsat_i16(i16 %lhs, i16 %rhs) {
 ; GFX6-LABEL: v_uaddsat_i16:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

 ; GFX8-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX9-LABEL: v_uaddsat_i16:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    v_add_u16_e64 v0, v0, v1 clamp
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX10-LABEL: v_uaddsat_i16:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_add_nc_u16 v0, v0, v1 clamp
-; GFX10-NEXT:    s_setpc_b64 s[30:31]
+; GFX10PLUS-LABEL: v_uaddsat_i16:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX10PLUS-NEXT:    v_add_nc_u16 v0, v0, v1 clamp
+; GFX10PLUS-NEXT:    s_setpc_b64 s[30:31]
   %result = call i16 @llvm.uadd.sat.i16(i16 %lhs, i16 %rhs)
   ret i16 %result
 }
 
 define amdgpu_ps i16 @s_uaddsat_i16(i16 inreg %lhs, i16 inreg %rhs) {
 ; GFX6-LABEL: s_uaddsat_i16:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_lshl_b32 s0, s0, 16

 ;
 ; GFX9-LABEL: s_uaddsat_i16:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    v_mov_b32_e32 v0, s1
 ; GFX9-NEXT:    v_add_u16_e64 v0, s0, v0 clamp
 ; GFX9-NEXT:    v_readfirstlane_b32 s0, v0
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
-; GFX10-LABEL: s_uaddsat_i16:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_add_nc_u16 v0, s0, s1 clamp
-; GFX10-NEXT:    v_readfirstlane_b32 s0, v0
-; GFX10-NEXT:    ; return to shader part epilog
+; GFX10PLUS-LABEL: s_uaddsat_i16:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    v_add_nc_u16 v0, s0, s1 clamp
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s0, v0
+; GFX10PLUS-NEXT:    ; return to shader part epilog
   %result = call i16 @llvm.uadd.sat.i16(i16 %lhs, i16 %rhs)
   ret i16 %result
 }
 
 define amdgpu_ps half @uaddsat_i16_sv(i16 inreg %lhs, i16 %rhs) {
 ; GFX6-LABEL: uaddsat_i16_sv:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_lshl_b32 s0, s0, 16

 ; GFX8-NEXT:    v_add_u16_e64 v0, s0, v0 clamp
 ; GFX8-NEXT:    ; return to shader part epilog
 ;
 ; GFX9-LABEL: uaddsat_i16_sv:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    v_add_u16_e64 v0, s0, v0 clamp
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
-; GFX10-LABEL: uaddsat_i16_sv:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_add_nc_u16 v0, s0, v0 clamp
-; GFX10-NEXT:    ; return to shader part epilog
+; GFX10PLUS-LABEL: uaddsat_i16_sv:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    v_add_nc_u16 v0, s0, v0 clamp
+; GFX10PLUS-NEXT:    ; return to shader part epilog
   %result = call i16 @llvm.uadd.sat.i16(i16 %lhs, i16 %rhs)
   %cast = bitcast i16 %result to half
   ret half %cast
 }
 
 define amdgpu_ps half @uaddsat_i16_vs(i16 %lhs, i16 inreg %rhs) {
 ; GFX6-LABEL: uaddsat_i16_vs:
 ; GFX6:       ; %bb.0:

 ; GFX8-NEXT:    v_add_u16_e64 v0, v0, s0 clamp
 ; GFX8-NEXT:    ; return to shader part epilog
 ;
 ; GFX9-LABEL: uaddsat_i16_vs:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    v_add_u16_e64 v0, v0, s0 clamp
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
-; GFX10-LABEL: uaddsat_i16_vs:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_add_nc_u16 v0, v0, s0 clamp
-; GFX10-NEXT:    ; return to shader part epilog
+; GFX10PLUS-LABEL: uaddsat_i16_vs:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    v_add_nc_u16 v0, v0, s0 clamp
+; GFX10PLUS-NEXT:    ; return to shader part epilog
   %result = call i16 @llvm.uadd.sat.i16(i16 %lhs, i16 %rhs)
   %cast = bitcast i16 %result to half
   ret half %cast
 }
 
 define <2 x i16> @v_uaddsat_v2i16(<2 x i16> %lhs, <2 x i16> %rhs) {
 ; GFX6-LABEL: v_uaddsat_v2i16:
 ; GFX6:       ; %bb.0:

 ; GFX8-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX9-LABEL: v_uaddsat_v2i16:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    v_pk_add_u16 v0, v0, v1 clamp
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX10-LABEL: v_uaddsat_v2i16:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_pk_add_u16 v0, v0, v1 clamp
-; GFX10-NEXT:    s_setpc_b64 s[30:31]
+; GFX10PLUS-LABEL: v_uaddsat_v2i16:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX10PLUS-NEXT:    v_pk_add_u16 v0, v0, v1 clamp
+; GFX10PLUS-NEXT:    s_setpc_b64 s[30:31]
   %result = call <2 x i16> @llvm.uadd.sat.v2i16(<2 x i16> %lhs, <2 x i16> %rhs)
   ret <2 x i16> %result
 }
 
 define amdgpu_ps i32 @s_uaddsat_v2i16(<2 x i16> inreg %lhs, <2 x i16> inreg %rhs) {
 ; GFX6-LABEL: s_uaddsat_v2i16:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_lshl_b32 s0, s0, 16

 ;
 ; GFX9-LABEL: s_uaddsat_v2i16:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    v_mov_b32_e32 v0, s1
 ; GFX9-NEXT:    v_pk_add_u16 v0, s0, v0 clamp
 ; GFX9-NEXT:    v_readfirstlane_b32 s0, v0
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
-; GFX10-LABEL: s_uaddsat_v2i16:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_pk_add_u16 v0, s0, s1 clamp
-; GFX10-NEXT:    v_readfirstlane_b32 s0, v0
-; GFX10-NEXT:    ; return to shader part epilog
+; GFX10PLUS-LABEL: s_uaddsat_v2i16:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    v_pk_add_u16 v0, s0, s1 clamp
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s0, v0
+; GFX10PLUS-NEXT:    ; return to shader part epilog
   %result = call <2 x i16> @llvm.uadd.sat.v2i16(<2 x i16> %lhs, <2 x i16> %rhs)
   %cast = bitcast <2 x i16> %result to i32
   ret i32 %cast
 }
 
 define amdgpu_ps float @uaddsat_v2i16_sv(<2 x i16> inreg %lhs, <2 x i16> %rhs) {
 ; GFX6-LABEL: uaddsat_v2i16_sv:
 ; GFX6:       ; %bb.0:

 ; GFX8-NEXT:    v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
 ; GFX8-NEXT:    ; return to shader part epilog
 ;
 ; GFX9-LABEL: uaddsat_v2i16_sv:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    v_pk_add_u16 v0, s0, v0 clamp
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
-; GFX10-LABEL: uaddsat_v2i16_sv:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_pk_add_u16 v0, s0, v0 clamp
-; GFX10-NEXT:    ; return to shader part epilog
+; GFX10PLUS-LABEL: uaddsat_v2i16_sv:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    v_pk_add_u16 v0, s0, v0 clamp
+; GFX10PLUS-NEXT:    ; return to shader part epilog
   %result = call <2 x i16> @llvm.uadd.sat.v2i16(<2 x i16> %lhs, <2 x i16> %rhs)
   %cast = bitcast <2 x i16> %result to float
   ret float %cast
 }
 
 define amdgpu_ps float @uaddsat_v2i16_vs(<2 x i16> %lhs, <2 x i16> inreg %rhs) {
 ; GFX6-LABEL: uaddsat_v2i16_vs:
 ; GFX6:       ; %bb.0:

 ; GFX8-NEXT:    v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
 ; GFX8-NEXT:    ; return to shader part epilog
 ;
 ; GFX9-LABEL: uaddsat_v2i16_vs:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    v_pk_add_u16 v0, v0, s0 clamp
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
-; GFX10-LABEL: uaddsat_v2i16_vs:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_pk_add_u16 v0, v0, s0 clamp
-; GFX10-NEXT:    ; return to shader part epilog
+; GFX10PLUS-LABEL: uaddsat_v2i16_vs:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    v_pk_add_u16 v0, v0, s0 clamp
+; GFX10PLUS-NEXT:    ; return to shader part epilog
   %result = call <2 x i16> @llvm.uadd.sat.v2i16(<2 x i16> %lhs, <2 x i16> %rhs)
   %cast = bitcast <2 x i16> %result to float
   ret float %cast
 }
 
 ; FIXME: v3i16 insert/extract
 ; define <3 x i16> @v_uaddsat_v3i16(<3 x i16> %lhs, <3 x i16> %rhs) {
 ;   %result = call <3 x i16> @llvm.uadd.sat.v3i16(<3 x i16> %lhs, <3 x i16> %rhs)

 ;
 ; GFX9-LABEL: v_uaddsat_v4i16:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    v_pk_add_u16 v0, v0, v2 clamp
 ; GFX9-NEXT:    v_pk_add_u16 v1, v1, v3 clamp
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX10-LABEL: v_uaddsat_v4i16:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_pk_add_u16 v0, v0, v2 clamp
-; GFX10-NEXT:    v_pk_add_u16 v1, v1, v3 clamp
-; GFX10-NEXT:    s_setpc_b64 s[30:31]
+; GFX10PLUS-LABEL: v_uaddsat_v4i16:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX10PLUS-NEXT:    v_pk_add_u16 v0, v0, v2 clamp
+; GFX10PLUS-NEXT:    v_pk_add_u16 v1, v1, v3 clamp
+; GFX10PLUS-NEXT:    s_setpc_b64 s[30:31]
   %result = call <4 x i16> @llvm.uadd.sat.v4i16(<4 x i16> %lhs, <4 x i16> %rhs)
   %cast = bitcast <4 x i16> %result to <2 x float>
   ret <2 x float> %cast
 }
 
 define amdgpu_ps <2 x i32> @s_uaddsat_v4i16(<4 x i16> inreg %lhs, <4 x i16> inreg %rhs) {
 ; GFX6-LABEL: s_uaddsat_v4i16:
 ; GFX6:       ; %bb.0:

 ; GFX9-NEXT:    v_mov_b32_e32 v0, s2
 ; GFX9-NEXT:    v_mov_b32_e32 v1, s3
 ; GFX9-NEXT:    v_pk_add_u16 v0, s0, v0 clamp
 ; GFX9-NEXT:    v_pk_add_u16 v1, s1, v1 clamp
 ; GFX9-NEXT:    v_readfirstlane_b32 s0, v0
 ; GFX9-NEXT:    v_readfirstlane_b32 s1, v1
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
-; GFX10-LABEL: s_uaddsat_v4i16:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_pk_add_u16 v0, s0, s2 clamp
-; GFX10-NEXT:    v_pk_add_u16 v1, s1, s3 clamp
-; GFX10-NEXT:    v_readfirstlane_b32 s0, v0
-; GFX10-NEXT:    v_readfirstlane_b32 s1, v1
-; GFX10-NEXT:    ; return to shader part epilog
+; GFX10PLUS-LABEL: s_uaddsat_v4i16:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    v_pk_add_u16 v0, s0, s2 clamp
+; GFX10PLUS-NEXT:    v_pk_add_u16 v1, s1, s3 clamp
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s0, v0
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s1, v1
+; GFX10PLUS-NEXT:    ; return to shader part epilog
   %result = call <4 x i16> @llvm.uadd.sat.v4i16(<4 x i16> %lhs, <4 x i16> %rhs)
   %cast = bitcast <4 x i16> %result to <2 x i32>
   ret <2 x i32> %cast
 }
 
 ; FIXME
 ; define <5 x i16> @v_uaddsat_v5i16(<5 x i16> %lhs, <5 x i16> %rhs) {
 ;   %result = call <5 x i16> @llvm.uadd.sat.v5i16(<5 x i16> %lhs, <5 x i16> %rhs)

 ; GFX9-LABEL: v_uaddsat_v6i16:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    v_pk_add_u16 v0, v0, v3 clamp
 ; GFX9-NEXT:    v_pk_add_u16 v1, v1, v4 clamp
 ; GFX9-NEXT:    v_pk_add_u16 v2, v2, v5 clamp
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX10-LABEL: v_uaddsat_v6i16:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_pk_add_u16 v0, v0, v3 clamp
-; GFX10-NEXT:    v_pk_add_u16 v1, v1, v4 clamp
-; GFX10-NEXT:    v_pk_add_u16 v2, v2, v5 clamp
-; GFX10-NEXT:    s_setpc_b64 s[30:31]
+; GFX10PLUS-LABEL: v_uaddsat_v6i16:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX10PLUS-NEXT:    v_pk_add_u16 v0, v0, v3 clamp
+; GFX10PLUS-NEXT:    v_pk_add_u16 v1, v1, v4 clamp
+; GFX10PLUS-NEXT:    v_pk_add_u16 v2, v2, v5 clamp
+; GFX10PLUS-NEXT:    s_setpc_b64 s[30:31]
   %result = call <6 x i16> @llvm.uadd.sat.v6i16(<6 x i16> %lhs, <6 x i16> %rhs)
   %cast = bitcast <6 x i16> %result to <3 x float>
   ret <3 x float> %cast
 }
 
 define amdgpu_ps <3 x i32> @s_uaddsat_v6i16(<6 x i16> inreg %lhs, <6 x i16> inreg %rhs) {
 ; GFX6-LABEL: s_uaddsat_v6i16:
 ; GFX6:       ; %bb.0:

 ; GFX9-NEXT:    v_pk_add_u16 v0, s0, v0 clamp
 ; GFX9-NEXT:    v_pk_add_u16 v1, s1, v1 clamp
 ; GFX9-NEXT:    v_pk_add_u16 v2, s2, v2 clamp
 ; GFX9-NEXT:    v_readfirstlane_b32 s0, v0
 ; GFX9-NEXT:    v_readfirstlane_b32 s1, v1
 ; GFX9-NEXT:    v_readfirstlane_b32 s2, v2
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
-; GFX10-LABEL: s_uaddsat_v6i16:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_pk_add_u16 v0, s0, s3 clamp
-; GFX10-NEXT:    v_pk_add_u16 v1, s1, s4 clamp
-; GFX10-NEXT:    v_pk_add_u16 v2, s2, s5 clamp
-; GFX10-NEXT:    v_readfirstlane_b32 s0, v0
-; GFX10-NEXT:    v_readfirstlane_b32 s1, v1
-; GFX10-NEXT:    v_readfirstlane_b32 s2, v2
-; GFX10-NEXT:    ; return to shader part epilog
+; GFX10PLUS-LABEL: s_uaddsat_v6i16:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    v_pk_add_u16 v0, s0, s3 clamp
+; GFX10PLUS-NEXT:    v_pk_add_u16 v1, s1, s4 clamp
+; GFX10PLUS-NEXT:    v_pk_add_u16 v2, s2, s5 clamp
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s0, v0
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s1, v1
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s2, v2
+; GFX10PLUS-NEXT:    ; return to shader part epilog
   %result = call <6 x i16> @llvm.uadd.sat.v6i16(<6 x i16> %lhs, <6 x i16> %rhs)
   %cast = bitcast <6 x i16> %result to <3 x i32>
   ret <3 x i32> %cast
 }
 
 define <4 x float> @v_uaddsat_v8i16(<8 x i16> %lhs, <8 x i16> %rhs) {
 ; GFX6-LABEL: v_uaddsat_v8i16:
 ; GFX6:       ; %bb.0:

 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    v_pk_add_u16 v0, v0, v4 clamp
 ; GFX9-NEXT:    v_pk_add_u16 v1, v1, v5 clamp
 ; GFX9-NEXT:    v_pk_add_u16 v2, v2, v6 clamp
 ; GFX9-NEXT:    v_pk_add_u16 v3, v3, v7 clamp
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX10-LABEL: v_uaddsat_v8i16:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_pk_add_u16 v0, v0, v4 clamp
-; GFX10-NEXT:    v_pk_add_u16 v1, v1, v5 clamp
-; GFX10-NEXT:    v_pk_add_u16 v2, v2, v6 clamp
-; GFX10-NEXT:    v_pk_add_u16 v3, v3, v7 clamp
-; GFX10-NEXT:    s_setpc_b64 s[30:31]
+; GFX10PLUS-LABEL: v_uaddsat_v8i16:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX10PLUS-NEXT:    v_pk_add_u16 v0, v0, v4 clamp
+; GFX10PLUS-NEXT:    v_pk_add_u16 v1, v1, v5 clamp
+; GFX10PLUS-NEXT:    v_pk_add_u16 v2, v2, v6 clamp
+; GFX10PLUS-NEXT:    v_pk_add_u16 v3, v3, v7 clamp
+; GFX10PLUS-NEXT:    s_setpc_b64 s[30:31]
   %result = call <8 x i16> @llvm.uadd.sat.v8i16(<8 x i16> %lhs, <8 x i16> %rhs)
   %cast = bitcast <8 x i16> %result to <4 x float>
   ret <4 x float> %cast
 }
 
 define amdgpu_ps <4 x i32> @s_uaddsat_v8i16(<8 x i16> inreg %lhs, <8 x i16> inreg %rhs) {
 ; GFX6-LABEL: s_uaddsat_v8i16:
 ; GFX6:       ; %bb.0:

 ; GFX9-NEXT:    v_pk_add_u16 v2, s2, v2 clamp
 ; GFX9-NEXT:    v_pk_add_u16 v3, s3, v3 clamp
 ; GFX9-NEXT:    v_readfirstlane_b32 s0, v0
 ; GFX9-NEXT:    v_readfirstlane_b32 s1, v1
 ; GFX9-NEXT:    v_readfirstlane_b32 s2, v2
 ; GFX9-NEXT:    v_readfirstlane_b32 s3, v3
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
-; GFX10-LABEL: s_uaddsat_v8i16:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_pk_add_u16 v0, s0, s4 clamp
-; GFX10-NEXT:    v_pk_add_u16 v1, s1, s5 clamp
-; GFX10-NEXT:    v_pk_add_u16 v2, s2, s6 clamp
-; GFX10-NEXT:    v_pk_add_u16 v3, s3, s7 clamp
-; GFX10-NEXT:    v_readfirstlane_b32 s0, v0
-; GFX10-NEXT:    v_readfirstlane_b32 s1, v1
-; GFX10-NEXT:    v_readfirstlane_b32 s2, v2
-; GFX10-NEXT:    v_readfirstlane_b32 s3, v3
-; GFX10-NEXT:    ; return to shader part epilog
+; GFX10PLUS-LABEL: s_uaddsat_v8i16:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    v_pk_add_u16 v0, s0, s4 clamp
+; GFX10PLUS-NEXT:    v_pk_add_u16 v1, s1, s5 clamp
+; GFX10PLUS-NEXT:    v_pk_add_u16 v2, s2, s6 clamp
+; GFX10PLUS-NEXT:    v_pk_add_u16 v3, s3, s7 clamp
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s0, v0
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s1, v1
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s2, v2
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s3, v3
+; GFX10PLUS-NEXT:    ; return to shader part epilog
   %result = call <8 x i16> @llvm.uadd.sat.v8i16(<8 x i16> %lhs, <8 x i16> %rhs)
   %cast = bitcast <8 x i16> %result to <4 x i32>
   ret <4 x i32> %cast
 }
 
 ; FIXME: i48 broken because i48 add broken
 ; define i48 @v_uaddsat_i48(i48 %lhs, i48 %rhs) {
 ;   %result = call i48 @llvm.uadd.sat.i48(i48 %lhs, i48 %rhs)

 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v2
 ; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, v1, v3, vcc
 ; GFX9-NEXT:    v_cmp_lt_u64_e32 vcc, v[0:1], v[2:3]
 ; GFX9-NEXT:    v_cndmask_b32_e64 v0, v0, -1, vcc
 ; GFX9-NEXT:    v_cndmask_b32_e64 v1, v1, -1, vcc
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX10-LABEL: v_uaddsat_i64:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_add_co_u32 v0, vcc_lo, v0, v2
-; GFX10-NEXT:    v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo
-; GFX10-NEXT:    v_cmp_lt_u64_e32 vcc_lo, v[0:1], v[2:3]
-; GFX10-NEXT:    v_cndmask_b32_e64 v0, v0, -1, vcc_lo
-; GFX10-NEXT:    v_cndmask_b32_e64 v1, v1, -1, vcc_lo
-; GFX10-NEXT:    s_setpc_b64 s[30:31]
+; GFX10PLUS-LABEL: v_uaddsat_i64:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX10PLUS-NEXT:    v_add_co_u32 v0, vcc_lo, v0, v2
+; GFX10PLUS-NEXT:    v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo
+; GFX10PLUS-NEXT:    v_cmp_lt_u64_e32 vcc_lo, v[0:1], v[2:3]
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v0, v0, -1, vcc_lo
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v1, v1, -1, vcc_lo
+; GFX10PLUS-NEXT:    s_setpc_b64 s[30:31]
   %result = call i64 @llvm.uadd.sat.i64(i64 %lhs, i64 %rhs)
   ret i64 %result
 }
 
 define amdgpu_ps i64 @s_uaddsat_i64(i64 inreg %lhs, i64 inreg %rhs) {
 ; GFX6-LABEL: s_uaddsat_i64:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_add_u32 s0, s0, s2

 ; GFX9-NEXT:    v_mov_b32_e32 v2, s0
 ; GFX9-NEXT:    v_mov_b32_e32 v3, s1
 ; GFX9-NEXT:    v_cndmask_b32_e64 v0, v2, -1, vcc
 ; GFX9-NEXT:    v_cndmask_b32_e64 v1, v3, -1, vcc
 ; GFX9-NEXT:    v_readfirstlane_b32 s0, v0
 ; GFX9-NEXT:    v_readfirstlane_b32 s1, v1
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
-; GFX10-LABEL: s_uaddsat_i64:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    s_add_u32 s0, s0, s2
-; GFX10-NEXT:    s_addc_u32 s1, s1, s3
-; GFX10-NEXT:    v_cmp_lt_u64_e64 s2, s[0:1], s[2:3]
-; GFX10-NEXT:    v_cndmask_b32_e64 v0, s0, -1, s2
-; GFX10-NEXT:    v_cndmask_b32_e64 v1, s1, -1, s2
-; GFX10-NEXT:    v_readfirstlane_b32 s0, v0
-; GFX10-NEXT:    v_readfirstlane_b32 s1, v1
-; GFX10-NEXT:    ; return to shader part epilog
+; GFX10PLUS-LABEL: s_uaddsat_i64:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    s_add_u32 s0, s0, s2
+; GFX10PLUS-NEXT:    s_addc_u32 s1, s1, s3
+; GFX10PLUS-NEXT:    v_cmp_lt_u64_e64 s2, s[0:1], s[2:3]
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v0, s0, -1, s2
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v1, s1, -1, s2
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s0, v0
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s1, v1
+; GFX10PLUS-NEXT:    ; return to shader part epilog
   %result = call i64 @llvm.uadd.sat.i64(i64 %lhs, i64 %rhs)
   ret i64 %result
 }
 
 define amdgpu_ps <2 x float> @uaddsat_i64_sv(i64 inreg %lhs, i64 %rhs) {
 ; GFX6-LABEL: uaddsat_i64_sv:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    v_mov_b32_e32 v3, s1

 ; GFX9-NEXT:    v_mov_b32_e32 v3, s1
 ; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, s0, v0
 ; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v3, v1, vcc
 ; GFX9-NEXT:    v_cmp_lt_u64_e32 vcc, v[2:3], v[0:1]
 ; GFX9-NEXT:    v_cndmask_b32_e64 v0, v2, -1, vcc
 ; GFX9-NEXT:    v_cndmask_b32_e64 v1, v3, -1, vcc
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
-; GFX10-LABEL: uaddsat_i64_sv:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_add_co_u32 v2, vcc_lo, s0, v0
-; GFX10-NEXT:    v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
-; GFX10-NEXT:    v_cmp_lt_u64_e32 vcc_lo, v[2:3], v[0:1]
-; GFX10-NEXT:    v_cndmask_b32_e64 v0, v2, -1, vcc_lo
-; GFX10-NEXT:    v_cndmask_b32_e64 v1, v3, -1, vcc_lo
-; GFX10-NEXT:    ; return to shader part epilog
+; GFX10PLUS-LABEL: uaddsat_i64_sv:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    v_add_co_u32 v2, vcc_lo, s0, v0
+; GFX10PLUS-NEXT:    v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
+; GFX10PLUS-NEXT:    v_cmp_lt_u64_e32 vcc_lo, v[2:3], v[0:1]
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v0, v2, -1, vcc_lo
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v1, v3, -1, vcc_lo
+; GFX10PLUS-NEXT:    ; return to shader part epilog
   %result = call i64 @llvm.uadd.sat.i64(i64 %lhs, i64 %rhs)
   %cast = bitcast i64 %result to <2 x float>
   ret <2 x float> %cast
 }
 
 define amdgpu_ps <2 x float> @uaddsat_i64_vs(i64 %lhs, i64 inreg %rhs) {
 ; GFX6-LABEL: uaddsat_i64_vs:
 ; GFX6:       ; %bb.0:

 ; GFX9-NEXT:    v_mov_b32_e32 v2, s1
 ; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, s0, v0
 ; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, v1, v2, vcc
 ; GFX9-NEXT:    v_cmp_gt_u64_e32 vcc, s[0:1], v[0:1]
 ; GFX9-NEXT:    v_cndmask_b32_e64 v0, v0, -1, vcc
 ; GFX9-NEXT:    v_cndmask_b32_e64 v1, v1, -1, vcc
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
-; GFX10-LABEL: uaddsat_i64_vs:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_add_co_u32 v0, vcc_lo, v0, s0
-; GFX10-NEXT:    v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
-; GFX10-NEXT:    v_cmp_gt_u64_e32 vcc_lo, s[0:1], v[0:1]
-; GFX10-NEXT:    v_cndmask_b32_e64 v0, v0, -1, vcc_lo
-; GFX10-NEXT:    v_cndmask_b32_e64 v1, v1, -1, vcc_lo
-; GFX10-NEXT:    ; return to shader part epilog
+; GFX10PLUS-LABEL: uaddsat_i64_vs:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    v_add_co_u32 v0, vcc_lo, v0, s0
+; GFX10PLUS-NEXT:    v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
+; GFX10PLUS-NEXT:    v_cmp_gt_u64_e32 vcc_lo, s[0:1], v[0:1]
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v0, v0, -1, vcc_lo
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v1, v1, -1, vcc_lo
+; GFX10PLUS-NEXT:    ; return to shader part epilog
   %result = call i64 @llvm.uadd.sat.i64(i64 %lhs, i64 %rhs)
   %cast = bitcast i64 %result to <2 x float>
   ret <2 x float> %cast
 }
 
 define <2 x i64> @v_uaddsat_v2i64(<2 x i64> %lhs, <2 x i64> %rhs) {
 ; GFX6-LABEL: v_uaddsat_v2i64:
 ; GFX6:       ; %bb.0:

 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v3, vcc_lo, v3, v7, vcc_lo
 ; GFX10-NEXT:    v_cmp_lt_u64_e32 vcc_lo, v[0:1], v[4:5]
 ; GFX10-NEXT:    v_cmp_lt_u64_e64 s4, v[2:3], v[6:7]
 ; GFX10-NEXT:    v_cndmask_b32_e64 v0, v0, -1, vcc_lo
 ; GFX10-NEXT:    v_cndmask_b32_e64 v1, v1, -1, vcc_lo
 ; GFX10-NEXT:    v_cndmask_b32_e64 v2, v2, -1, s4
 ; GFX10-NEXT:    v_cndmask_b32_e64 v3, v3, -1, s4
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_uaddsat_v2i64:
+; GFX11:       ; %bb.0:
+; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT:    v_add_co_u32 v0, vcc_lo, v0, v4
+; GFX11-NEXT:    v_add_co_ci_u32_e32 v1, vcc_lo, v1, v5, vcc_lo
+; GFX11-NEXT:    v_add_co_u32 v2, vcc_lo, v2, v6
+; GFX11-NEXT:    v_add_co_ci_u32_e32 v3, vcc_lo, v3, v7, vcc_lo
+; GFX11-NEXT:    v_cmp_lt_u64_e32 vcc_lo, v[0:1], v[4:5]
+; GFX11-NEXT:    v_cmp_lt_u64_e64 s0, v[2:3], v[6:7]
+; GFX11-NEXT:    v_cndmask_b32_e64 v0, v0, -1, vcc_lo
+; GFX11-NEXT:    v_cndmask_b32_e64 v1, v1, -1, vcc_lo
+; GFX11-NEXT:    v_cndmask_b32_e64 v2, v2, -1, s0
+; GFX11-NEXT:    v_cndmask_b32_e64 v3, v3, -1, s0
+; GFX11-NEXT:    s_setpc_b64 s[30:31]
   %result = call <2 x i64> @llvm.uadd.sat.v2i64(<2 x i64> %lhs, <2 x i64> %rhs)
   ret <2 x i64> %result
 }
 
 define amdgpu_ps <2 x i64> @s_uaddsat_v2i64(<2 x i64> inreg %lhs, <2 x i64> inreg %rhs) {
 ; GFX6-LABEL: s_uaddsat_v2i64:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_add_u32 s0, s0, s4

 ; GFX9-NEXT:    v_cndmask_b32_e64 v0, v4, -1, vcc
 ; GFX9-NEXT:    v_cndmask_b32_e64 v1, v5, -1, vcc
 ; GFX9-NEXT:    v_readfirstlane_b32 s0, v2
 ; GFX9-NEXT:    v_readfirstlane_b32 s1, v3
 ; GFX9-NEXT:    v_readfirstlane_b32 s2, v0
 ; GFX9-NEXT:    v_readfirstlane_b32 s3, v1
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
-; GFX10-LABEL: s_uaddsat_v2i64:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    s_add_u32 s0, s0, s4
-; GFX10-NEXT:    s_addc_u32 s1, s1, s5
-; GFX10-NEXT:    s_add_u32 s2, s2, s6
-; GFX10-NEXT:    s_addc_u32 s3, s3, s7
-; GFX10-NEXT:    v_cmp_lt_u64_e64 s4, s[0:1], s[4:5]
-; GFX10-NEXT:    v_cmp_lt_u64_e64 s5, s[2:3], s[6:7]
-; GFX10-NEXT:    v_cndmask_b32_e64 v0, s0, -1, s4
-; GFX10-NEXT:    v_cndmask_b32_e64 v1, s1, -1, s4
-; GFX10-NEXT:    v_cndmask_b32_e64 v2, s2, -1, s5
-; GFX10-NEXT:    v_cndmask_b32_e64 v3, s3, -1, s5
-; GFX10-NEXT:    v_readfirstlane_b32 s0, v0
-; GFX10-NEXT:    v_readfirstlane_b32 s1, v1
-; GFX10-NEXT:    v_readfirstlane_b32 s2, v2
-; GFX10-NEXT:    v_readfirstlane_b32 s3, v3
-; GFX10-NEXT:    ; return to shader part epilog
+; GFX10PLUS-LABEL: s_uaddsat_v2i64:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    s_add_u32 s0, s0, s4
+; GFX10PLUS-NEXT:    s_addc_u32 s1, s1, s5
+; GFX10PLUS-NEXT:    s_add_u32 s2, s2, s6
+; GFX10PLUS-NEXT:    s_addc_u32 s3, s3, s7
+; GFX10PLUS-NEXT:    v_cmp_lt_u64_e64 s4, s[0:1], s[4:5]
+; GFX10PLUS-NEXT:    v_cmp_lt_u64_e64 s5, s[2:3], s[6:7]
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v0, s0, -1, s4
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v1, s1, -1, s4
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v2, s2, -1, s5
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v3, s3, -1, s5
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s0, v0
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s1, v1
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s2, v2
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s3, v3
+; GFX10PLUS-NEXT:    ; return to shader part epilog
   %result = call <2 x i64> @llvm.uadd.sat.v2i64(<2 x i64> %lhs, <2 x i64> %rhs)
   ret <2 x i64> %result
 }
 
 define amdgpu_ps i128 @s_uaddsat_i128(i128 inreg %lhs, i128 inreg %rhs) {
 ; GFX6-LABEL: s_uaddsat_i128:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_add_u32 s0, s0, s4

 ; GFX9-NEXT:    v_cndmask_b32_e64 v2, v2, -1, vcc
 ; GFX9-NEXT:    v_cndmask_b32_e64 v3, v3, -1, vcc
 ; GFX9-NEXT:    v_readfirstlane_b32 s0, v0
 ; GFX9-NEXT:    v_readfirstlane_b32 s1, v1
 ; GFX9-NEXT:    v_readfirstlane_b32 s2, v2
 ; GFX9-NEXT:    v_readfirstlane_b32 s3, v3
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
-; GFX10-LABEL: s_uaddsat_i128:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    s_add_u32 s0, s0, s4
-; GFX10-NEXT:    s_addc_u32 s1, s1, s5
-; GFX10-NEXT:    s_addc_u32 s2, s2, s6
-; GFX10-NEXT:    v_cmp_lt_u64_e64 s4, s[0:1], s[4:5]
-; GFX10-NEXT:    s_addc_u32 s3, s3, s7
-; GFX10-NEXT:    s_cmp_eq_u64 s[2:3], s[6:7]
-; GFX10-NEXT:    s_cselect_b32 s8, 1, 0
-; GFX10-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s4
-; GFX10-NEXT:    v_cmp_lt_u64_e64 s4, s[2:3], s[6:7]
-; GFX10-NEXT:    v_cndmask_b32_e64 v1, 0, 1, s4
-; GFX10-NEXT:    s_and_b32 s4, 1, s8
-; GFX10-NEXT:    v_cmp_ne_u32_e64 vcc_lo, 0, s4
-; GFX10-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc_lo
-; GFX10-NEXT:    v_and_b32_e32 v0, 1, v0
-; GFX10-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v0
-; GFX10-NEXT:    v_cndmask_b32_e64 v0, s0, -1, vcc_lo
-; GFX10-NEXT:    v_cndmask_b32_e64 v1, s1, -1, vcc_lo
-; GFX10-NEXT:    v_cndmask_b32_e64 v2, s2, -1, vcc_lo
-; GFX10-NEXT:    v_cndmask_b32_e64 v3, s3, -1, vcc_lo
-; GFX10-NEXT:    v_readfirstlane_b32 s0, v0
-; GFX10-NEXT:    v_readfirstlane_b32 s1, v1
-; GFX10-NEXT:    v_readfirstlane_b32 s2, v2
-; GFX10-NEXT:    v_readfirstlane_b32 s3, v3
-; GFX10-NEXT:    ; return to shader part epilog
+; GFX10PLUS-LABEL: s_uaddsat_i128:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    s_add_u32 s0, s0, s4
+; GFX10PLUS-NEXT:    s_addc_u32 s1, s1, s5
+; GFX10PLUS-NEXT:    s_addc_u32 s2, s2, s6
+; GFX10PLUS-NEXT:    v_cmp_lt_u64_e64 s4, s[0:1], s[4:5]
+; GFX10PLUS-NEXT:    s_addc_u32 s3, s3, s7
+; GFX10PLUS-NEXT:    s_cmp_eq_u64 s[2:3], s[6:7]
+; GFX10PLUS-NEXT:    s_cselect_b32 s8, 1, 0
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s4
+; GFX10PLUS-NEXT:    v_cmp_lt_u64_e64 s4, s[2:3], s[6:7]
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v1, 0, 1, s4
+; GFX10PLUS-NEXT:    s_and_b32 s4, 1, s8
+; GFX10PLUS-NEXT:    v_cmp_ne_u32_e64 vcc_lo, 0, s4
+; GFX10PLUS-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc_lo
+; GFX10PLUS-NEXT:    v_and_b32_e32 v0, 1, v0
+; GFX10PLUS-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v0
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v0, s0, -1, vcc_lo
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v1, s1, -1, vcc_lo
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v2, s2, -1, vcc_lo
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v3, s3, -1, vcc_lo
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s0, v0
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s1, v1
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s2, v2
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s3, v3
+; GFX10PLUS-NEXT:    ; return to shader part epilog
   %result = call i128 @llvm.uadd.sat.i128(i128 %lhs, i128 %rhs)
   ret i128 %result
 }
 
 define amdgpu_ps <4 x float> @uaddsat_i128_sv(i128 inreg %lhs, i128 %rhs) {
 ; GFX6-LABEL: uaddsat_i128_sv:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    v_mov_b32_e32 v5, s1

 ; GFX9-NEXT:    v_and_b32_e32 v0, 1, v0
 ; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
 ; GFX9-NEXT:    v_cndmask_b32_e64 v0, v4, -1, vcc
 ; GFX9-NEXT:    v_cndmask_b32_e64 v1, v5, -1, vcc
 ; GFX9-NEXT:    v_cndmask_b32_e64 v2, v6, -1, vcc
 ; GFX9-NEXT:    v_cndmask_b32_e64 v3, v7, -1, vcc
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
-; GFX10-LABEL: uaddsat_i128_sv:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_add_co_u32 v4, vcc_lo, s0, v0
-; GFX10-NEXT:    v_add_co_ci_u32_e32 v5, vcc_lo, s1, v1, vcc_lo
-; GFX10-NEXT:    v_add_co_ci_u32_e32 v6, vcc_lo, s2, v2, vcc_lo
-; GFX10-NEXT:    v_add_co_ci_u32_e32 v7, vcc_lo, s3, v3, vcc_lo
-; GFX10-NEXT:    v_cmp_lt_u64_e32 vcc_lo, v[4:5], v[0:1]
-; GFX10-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX10-NEXT:    v_cmp_lt_u64_e32 vcc_lo, v[6:7], v[2:3]
-; GFX10-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc_lo
-; GFX10-NEXT:    v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[2:3]
-; GFX10-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc_lo
-; GFX10-NEXT:    v_and_b32_e32 v0, 1, v0
-; GFX10-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v0
-; GFX10-NEXT:    v_cndmask_b32_e64 v0, v4, -1, vcc_lo
-; GFX10-NEXT:    v_cndmask_b32_e64 v1, v5, -1, vcc_lo
-; GFX10-NEXT:    v_cndmask_b32_e64 v2, v6, -1, vcc_lo
-; GFX10-NEXT:    v_cndmask_b32_e64 v3, v7, -1, vcc_lo
-; GFX10-NEXT:    ; return to shader part epilog
+; GFX10PLUS-LABEL: uaddsat_i128_sv:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    v_add_co_u32 v4, vcc_lo, s0, v0
+; GFX10PLUS-NEXT:    v_add_co_ci_u32_e32 v5, vcc_lo, s1, v1, vcc_lo
+; GFX10PLUS-NEXT:    v_add_co_ci_u32_e32 v6, vcc_lo, s2, v2, vcc_lo
+; GFX10PLUS-NEXT:    v_add_co_ci_u32_e32 v7, vcc_lo, s3, v3, vcc_lo
+; GFX10PLUS-NEXT:    v_cmp_lt_u64_e32 vcc_lo, v[4:5], v[0:1]
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX10PLUS-NEXT:    v_cmp_lt_u64_e32 vcc_lo, v[6:7], v[2:3]
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; GFX10PLUS-NEXT:    v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[2:3]
+; GFX10PLUS-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc_lo
+; GFX10PLUS-NEXT:    v_and_b32_e32 v0, 1, v0
+; GFX10PLUS-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v0
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v0, v4, -1, vcc_lo
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v1, v5, -1, vcc_lo
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v2, v6, -1, vcc_lo
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v3, v7, -1, vcc_lo
+; GFX10PLUS-NEXT:    ; return to shader part epilog
   %result = call i128 @llvm.uadd.sat.i128(i128 %lhs, i128 %rhs)
   %cast = bitcast i128 %result to <4 x float>
   ret <4 x float> %cast
 }
 
 define amdgpu_ps <4 x float> @uaddsat_i128_vs(i128 %lhs, i128 inreg %rhs) {
 ; GFX6-LABEL: uaddsat_i128_vs:
 ; GFX6:       ; %bb.0:

 ; GFX9-NEXT:    v_and_b32_e32 v4, 1, v4
 ; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v4
 ; GFX9-NEXT:    v_cndmask_b32_e64 v0, v0, -1, vcc
 ; GFX9-NEXT:    v_cndmask_b32_e64 v1, v1, -1, vcc
 ; GFX9-NEXT:    v_cndmask_b32_e64 v2, v2, -1, vcc
 ; GFX9-NEXT:    v_cndmask_b32_e64 v3, v3, -1, vcc
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
-; GFX10-LABEL: uaddsat_i128_vs:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_add_co_u32 v0, vcc_lo, v0, s0
-; GFX10-NEXT:    v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
-; GFX10-NEXT:    v_add_co_ci_u32_e32 v2, vcc_lo, s2, v2, vcc_lo
-; GFX10-NEXT:    v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
-; GFX10-NEXT:    v_cmp_gt_u64_e32 vcc_lo, s[0:1], v[0:1]
-; GFX10-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc_lo
-; GFX10-NEXT:    v_cmp_gt_u64_e32 vcc_lo, s[2:3], v[2:3]
-; GFX10-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc_lo
-; GFX10-NEXT:    v_cmp_eq_u64_e32 vcc_lo, s[2:3], v[2:3]
-; GFX10-NEXT:    v_cndmask_b32_e32 v4, v5, v4, vcc_lo
-; GFX10-NEXT:    v_and_b32_e32 v4, 1, v4
-; GFX10-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v4
-; GFX10-NEXT:    v_cndmask_b32_e64 v0, v0, -1, vcc_lo
-; GFX10-NEXT:    v_cndmask_b32_e64 v1, v1, -1, vcc_lo
-; GFX10-NEXT:    v_cndmask_b32_e64 v2, v2, -1, vcc_lo
-; GFX10-NEXT:    v_cndmask_b32_e64 v3, v3, -1, vcc_lo
-; GFX10-NEXT:    ; return to shader part epilog
+; GFX10PLUS-LABEL: uaddsat_i128_vs:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    v_add_co_u32 v0, vcc_lo, v0, s0
+; GFX10PLUS-NEXT:    v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
+; GFX10PLUS-NEXT:    v_add_co_ci_u32_e32 v2, vcc_lo, s2, v2, vcc_lo
+; GFX10PLUS-NEXT:    v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
+; GFX10PLUS-NEXT:    v_cmp_gt_u64_e32 vcc_lo, s[0:1], v[0:1]
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc_lo
+; GFX10PLUS-NEXT:    v_cmp_gt_u64_e32 vcc_lo, s[2:3], v[2:3]
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc_lo
+; GFX10PLUS-NEXT:    v_cmp_eq_u64_e32 vcc_lo, s[2:3], v[2:3]
+; GFX10PLUS-NEXT:    v_cndmask_b32_e32 v4, v5, v4, vcc_lo
+; GFX10PLUS-NEXT:    v_and_b32_e32 v4, 1, v4
+; GFX10PLUS-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v4
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v0, v0, -1, vcc_lo
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v1, v1, -1, vcc_lo
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v2, v2, -1, vcc_lo
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v3, v3, -1, vcc_lo
+; GFX10PLUS-NEXT:    ; return to shader part epilog
   %result = call i128 @llvm.uadd.sat.i128(i128 %lhs, i128 %rhs)
   %cast = bitcast i128 %result to <4 x float>
   ret <4 x float> %cast
 }
 
 define <2 x i128> @v_uaddsat_v2i128(<2 x i128> %lhs, <2 x i128> %rhs) {
 ; GFX6-LABEL: v_uaddsat_v2i128:
 ; GFX6:       ; %bb.0:

 ; GFX10-NEXT:    v_cmp_ne_u32_e64 s4, 0, v9
 ; GFX10-NEXT:    v_cndmask_b32_e64 v2, v2, -1, vcc_lo
 ; GFX10-NEXT:    v_cndmask_b32_e64 v3, v3, -1, vcc_lo
 ; GFX10-NEXT:    v_cndmask_b32_e64 v4, v4, -1, s4
 ; GFX10-NEXT:    v_cndmask_b32_e64 v5, v5, -1, s4
 ; GFX10-NEXT:    v_cndmask_b32_e64 v6, v6, -1, s4
 ; GFX10-NEXT:    v_cndmask_b32_e64 v7, v7, -1, s4
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_uaddsat_v2i128:
+; GFX11:       ; %bb.0:
+; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT:    v_add_co_u32 v0, vcc_lo, v0, v8
+; GFX11-NEXT:    v_add_co_ci_u32_e32 v1, vcc_lo, v1, v9, vcc_lo
+; GFX11-NEXT:    v_add_co_ci_u32_e32 v2, vcc_lo, v2, v10, vcc_lo
+; GFX11-NEXT:    v_add_co_ci_u32_e32 v3, vcc_lo, v3, v11, vcc_lo
+; GFX11-NEXT:    v_cmp_lt_u64_e32 vcc_lo, v[0:1], v[8:9]
+; GFX11-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc_lo
+; GFX11-NEXT:    v_add_co_u32 v4, vcc_lo, v4, v12
+; GFX11-NEXT:    v_add_co_ci_u32_e32 v5, vcc_lo, v5, v13, vcc_lo
+; GFX11-NEXT:    v_add_co_ci_u32_e32 v6, vcc_lo, v6, v14, vcc_lo
+; GFX11-NEXT:    v_add_co_ci_u32_e32 v7, vcc_lo, v7, v15, vcc_lo
+; GFX11-NEXT:    v_cmp_lt_u64_e32 vcc_lo, v[2:3], v[10:11]
+; GFX11-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc_lo
+; GFX11-NEXT:    v_cmp_lt_u64_e32 vcc_lo, v[4:5], v[12:13]
+; GFX11-NEXT:    v_cndmask_b32_e64 v12, 0, 1, vcc_lo
+; GFX11-NEXT:    v_cmp_lt_u64_e32 vcc_lo, v[6:7], v[14:15]
+; GFX11-NEXT:    v_cndmask_b32_e64 v13, 0, 1, vcc_lo
+; GFX11-NEXT:    v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[10:11]
+; GFX11-NEXT:    v_cndmask_b32_e32 v8, v9, v8, vcc_lo
+; GFX11-NEXT:    v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[14:15]
+; GFX11-NEXT:    v_and_b32_e32 v8, 1, v8
+; GFX11-NEXT:    v_cndmask_b32_e32 v9, v13, v12, vcc_lo
+; GFX11-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v8
+; GFX11-NEXT:    v_and_b32_e32 v9, 1, v9
+; GFX11-NEXT:    v_cndmask_b32_e64 v0, v0, -1, vcc_lo
+; GFX11-NEXT:    v_cndmask_b32_e64 v1, v1, -1, vcc_lo
+; GFX11-NEXT:    v_cmp_ne_u32_e64 s0, 0, v9
+; GFX11-NEXT:    v_cndmask_b32_e64 v2, v2, -1, vcc_lo
+; GFX11-NEXT:    v_cndmask_b32_e64 v3, v3, -1, vcc_lo
+; GFX11-NEXT:    v_cndmask_b32_e64 v4, v4, -1, s0
+; GFX11-NEXT:    v_cndmask_b32_e64 v5, v5, -1, s0
+; GFX11-NEXT:    v_cndmask_b32_e64 v6, v6, -1, s0
+; GFX11-NEXT:    v_cndmask_b32_e64 v7, v7, -1, s0
+; GFX11-NEXT:    s_setpc_b64 s[30:31]
   %result = call <2 x i128> @llvm.uadd.sat.v2i128(<2 x i128> %lhs, <2 x i128> %rhs)
   ret <2 x i128> %result
 }
 
 define amdgpu_ps <2 x i128> @s_uaddsat_v2i128(<2 x i128> inreg %lhs, <2 x i128> inreg %rhs) {
 ; GFX6-LABEL: s_uaddsat_v2i128:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_add_u32 s0, s0, s8

 ; GFX9-NEXT:    v_readfirstlane_b32 s2, v6
 ; GFX9-NEXT:    v_readfirstlane_b32 s3, v7
 ; GFX9-NEXT:    v_readfirstlane_b32 s4, v0
 ; GFX9-NEXT:    v_readfirstlane_b32 s5, v1
 ; GFX9-NEXT:    v_readfirstlane_b32 s6, v2
 ; GFX9-NEXT:    v_readfirstlane_b32 s7, v3
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
-; GFX10-LABEL: s_uaddsat_v2i128:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    s_add_u32 s0, s0, s8
-; GFX10-NEXT:    s_addc_u32 s1, s1, s9
-; GFX10-NEXT:    s_addc_u32 s2, s2, s10
-; GFX10-NEXT:    v_cmp_lt_u64_e64 s8, s[0:1], s[8:9]
-; GFX10-NEXT:    s_addc_u32 s3, s3, s11
-; GFX10-NEXT:    s_cmp_eq_u64 s[2:3], s[10:11]
-; GFX10-NEXT:    s_cselect_b32 s16, 1, 0
-; GFX10-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s8
-; GFX10-NEXT:    v_cmp_lt_u64_e64 s8, s[2:3], s[10:11]
-; GFX10-NEXT:    v_cndmask_b32_e64 v1, 0, 1, s8
-; GFX10-NEXT:    s_and_b32 s8, 1, s16
-; GFX10-NEXT:    s_add_u32 s4, s4, s12
-; GFX10-NEXT:    s_addc_u32 s5, s5, s13
-; GFX10-NEXT:    v_cmp_ne_u32_e64 vcc_lo, 0, s8
-; GFX10-NEXT:    v_cmp_lt_u64_e64 s9, s[4:5], s[12:13]
-; GFX10-NEXT:    s_addc_u32 s6, s6, s14
-; GFX10-NEXT:    s_addc_u32 s7, s7, s15
-; GFX10-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc_lo
-; GFX10-NEXT:    s_cmp_eq_u64 s[6:7], s[14:15]
-; GFX10-NEXT:    v_cndmask_b32_e64 v1, 0, 1, s9
-; GFX10-NEXT:    v_cmp_lt_u64_e64 s9, s[6:7], s[14:15]
-; GFX10-NEXT:    s_cselect_b32 s8, 1, 0
-; GFX10-NEXT:    v_and_b32_e32 v0, 1, v0
-; GFX10-NEXT:    s_and_b32 s8, 1, s8
-; GFX10-NEXT:    v_cmp_ne_u32_e64 vcc_lo, 0, s8
-; GFX10-NEXT:    v_cndmask_b32_e64 v2, 0, 1, s9
-; GFX10-NEXT:    v_cndmask_b32_e32 v1, v2, v1, vcc_lo
-; GFX10-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v0
-; GFX10-NEXT:    v_and_b32_e32 v1, 1, v1
-; GFX10-NEXT:    v_cndmask_b32_e64 v0, s0, -1, vcc_lo
-; GFX10-NEXT:    v_cndmask_b32_e64 v2, s2, -1, vcc_lo
-; GFX10-NEXT:    v_cndmask_b32_e64 v3, s3, -1, vcc_lo
-; GFX10-NEXT:    v_cmp_ne_u32_e64 s0, 0, v1
-; GFX10-NEXT:    v_cndmask_b32_e64 v1, s1, -1, vcc_lo
-; GFX10-NEXT:    v_readfirstlane_b32 s2, v2
-; GFX10-NEXT:    v_readfirstlane_b32 s3, v3
-; GFX10-NEXT:    v_cndmask_b32_e64 v4, s4, -1, s0
-; GFX10-NEXT:    v_cndmask_b32_e64 v5, s5, -1, s0
-; GFX10-NEXT:    v_cndmask_b32_e64 v6, s6, -1, s0
-; GFX10-NEXT:    v_cndmask_b32_e64 v7, s7, -1, s0
-; GFX10-NEXT:    v_readfirstlane_b32 s0, v0
-; GFX10-NEXT:    v_readfirstlane_b32 s1, v1
-; GFX10-NEXT:    v_readfirstlane_b32 s4, v4
-; GFX10-NEXT:    v_readfirstlane_b32 s5, v5
-; GFX10-NEXT:    v_readfirstlane_b32 s6, v6
-; GFX10-NEXT:    v_readfirstlane_b32 s7, v7
-; GFX10-NEXT:    ; return to shader part epilog
+; GFX10PLUS-LABEL: s_uaddsat_v2i128:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    s_add_u32 s0, s0, s8
+; GFX10PLUS-NEXT:    s_addc_u32 s1, s1, s9
+; GFX10PLUS-NEXT:    s_addc_u32 s2, s2, s10
+; GFX10PLUS-NEXT:    v_cmp_lt_u64_e64 s8, s[0:1], s[8:9]
+; GFX10PLUS-NEXT:    s_addc_u32 s3, s3, s11
+; GFX10PLUS-NEXT:    s_cmp_eq_u64 s[2:3], s[10:11]
+; GFX10PLUS-NEXT:    s_cselect_b32 s16, 1, 0
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s8
+; GFX10PLUS-NEXT:    v_cmp_lt_u64_e64 s8, s[2:3], s[10:11]
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v1, 0, 1, s8
+; GFX10PLUS-NEXT:    s_and_b32 s8, 1, s16
+; GFX10PLUS-NEXT:    s_add_u32 s4, s4, s12
+; GFX10PLUS-NEXT:    s_addc_u32 s5, s5, s13
+; GFX10PLUS-NEXT:    v_cmp_ne_u32_e64 vcc_lo, 0, s8
+; GFX10PLUS-NEXT:    v_cmp_lt_u64_e64 s9, s[4:5], s[12:13]
+; GFX10PLUS-NEXT:    s_addc_u32 s6, s6, s14
+; GFX10PLUS-NEXT:    s_addc_u32 s7, s7, s15
+; GFX10PLUS-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc_lo
+; GFX10PLUS-NEXT:    s_cmp_eq_u64 s[6:7], s[14:15]
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v1, 0, 1, s9
+; GFX10PLUS-NEXT:    v_cmp_lt_u64_e64 s9, s[6:7], s[14:15]
+; GFX10PLUS-NEXT:    s_cselect_b32 s8, 1, 0
+; GFX10PLUS-NEXT:    v_and_b32_e32 v0, 1, v0
+; GFX10PLUS-NEXT:    s_and_b32 s8, 1, s8
+; GFX10PLUS-NEXT:    v_cmp_ne_u32_e64 vcc_lo, 0, s8
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v2, 0, 1, s9
+; GFX10PLUS-NEXT:    v_cndmask_b32_e32 v1, v2, v1, vcc_lo
+; GFX10PLUS-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v0
+; GFX10PLUS-NEXT:    v_and_b32_e32 v1, 1, v1
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v0, s0, -1, vcc_lo
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v2, s2, -1, vcc_lo
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v3, s3, -1, vcc_lo
+; GFX10PLUS-NEXT:    v_cmp_ne_u32_e64 s0, 0, v1
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v1, s1, -1, vcc_lo
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s2, v2
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s3, v3
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v4, s4, -1, s0
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v5, s5, -1, s0
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v6, s6, -1, s0
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v7, s7, -1, s0
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s0, v0
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s1, v1
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s4, v4
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s5, v5
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s6, v6
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s7, v7
+; GFX10PLUS-NEXT:    ; return to shader part epilog
   %result = call <2 x i128> @llvm.uadd.sat.v2i128(<2 x i128> %lhs, <2 x i128> %rhs)
   ret <2 x i128> %result
 }
 
 declare i7 @llvm.uadd.sat.i7(i7, i7) #0
 declare i8 @llvm.uadd.sat.i8(i8, i8) #0
 declare <2 x i8> @llvm.uadd.sat.v2i8(<2 x i8>, <2 x i8>) #0
 declare <4 x i8> @llvm.uadd.sat.v4i8(<4 x i8>, <4 x i8>) #0

llvm/test/CodeGen/AMDGPU/GlobalISel/usubsat.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=tahiti -o - %s | FileCheck -check-prefix=GFX6 %s
 ; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=fiji -o - %s | FileCheck -check-prefix=GFX8 %s
 ; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 -o - %s | FileCheck -check-prefix=GFX9 %s
-; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx1010 -o - %s | FileCheck -check-prefix=GFX10 %s
+; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx1010 -o - %s | FileCheck -check-prefixes=GFX10PLUS,GFX10 %s
+; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx1100 -o - %s | FileCheck -check-prefixes=GFX10PLUS,GFX11 %s
 
 define i7 @v_usubsat_i7(i7 %lhs, i7 %rhs) {
 ; GFX6-LABEL: v_usubsat_i7:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX6-NEXT:    v_lshlrev_b32_e32 v0, 25, v0
 ; GFX6-NEXT:    v_lshlrev_b32_e32 v1, 25, v1
 ; GFX6-NEXT:    v_min_u32_e32 v1, v0, v1

 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    v_lshlrev_b16_e32 v0, 9, v0
 ; GFX9-NEXT:    v_lshlrev_b16_e32 v1, 9, v1
 ; GFX9-NEXT:    v_sub_u16_e64 v0, v0, v1 clamp
 ; GFX9-NEXT:    v_lshrrev_b16_e32 v0, 9, v0
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX10-LABEL: v_usubsat_i7:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_lshlrev_b16 v0, 9, v0
-; GFX10-NEXT:    v_lshlrev_b16 v1, 9, v1
-; GFX10-NEXT:    v_sub_nc_u16 v0, v0, v1 clamp
-; GFX10-NEXT:    v_lshrrev_b16 v0, 9, v0
-; GFX10-NEXT:    s_setpc_b64 s[30:31]
+; GFX10PLUS-LABEL: v_usubsat_i7:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX10PLUS-NEXT:    v_lshlrev_b16 v0, 9, v0
+; GFX10PLUS-NEXT:    v_lshlrev_b16 v1, 9, v1
+; GFX10PLUS-NEXT:    v_sub_nc_u16 v0, v0, v1 clamp
+; GFX10PLUS-NEXT:    v_lshrrev_b16 v0, 9, v0
+; GFX10PLUS-NEXT:    s_setpc_b64 s[30:31]
   %result = call i7 @llvm.usub.sat.i7(i7 %lhs, i7 %rhs)
   ret i7 %result
 }
 
 define amdgpu_ps i7 @s_usubsat_i7(i7 inreg %lhs, i7 inreg %rhs) {
 ; GFX6-LABEL: s_usubsat_i7:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_lshl_b32 s0, s0, 25

 ; GFX9-NEXT:    s_lshl_b32 s1, s1, s2
 ; GFX9-NEXT:    s_lshl_b32 s0, s0, s2
 ; GFX9-NEXT:    v_mov_b32_e32 v0, s1
 ; GFX9-NEXT:    v_sub_u16_e64 v0, s0, v0 clamp
 ; GFX9-NEXT:    v_lshrrev_b16_e32 v0, 9, v0
 ; GFX9-NEXT:    v_readfirstlane_b32 s0, v0
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
-; GFX10-LABEL: s_usubsat_i7:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    s_bfe_u32 s2, 9, 0x100000
-; GFX10-NEXT:    s_lshl_b32 s0, s0, s2
-; GFX10-NEXT:    s_lshl_b32 s1, s1, s2
-; GFX10-NEXT:    v_sub_nc_u16 v0, s0, s1 clamp
-; GFX10-NEXT:    v_lshrrev_b16 v0, 9, v0
-; GFX10-NEXT:    v_readfirstlane_b32 s0, v0
-; GFX10-NEXT:    ; return to shader part epilog
+; GFX10PLUS-LABEL: s_usubsat_i7:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    s_bfe_u32 s2, 9, 0x100000
+; GFX10PLUS-NEXT:    s_lshl_b32 s0, s0, s2
+; GFX10PLUS-NEXT:    s_lshl_b32 s1, s1, s2
+; GFX10PLUS-NEXT:    v_sub_nc_u16 v0, s0, s1 clamp
+; GFX10PLUS-NEXT:    v_lshrrev_b16 v0, 9, v0
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s0, v0
+; GFX10PLUS-NEXT:    ; return to shader part epilog
   %result = call i7 @llvm.usub.sat.i7(i7 %lhs, i7 %rhs)
   ret i7 %result
 }
 
 define i8 @v_usubsat_i8(i8 %lhs, i8 %rhs) {
 ; GFX6-LABEL: v_usubsat_i8:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    v_lshlrev_b16_e32 v0, 8, v0
 ; GFX9-NEXT:    v_lshlrev_b16_e32 v1, 8, v1
 ; GFX9-NEXT:    v_sub_u16_e64 v0, v0, v1 clamp
 ; GFX9-NEXT:    v_lshrrev_b16_e32 v0, 8, v0
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX10-LABEL: v_usubsat_i8:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_lshlrev_b16 v0, 8, v0
-; GFX10-NEXT:    v_lshlrev_b16 v1, 8, v1
-; GFX10-NEXT:    v_sub_nc_u16 v0, v0, v1 clamp
-; GFX10-NEXT:    v_lshrrev_b16 v0, 8, v0
-; GFX10-NEXT:    s_setpc_b64 s[30:31]
+; GFX10PLUS-LABEL: v_usubsat_i8:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX10PLUS-NEXT:    v_lshlrev_b16 v0, 8, v0
+; GFX10PLUS-NEXT:    v_lshlrev_b16 v1, 8, v1
+; GFX10PLUS-NEXT:    v_sub_nc_u16 v0, v0, v1 clamp
+; GFX10PLUS-NEXT:    v_lshrrev_b16 v0, 8, v0
+; GFX10PLUS-NEXT:    s_setpc_b64 s[30:31]
   %result = call i8 @llvm.usub.sat.i8(i8 %lhs, i8 %rhs)
   ret i8 %result
 }
 
 define amdgpu_ps i8 @s_usubsat_i8(i8 inreg %lhs, i8 inreg %rhs) {
 ; GFX6-LABEL: s_usubsat_i8:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_lshl_b32 s0, s0, 24

 ; GFX9-NEXT:    s_lshl_b32 s1, s1, s2
 ; GFX9-NEXT:    s_lshl_b32 s0, s0, s2
 ; GFX9-NEXT:    v_mov_b32_e32 v0, s1
 ; GFX9-NEXT:    v_sub_u16_e64 v0, s0, v0 clamp
 ; GFX9-NEXT:    v_lshrrev_b16_e32 v0, 8, v0
 ; GFX9-NEXT:    v_readfirstlane_b32 s0, v0
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
-; GFX10-LABEL: s_usubsat_i8:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    s_bfe_u32 s2, 8, 0x100000
-; GFX10-NEXT:    s_lshl_b32 s0, s0, s2
-; GFX10-NEXT:    s_lshl_b32 s1, s1, s2
-; GFX10-NEXT:    v_sub_nc_u16 v0, s0, s1 clamp
-; GFX10-NEXT:    v_lshrrev_b16 v0, 8, v0
-; GFX10-NEXT:    v_readfirstlane_b32 s0, v0
-; GFX10-NEXT:    ; return to shader part epilog
+; GFX10PLUS-LABEL: s_usubsat_i8:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    s_bfe_u32 s2, 8, 0x100000
+; GFX10PLUS-NEXT:    s_lshl_b32 s0, s0, s2
+; GFX10PLUS-NEXT:    s_lshl_b32 s1, s1, s2
+; GFX10PLUS-NEXT:    v_sub_nc_u16 v0, s0, s1 clamp
+; GFX10PLUS-NEXT:    v_lshrrev_b16 v0, 8, v0
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s0, v0
+; GFX10PLUS-NEXT:    ; return to shader part epilog
   %result = call i8 @llvm.usub.sat.i8(i8 %lhs, i8 %rhs)
   ret i8 %result
 }
 
 define i16 @v_usubsat_v2i8(i16 %lhs.arg, i16 %rhs.arg) {
 ; GFX6-LABEL: v_usubsat_v2i8:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

 ; GFX10-NEXT:    v_and_or_b32 v1, 0xffff, v1, v3
 ; GFX10-NEXT:    v_pk_lshlrev_b16 v0, 8, v0 op_sel_hi:[0,1]
 ; GFX10-NEXT:    v_pk_lshlrev_b16 v1, 8, v1 op_sel_hi:[0,1]
 ; GFX10-NEXT:    v_pk_sub_u16 v0, v0, v1 clamp
 ; GFX10-NEXT:    v_pk_lshrrev_b16 v0, 8, v0 op_sel_hi:[0,1]
 ; GFX10-NEXT:    v_and_b32_sdwa v1, v0, s4 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
 ; GFX10-NEXT:    v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_usubsat_v2i8:
+; GFX11:       ; %bb.0:
+; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT:    v_lshrrev_b32_e32 v2, 8, v0
+; GFX11-NEXT:    v_lshrrev_b32_e32 v3, 8, v1
+; GFX11-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-NEXT:    v_and_or_b32 v0, 0xffff, v0, v2
+; GFX11-NEXT:    v_and_or_b32 v1, 0xffff, v1, v3
+; GFX11-NEXT:    v_pk_lshlrev_b16 v0, 8, v0 op_sel_hi:[0,1]
+; GFX11-NEXT:    v_pk_lshlrev_b16 v1, 8, v1 op_sel_hi:[0,1]
+; GFX11-NEXT:    v_pk_sub_u16 v0, v0, v1 clamp
+; GFX11-NEXT:    v_pk_lshrrev_b16 v0, 8, v0 op_sel_hi:[0,1]
+; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; GFX11-NEXT:    v_lshlrev_b16 v1, 8, v1
+; GFX11-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-NEXT:    s_setpc_b64 s[30:31]
   %lhs = bitcast i16 %lhs.arg to <2 x i8>
   %rhs = bitcast i16 %rhs.arg to <2 x i8>
   %result = call <2 x i8> @llvm.usub.sat.v2i8(<2 x i8> %lhs, <2 x i8> %rhs)
   %cast.result = bitcast <2 x i8> %result to i16
   ret i16 %cast.result
 }
 
 define amdgpu_ps i16 @s_usubsat_v2i8(i16 inreg %lhs.arg, i16 inreg %rhs.arg) {

 ; GFX10-NEXT:    s_pack_ll_b32_b16 s1, s1, s3
 ; GFX10-NEXT:    v_pk_sub_u16 v0, s0, s1 clamp
 ; GFX10-NEXT:    s_movk_i32 s0, 0xff
 ; GFX10-NEXT:    v_pk_lshrrev_b16 v0, 8, v0 op_sel_hi:[0,1]
 ; GFX10-NEXT:    v_and_b32_sdwa v1, v0, s0 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
 ; GFX10-NEXT:    v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
 ; GFX10-NEXT:    v_readfirstlane_b32 s0, v0
 ; GFX10-NEXT:    ; return to shader part epilog
+;
+; GFX11-LABEL: s_usubsat_v2i8:
+; GFX11:       ; %bb.0:
+; GFX11-NEXT:    s_lshr_b32 s2, s0, 8
+; GFX11-NEXT:    s_lshr_b32 s3, s1, 8
+; GFX11-NEXT:    s_pack_ll_b32_b16 s0, s0, s2
+; GFX11-NEXT:    s_pack_ll_b32_b16 s1, s1, s3
+; GFX11-NEXT:    s_lshr_b32 s2, s0, 16
+; GFX11-NEXT:    s_lshr_b32 s3, s1, 16
+; GFX11-NEXT:    s_lshl_b32 s0, s0, 0x80008
+; GFX11-NEXT:    s_lshl_b32 s2, s2, 8
+; GFX11-NEXT:    s_lshl_b32 s1, s1, 0x80008
+; GFX11-NEXT:    s_lshl_b32 s3, s3, 8
+; GFX11-NEXT:    s_pack_ll_b32_b16 s0, s0, s2
+; GFX11-NEXT:    s_pack_ll_b32_b16 s1, s1, s3
+; GFX11-NEXT:    v_pk_sub_u16 v0, s0, s1 clamp
+; GFX11-NEXT:    v_pk_lshrrev_b16 v0, 8, v0 op_sel_hi:[0,1]
+; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; GFX11-NEXT:    v_lshlrev_b16 v1, 8, v1
+; GFX11-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-NEXT:    v_readfirstlane_b32 s0, v0
+; GFX11-NEXT:    ; return to shader part epilog
   %lhs = bitcast i16 %lhs.arg to <2 x i8>
   %rhs = bitcast i16 %rhs.arg to <2 x i8>
   %result = call <2 x i8> @llvm.usub.sat.v2i8(<2 x i8> %lhs, <2 x i8> %rhs)
   %cast.result = bitcast <2 x i8> %result to i16
   ret i16 %cast.result
 }
 
 define i32 @v_usubsat_v4i8(i32 %lhs.arg, i32 %rhs.arg) {

 ; GFX10-NEXT:    v_pk_lshrrev_b16 v1, 8, v1 op_sel_hi:[0,1]
 ; GFX10-NEXT:    v_lshlrev_b32_sdwa v2, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
 ; GFX10-NEXT:    v_and_b32_e32 v3, 0xff, v1
 ; GFX10-NEXT:    v_lshlrev_b32_sdwa v1, v4, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
 ; GFX10-NEXT:    v_and_or_b32 v0, v0, 0xff, v2
 ; GFX10-NEXT:    v_lshlrev_b32_e32 v2, 16, v3
 ; GFX10-NEXT:    v_or3_b32 v0, v0, v2, v1
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_usubsat_v4i8:
+; GFX11:       ; %bb.0:
+; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT:    v_lshrrev_b32_e32 v2, 8, v0
+; GFX11-NEXT:    v_lshrrev_b32_e32 v3, 8, v1
+; GFX11-NEXT:    v_lshrrev_b32_e32 v5, 24, v0
+; GFX11-NEXT:    v_lshrrev_b32_e32 v6, 24, v1
+; GFX11-NEXT:    v_lshrrev_b32_e32 v4, 16, v0
+; GFX11-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-NEXT:    v_lshrrev_b32_e32 v7, 16, v1
+; GFX11-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
+; GFX11-NEXT:    v_and_or_b32 v0, 0xffff, v0, v2
+; GFX11-NEXT:    v_and_or_b32 v1, 0xffff, v1, v3
+; GFX11-NEXT:    v_and_or_b32 v2, 0xffff, v4, v5
+; GFX11-NEXT:    v_and_or_b32 v3, 0xffff, v7, v6
+; GFX11-NEXT:    v_pk_lshlrev_b16 v0, 8, v0 op_sel_hi:[0,1]
+; GFX11-NEXT:    v_pk_lshlrev_b16 v1, 8, v1 op_sel_hi:[0,1]
+; GFX11-NEXT:    v_pk_lshlrev_b16 v2, 8, v2 op_sel_hi:[0,1]
+; GFX11-NEXT:    v_pk_lshlrev_b16 v3, 8, v3 op_sel_hi:[0,1]
+; GFX11-NEXT:    v_pk_sub_u16 v0, v0, v1 clamp
+; GFX11-NEXT:    v_pk_sub_u16 v1, v2, v3 clamp
+; GFX11-NEXT:    v_pk_lshrrev_b16 v0, 8, v0 op_sel_hi:[0,1]
+; GFX11-NEXT:    v_pk_lshrrev_b16 v1, 8, v1 op_sel_hi:[0,1]
+; GFX11-NEXT:    v_bfe_u32 v2, v0, 16, 8
+; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v1
+; GFX11-NEXT:    v_bfe_u32 v1, v1, 16, 8
+; GFX11-NEXT:    v_lshlrev_b32_e32 v2, 8, v2
+; GFX11-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-NEXT:    v_lshlrev_b32_e32 v1, 24, v1
+; GFX11-NEXT:    v_and_or_b32 v0, v0, 0xff, v2
+; GFX11-NEXT:    v_or3_b32 v0, v0, v3, v1
+; GFX11-NEXT:    s_setpc_b64 s[30:31]
   %lhs = bitcast i32 %lhs.arg to <4 x i8>
   %rhs = bitcast i32 %rhs.arg to <4 x i8>
   %result = call <4 x i8> @llvm.usub.sat.v4i8(<4 x i8> %lhs, <4 x i8> %rhs)
   %cast.result = bitcast <4 x i8> %result to i32
   ret i32 %cast.result
 }
 
 define amdgpu_ps i32 @s_usubsat_v4i8(i32 inreg %lhs.arg, i32 inreg %rhs.arg) {

 ; GFX10-NEXT:    v_and_b32_e32 v3, 0xff, v1
 ; GFX10-NEXT:    s_mov_b32 s0, 24
 ; GFX10-NEXT:    v_lshlrev_b32_sdwa v1, s0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
 ; GFX10-NEXT:    v_and_or_b32 v0, v0, 0xff, v2
 ; GFX10-NEXT:    v_lshlrev_b32_e32 v2, 16, v3
 ; GFX10-NEXT:    v_or3_b32 v0, v0, v2, v1
 ; GFX10-NEXT:    v_readfirstlane_b32 s0, v0
 ; GFX10-NEXT:    ; return to shader part epilog
+;
+; GFX11-LABEL: s_usubsat_v4i8:
+; GFX11:       ; %bb.0:
+; GFX11-NEXT:    s_lshr_b32 s2, s0, 8
+; GFX11-NEXT:    s_lshr_b32 s4, s1, 8
+; GFX11-NEXT:    s_pack_ll_b32_b16 s2, s0, s2
+; GFX11-NEXT:    s_pack_ll_b32_b16 s4, s1, s4
+; GFX11-NEXT:    s_lshr_b32 s6, s2, 16
+; GFX11-NEXT:    s_lshl_b32 s2, s2, 0x80008
+; GFX11-NEXT:    s_lshl_b32 s6, s6, 8
+; GFX11-NEXT:    s_lshr_b32 s3, s0, 24
+; GFX11-NEXT:    s_pack_ll_b32_b16 s2, s2, s6
+; GFX11-NEXT:    s_lshr_b32 s6, s4, 16
+; GFX11-NEXT:    s_lshr_b32 s5, s1, 24
+; GFX11-NEXT:    s_lshl_b32 s4, s4, 0x80008
+; GFX11-NEXT:    s_lshl_b32 s6, s6, 8
+; GFX11-NEXT:    s_pack_hl_b32_b16 s0, s0, s3
+; GFX11-NEXT:    s_pack_hl_b32_b16 s1, s1, s5
+; GFX11-NEXT:    s_pack_ll_b32_b16 s4, s4, s6
+; GFX11-NEXT:    s_lshr_b32 s3, s0, 16
+; GFX11-NEXT:    s_lshr_b32 s5, s1, 16
+; GFX11-NEXT:    v_pk_sub_u16 v0, s2, s4 clamp
+; GFX11-NEXT:    s_lshl_b32 s0, s0, 0x80008
+; GFX11-NEXT:    s_lshl_b32 s3, s3, 8
+; GFX11-NEXT:    s_lshl_b32 s1, s1, 0x80008
+; GFX11-NEXT:    s_lshl_b32 s2, s5, 8
+; GFX11-NEXT:    s_pack_ll_b32_b16 s0, s0, s3
+; GFX11-NEXT:    s_pack_ll_b32_b16 s1, s1, s2
+; GFX11-NEXT:    v_pk_lshrrev_b16 v0, 8, v0 op_sel_hi:[0,1]
+; GFX11-NEXT:    v_pk_sub_u16 v1, s0, s1 clamp
+; GFX11-NEXT:    v_bfe_u32 v2, v0, 16, 8
+; GFX11-NEXT:    v_pk_lshrrev_b16 v1, 8, v1 op_sel_hi:[0,1]
+; GFX11-NEXT:    v_lshlrev_b32_e32 v2, 8, v2
+; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v1
+; GFX11-NEXT:    v_bfe_u32 v1, v1, 16, 8
+; GFX11-NEXT:    v_and_or_b32 v0, v0, 0xff, v2
+; GFX11-NEXT:    v_lshlrev_b32_e32 v2, 16, v3
+; GFX11-NEXT:    v_lshlrev_b32_e32 v1, 24, v1
+; GFX11-NEXT:    v_or3_b32 v0, v0, v2, v1
+; GFX11-NEXT:    v_readfirstlane_b32 s0, v0
+; GFX11-NEXT:    ; return to shader part epilog
   %lhs = bitcast i32 %lhs.arg to <4 x i8>
   %rhs = bitcast i32 %rhs.arg to <4 x i8>
   %result = call <4 x i8> @llvm.usub.sat.v4i8(<4 x i8> %lhs, <4 x i8> %rhs)
   %cast.result = bitcast <4 x i8> %result to i32
   ret i32 %cast.result
 }
 
 define i24 @v_usubsat_i24(i24 %lhs, i24 %rhs) {

 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    v_lshlrev_b32_e32 v0, 8, v0
 ; GFX9-NEXT:    v_lshlrev_b32_e32 v1, 8, v1
 ; GFX9-NEXT:    v_sub_u32_e64 v0, v0, v1 clamp
 ; GFX9-NEXT:    v_lshrrev_b32_e32 v0, 8, v0
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX10-LABEL: v_usubsat_i24:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_lshlrev_b32_e32 v0, 8, v0
-; GFX10-NEXT:    v_lshlrev_b32_e32 v1, 8, v1
-; GFX10-NEXT:    v_sub_nc_u32_e64 v0, v0, v1 clamp
-; GFX10-NEXT:    v_lshrrev_b32_e32 v0, 8, v0
-; GFX10-NEXT:    s_setpc_b64 s[30:31]
+; GFX10PLUS-LABEL: v_usubsat_i24:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX10PLUS-NEXT:    v_lshlrev_b32_e32 v0, 8, v0
+; GFX10PLUS-NEXT:    v_lshlrev_b32_e32 v1, 8, v1
+; GFX10PLUS-NEXT:    v_sub_nc_u32_e64 v0, v0, v1 clamp
+; GFX10PLUS-NEXT:    v_lshrrev_b32_e32 v0, 8, v0
+; GFX10PLUS-NEXT:    s_setpc_b64 s[30:31]
   %result = call i24 @llvm.usub.sat.i24(i24 %lhs, i24 %rhs)
   ret i24 %result
 }
 
 define amdgpu_ps i24 @s_usubsat_i24(i24 inreg %lhs, i24 inreg %rhs) {
 ; GFX6-LABEL: s_usubsat_i24:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_lshl_b32 s0, s0, 8

 ; GFX9-NEXT:    s_lshl_b32 s1, s1, 8
 ; GFX9-NEXT:    s_lshl_b32 s0, s0, 8
 ; GFX9-NEXT:    v_mov_b32_e32 v0, s1
 ; GFX9-NEXT:    v_sub_u32_e64 v0, s0, v0 clamp
 ; GFX9-NEXT:    v_lshrrev_b32_e32 v0, 8, v0
 ; GFX9-NEXT:    v_readfirstlane_b32 s0, v0
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
-; GFX10-LABEL: s_usubsat_i24:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    s_lshl_b32 s0, s0, 8
-; GFX10-NEXT:    s_lshl_b32 s1, s1, 8
-; GFX10-NEXT:    v_sub_nc_u32_e64 v0, s0, s1 clamp
-; GFX10-NEXT:    v_lshrrev_b32_e32 v0, 8, v0
-; GFX10-NEXT:    v_readfirstlane_b32 s0, v0
-; GFX10-NEXT:    ; return to shader part epilog
+; GFX10PLUS-LABEL: s_usubsat_i24:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    s_lshl_b32 s0, s0, 8
+; GFX10PLUS-NEXT:    s_lshl_b32 s1, s1, 8
+; GFX10PLUS-NEXT:    v_sub_nc_u32_e64 v0, s0, s1 clamp
+; GFX10PLUS-NEXT:    v_lshrrev_b32_e32 v0, 8, v0
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s0, v0
+; GFX10PLUS-NEXT:    ; return to shader part epilog
   %result = call i24 @llvm.usub.sat.i24(i24 %lhs, i24 %rhs)
   ret i24 %result
 }
 
 define i32 @v_usubsat_i32(i32 %lhs, i32 %rhs) {
 ; GFX6-LABEL: v_usubsat_i32:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX6-NEXT:    v_min_u32_e32 v1, v0, v1
 ; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, v0, v1
 ; GFX6-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX8-LABEL: v_usubsat_i32:
 ; GFX8:       ; %bb.0:
 ; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX8-NEXT:    v_sub_u32_e64 v0, s[4:5], v0, v1 clamp
 ; GFX8-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX9-LABEL: v_usubsat_i32:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    v_sub_u32_e64 v0, v0, v1 clamp
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX10-LABEL: v_usubsat_i32:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_sub_nc_u32_e64 v0, v0, v1 clamp
-; GFX10-NEXT:    s_setpc_b64 s[30:31]
+; GFX10PLUS-LABEL: v_usubsat_i32:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX10PLUS-NEXT:    v_sub_nc_u32_e64 v0, v0, v1 clamp
+; GFX10PLUS-NEXT:    s_setpc_b64 s[30:31]
   %result = call i32 @llvm.usub.sat.i32(i32 %lhs, i32 %rhs)
   ret i32 %result
 }
 
 define amdgpu_ps i32 @s_usubsat_i32(i32 inreg %lhs, i32 inreg %rhs) {
 ; GFX6-LABEL: s_usubsat_i32:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_min_u32 s1, s0, s1

 ;
 ; GFX9-LABEL: s_usubsat_i32:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    v_mov_b32_e32 v0, s1
 ; GFX9-NEXT:    v_sub_u32_e64 v0, s0, v0 clamp
 ; GFX9-NEXT:    v_readfirstlane_b32 s0, v0
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
-; GFX10-LABEL: s_usubsat_i32:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_sub_nc_u32_e64 v0, s0, s1 clamp
-; GFX10-NEXT:    v_readfirstlane_b32 s0, v0
-; GFX10-NEXT:    ; return to shader part epilog
+; GFX10PLUS-LABEL: s_usubsat_i32:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    v_sub_nc_u32_e64 v0, s0, s1 clamp
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s0, v0
+; GFX10PLUS-NEXT:    ; return to shader part epilog
   %result = call i32 @llvm.usub.sat.i32(i32 %lhs, i32 %rhs)
   ret i32 %result
 }
 
 define amdgpu_ps float @usubsat_i32_sv(i32 inreg %lhs, i32 %rhs) {
 ; GFX6-LABEL: usubsat_i32_sv:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    v_min_u32_e32 v0, s0, v0
 ; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, s0, v0
 ; GFX6-NEXT:    ; return to shader part epilog
 ;
 ; GFX8-LABEL: usubsat_i32_sv:
 ; GFX8:       ; %bb.0:
 ; GFX8-NEXT:    v_sub_u32_e64 v0, s[0:1], s0, v0 clamp
 ; GFX8-NEXT:    ; return to shader part epilog
 ;
 ; GFX9-LABEL: usubsat_i32_sv:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    v_sub_u32_e64 v0, s0, v0 clamp
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
-; GFX10-LABEL: usubsat_i32_sv:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_sub_nc_u32_e64 v0, s0, v0 clamp
-; GFX10-NEXT:    ; return to shader part epilog
+; GFX10PLUS-LABEL: usubsat_i32_sv:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    v_sub_nc_u32_e64 v0, s0, v0 clamp
+; GFX10PLUS-NEXT:    ; return to shader part epilog
   %result = call i32 @llvm.usub.sat.i32(i32 %lhs, i32 %rhs)
   %cast = bitcast i32 %result to float
   ret float %cast
 }
 
 define amdgpu_ps float @usubsat_i32_vs(i32 %lhs, i32 inreg %rhs) {
 ; GFX6-LABEL: usubsat_i32_vs:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    v_min_u32_e32 v1, s0, v0
 ; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, v0, v1
 ; GFX6-NEXT:    ; return to shader part epilog
 ;
 ; GFX8-LABEL: usubsat_i32_vs:
 ; GFX8:       ; %bb.0:
 ; GFX8-NEXT:    v_sub_u32_e64 v0, s[0:1], v0, s0 clamp
 ; GFX8-NEXT:    ; return to shader part epilog
 ;
 ; GFX9-LABEL: usubsat_i32_vs:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    v_sub_u32_e64 v0, v0, s0 clamp
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
-; GFX10-LABEL: usubsat_i32_vs:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_sub_nc_u32_e64 v0, v0, s0 clamp
-; GFX10-NEXT:    ; return to shader part epilog
+; GFX10PLUS-LABEL: usubsat_i32_vs:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    v_sub_nc_u32_e64 v0, v0, s0 clamp
+; GFX10PLUS-NEXT:    ; return to shader part epilog
   %result = call i32 @llvm.usub.sat.i32(i32 %lhs, i32 %rhs)
   %cast = bitcast i32 %result to float
   ret float %cast
 }
 
 define <2 x i32> @v_usubsat_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) {
 ; GFX6-LABEL: v_usubsat_v2i32:
 ; GFX6:       ; %bb.0:

 ;
 ; GFX9-LABEL: v_usubsat_v2i32:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    v_sub_u32_e64 v0, v0, v2 clamp
 ; GFX9-NEXT:    v_sub_u32_e64 v1, v1, v3 clamp
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX10-LABEL: v_usubsat_v2i32:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_sub_nc_u32_e64 v0, v0, v2 clamp
-; GFX10-NEXT:    v_sub_nc_u32_e64 v1, v1, v3 clamp
-; GFX10-NEXT:    s_setpc_b64 s[30:31]
+; GFX10PLUS-LABEL: v_usubsat_v2i32:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX10PLUS-NEXT:    v_sub_nc_u32_e64 v0, v0, v2 clamp
+; GFX10PLUS-NEXT:    v_sub_nc_u32_e64 v1, v1, v3 clamp
+; GFX10PLUS-NEXT:    s_setpc_b64 s[30:31]
   %result = call <2 x i32> @llvm.usub.sat.v2i32(<2 x i32> %lhs, <2 x i32> %rhs)
   ret <2 x i32> %result
 }
 
 define amdgpu_ps <2 x i32> @s_usubsat_v2i32(<2 x i32> inreg %lhs, <2 x i32> inreg %rhs) {
 ; GFX6-LABEL: s_usubsat_v2i32:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_min_u32 s2, s0, s2

 ; GFX9-NEXT:    v_mov_b32_e32 v0, s2
 ; GFX9-NEXT:    v_mov_b32_e32 v1, s3
 ; GFX9-NEXT:    v_sub_u32_e64 v0, s0, v0 clamp
 ; GFX9-NEXT:    v_sub_u32_e64 v1, s1, v1 clamp
 ; GFX9-NEXT:    v_readfirstlane_b32 s0, v0
 ; GFX9-NEXT:    v_readfirstlane_b32 s1, v1
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
-; GFX10-LABEL: s_usubsat_v2i32:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_sub_nc_u32_e64 v0, s0, s2 clamp
-; GFX10-NEXT:    v_sub_nc_u32_e64 v1, s1, s3 clamp
-; GFX10-NEXT:    v_readfirstlane_b32 s0, v0
-; GFX10-NEXT:    v_readfirstlane_b32 s1, v1
-; GFX10-NEXT:    ; return to shader part epilog
+; GFX10PLUS-LABEL: s_usubsat_v2i32:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    v_sub_nc_u32_e64 v0, s0, s2 clamp
+; GFX10PLUS-NEXT:    v_sub_nc_u32_e64 v1, s1, s3 clamp
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s0, v0
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s1, v1
+; GFX10PLUS-NEXT:    ; return to shader part epilog
   %result = call <2 x i32> @llvm.usub.sat.v2i32(<2 x i32> %lhs, <2 x i32> %rhs)
   ret <2 x i32> %result
 }
 
 define <3 x i32> @v_usubsat_v3i32(<3 x i32> %lhs, <3 x i32> %rhs) {
 ; GFX6-LABEL: v_usubsat_v3i32:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

 ; GFX9-LABEL: v_usubsat_v3i32:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    v_sub_u32_e64 v0, v0, v3 clamp
 ; GFX9-NEXT:    v_sub_u32_e64 v1, v1, v4 clamp
 ; GFX9-NEXT:    v_sub_u32_e64 v2, v2, v5 clamp
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX10-LABEL: v_usubsat_v3i32:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_sub_nc_u32_e64 v0, v0, v3 clamp
-; GFX10-NEXT:    v_sub_nc_u32_e64 v1, v1, v4 clamp
-; GFX10-NEXT:    v_sub_nc_u32_e64 v2, v2, v5 clamp
-; GFX10-NEXT:    s_setpc_b64 s[30:31]
+; GFX10PLUS-LABEL: v_usubsat_v3i32:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX10PLUS-NEXT:    v_sub_nc_u32_e64 v0, v0, v3 clamp
+; GFX10PLUS-NEXT:    v_sub_nc_u32_e64 v1, v1, v4 clamp
+; GFX10PLUS-NEXT:    v_sub_nc_u32_e64 v2, v2, v5 clamp
+; GFX10PLUS-NEXT:    s_setpc_b64 s[30:31]
   %result = call <3 x i32> @llvm.usub.sat.v3i32(<3 x i32> %lhs, <3 x i32> %rhs)
   ret <3 x i32> %result
 }
 
 define amdgpu_ps <3 x i32> @s_usubsat_v3i32(<3 x i32> inreg %lhs, <3 x i32> inreg %rhs) {
 ; GFX6-LABEL: s_usubsat_v3i32:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_min_u32 s3, s0, s3

 ; GFX9-NEXT:    v_sub_u32_e64 v0, s0, v0 clamp
 ; GFX9-NEXT:    v_sub_u32_e64 v1, s1, v1 clamp
 ; GFX9-NEXT:    v_sub_u32_e64 v2, s2, v2 clamp
 ; GFX9-NEXT:    v_readfirstlane_b32 s0, v0
 ; GFX9-NEXT:    v_readfirstlane_b32 s1, v1
 ; GFX9-NEXT:    v_readfirstlane_b32 s2, v2
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
-; GFX10-LABEL: s_usubsat_v3i32:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_sub_nc_u32_e64 v0, s0, s3 clamp
-; GFX10-NEXT:    v_sub_nc_u32_e64 v1, s1, s4 clamp
-; GFX10-NEXT:    v_sub_nc_u32_e64 v2, s2, s5 clamp
-; GFX10-NEXT:    v_readfirstlane_b32 s0, v0
-; GFX10-NEXT:    v_readfirstlane_b32 s1, v1
-; GFX10-NEXT:    v_readfirstlane_b32 s2, v2
-; GFX10-NEXT:    ; return to shader part epilog
+; GFX10PLUS-LABEL: s_usubsat_v3i32:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    v_sub_nc_u32_e64 v0, s0, s3 clamp
+; GFX10PLUS-NEXT:    v_sub_nc_u32_e64 v1, s1, s4 clamp
+; GFX10PLUS-NEXT:    v_sub_nc_u32_e64 v2, s2, s5 clamp
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s0, v0
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s1, v1
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s2, v2
+; GFX10PLUS-NEXT:    ; return to shader part epilog
   %result = call <3 x i32> @llvm.usub.sat.v3i32(<3 x i32> %lhs, <3 x i32> %rhs)
   ret <3 x i32> %result
 }
 
 define <4 x i32> @v_usubsat_v4i32(<4 x i32> %lhs, <4 x i32> %rhs) {
 ; GFX6-LABEL: v_usubsat_v4i32:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    v_sub_u32_e64 v0, v0, v4 clamp
 ; GFX9-NEXT:    v_sub_u32_e64 v1, v1, v5 clamp
 ; GFX9-NEXT:    v_sub_u32_e64 v2, v2, v6 clamp
 ; GFX9-NEXT:    v_sub_u32_e64 v3, v3, v7 clamp
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX10-LABEL: v_usubsat_v4i32:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_sub_nc_u32_e64 v0, v0, v4 clamp
-; GFX10-NEXT:    v_sub_nc_u32_e64 v1, v1, v5 clamp
-; GFX10-NEXT:    v_sub_nc_u32_e64 v2, v2, v6 clamp
-; GFX10-NEXT:    v_sub_nc_u32_e64 v3, v3, v7 clamp
-; GFX10-NEXT:    s_setpc_b64 s[30:31]
+; GFX10PLUS-LABEL: v_usubsat_v4i32:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX10PLUS-NEXT:    v_sub_nc_u32_e64 v0, v0, v4 clamp
+; GFX10PLUS-NEXT:    v_sub_nc_u32_e64 v1, v1, v5 clamp
+; GFX10PLUS-NEXT:    v_sub_nc_u32_e64 v2, v2, v6 clamp
+; GFX10PLUS-NEXT:    v_sub_nc_u32_e64 v3, v3, v7 clamp
+; GFX10PLUS-NEXT:    s_setpc_b64 s[30:31]
   %result = call <4 x i32> @llvm.usub.sat.v4i32(<4 x i32> %lhs, <4 x i32> %rhs)
   ret <4 x i32> %result
 }
 
 define amdgpu_ps <4 x i32> @s_usubsat_v4i32(<4 x i32> inreg %lhs, <4 x i32> inreg %rhs) {
 ; GFX6-LABEL: s_usubsat_v4i32:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_min_u32 s4, s0, s4

 ; GFX9-NEXT:    v_sub_u32_e64 v2, s2, v2 clamp
 ; GFX9-NEXT:    v_sub_u32_e64 v3, s3, v3 clamp
 ; GFX9-NEXT:    v_readfirstlane_b32 s0, v0
 ; GFX9-NEXT:    v_readfirstlane_b32 s1, v1
 ; GFX9-NEXT:    v_readfirstlane_b32 s2, v2
 ; GFX9-NEXT:    v_readfirstlane_b32 s3, v3
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
-; GFX10-LABEL: s_usubsat_v4i32:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_sub_nc_u32_e64 v0, s0, s4 clamp
-; GFX10-NEXT:    v_sub_nc_u32_e64 v1, s1, s5 clamp
-; GFX10-NEXT:    v_sub_nc_u32_e64 v2, s2, s6 clamp
-; GFX10-NEXT:    v_sub_nc_u32_e64 v3, s3, s7 clamp
-; GFX10-NEXT:    v_readfirstlane_b32 s0, v0
-; GFX10-NEXT:    v_readfirstlane_b32 s1, v1
-; GFX10-NEXT:    v_readfirstlane_b32 s2, v2
-; GFX10-NEXT:    v_readfirstlane_b32 s3, v3
-; GFX10-NEXT:    ; return to shader part epilog
+; GFX10PLUS-LABEL: s_usubsat_v4i32:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    v_sub_nc_u32_e64 v0, s0, s4 clamp
+; GFX10PLUS-NEXT:    v_sub_nc_u32_e64 v1, s1, s5 clamp
+; GFX10PLUS-NEXT:    v_sub_nc_u32_e64 v2, s2, s6 clamp
+; GFX10PLUS-NEXT:    v_sub_nc_u32_e64 v3, s3, s7 clamp
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s0, v0
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s1, v1
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s2, v2
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s3, v3
+; GFX10PLUS-NEXT:    ; return to shader part epilog
   %result = call <4 x i32> @llvm.usub.sat.v4i32(<4 x i32> %lhs, <4 x i32> %rhs)
   ret <4 x i32> %result
 }
 
 define <5 x i32> @v_usubsat_v5i32(<5 x i32> %lhs, <5 x i32> %rhs) {
 ; GFX6-LABEL: v_usubsat_v5i32:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    v_sub_u32_e64 v0, v0, v5 clamp
 ; GFX9-NEXT:    v_sub_u32_e64 v1, v1, v6 clamp
 ; GFX9-NEXT:    v_sub_u32_e64 v2, v2, v7 clamp
 ; GFX9-NEXT:    v_sub_u32_e64 v3, v3, v8 clamp
 ; GFX9-NEXT:    v_sub_u32_e64 v4, v4, v9 clamp
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX10-LABEL: v_usubsat_v5i32:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_sub_nc_u32_e64 v0, v0, v5 clamp
-; GFX10-NEXT:    v_sub_nc_u32_e64 v1, v1, v6 clamp
-; GFX10-NEXT:    v_sub_nc_u32_e64 v2, v2, v7 clamp
-; GFX10-NEXT:    v_sub_nc_u32_e64 v3, v3, v8 clamp
-; GFX10-NEXT:    v_sub_nc_u32_e64 v4, v4, v9 clamp
-; GFX10-NEXT:    s_setpc_b64 s[30:31]
+; GFX10PLUS-LABEL: v_usubsat_v5i32:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX10PLUS-NEXT:    v_sub_nc_u32_e64 v0, v0, v5 clamp
+; GFX10PLUS-NEXT:    v_sub_nc_u32_e64 v1, v1, v6 clamp
+; GFX10PLUS-NEXT:    v_sub_nc_u32_e64 v2, v2, v7 clamp
+; GFX10PLUS-NEXT:    v_sub_nc_u32_e64 v3, v3, v8 clamp
+; GFX10PLUS-NEXT:    v_sub_nc_u32_e64 v4, v4, v9 clamp
+; GFX10PLUS-NEXT:    s_setpc_b64 s[30:31]
   %result = call <5 x i32> @llvm.usub.sat.v5i32(<5 x i32> %lhs, <5 x i32> %rhs)
   ret <5 x i32> %result
 }
 
 define amdgpu_ps <5 x i32> @s_usubsat_v5i32(<5 x i32> inreg %lhs, <5 x i32> inreg %rhs) {
 ; GFX6-LABEL: s_usubsat_v5i32:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_min_u32 s5, s0, s5

 ; GFX9-NEXT:    v_sub_u32_e64 v4, s4, v4 clamp
 ; GFX9-NEXT:    v_readfirstlane_b32 s0, v0
 ; GFX9-NEXT:    v_readfirstlane_b32 s1, v1
 ; GFX9-NEXT:    v_readfirstlane_b32 s2, v2
 ; GFX9-NEXT:    v_readfirstlane_b32 s3, v3
 ; GFX9-NEXT:    v_readfirstlane_b32 s4, v4
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
-; GFX10-LABEL: s_usubsat_v5i32:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_sub_nc_u32_e64 v0, s0, s5 clamp
-; GFX10-NEXT:    v_sub_nc_u32_e64 v1, s1, s6 clamp
-; GFX10-NEXT:    v_sub_nc_u32_e64 v2, s2, s7 clamp
-; GFX10-NEXT:    v_sub_nc_u32_e64 v3, s3, s8 clamp
-; GFX10-NEXT:    v_sub_nc_u32_e64 v4, s4, s9 clamp
-; GFX10-NEXT:    v_readfirstlane_b32 s0, v0
-; GFX10-NEXT:    v_readfirstlane_b32 s1, v1
-; GFX10-NEXT:    v_readfirstlane_b32 s2, v2
-; GFX10-NEXT:    v_readfirstlane_b32 s3, v3
-; GFX10-NEXT:    v_readfirstlane_b32 s4, v4
-; GFX10-NEXT:    ; return to shader part epilog
+; GFX10PLUS-LABEL: s_usubsat_v5i32:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    v_sub_nc_u32_e64 v0, s0, s5 clamp
+; GFX10PLUS-NEXT:    v_sub_nc_u32_e64 v1, s1, s6 clamp
+; GFX10PLUS-NEXT:    v_sub_nc_u32_e64 v2, s2, s7 clamp
+; GFX10PLUS-NEXT:    v_sub_nc_u32_e64 v3, s3, s8 clamp
+; GFX10PLUS-NEXT:    v_sub_nc_u32_e64 v4, s4, s9 clamp
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s0, v0
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s1, v1
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s2, v2
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s3, v3
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s4, v4
+; GFX10PLUS-NEXT:    ; return to shader part epilog
   %result = call <5 x i32> @llvm.usub.sat.v5i32(<5 x i32> %lhs, <5 x i32> %rhs)
   ret <5 x i32> %result
 }
 
 define <16 x i32> @v_usubsat_v16i32(<16 x i32> %lhs, <16 x i32> %rhs) {
 ; GFX6-LABEL: v_usubsat_v16i32:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

 ; GFX10-NEXT:    v_sub_nc_u32_e64 v10, v10, v26 clamp
 ; GFX10-NEXT:    v_sub_nc_u32_e64 v11, v11, v27 clamp
 ; GFX10-NEXT:    v_sub_nc_u32_e64 v12, v12, v28 clamp
 ; GFX10-NEXT:    v_sub_nc_u32_e64 v13, v13, v29 clamp
 ; GFX10-NEXT:    v_sub_nc_u32_e64 v14, v14, v30 clamp
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    v_sub_nc_u32_e64 v15, v15, v31 clamp
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_usubsat_v16i32:
+; GFX11:       ; %bb.0:
+; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT:    scratch_load_b32 v31, off, s32
+; GFX11-NEXT:    v_sub_nc_u32_e64 v0, v0, v16 clamp
+; GFX11-NEXT:    v_sub_nc_u32_e64 v1, v1, v17 clamp
+; GFX11-NEXT:    v_sub_nc_u32_e64 v2, v2, v18 clamp
+; GFX11-NEXT:    v_sub_nc_u32_e64 v3, v3, v19 clamp
+; GFX11-NEXT:    v_sub_nc_u32_e64 v4, v4, v20 clamp
+; GFX11-NEXT:    v_sub_nc_u32_e64 v5, v5, v21 clamp
+; GFX11-NEXT:    v_sub_nc_u32_e64 v6, v6, v22 clamp
+; GFX11-NEXT:    v_sub_nc_u32_e64 v7, v7, v23 clamp
+; GFX11-NEXT:    v_sub_nc_u32_e64 v8, v8, v24 clamp
+; GFX11-NEXT:    v_sub_nc_u32_e64 v9, v9, v25 clamp
+; GFX11-NEXT:    v_sub_nc_u32_e64 v10, v10, v26 clamp
+; GFX11-NEXT:    v_sub_nc_u32_e64 v11, v11, v27 clamp
+; GFX11-NEXT:    v_sub_nc_u32_e64 v12, v12, v28 clamp
+; GFX11-NEXT:    v_sub_nc_u32_e64 v13, v13, v29 clamp
+; GFX11-NEXT:    v_sub_nc_u32_e64 v14, v14, v30 clamp
+; GFX11-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-NEXT:    v_sub_nc_u32_e64 v15, v15, v31 clamp
+; GFX11-NEXT:    s_setpc_b64 s[30:31]
   %result = call <16 x i32> @llvm.usub.sat.v16i32(<16 x i32> %lhs, <16 x i32> %rhs)
   ret <16 x i32> %result
 }
 
 define amdgpu_ps <16 x i32> @s_usubsat_v16i32(<16 x i32> inreg %lhs, <16 x i32> inreg %rhs) {
 ; GFX6-LABEL: s_usubsat_v16i32:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_min_u32 s16, s0, s16

 ; GFX9-NEXT:    v_readfirstlane_b32 s10, v10
 ; GFX9-NEXT:    v_readfirstlane_b32 s11, v11
 ; GFX9-NEXT:    v_readfirstlane_b32 s12, v12
 ; GFX9-NEXT:    v_readfirstlane_b32 s13, v13
 ; GFX9-NEXT:    v_readfirstlane_b32 s14, v14
 ; GFX9-NEXT:    v_readfirstlane_b32 s15, v15
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
-; GFX10-LABEL: s_usubsat_v16i32:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_sub_nc_u32_e64 v0, s0, s16 clamp
-; GFX10-NEXT:    v_sub_nc_u32_e64 v1, s1, s17 clamp
-; GFX10-NEXT:    v_sub_nc_u32_e64 v2, s2, s18 clamp
-; GFX10-NEXT:    v_sub_nc_u32_e64 v3, s3, s19 clamp
-; GFX10-NEXT:    v_sub_nc_u32_e64 v4, s4, s20 clamp
-; GFX10-NEXT:    v_sub_nc_u32_e64 v5, s5, s21 clamp
-; GFX10-NEXT:    v_sub_nc_u32_e64 v6, s6, s22 clamp
-; GFX10-NEXT:    v_sub_nc_u32_e64 v7, s7, s23 clamp
-; GFX10-NEXT:    v_sub_nc_u32_e64 v8, s8, s24 clamp
-; GFX10-NEXT:    v_sub_nc_u32_e64 v9, s9, s25 clamp
-; GFX10-NEXT:    v_sub_nc_u32_e64 v10, s10, s26 clamp
-; GFX10-NEXT:    v_sub_nc_u32_e64 v11, s11, s27 clamp
-; GFX10-NEXT:    v_sub_nc_u32_e64 v12, s12, s28 clamp
-; GFX10-NEXT:    v_sub_nc_u32_e64 v13, s13, s29 clamp
-; GFX10-NEXT:    v_sub_nc_u32_e64 v14, s14, s30 clamp
-; GFX10-NEXT:    v_sub_nc_u32_e64 v15, s15, s31 clamp
-; GFX10-NEXT:    v_readfirstlane_b32 s0, v0
-; GFX10-NEXT:    v_readfirstlane_b32 s1, v1
-; GFX10-NEXT:    v_readfirstlane_b32 s2, v2
-; GFX10-NEXT:    v_readfirstlane_b32 s3, v3
-; GFX10-NEXT:    v_readfirstlane_b32 s4, v4
-; GFX10-NEXT:    v_readfirstlane_b32 s5, v5
-; GFX10-NEXT:    v_readfirstlane_b32 s6, v6
-; GFX10-NEXT:    v_readfirstlane_b32 s7, v7
-; GFX10-NEXT:    v_readfirstlane_b32 s8, v8
-; GFX10-NEXT:    v_readfirstlane_b32 s9, v9
-; GFX10-NEXT:    v_readfirstlane_b32 s10, v10
-; GFX10-NEXT:    v_readfirstlane_b32 s11, v11
-; GFX10-NEXT:    v_readfirstlane_b32 s12, v12
-; GFX10-NEXT:    v_readfirstlane_b32 s13, v13
-; GFX10-NEXT:    v_readfirstlane_b32 s14, v14
-; GFX10-NEXT:    v_readfirstlane_b32 s15, v15
-; GFX10-NEXT:    ; return to shader part epilog
+; GFX10PLUS-LABEL: s_usubsat_v16i32:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    v_sub_nc_u32_e64 v0, s0, s16 clamp
+; GFX10PLUS-NEXT:    v_sub_nc_u32_e64 v1, s1, s17 clamp
+; GFX10PLUS-NEXT:    v_sub_nc_u32_e64 v2, s2, s18 clamp
+; GFX10PLUS-NEXT:    v_sub_nc_u32_e64 v3, s3, s19 clamp
+; GFX10PLUS-NEXT:    v_sub_nc_u32_e64 v4, s4, s20 clamp
+; GFX10PLUS-NEXT:    v_sub_nc_u32_e64 v5, s5, s21 clamp
+; GFX10PLUS-NEXT:    v_sub_nc_u32_e64 v6, s6, s22 clamp
+; GFX10PLUS-NEXT:    v_sub_nc_u32_e64 v7, s7, s23 clamp
+; GFX10PLUS-NEXT:    v_sub_nc_u32_e64 v8, s8, s24 clamp
+; GFX10PLUS-NEXT:    v_sub_nc_u32_e64 v9, s9, s25 clamp
+; GFX10PLUS-NEXT:    v_sub_nc_u32_e64 v10, s10, s26 clamp
+; GFX10PLUS-NEXT:    v_sub_nc_u32_e64 v11, s11, s27 clamp
+; GFX10PLUS-NEXT:    v_sub_nc_u32_e64 v12, s12, s28 clamp
+; GFX10PLUS-NEXT:    v_sub_nc_u32_e64 v13, s13, s29 clamp
+; GFX10PLUS-NEXT:    v_sub_nc_u32_e64 v14, s14, s30 clamp
+; GFX10PLUS-NEXT:    v_sub_nc_u32_e64 v15, s15, s31 clamp
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s0, v0
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s1, v1
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s2, v2
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s3, v3
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s4, v4
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s5, v5
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s6, v6
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s7, v7
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s8, v8
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s9, v9
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s10, v10
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s11, v11
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s12, v12
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s13, v13
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s14, v14
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s15, v15
+; GFX10PLUS-NEXT:    ; return to shader part epilog
   %result = call <16 x i32> @llvm.usub.sat.v16i32(<16 x i32> %lhs, <16 x i32> %rhs)
   ret <16 x i32> %result
 }
 
 define i16 @v_usubsat_i16(i16 %lhs, i16 %rhs) {
 ; GFX6-LABEL: v_usubsat_i16:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

 ; GFX8-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX9-LABEL: v_usubsat_i16:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    v_sub_u16_e64 v0, v0, v1 clamp
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX10-LABEL: v_usubsat_i16:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_sub_nc_u16 v0, v0, v1 clamp
-; GFX10-NEXT:    s_setpc_b64 s[30:31]
+; GFX10PLUS-LABEL: v_usubsat_i16:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX10PLUS-NEXT:    v_sub_nc_u16 v0, v0, v1 clamp
+; GFX10PLUS-NEXT:    s_setpc_b64 s[30:31]
   %result = call i16 @llvm.usub.sat.i16(i16 %lhs, i16 %rhs)
   ret i16 %result
 }
 
 define amdgpu_ps i16 @s_usubsat_i16(i16 inreg %lhs, i16 inreg %rhs) {
 ; GFX6-LABEL: s_usubsat_i16:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_lshl_b32 s0, s0, 16

 ;
 ; GFX9-LABEL: s_usubsat_i16:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    v_mov_b32_e32 v0, s1
 ; GFX9-NEXT:    v_sub_u16_e64 v0, s0, v0 clamp
 ; GFX9-NEXT:    v_readfirstlane_b32 s0, v0
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
-; GFX10-LABEL: s_usubsat_i16:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_sub_nc_u16 v0, s0, s1 clamp
-; GFX10-NEXT:    v_readfirstlane_b32 s0, v0
-; GFX10-NEXT:    ; return to shader part epilog
+; GFX10PLUS-LABEL: s_usubsat_i16:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    v_sub_nc_u16 v0, s0, s1 clamp
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s0, v0
+; GFX10PLUS-NEXT:    ; return to shader part epilog
   %result = call i16 @llvm.usub.sat.i16(i16 %lhs, i16 %rhs)
   ret i16 %result
 }
 
 define amdgpu_ps half @usubsat_i16_sv(i16 inreg %lhs, i16 %rhs) {
 ; GFX6-LABEL: usubsat_i16_sv:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_lshl_b32 s0, s0, 16
 ; GFX6-NEXT:    v_lshlrev_b32_e32 v0, 16, v0
 ; GFX6-NEXT:    v_min_u32_e32 v0, s0, v0
 ; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, s0, v0
 ; GFX6-NEXT:    v_lshrrev_b32_e32 v0, 16, v0
 ; GFX6-NEXT:    ; return to shader part epilog
 ;
 ; GFX8-LABEL: usubsat_i16_sv:
 ; GFX8:       ; %bb.0:
 ; GFX8-NEXT:    v_sub_u16_e64 v0, s0, v0 clamp
 ; GFX8-NEXT:    ; return to shader part epilog
 ;
 ; GFX9-LABEL: usubsat_i16_sv:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    v_sub_u16_e64 v0, s0, v0 clamp
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
-; GFX10-LABEL: usubsat_i16_sv:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_sub_nc_u16 v0, s0, v0 clamp
-; GFX10-NEXT:    ; return to shader part epilog
+; GFX10PLUS-LABEL: usubsat_i16_sv:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    v_sub_nc_u16 v0, s0, v0 clamp
+; GFX10PLUS-NEXT:    ; return to shader part epilog
   %result = call i16 @llvm.usub.sat.i16(i16 %lhs, i16 %rhs)
   %cast = bitcast i16 %result to half
   ret half %cast
 }
 
 define amdgpu_ps half @usubsat_i16_vs(i16 %lhs, i16 inreg %rhs) {
 ; GFX6-LABEL: usubsat_i16_vs:
 ; GFX6:       ; %bb.0:

 ; GFX8-NEXT:    v_sub_u16_e64 v0, v0, s0 clamp
 ; GFX8-NEXT:    ; return to shader part epilog
 ;
 ; GFX9-LABEL: usubsat_i16_vs:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    v_sub_u16_e64 v0, v0, s0 clamp
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
-; GFX10-LABEL: usubsat_i16_vs:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_sub_nc_u16 v0, v0, s0 clamp
-; GFX10-NEXT:    ; return to shader part epilog
+; GFX10PLUS-LABEL: usubsat_i16_vs:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    v_sub_nc_u16 v0, v0, s0 clamp
+; GFX10PLUS-NEXT:    ; return to shader part epilog
   %result = call i16 @llvm.usub.sat.i16(i16 %lhs, i16 %rhs)
   %cast = bitcast i16 %result to half
   ret half %cast
 }
 
 define <2 x i16> @v_usubsat_v2i16(<2 x i16> %lhs, <2 x i16> %rhs) {
 ; GFX6-LABEL: v_usubsat_v2i16:
 ; GFX6:       ; %bb.0:

 ; GFX8-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX9-LABEL: v_usubsat_v2i16:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    v_pk_sub_u16 v0, v0, v1 clamp
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX10-LABEL: v_usubsat_v2i16:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_pk_sub_u16 v0, v0, v1 clamp
-; GFX10-NEXT:    s_setpc_b64 s[30:31]
+; GFX10PLUS-LABEL: v_usubsat_v2i16:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX10PLUS-NEXT:    v_pk_sub_u16 v0, v0, v1 clamp
+; GFX10PLUS-NEXT:    s_setpc_b64 s[30:31]
   %result = call <2 x i16> @llvm.usub.sat.v2i16(<2 x i16> %lhs, <2 x i16> %rhs)
   ret <2 x i16> %result
 }
 
 define amdgpu_ps i32 @s_usubsat_v2i16(<2 x i16> inreg %lhs, <2 x i16> inreg %rhs) {
 ; GFX6-LABEL: s_usubsat_v2i16:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_lshl_b32 s0, s0, 16

 ;
 ; GFX9-LABEL: s_usubsat_v2i16:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    v_mov_b32_e32 v0, s1
 ; GFX9-NEXT:    v_pk_sub_u16 v0, s0, v0 clamp
 ; GFX9-NEXT:    v_readfirstlane_b32 s0, v0
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
-; GFX10-LABEL: s_usubsat_v2i16:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_pk_sub_u16 v0, s0, s1 clamp
-; GFX10-NEXT:    v_readfirstlane_b32 s0, v0
-; GFX10-NEXT:    ; return to shader part epilog
+; GFX10PLUS-LABEL: s_usubsat_v2i16:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    v_pk_sub_u16 v0, s0, s1 clamp
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s0, v0
+; GFX10PLUS-NEXT:    ; return to shader part epilog
   %result = call <2 x i16> @llvm.usub.sat.v2i16(<2 x i16> %lhs, <2 x i16> %rhs)
   %cast = bitcast <2 x i16> %result to i32
   ret i32 %cast
 }
 
 define amdgpu_ps float @usubsat_v2i16_sv(<2 x i16> inreg %lhs, <2 x i16> %rhs) {
 ; GFX6-LABEL: usubsat_v2i16_sv:
 ; GFX6:       ; %bb.0:

 ; GFX8-NEXT:    v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
 ; GFX8-NEXT:    ; return to shader part epilog
 ;
 ; GFX9-LABEL: usubsat_v2i16_sv:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    v_pk_sub_u16 v0, s0, v0 clamp
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
-; GFX10-LABEL: usubsat_v2i16_sv:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_pk_sub_u16 v0, s0, v0 clamp
-; GFX10-NEXT:    ; return to shader part epilog
+; GFX10PLUS-LABEL: usubsat_v2i16_sv:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    v_pk_sub_u16 v0, s0, v0 clamp
+; GFX10PLUS-NEXT:    ; return to shader part epilog
   %result = call <2 x i16> @llvm.usub.sat.v2i16(<2 x i16> %lhs, <2 x i16> %rhs)
   %cast = bitcast <2 x i16> %result to float
   ret float %cast
 }
 
 define amdgpu_ps float @usubsat_v2i16_vs(<2 x i16> %lhs, <2 x i16> inreg %rhs) {
 ; GFX6-LABEL: usubsat_v2i16_vs:
 ; GFX6:       ; %bb.0:

 ; GFX8-NEXT:    v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
 ; GFX8-NEXT:    ; return to shader part epilog
 ;
 ; GFX9-LABEL: usubsat_v2i16_vs:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    v_pk_sub_u16 v0, v0, s0 clamp
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
-; GFX10-LABEL: usubsat_v2i16_vs:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_pk_sub_u16 v0, v0, s0 clamp
-; GFX10-NEXT:    ; return to shader part epilog
+; GFX10PLUS-LABEL: usubsat_v2i16_vs:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    v_pk_sub_u16 v0, v0, s0 clamp
+; GFX10PLUS-NEXT:    ; return to shader part epilog
   %result = call <2 x i16> @llvm.usub.sat.v2i16(<2 x i16> %lhs, <2 x i16> %rhs)
   %cast = bitcast <2 x i16> %result to float
   ret float %cast
 }
 
 ; FIXME: v3i16 insert/extract
 ; define <3 x i16> @v_usubsat_v3i16(<3 x i16> %lhs, <3 x i16> %rhs) {
 ;   %result = call <3 x i16> @llvm.usub.sat.v3i16(<3 x i16> %lhs, <3 x i16> %rhs)

 ;
 ; GFX9-LABEL: v_usubsat_v4i16:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    v_pk_sub_u16 v0, v0, v2 clamp
 ; GFX9-NEXT:    v_pk_sub_u16 v1, v1, v3 clamp
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX10-LABEL: v_usubsat_v4i16:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_pk_sub_u16 v0, v0, v2 clamp
-; GFX10-NEXT:    v_pk_sub_u16 v1, v1, v3 clamp
-; GFX10-NEXT:    s_setpc_b64 s[30:31]
+; GFX10PLUS-LABEL: v_usubsat_v4i16:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX10PLUS-NEXT:    v_pk_sub_u16 v0, v0, v2 clamp
+; GFX10PLUS-NEXT:    v_pk_sub_u16 v1, v1, v3 clamp
+; GFX10PLUS-NEXT:    s_setpc_b64 s[30:31]
   %result = call <4 x i16> @llvm.usub.sat.v4i16(<4 x i16> %lhs, <4 x i16> %rhs)
   %cast = bitcast <4 x i16> %result to <2 x float>
   ret <2 x float> %cast
 }
 
 define amdgpu_ps <2 x i32> @s_usubsat_v4i16(<4 x i16> inreg %lhs, <4 x i16> inreg %rhs) {
 ; GFX6-LABEL: s_usubsat_v4i16:
 ; GFX6:       ; %bb.0:

 ; GFX9-NEXT:    v_mov_b32_e32 v0, s2
 ; GFX9-NEXT:    v_mov_b32_e32 v1, s3
 ; GFX9-NEXT:    v_pk_sub_u16 v0, s0, v0 clamp
 ; GFX9-NEXT:    v_pk_sub_u16 v1, s1, v1 clamp
 ; GFX9-NEXT:    v_readfirstlane_b32 s0, v0
 ; GFX9-NEXT:    v_readfirstlane_b32 s1, v1
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
-; GFX10-LABEL: s_usubsat_v4i16:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_pk_sub_u16 v0, s0, s2 clamp
-; GFX10-NEXT:    v_pk_sub_u16 v1, s1, s3 clamp
-; GFX10-NEXT:    v_readfirstlane_b32 s0, v0
-; GFX10-NEXT:    v_readfirstlane_b32 s1, v1
-; GFX10-NEXT:    ; return to shader part epilog
+; GFX10PLUS-LABEL: s_usubsat_v4i16:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    v_pk_sub_u16 v0, s0, s2 clamp
+; GFX10PLUS-NEXT:    v_pk_sub_u16 v1, s1, s3 clamp
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s0, v0
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s1, v1
+; GFX10PLUS-NEXT:    ; return to shader part epilog
   %result = call <4 x i16> @llvm.usub.sat.v4i16(<4 x i16> %lhs, <4 x i16> %rhs)
   %cast = bitcast <4 x i16> %result to <2 x i32>
   ret <2 x i32> %cast
 }
 
 ; FIXME
 ; define <5 x i16> @v_usubsat_v5i16(<5 x i16> %lhs, <5 x i16> %rhs) {
 ;   %result = call <5 x i16> @llvm.usub.sat.v5i16(<5 x i16> %lhs, <5 x i16> %rhs)

 ; GFX9-LABEL: v_usubsat_v6i16:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    v_pk_sub_u16 v0, v0, v3 clamp
 ; GFX9-NEXT:    v_pk_sub_u16 v1, v1, v4 clamp
 ; GFX9-NEXT:    v_pk_sub_u16 v2, v2, v5 clamp
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX10-LABEL: v_usubsat_v6i16:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_pk_sub_u16 v0, v0, v3 clamp
-; GFX10-NEXT:    v_pk_sub_u16 v1, v1, v4 clamp
-; GFX10-NEXT:    v_pk_sub_u16 v2, v2, v5 clamp
-; GFX10-NEXT:    s_setpc_b64 s[30:31]
+; GFX10PLUS-LABEL: v_usubsat_v6i16:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX10PLUS-NEXT:    v_pk_sub_u16 v0, v0, v3 clamp
+; GFX10PLUS-NEXT:    v_pk_sub_u16 v1, v1, v4 clamp
+; GFX10PLUS-NEXT:    v_pk_sub_u16 v2, v2, v5 clamp
+; GFX10PLUS-NEXT:    s_setpc_b64 s[30:31]
   %result = call <6 x i16> @llvm.usub.sat.v6i16(<6 x i16> %lhs, <6 x i16> %rhs)
   %cast = bitcast <6 x i16> %result to <3 x float>
   ret <3 x float> %cast
 }
 
 define amdgpu_ps <3 x i32> @s_usubsat_v6i16(<6 x i16> inreg %lhs, <6 x i16> inreg %rhs) {
 ; GFX6-LABEL: s_usubsat_v6i16:
 ; GFX6:       ; %bb.0:

 ; GFX9-NEXT:    v_pk_sub_u16 v0, s0, v0 clamp
 ; GFX9-NEXT:    v_pk_sub_u16 v1, s1, v1 clamp
 ; GFX9-NEXT:    v_pk_sub_u16 v2, s2, v2 clamp
 ; GFX9-NEXT:    v_readfirstlane_b32 s0, v0
 ; GFX9-NEXT:    v_readfirstlane_b32 s1, v1
 ; GFX9-NEXT:    v_readfirstlane_b32 s2, v2
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
-; GFX10-LABEL: s_usubsat_v6i16:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_pk_sub_u16 v0, s0, s3 clamp
-; GFX10-NEXT:    v_pk_sub_u16 v1, s1, s4 clamp
-; GFX10-NEXT:    v_pk_sub_u16 v2, s2, s5 clamp
-; GFX10-NEXT:    v_readfirstlane_b32 s0, v0
-; GFX10-NEXT:    v_readfirstlane_b32 s1, v1
-; GFX10-NEXT:    v_readfirstlane_b32 s2, v2
-; GFX10-NEXT:    ; return to shader part epilog
+; GFX10PLUS-LABEL: s_usubsat_v6i16:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    v_pk_sub_u16 v0, s0, s3 clamp
+; GFX10PLUS-NEXT:    v_pk_sub_u16 v1, s1, s4 clamp
+; GFX10PLUS-NEXT:    v_pk_sub_u16 v2, s2, s5 clamp
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s0, v0
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s1, v1
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s2, v2
+; GFX10PLUS-NEXT:    ; return to shader part epilog
   %result = call <6 x i16> @llvm.usub.sat.v6i16(<6 x i16> %lhs, <6 x i16> %rhs)
   %cast = bitcast <6 x i16> %result to <3 x i32>
   ret <3 x i32> %cast
 }
 
 define <4 x float> @v_usubsat_v8i16(<8 x i16> %lhs, <8 x i16> %rhs) {
 ; GFX6-LABEL: v_usubsat_v8i16:
 ; GFX6:       ; %bb.0:

 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    v_pk_sub_u16 v0, v0, v4 clamp
 ; GFX9-NEXT:    v_pk_sub_u16 v1, v1, v5 clamp
 ; GFX9-NEXT:    v_pk_sub_u16 v2, v2, v6 clamp
 ; GFX9-NEXT:    v_pk_sub_u16 v3, v3, v7 clamp
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX10-LABEL: v_usubsat_v8i16:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_pk_sub_u16 v0, v0, v4 clamp
-; GFX10-NEXT:    v_pk_sub_u16 v1, v1, v5 clamp
-; GFX10-NEXT:    v_pk_sub_u16 v2, v2, v6 clamp
-; GFX10-NEXT:    v_pk_sub_u16 v3, v3, v7 clamp
-; GFX10-NEXT:    s_setpc_b64 s[30:31]
+; GFX10PLUS-LABEL: v_usubsat_v8i16:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX10PLUS-NEXT:    v_pk_sub_u16 v0, v0, v4 clamp
+; GFX10PLUS-NEXT:    v_pk_sub_u16 v1, v1, v5 clamp
+; GFX10PLUS-NEXT:    v_pk_sub_u16 v2, v2, v6 clamp
+; GFX10PLUS-NEXT:    v_pk_sub_u16 v3, v3, v7 clamp
+; GFX10PLUS-NEXT:    s_setpc_b64 s[30:31]
   %result = call <8 x i16> @llvm.usub.sat.v8i16(<8 x i16> %lhs, <8 x i16> %rhs)
   %cast = bitcast <8 x i16> %result to <4 x float>
   ret <4 x float> %cast
 }
 
 define amdgpu_ps <4 x i32> @s_usubsat_v8i16(<8 x i16> inreg %lhs, <8 x i16> inreg %rhs) {
 ; GFX6-LABEL: s_usubsat_v8i16:
 ; GFX6:       ; %bb.0:

 ; GFX9-NEXT:    v_pk_sub_u16 v2, s2, v2 clamp
 ; GFX9-NEXT:    v_pk_sub_u16 v3, s3, v3 clamp
 ; GFX9-NEXT:    v_readfirstlane_b32 s0, v0
 ; GFX9-NEXT:    v_readfirstlane_b32 s1, v1
 ; GFX9-NEXT:    v_readfirstlane_b32 s2, v2
 ; GFX9-NEXT:    v_readfirstlane_b32 s3, v3
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
-; GFX10-LABEL: s_usubsat_v8i16:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_pk_sub_u16 v0, s0, s4 clamp
-; GFX10-NEXT:    v_pk_sub_u16 v1, s1, s5 clamp
-; GFX10-NEXT:    v_pk_sub_u16 v2, s2, s6 clamp
-; GFX10-NEXT:    v_pk_sub_u16 v3, s3, s7 clamp
-; GFX10-NEXT:    v_readfirstlane_b32 s0, v0
-; GFX10-NEXT:    v_readfirstlane_b32 s1, v1
-; GFX10-NEXT:    v_readfirstlane_b32 s2, v2
-; GFX10-NEXT:    v_readfirstlane_b32 s3, v3
-; GFX10-NEXT:    ; return to shader part epilog
+; GFX10PLUS-LABEL: s_usubsat_v8i16:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    v_pk_sub_u16 v0, s0, s4 clamp
+; GFX10PLUS-NEXT:    v_pk_sub_u16 v1, s1, s5 clamp
+; GFX10PLUS-NEXT:    v_pk_sub_u16 v2, s2, s6 clamp
+; GFX10PLUS-NEXT:    v_pk_sub_u16 v3, s3, s7 clamp
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s0, v0
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s1, v1
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s2, v2
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s3, v3
+; GFX10PLUS-NEXT:    ; return to shader part epilog
   %result = call <8 x i16> @llvm.usub.sat.v8i16(<8 x i16> %lhs, <8 x i16> %rhs)
   %cast = bitcast <8 x i16> %result to <4 x i32>
   ret <4 x i32> %cast
 }
 
 ; FIXME: i48 broken because i48 add broken
 ; define i48 @v_usubsat_i48(i48 %lhs, i48 %rhs) {
 ;   %result = call i48 @llvm.usub.sat.i48(i48 %lhs, i48 %rhs)

 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    v_sub_co_u32_e32 v4, vcc, v0, v2
 ; GFX9-NEXT:    v_subb_co_u32_e32 v5, vcc, v1, v3, vcc
 ; GFX9-NEXT:    v_cmp_lt_u64_e32 vcc, v[0:1], v[2:3]
 ; GFX9-NEXT:    v_cndmask_b32_e64 v0, v4, 0, vcc
 ; GFX9-NEXT:    v_cndmask_b32_e64 v1, v5, 0, vcc
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX10-LABEL: v_usubsat_i64:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_sub_co_u32 v4, vcc_lo, v0, v2
-; GFX10-NEXT:    v_sub_co_ci_u32_e32 v5, vcc_lo, v1, v3, vcc_lo
-; GFX10-NEXT:    v_cmp_lt_u64_e32 vcc_lo, v[0:1], v[2:3]
-; GFX10-NEXT:    v_cndmask_b32_e64 v0, v4, 0, vcc_lo
-; GFX10-NEXT:    v_cndmask_b32_e64 v1, v5, 0, vcc_lo
-; GFX10-NEXT:    s_setpc_b64 s[30:31]
+; GFX10PLUS-LABEL: v_usubsat_i64:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX10PLUS-NEXT:    v_sub_co_u32 v4, vcc_lo, v0, v2
+; GFX10PLUS-NEXT:    v_sub_co_ci_u32_e32 v5, vcc_lo, v1, v3, vcc_lo
+; GFX10PLUS-NEXT:    v_cmp_lt_u64_e32 vcc_lo, v[0:1], v[2:3]
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v0, v4, 0, vcc_lo
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v1, v5, 0, vcc_lo
+; GFX10PLUS-NEXT:    s_setpc_b64 s[30:31]
   %result = call i64 @llvm.usub.sat.i64(i64 %lhs, i64 %rhs)
   ret i64 %result
 }
 
 define amdgpu_ps i64 @s_usubsat_i64(i64 inreg %lhs, i64 inreg %rhs) {
 ; GFX6-LABEL: s_usubsat_i64:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2

 ; GFX9-NEXT:    v_mov_b32_e32 v2, s4
 ; GFX9-NEXT:    v_mov_b32_e32 v3, s5
 ; GFX9-NEXT:    v_cndmask_b32_e64 v0, v2, 0, vcc
 ; GFX9-NEXT:    v_cndmask_b32_e64 v1, v3, 0, vcc
 ; GFX9-NEXT:    v_readfirstlane_b32 s0, v0
 ; GFX9-NEXT:    v_readfirstlane_b32 s1, v1
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
-; GFX10-LABEL: s_usubsat_i64:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    s_sub_u32 s4, s0, s2
-; GFX10-NEXT:    v_cmp_lt_u64_e64 s0, s[0:1], s[2:3]
-; GFX10-NEXT:    s_subb_u32 s1, s1, s3
-; GFX10-NEXT:    v_cndmask_b32_e64 v0, s4, 0, s0
-; GFX10-NEXT:    v_cndmask_b32_e64 v1, s1, 0, s0
-; GFX10-NEXT:    v_readfirstlane_b32 s0, v0
-; GFX10-NEXT:    v_readfirstlane_b32 s1, v1
-; GFX10-NEXT:    ; return to shader part epilog
+; GFX10PLUS-LABEL: s_usubsat_i64:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    s_sub_u32 s4, s0, s2
+; GFX10PLUS-NEXT:    v_cmp_lt_u64_e64 s0, s[0:1], s[2:3]
+; GFX10PLUS-NEXT:    s_subb_u32 s1, s1, s3
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v0, s4, 0, s0
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v1, s1, 0, s0
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s0, v0
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s1, v1
+; GFX10PLUS-NEXT:    ; return to shader part epilog
   %result = call i64 @llvm.usub.sat.i64(i64 %lhs, i64 %rhs)
   ret i64 %result
 }
 
 define amdgpu_ps <2 x float> @usubsat_i64_sv(i64 inreg %lhs, i64 %rhs) {
 ; GFX6-LABEL: usubsat_i64_sv:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    v_mov_b32_e32 v2, s1

 ; GFX9-NEXT:    v_mov_b32_e32 v2, s1
 ; GFX9-NEXT:    v_sub_co_u32_e32 v3, vcc, s0, v0
 ; GFX9-NEXT:    v_subb_co_u32_e32 v2, vcc, v2, v1, vcc
 ; GFX9-NEXT:    v_cmp_lt_u64_e32 vcc, s[0:1], v[0:1]
 ; GFX9-NEXT:    v_cndmask_b32_e64 v0, v3, 0, vcc
 ; GFX9-NEXT:    v_cndmask_b32_e64 v1, v2, 0, vcc
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
-; GFX10-LABEL: usubsat_i64_sv:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_sub_co_u32 v2, vcc_lo, s0, v0
-; GFX10-NEXT:    v_sub_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
-; GFX10-NEXT:    v_cmp_lt_u64_e32 vcc_lo, s[0:1], v[0:1]
-; GFX10-NEXT:    v_cndmask_b32_e64 v0, v2, 0, vcc_lo
-; GFX10-NEXT:    v_cndmask_b32_e64 v1, v3, 0, vcc_lo
-; GFX10-NEXT:    ; return to shader part epilog
+; GFX10PLUS-LABEL: usubsat_i64_sv:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    v_sub_co_u32 v2, vcc_lo, s0, v0
+; GFX10PLUS-NEXT:    v_sub_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
+; GFX10PLUS-NEXT:    v_cmp_lt_u64_e32 vcc_lo, s[0:1], v[0:1]
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v0, v2, 0, vcc_lo
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v1, v3, 0, vcc_lo
+; GFX10PLUS-NEXT:    ; return to shader part epilog
   %result = call i64 @llvm.usub.sat.i64(i64 %lhs, i64 %rhs)
   %cast = bitcast i64 %result to <2 x float>
   ret <2 x float> %cast
 }
 
 define amdgpu_ps <2 x float> @usubsat_i64_vs(i64 %lhs, i64 inreg %rhs) {
 ; GFX6-LABEL: usubsat_i64_vs:
 ; GFX6:       ; %bb.0:

 ; GFX9-NEXT:    v_mov_b32_e32 v2, s1
 ; GFX9-NEXT:    v_subrev_co_u32_e32 v3, vcc, s0, v0
 ; GFX9-NEXT:    v_subb_co_u32_e32 v2, vcc, v1, v2, vcc
 ; GFX9-NEXT:    v_cmp_gt_u64_e32 vcc, s[0:1], v[0:1]
 ; GFX9-NEXT:    v_cndmask_b32_e64 v0, v3, 0, vcc
 ; GFX9-NEXT:    v_cndmask_b32_e64 v1, v2, 0, vcc
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
-; GFX10-LABEL: usubsat_i64_vs:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_sub_co_u32 v2, vcc_lo, v0, s0
-; GFX10-NEXT:    v_subrev_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
-; GFX10-NEXT:    v_cmp_gt_u64_e32 vcc_lo, s[0:1], v[0:1]
-; GFX10-NEXT:    v_cndmask_b32_e64 v0, v2, 0, vcc_lo
-; GFX10-NEXT:    v_cndmask_b32_e64 v1, v3, 0, vcc_lo
-; GFX10-NEXT:    ; return to shader part epilog
+; GFX10PLUS-LABEL: usubsat_i64_vs:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    v_sub_co_u32 v2, vcc_lo, v0, s0
+; GFX10PLUS-NEXT:    v_subrev_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
+; GFX10PLUS-NEXT:    v_cmp_gt_u64_e32 vcc_lo, s[0:1], v[0:1]
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v0, v2, 0, vcc_lo
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v1, v3, 0, vcc_lo
+; GFX10PLUS-NEXT:    ; return to shader part epilog
   %result = call i64 @llvm.usub.sat.i64(i64 %lhs, i64 %rhs)
   %cast = bitcast i64 %result to <2 x float>
   ret <2 x float> %cast
 }
 
 define <2 x i64> @v_usubsat_v2i64(<2 x i64> %lhs, <2 x i64> %rhs) {
 ; GFX6-LABEL: v_usubsat_v2i64:
 ; GFX6:       ; %bb.0:

 ; GFX10-NEXT:    v_sub_co_u32 v4, s4, v2, v6
 ; GFX10-NEXT:    v_sub_co_ci_u32_e64 v5, s4, v3, v7, s4
 ; GFX10-NEXT:    v_cmp_lt_u64_e64 s4, v[2:3], v[6:7]
 ; GFX10-NEXT:    v_cndmask_b32_e64 v0, v8, 0, vcc_lo
 ; GFX10-NEXT:    v_cndmask_b32_e64 v1, v9, 0, vcc_lo
 ; GFX10-NEXT:    v_cndmask_b32_e64 v2, v4, 0, s4
 ; GFX10-NEXT:    v_cndmask_b32_e64 v3, v5, 0, s4
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_usubsat_v2i64:
+; GFX11:       ; %bb.0:
+; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT:    v_sub_co_u32 v8, vcc_lo, v0, v4
+; GFX11-NEXT:    v_sub_co_ci_u32_e32 v9, vcc_lo, v1, v5, vcc_lo
+; GFX11-NEXT:    v_cmp_lt_u64_e32 vcc_lo, v[0:1], v[4:5]
+; GFX11-NEXT:    v_sub_co_u32 v4, s0, v2, v6
+; GFX11-NEXT:    v_sub_co_ci_u32_e64 v5, s0, v3, v7, s0
+; GFX11-NEXT:    v_cmp_lt_u64_e64 s0, v[2:3], v[6:7]
+; GFX11-NEXT:    v_cndmask_b32_e64 v0, v8, 0, vcc_lo
+; GFX11-NEXT:    v_cndmask_b32_e64 v1, v9, 0, vcc_lo
+; GFX11-NEXT:    v_cndmask_b32_e64 v2, v4, 0, s0
+; GFX11-NEXT:    v_cndmask_b32_e64 v3, v5, 0, s0
+; GFX11-NEXT:    s_setpc_b64 s[30:31]
   %result = call <2 x i64> @llvm.usub.sat.v2i64(<2 x i64> %lhs, <2 x i64> %rhs)
   ret <2 x i64> %result
 }
 
 define amdgpu_ps <2 x i64> @s_usubsat_v2i64(<2 x i64> inreg %lhs, <2 x i64> inreg %rhs) {
 ; GFX6-LABEL: s_usubsat_v2i64:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s4

 ; GFX9-NEXT:    v_cndmask_b32_e64 v0, v4, 0, vcc
 ; GFX9-NEXT:    v_cndmask_b32_e64 v1, v5, 0, vcc
 ; GFX9-NEXT:    v_readfirstlane_b32 s0, v2
 ; GFX9-NEXT:    v_readfirstlane_b32 s1, v3
 ; GFX9-NEXT:    v_readfirstlane_b32 s2, v0
 ; GFX9-NEXT:    v_readfirstlane_b32 s3, v1
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
-; GFX10-LABEL: s_usubsat_v2i64:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    s_sub_u32 s8, s0, s4
-; GFX10-NEXT:    v_cmp_lt_u64_e64 s4, s[0:1], s[4:5]
-; GFX10-NEXT:    s_subb_u32 s1, s1, s5
-; GFX10-NEXT:    s_sub_u32 s0, s2, s6
-; GFX10-NEXT:    v_cmp_lt_u64_e64 s2, s[2:3], s[6:7]
-; GFX10-NEXT:    v_cndmask_b32_e64 v1, s1, 0, s4
-; GFX10-NEXT:    s_subb_u32 s1, s3, s7
-; GFX10-NEXT:    v_cndmask_b32_e64 v0, s8, 0, s4
-; GFX10-NEXT:    v_cndmask_b32_e64 v2, s0, 0, s2
-; GFX10-NEXT:    v_cndmask_b32_e64 v3, s1, 0, s2
-; GFX10-NEXT:    v_readfirstlane_b32 s1, v1
-; GFX10-NEXT:    v_readfirstlane_b32 s0, v0
-; GFX10-NEXT:    v_readfirstlane_b32 s2, v2
-; GFX10-NEXT:    v_readfirstlane_b32 s3, v3
-; GFX10-NEXT:    ; return to shader part epilog
+; GFX10PLUS-LABEL: s_usubsat_v2i64:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    s_sub_u32 s8, s0, s4
+; GFX10PLUS-NEXT:    v_cmp_lt_u64_e64 s4, s[0:1], s[4:5]
+; GFX10PLUS-NEXT:    s_subb_u32 s1, s1, s5
+; GFX10PLUS-NEXT:    s_sub_u32 s0, s2, s6
+; GFX10PLUS-NEXT:    v_cmp_lt_u64_e64 s2, s[2:3], s[6:7]
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v1, s1, 0, s4
+; GFX10PLUS-NEXT:    s_subb_u32 s1, s3, s7
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v0, s8, 0, s4
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v2, s0, 0, s2
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v3, s1, 0, s2
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s1, v1
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s0, v0
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s2, v2
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s3, v3
+; GFX10PLUS-NEXT:    ; return to shader part epilog
   %result = call <2 x i64> @llvm.usub.sat.v2i64(<2 x i64> %lhs, <2 x i64> %rhs)
   ret <2 x i64> %result
 }
 
 define amdgpu_ps i128 @s_usubsat_i128(i128 inreg %lhs, i128 inreg %rhs) {
 ; GFX6-LABEL: s_usubsat_i128:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    v_mov_b32_e32 v2, s4

 ; GFX9-NEXT:    v_cndmask_b32_e64 v2, v2, 0, vcc
 ; GFX9-NEXT:    v_cndmask_b32_e64 v3, v3, 0, vcc
 ; GFX9-NEXT:    v_readfirstlane_b32 s0, v0
 ; GFX9-NEXT:    v_readfirstlane_b32 s1, v1
 ; GFX9-NEXT:    v_readfirstlane_b32 s2, v2
 ; GFX9-NEXT:    v_readfirstlane_b32 s3, v3
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
-; GFX10-LABEL: s_usubsat_i128:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    s_sub_u32 s8, s0, s4
-; GFX10-NEXT:    v_cmp_lt_u64_e64 s0, s[0:1], s[4:5]
-; GFX10-NEXT:    s_subb_u32 s9, s1, s5
-; GFX10-NEXT:    s_subb_u32 s10, s2, s6
-; GFX10-NEXT:    s_subb_u32 s11, s3, s7
-; GFX10-NEXT:    s_cmp_eq_u64 s[2:3], s[6:7]
-; GFX10-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
-; GFX10-NEXT:    v_cmp_lt_u64_e64 s0, s[2:3], s[6:7]
-; GFX10-NEXT:    s_cselect_b32 s12, 1, 0
-; GFX10-NEXT:    v_cndmask_b32_e64 v1, 0, 1, s0
-; GFX10-NEXT:    s_and_b32 s0, 1, s12
-; GFX10-NEXT:    v_cmp_ne_u32_e64 vcc_lo, 0, s0
-; GFX10-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc_lo
-; GFX10-NEXT:    v_and_b32_e32 v0, 1, v0
-; GFX10-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v0
-; GFX10-NEXT:    v_cndmask_b32_e64 v0, s8, 0, vcc_lo
-; GFX10-NEXT:    v_cndmask_b32_e64 v1, s9, 0, vcc_lo
-; GFX10-NEXT:    v_cndmask_b32_e64 v2, s10, 0, vcc_lo
-; GFX10-NEXT:    v_cndmask_b32_e64 v3, s11, 0, vcc_lo
-; GFX10-NEXT:    v_readfirstlane_b32 s0, v0
-; GFX10-NEXT:    v_readfirstlane_b32 s1, v1
-; GFX10-NEXT:    v_readfirstlane_b32 s2, v2
-; GFX10-NEXT:    v_readfirstlane_b32 s3, v3
-; GFX10-NEXT:    ; return to shader part epilog
+; GFX10PLUS-LABEL: s_usubsat_i128:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    s_sub_u32 s8, s0, s4
+; GFX10PLUS-NEXT:    v_cmp_lt_u64_e64 s0, s[0:1], s[4:5]
+; GFX10PLUS-NEXT:    s_subb_u32 s9, s1, s5
+; GFX10PLUS-NEXT:    s_subb_u32 s10, s2, s6
+; GFX10PLUS-NEXT:    s_subb_u32 s11, s3, s7
+; GFX10PLUS-NEXT:    s_cmp_eq_u64 s[2:3], s[6:7]
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; GFX10PLUS-NEXT:    v_cmp_lt_u64_e64 s0, s[2:3], s[6:7]
+; GFX10PLUS-NEXT:    s_cselect_b32 s12, 1, 0
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v1, 0, 1, s0
+; GFX10PLUS-NEXT:    s_and_b32 s0, 1, s12
+; GFX10PLUS-NEXT:    v_cmp_ne_u32_e64 vcc_lo, 0, s0
+; GFX10PLUS-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc_lo
+; GFX10PLUS-NEXT:    v_and_b32_e32 v0, 1, v0
+; GFX10PLUS-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v0
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v0, s8, 0, vcc_lo
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v1, s9, 0, vcc_lo
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v2, s10, 0, vcc_lo
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v3, s11, 0, vcc_lo
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s0, v0
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s1, v1
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s2, v2
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s3, v3
+; GFX10PLUS-NEXT:    ; return to shader part epilog
   %result = call i128 @llvm.usub.sat.i128(i128 %lhs, i128 %rhs)
   ret i128 %result
 }
 
 define amdgpu_ps <4 x float> @usubsat_i128_sv(i128 inreg %lhs, i128 %rhs) {
 ; GFX6-LABEL: usubsat_i128_sv:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    v_mov_b32_e32 v4, s1

 ; GFX9-NEXT:    v_and_b32_e32 v0, 1, v0
 ; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
 ; GFX9-NEXT:    v_cndmask_b32_e64 v0, v5, 0, vcc
 ; GFX9-NEXT:    v_cndmask_b32_e64 v1, v4, 0, vcc
 ; GFX9-NEXT:    v_cndmask_b32_e64 v2, v6, 0, vcc
 ; GFX9-NEXT:    v_cndmask_b32_e64 v3, v7, 0, vcc
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
-; GFX10-LABEL: usubsat_i128_sv:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_cmp_lt_u64_e32 vcc_lo, s[0:1], v[0:1]
-; GFX10-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc_lo
-; GFX10-NEXT:    v_cmp_lt_u64_e32 vcc_lo, s[2:3], v[2:3]
-; GFX10-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc_lo
-; GFX10-NEXT:    v_cmp_eq_u64_e32 vcc_lo, s[2:3], v[2:3]
-; GFX10-NEXT:    v_cndmask_b32_e32 v4, v5, v4, vcc_lo
-; GFX10-NEXT:    v_sub_co_u32 v0, vcc_lo, s0, v0
-; GFX10-NEXT:    v_sub_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
-; GFX10-NEXT:    v_and_b32_e32 v4, 1, v4
-; GFX10-NEXT:    v_sub_co_ci_u32_e32 v2, vcc_lo, s2, v2, vcc_lo
-; GFX10-NEXT:    v_sub_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
-; GFX10-NEXT:    v_cmp_ne_u32_e64 s0, 0, v4
-; GFX10-NEXT:    v_cndmask_b32_e64 v0, v0, 0, s0
-; GFX10-NEXT:    v_cndmask_b32_e64 v1, v1, 0, s0
-; GFX10-NEXT:    v_cndmask_b32_e64 v2, v2, 0, s0
-; GFX10-NEXT:    v_cndmask_b32_e64 v3, v3, 0, s0
-; GFX10-NEXT:    ; return to shader part epilog
+; GFX10PLUS-LABEL: usubsat_i128_sv:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    v_cmp_lt_u64_e32 vcc_lo, s[0:1], v[0:1]
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc_lo
+; GFX10PLUS-NEXT:    v_cmp_lt_u64_e32 vcc_lo, s[2:3], v[2:3]
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc_lo
+; GFX10PLUS-NEXT:    v_cmp_eq_u64_e32 vcc_lo, s[2:3], v[2:3]
+; GFX10PLUS-NEXT:    v_cndmask_b32_e32 v4, v5, v4, vcc_lo
+; GFX10PLUS-NEXT:    v_sub_co_u32 v0, vcc_lo, s0, v0
+; GFX10PLUS-NEXT:    v_sub_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
+; GFX10PLUS-NEXT:    v_and_b32_e32 v4, 1, v4
+; GFX10PLUS-NEXT:    v_sub_co_ci_u32_e32 v2, vcc_lo, s2, v2, vcc_lo
+; GFX10PLUS-NEXT:    v_sub_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
+; GFX10PLUS-NEXT:    v_cmp_ne_u32_e64 s0, 0, v4
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v0, v0, 0, s0
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v1, v1, 0, s0
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v2, v2, 0, s0
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v3, v3, 0, s0
+; GFX10PLUS-NEXT:    ; return to shader part epilog
   %result = call i128 @llvm.usub.sat.i128(i128 %lhs, i128 %rhs)
   %cast = bitcast i128 %result to <4 x float>
   ret <4 x float> %cast
 }
 
 define amdgpu_ps <4 x float> @usubsat_i128_vs(i128 %lhs, i128 inreg %rhs) {
 ; GFX6-LABEL: usubsat_i128_vs:
 ; GFX6:       ; %bb.0:

 ; GFX9-NEXT:    v_and_b32_e32 v0, 1, v0
 ; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
 ; GFX9-NEXT:    v_cndmask_b32_e64 v0, v5, 0, vcc
 ; GFX9-NEXT:    v_cndmask_b32_e64 v1, v4, 0, vcc
 ; GFX9-NEXT:    v_cndmask_b32_e64 v2, v6, 0, vcc
 ; GFX9-NEXT:    v_cndmask_b32_e64 v3, v7, 0, vcc
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
-; GFX10-LABEL: usubsat_i128_vs:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_cmp_gt_u64_e32 vcc_lo, s[0:1], v[0:1]
-; GFX10-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc_lo
-; GFX10-NEXT:    v_cmp_gt_u64_e32 vcc_lo, s[2:3], v[2:3]
-; GFX10-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc_lo
-; GFX10-NEXT:    v_cmp_eq_u64_e32 vcc_lo, s[2:3], v[2:3]
-; GFX10-NEXT:    v_cndmask_b32_e32 v4, v5, v4, vcc_lo
-; GFX10-NEXT:    v_sub_co_u32 v0, vcc_lo, v0, s0
-; GFX10-NEXT:    v_subrev_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
-; GFX10-NEXT:    v_and_b32_e32 v4, 1, v4
-; GFX10-NEXT:    v_subrev_co_ci_u32_e32 v2, vcc_lo, s2, v2, vcc_lo
-; GFX10-NEXT:    v_subrev_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
-; GFX10-NEXT:    v_cmp_ne_u32_e64 s0, 0, v4
-; GFX10-NEXT:    v_cndmask_b32_e64 v0, v0, 0, s0
-; GFX10-NEXT:    v_cndmask_b32_e64 v1, v1, 0, s0
-; GFX10-NEXT:    v_cndmask_b32_e64 v2, v2, 0, s0
-; GFX10-NEXT:    v_cndmask_b32_e64 v3, v3, 0, s0
-; GFX10-NEXT:    ; return to shader part epilog
+; GFX10PLUS-LABEL: usubsat_i128_vs:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    v_cmp_gt_u64_e32 vcc_lo, s[0:1], v[0:1]
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc_lo
+; GFX10PLUS-NEXT:    v_cmp_gt_u64_e32 vcc_lo, s[2:3], v[2:3]
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc_lo
+; GFX10PLUS-NEXT:    v_cmp_eq_u64_e32 vcc_lo, s[2:3], v[2:3]
+; GFX10PLUS-NEXT:    v_cndmask_b32_e32 v4, v5, v4, vcc_lo
+; GFX10PLUS-NEXT:    v_sub_co_u32 v0, vcc_lo, v0, s0
+; GFX10PLUS-NEXT:    v_subrev_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
+; GFX10PLUS-NEXT:    v_and_b32_e32 v4, 1, v4
+; GFX10PLUS-NEXT:    v_subrev_co_ci_u32_e32 v2, vcc_lo, s2, v2, vcc_lo
+; GFX10PLUS-NEXT:    v_subrev_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
+; GFX10PLUS-NEXT:    v_cmp_ne_u32_e64 s0, 0, v4
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v0, v0, 0, s0
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v1, v1, 0, s0
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v2, v2, 0, s0
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v3, v3, 0, s0
+; GFX10PLUS-NEXT:    ; return to shader part epilog
   %result = call i128 @llvm.usub.sat.i128(i128 %lhs, i128 %rhs)
   %cast = bitcast i128 %result to <4 x float>
   ret <4 x float> %cast
 }
 
 define <2 x i128> @v_usubsat_v2i128(<2 x i128> %lhs, <2 x i128> %rhs) {
 ; GFX6-LABEL: v_usubsat_v2i128:
 ; GFX6:       ; %bb.0:

 ; GFX10-NEXT:    v_cndmask_b32_e64 v1, v1, 0, s4
 ; GFX10-NEXT:    v_cndmask_b32_e64 v2, v2, 0, s4
 ; GFX10-NEXT:    v_cndmask_b32_e64 v3, v3, 0, s4
 ; GFX10-NEXT:    v_cndmask_b32_e64 v4, v4, 0, s5
 ; GFX10-NEXT:    v_cndmask_b32_e64 v5, v5, 0, s5
 ; GFX10-NEXT:    v_cndmask_b32_e64 v6, v6, 0, s5
 ; GFX10-NEXT:    v_cndmask_b32_e64 v7, v7, 0, s5
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_usubsat_v2i128:
+; GFX11:       ; %bb.0:
+; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT:    v_cmp_lt_u64_e32 vcc_lo, v[0:1], v[8:9]
+; GFX11-NEXT:    v_cmp_eq_u64_e64 s1, v[6:7], v[14:15]
+; GFX11-NEXT:    v_cndmask_b32_e64 v16, 0, 1, vcc_lo
+; GFX11-NEXT:    v_cmp_lt_u64_e32 vcc_lo, v[2:3], v[10:11]
+; GFX11-NEXT:    v_cndmask_b32_e64 v17, 0, 1, vcc_lo
+; GFX11-NEXT:    v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[10:11]
+; GFX11-NEXT:    v_cndmask_b32_e32 v16, v17, v16, vcc_lo
+; GFX11-NEXT:    v_cmp_lt_u64_e32 vcc_lo, v[4:5], v[12:13]
+; GFX11-NEXT:    v_and_b32_e32 v16, 1, v16
+; GFX11-NEXT:    v_cndmask_b32_e64 v17, 0, 1, vcc_lo
+; GFX11-NEXT:    v_cmp_lt_u64_e32 vcc_lo, v[6:7], v[14:15]
+; GFX11-NEXT:    v_cmp_ne_u32_e64 s0, 0, v16
+; GFX11-NEXT:    v_cndmask_b32_e64 v18, 0, 1, vcc_lo
+; GFX11-NEXT:    v_sub_co_u32 v0, vcc_lo, v0, v8
+; GFX11-NEXT:    v_sub_co_ci_u32_e32 v1, vcc_lo, v1, v9, vcc_lo
+; GFX11-NEXT:    v_cndmask_b32_e64 v8, v18, v17, s1
+; GFX11-NEXT:    v_sub_co_ci_u32_e32 v2, vcc_lo, v2, v10, vcc_lo
+; GFX11-NEXT:    v_sub_co_ci_u32_e32 v3, vcc_lo, v3, v11, vcc_lo
+; GFX11-NEXT:    v_sub_co_u32 v4, vcc_lo, v4, v12
+; GFX11-NEXT:    v_and_b32_e32 v8, 1, v8
+; GFX11-NEXT:    v_sub_co_ci_u32_e32 v5, vcc_lo, v5, v13, vcc_lo
+; GFX11-NEXT:    v_sub_co_ci_u32_e32 v6, vcc_lo, v6, v14, vcc_lo
+; GFX11-NEXT:    v_cmp_ne_u32_e64 s1, 0, v8
+; GFX11-NEXT:    v_sub_co_ci_u32_e32 v7, vcc_lo, v7, v15, vcc_lo
+; GFX11-NEXT:    v_cndmask_b32_e64 v0, v0, 0, s0
+; GFX11-NEXT:    v_cndmask_b32_e64 v1, v1, 0, s0
+; GFX11-NEXT:    v_cndmask_b32_e64 v2, v2, 0, s0
+; GFX11-NEXT:    v_cndmask_b32_e64 v3, v3, 0, s0
+; GFX11-NEXT:    v_cndmask_b32_e64 v4, v4, 0, s1
+; GFX11-NEXT:    v_cndmask_b32_e64 v5, v5, 0, s1
+; GFX11-NEXT:    v_cndmask_b32_e64 v6, v6, 0, s1
+; GFX11-NEXT:    v_cndmask_b32_e64 v7, v7, 0, s1
+; GFX11-NEXT:    s_setpc_b64 s[30:31]
   %result = call <2 x i128> @llvm.usub.sat.v2i128(<2 x i128> %lhs, <2 x i128> %rhs)
   ret <2 x i128> %result
 }
 
 define amdgpu_ps <2 x i128> @s_usubsat_v2i128(<2 x i128> inreg %lhs, <2 x i128> inreg %rhs) {
 ; GFX6-LABEL: s_usubsat_v2i128:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    v_mov_b32_e32 v2, s8

 ; GFX9-NEXT:    v_readfirstlane_b32 s2, v6
 ; GFX9-NEXT:    v_readfirstlane_b32 s3, v7
 ; GFX9-NEXT:    v_readfirstlane_b32 s4, v0
 ; GFX9-NEXT:    v_readfirstlane_b32 s5, v1
 ; GFX9-NEXT:    v_readfirstlane_b32 s6, v2
 ; GFX9-NEXT:    v_readfirstlane_b32 s7, v3
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
-; GFX10-LABEL: s_usubsat_v2i128:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    s_sub_u32 s16, s0, s8
-; GFX10-NEXT:    v_cmp_lt_u64_e64 s0, s[0:1], s[8:9]
-; GFX10-NEXT:    s_subb_u32 s17, s1, s9
-; GFX10-NEXT:    s_subb_u32 s18, s2, s10
-; GFX10-NEXT:    s_subb_u32 s19, s3, s11
-; GFX10-NEXT:    s_cmp_eq_u64 s[2:3], s[10:11]
-; GFX10-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
-; GFX10-NEXT:    v_cmp_lt_u64_e64 s0, s[2:3], s[10:11]
-; GFX10-NEXT:    s_cselect_b32 s20, 1, 0
-; GFX10-NEXT:    v_cndmask_b32_e64 v1, 0, 1, s0
-; GFX10-NEXT:    s_and_b32 s0, 1, s20
-; GFX10-NEXT:    s_sub_u32 s2, s4, s12
-; GFX10-NEXT:    v_cmp_lt_u64_e64 s4, s[4:5], s[12:13]
-; GFX10-NEXT:    v_cmp_ne_u32_e64 vcc_lo, 0, s0
-; GFX10-NEXT:    s_subb_u32 s1, s5, s13
-; GFX10-NEXT:    s_subb_u32 s8, s6, s14
-; GFX10-NEXT:    s_subb_u32 s3, s7, s15
-; GFX10-NEXT:    s_cmp_eq_u64 s[6:7], s[14:15]
-; GFX10-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc_lo
-; GFX10-NEXT:    v_cndmask_b32_e64 v1, 0, 1, s4
-; GFX10-NEXT:    v_cmp_lt_u64_e64 s4, s[6:7], s[14:15]
-; GFX10-NEXT:    s_cselect_b32 s0, 1, 0
-; GFX10-NEXT:    s_and_b32 s0, 1, s0
-; GFX10-NEXT:    v_and_b32_e32 v0, 1, v0
-; GFX10-NEXT:    v_cmp_ne_u32_e64 vcc_lo, 0, s0
-; GFX10-NEXT:    v_cndmask_b32_e64 v2, 0, 1, s4
-; GFX10-NEXT:    v_cndmask_b32_e32 v1, v2, v1, vcc_lo
-; GFX10-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v0
-; GFX10-NEXT:    v_and_b32_e32 v1, 1, v1
-; GFX10-NEXT:    v_cndmask_b32_e64 v0, s16, 0, vcc_lo
-; GFX10-NEXT:    v_cndmask_b32_e64 v2, s18, 0, vcc_lo
-; GFX10-NEXT:    v_cndmask_b32_e64 v3, s19, 0, vcc_lo
-; GFX10-NEXT:    v_cmp_ne_u32_e64 s0, 0, v1
-; GFX10-NEXT:    v_cndmask_b32_e64 v1, s17, 0, vcc_lo
-; GFX10-NEXT:    v_cndmask_b32_e64 v4, s2, 0, s0
-; GFX10-NEXT:    v_cndmask_b32_e64 v5, s1, 0, s0
-; GFX10-NEXT:    v_cndmask_b32_e64 v6, s8, 0, s0
-; GFX10-NEXT:    v_cndmask_b32_e64 v7, s3, 0, s0
-; GFX10-NEXT:    v_readfirstlane_b32 s0, v0
-; GFX10-NEXT:    v_readfirstlane_b32 s1, v1
-; GFX10-NEXT:    v_readfirstlane_b32 s2, v2
-; GFX10-NEXT:    v_readfirstlane_b32 s3, v3
-; GFX10-NEXT:    v_readfirstlane_b32 s4, v4
-; GFX10-NEXT:    v_readfirstlane_b32 s5, v5
-; GFX10-NEXT:    v_readfirstlane_b32 s6, v6
-; GFX10-NEXT:    v_readfirstlane_b32 s7, v7
-; GFX10-NEXT:    ; return to shader part epilog
+; GFX10PLUS-LABEL: s_usubsat_v2i128:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    s_sub_u32 s16, s0, s8
+; GFX10PLUS-NEXT:    v_cmp_lt_u64_e64 s0, s[0:1], s[8:9]
+; GFX10PLUS-NEXT:    s_subb_u32 s17, s1, s9
+; GFX10PLUS-NEXT:    s_subb_u32 s18, s2, s10
+; GFX10PLUS-NEXT:    s_subb_u32 s19, s3, s11
+; GFX10PLUS-NEXT:    s_cmp_eq_u64 s[2:3], s[10:11]
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; GFX10PLUS-NEXT:    v_cmp_lt_u64_e64 s0, s[2:3], s[10:11]
+; GFX10PLUS-NEXT:    s_cselect_b32 s20, 1, 0
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v1, 0, 1, s0
+; GFX10PLUS-NEXT:    s_and_b32 s0, 1, s20
+; GFX10PLUS-NEXT:    s_sub_u32 s2, s4, s12
+; GFX10PLUS-NEXT:    v_cmp_lt_u64_e64 s4, s[4:5], s[12:13]
+; GFX10PLUS-NEXT:    v_cmp_ne_u32_e64 vcc_lo, 0, s0
+; GFX10PLUS-NEXT:    s_subb_u32 s1, s5, s13
+; GFX10PLUS-NEXT:    s_subb_u32 s8, s6, s14
+; GFX10PLUS-NEXT:    s_subb_u32 s3, s7, s15
+; GFX10PLUS-NEXT:    s_cmp_eq_u64 s[6:7], s[14:15]
+; GFX10PLUS-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc_lo
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v1, 0, 1, s4
+; GFX10PLUS-NEXT:    v_cmp_lt_u64_e64 s4, s[6:7], s[14:15]
+; GFX10PLUS-NEXT:    s_cselect_b32 s0, 1, 0
+; GFX10PLUS-NEXT:    s_and_b32 s0, 1, s0
+; GFX10PLUS-NEXT:    v_and_b32_e32 v0, 1, v0
+; GFX10PLUS-NEXT:    v_cmp_ne_u32_e64 vcc_lo, 0, s0
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v2, 0, 1, s4
+; GFX10PLUS-NEXT:    v_cndmask_b32_e32 v1, v2, v1, vcc_lo
+; GFX10PLUS-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v0
+; GFX10PLUS-NEXT:    v_and_b32_e32 v1, 1, v1
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v0, s16, 0, vcc_lo
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v2, s18, 0, vcc_lo
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v3, s19, 0, vcc_lo
+; GFX10PLUS-NEXT:    v_cmp_ne_u32_e64 s0, 0, v1
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v1, s17, 0, vcc_lo
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v4, s2, 0, s0
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v5, s1, 0, s0
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v6, s8, 0, s0
+; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v7, s3, 0, s0
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s0, v0
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s1, v1
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s2, v2
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s3, v3
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s4, v4
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s5, v5
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s6, v6
+; GFX10PLUS-NEXT:    v_readfirstlane_b32 s7, v7
+; GFX10PLUS-NEXT:    ; return to shader part epilog
   %result = call <2 x i128> @llvm.usub.sat.v2i128(<2 x i128> %lhs, <2 x i128> %rhs)
   ret <2 x i128> %result
 }
 
 declare i7 @llvm.usub.sat.i7(i7, i7) #0
 declare i8 @llvm.usub.sat.i8(i8, i8) #0
 declare <2 x i8> @llvm.usub.sat.v2i8(<2 x i8>, <2 x i8>) #0
 declare <4 x i8> @llvm.usub.sat.v4i8(<4 x i8>, <4 x i8>) #0

llvm/test/CodeGen/AMDGPU/build_vector.ll

 ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefixes=R600,ALL
-; RUN: llc < %s -march=amdgcn -verify-machineinstrs | FileCheck %s --check-prefixes=SI,GFX6,GFX678,ALL
-; RUN: llc < %s -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs | FileCheck %s --check-prefixes=SI,GFX8,GFX678,ALL
-; RUN: llc < %s -mtriple=amdgcn-amd-amdpal -mcpu=gfx1030 -verify-machineinstrs | FileCheck %s --check-prefixes=GFX10,SI,ALL
+; RUN: llc < %s -march=amdgcn -verify-machineinstrs | FileCheck %s --check-prefixes=GFX6,GFX678,ALL
+; RUN: llc < %s -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs | FileCheck %s --check-prefixes=GFX8,GFX678,ALL
+; RUN: llc < %s -mtriple=amdgcn-amd-amdpal -mcpu=gfx1030 -verify-machineinstrs | FileCheck %s --check-prefixes=GFX10,GFX1011,ALL
+; RUN: llc < %s -mtriple=amdgcn-amd-amdpal -mcpu=gfx1100 -verify-machineinstrs | FileCheck %s --check-prefixes=GFX11,GFX1011,ALL
 
 ; ALL-LABEL: {{^}}build_vector2:
 ; R600: MOV
 ; R600: MOV
 ; R600-NOT: MOV
-; SI-DAG: v_mov_b32_e32 v[[X:[0-9]]], 5
-; SI-DAG: v_mov_b32_e32 v[[Y:[0-9]]], 6
+; GFX678-DAG: v_mov_b32_e32 v[[X:[0-9]]], 5
+; GFX678-DAG: v_mov_b32_e32 v[[Y:[0-9]]], 6
+; GFX1011-DAG: v_mov_b32_e32 v[[X:[0-9]]], 5
+; GFX1011-DAG: v_mov_b32_e32 v[[Y:[0-9]]], 6
 ; GFX678: buffer_store_dwordx2 v[[[X]]:[[Y]]]
 ; GFX10: global_store_dwordx2 v2, v[0:1], s[0:1]
+; GFX11: global_store_b64 v2, v[0:1], s[0:1]
 define amdgpu_kernel void @build_vector2 (<2 x i32> addrspace(1)* %out) {
 entry:
   store <2 x i32> <i32 5, i32 6>, <2 x i32> addrspace(1)* %out
   ret void
 }
 
 ; ALL-LABEL: {{^}}build_vector4:
 ; R600: MOV
 ; R600: MOV
 ; R600: MOV
 ; R600: MOV
 ; R600-NOT: MOV
-; SI-DAG: v_mov_b32_e32 v[[X:[0-9]]], 5
-; SI-DAG: v_mov_b32_e32 v[[Y:[0-9]]], 6
-; SI-DAG: v_mov_b32_e32 v[[Z:[0-9]]], 7
-; SI-DAG: v_mov_b32_e32 v[[W:[0-9]]], 8
+; GFX678-DAG: v_mov_b32_e32 v[[X:[0-9]]], 5
+; GFX678-DAG: v_mov_b32_e32 v[[Y:[0-9]]], 6
+; GFX678-DAG: v_mov_b32_e32 v[[Z:[0-9]]], 7
+; GFX678-DAG: v_mov_b32_e32 v[[W:[0-9]]], 8
+; GFX1011-DAG: v_mov_b32_e32 v[[X:[0-9]]], 5
+; GFX1011-DAG: v_mov_b32_e32 v[[Y:[0-9]]], 6
+; GFX1011-DAG: v_mov_b32_e32 v[[Z:[0-9]]], 7
+; GFX1011-DAG: v_mov_b32_e32 v[[W:[0-9]]], 8
 ; GFX678: buffer_store_dwordx4 v[[[X]]:[[W]]]
 ; GFX10: global_store_dwordx4 v4, v[0:3], s[0:1]
+; GFX11: global_store_b128 v4, v[0:3], s[0:1]
 define amdgpu_kernel void @build_vector4 (<4 x i32> addrspace(1)* %out) {
 entry:
   store <4 x i32> <i32 5, i32 6, i32 7, i32 8>, <4 x i32> addrspace(1)* %out
   ret void
 }
 
 
 ; ALL-LABEL: {{^}}build_vector_v2i16:
 ; R600: MOV
 ; R600-NOT: MOV
 ; GFX678: s_mov_b32 s3, 0xf000
 ; GFX678: s_mov_b32 s2, -1
 ; GFX678: v_mov_b32_e32 v0, 0x60005
 ; GFX678: s_waitcnt lgkmcnt(0)
 ; GFX678: buffer_store_dword v0, off, s[0:3], 0
-; GFX10: v_mov_b32_e32 v0, 0
-; GFX10: v_mov_b32_e32 v1, 0x60005
-; GFX10: s_waitcnt lgkmcnt(0)
+; GFX1011: v_mov_b32_e32 v0, 0
+; GFX1011: v_mov_b32_e32 v1, 0x60005
+; GFX1011: s_waitcnt lgkmcnt(0)
 ; GFX10: global_store_dword v0, v1, s[0:1]
+; GFX11: global_store_b32 v0, v1, s[0:1]
 define amdgpu_kernel void @build_vector_v2i16 (<2 x i16> addrspace(1)* %out) {
 entry:
   store <2 x i16> <i16 5, i16 6>, <2 x i16> addrspace(1)* %out
   ret void
 }
 
 ; ALL-LABEL: {{^}}build_vector_v2i16_trunc:
 ; R600: LSHR

 ; GFX6: buffer_store_dword v0, off, s[0:3], 0
 ; GFX8: s_mov_b32 s3, 0xf000
 ; GFX8: s_mov_b32 s2, -1
 ; GFX8: s_waitcnt lgkmcnt(0)
 ; GFX8: s_lshr_b32 s4, s4, 16
 ; GFX8: s_or_b32 s4, s4, 0x50000
 ; GFX8: v_mov_b32_e32 v0, s4
 ; GFX8: buffer_store_dword v0, off, s[0:3], 0
-; GFX10: v_mov_b32_e32 v0, 0
-; GFX10: s_waitcnt lgkmcnt(0)
+; GFX1011: v_mov_b32_e32 v0, 0
+; GFX1011: s_waitcnt lgkmcnt(0)
 ; GFX10: s_lshr_b32 s2, s2, 16
 ; GFX10: s_pack_ll_b32_b16 s2, s2, 5
-; GFX10: v_mov_b32_e32 v1, s2
+; GFX11: s_pack_hl_b32_b16 s2, s2, 5
+; GFX1011: v_mov_b32_e32 v1, s2
 ; GFX10: global_store_dword v0, v1, s[0:1]
+; GFX11: global_store_b32 v0, v1, s[0:1]
 define amdgpu_kernel void @build_vector_v2i16_trunc (<2 x i16> addrspace(1)* %out, i32 %a) {
   %srl = lshr i32 %a, 16
   %trunc = trunc i32 %srl to i16
   %ins.0 = insertelement <2 x i16> undef, i16 %trunc, i32 0
   %ins.1 = insertelement <2 x i16> %ins.0, i16 5, i32 1
   store <2 x i16> %ins.1, <2 x i16> addrspace(1)* %out
   ret void
 }