[trace] Add a flag to the decoder to output the instruction type

[persona0220]

Summary

To build complex binding upon instruction trace, additional metadata 'instruction type' is needed.

This diff has followings:

• Add a flag -k / --kind for instruction dump
• Remove SetGranularity and SetIgnoreErros from Trace cursor

Sample output:

(lldb) thread trace dump instruction -k
thread #1: tid = 3198805
  libc.so.6`_IO_puts + 356
    2107: 0x00007ffff7163594 (    return)     retq
    2106: 0x00007ffff7163592 (     other)     popq   %r13
    2105: 0x00007ffff7163590 (     other)     popq   %r12
    2104: 0x00007ffff716358f (     other)     popq   %rbp
    2103: 0x00007ffff716358e (     other)     popq   %rbx
    2102: 0x00007ffff716358c (     other)     movl   %ebx, %eax
    2101: 0x00007ffff7163588 (     other)     addq   $0x8, %rsp
    2100: 0x00007ffff7163570 ( cond jump)     je     0x89588                   ; <+344>
    2099: 0x00007ffff716356e (     other)     decl   (%rdx)
    2098: 0x00007ffff7163565 ( cond jump)     je     0x8956e                   ; <+318>
    2097: 0x00007ffff716355e (     other)     cmpl   $0x0, 0x33c02b(%rip)      ; __libc_multiple_threads
    2096: 0x00007ffff7163556 (     other)     movq   $0x0, 0x8(%rdx)
    2095: 0x00007ffff7163554 ( cond jump)     jne    0x89588                   ; <+344>
    2094: 0x00007ffff7163550 (     other)     subl   $0x1, 0x4(%rdx)
    2093: 0x00007ffff7163549 (     other)     movq   0x88(%rbp), %rdx
    2092: 0x00007ffff7163547 ( cond jump)     jne    0x89588                   ; <+344>
    2091: 0x00007ffff7163540 (     other)     testl  $0x8000, (%rbp)           ; imm = 0x8000
    2090: 0x00007ffff716353c (     other)     cmovaq %rax, %rbx
    2089: 0x00007ffff7163535 (     other)     cmpq   $0x7fffffff, %rbx         ; imm = 0x7FFFFFFF
    2088: 0x00007ffff7163530 (     other)     movl   $0x7fffffff, %eax         ; imm = 0x7FFFFFFF

[jingham]

This categorization seems like it is relevant for any instruction, not just instructions found in a trace buffer. Is there any reason why this isn't just an annotation added by the standard instruction printer, that you then turn on with the -k flag to thread trace dump (but which might also be useful for the regular disassemble command)?

[wallace]

@jingham, that's a pretty good idea. We'll see how to implement it

[jj10306]

Thanks for working on this 🙂
Looks good overall, just left some minor comments.

lldb/include/lldb/Target/TraceCursor.h

64 ↗

(On Diff #439560)

For some reason I can't make inline suggestions, so I'll just put my suggested edit below:

s/which direction/which uses the current direction of the trace

lldb/include/lldb/Target/TraceInstructionDumper.h

105–107 ↗

(On Diff #439560)

Don't forget to rebase onto mainline, @wallace's recent diff (https://reviews.llvm.org/D128316) refactored some of this code, so that will effect where some of these new changes should live.

lldb/source/Commands/Options.td

1132

nit: add a period at the end of the description (:

lldb/source/Plugins/Trace/intel-pt/TraceCursorIntelPT.cpp

46–50 ↗

(On Diff #439560)

Apologies again bc I can't "Suggest Edits" inline, so leaving my suggestion in a code block below:

IIUC, we previously had a while loop here because the possibility of "skipping" instructions due to ignoring errors or not matching the granularity. Since this diff removes those two things, this logic can now be simplified since the trace cursor can no longer skip the instructions - below is roughly what I'm thinking:

bool TraceCursorIntelPT::Next() {
  auto canMoveOne = [&]() {
    if (IsForwards())
      return m_pos + 1 < GetInternalInstructionSize();
    return m_pos > 0;
  };

  if (!canMoveOne())
    return false;

  m_pos += IsForwards() ? 1 : -1;
  if (m_tsc_range && !m_tsc_range->InRange(m_pos))
    m_tsc_range = IsForwards() ? m_tsc_range->Next() : m_tsc_range->Prev();

  return true;
}

@wallace wdyt?

[persona0220]

This new diff attach additional metadata 'control flow kind' for instruction.
Add '-k / --kind' flag for both disassemble and thread trace dump command.

Thanks to @jingham for the suggestion!

Sample output:

(lldb) disas -k
a.out`main:
    0x4005b6 <+0>:  other     pushq  %rbp
    0x4005b7 <+1>:  other     movq   %rsp, %rbp
    0x4005ba <+4>:  other     movl   $0x400668, %edi           ; imm = 0x400668
    0x4005bf <+9>:  call      callq  0x4004c0                  ; symbol stub for: puts
->  0x4005c4 <+14>: other     movl   $0x0, %eax
    0x4005c9 <+19>: other     popq   %rbp
    0x4005ca <+20>: return    retq

(lldb) thread trace dump instruction --kind
    thread #1: tid = 1893259
  libc.so.6`write + 30
    2027: 0x00007ffff71fa86e    cond jump ja     0x1208c8                  ; <+120>
    2026: 0x00007ffff71fa868    other     cmpq   $-0x1000, %rax            ; imm = 0xF000
    2025: 0x00007ffff71fa866    far call  syscall
    2024: 0x00007ffff71fa861    other     movl   $0x1, %eax
    2023: 0x00007ffff71fa85f    cond jump jne    0x120878                  ; <+40>
    2022: 0x00007ffff71fa85d    other     testl  %eax, %eax
    2021: 0x00007ffff71fa85b    other     movl   (%rax), %eax
    2020: 0x00007ffff71fa854    other     leaq   0x2a4d35(%rip), %rax      ; __libc_multiple_threads
    2019: 0x00007ffff71fa850    other     endbr64

[wallace]

remove unwanted files

[wallace]

lldb/include/lldb/Core/Disassembler.h

82–86

as this code is new, please write documentation and function names should be in PascalCase. Try to have a more descriptive name as well, because instruction_decode is very vague.

152–153

let's try to be more explicit with the naming

226–233

add documentation. Also, if this mapping is intel-specific, I recommend moving this to the cpp file so that it's not exposed publicly. The Disassembler is architecture agnostic, so its API should try to remain that way

332

name

389

lldb/include/lldb/Target/TraceCursor.h

35 ↗

(On Diff #440806)

this file has changed, could you rebase from upstream/main.

230–234 ↗

(On Diff #440806)

when you rebase, could you delete any references to this method and its implementation as well? We won't use it anymore

lldb/include/lldb/Target/TraceInstructionDumper.h

38 ↗

(On Diff #440806)

name

lldb/include/lldb/lldb-enumerations.h

973–996

this doesn't need to be a FLAGS_ENUM anymore (i.e. bitmask), you can use a simple enum instead, like the ExpressionEvaluationPhase above

lldb/source/API/SBInstruction.cpp

244–245

include this kind of comment wherever you have added this parameter

lldb/source/Commands/CommandObjectDisassemble.h

49

ame

[wallace]

nice job!!

lldb/source/Commands/Options.td

304

mention here the enum to inspect for documentation. Besides that, you can quickly mention here that far jumps and far returns often indicate a kernel calls and returns. That might be enough because the other categories are pretty intuitive

1159

same here

lldb/source/Core/Disassembler.cpp

682

you have to check here that the triple of the current architecture of the current target (you can get that from exe_ctx) is x86, otherwise directly return eInstructionControlFlowTypeUnknown. You can just rely on the check you are doing in line 685 because that check might fail in the future

683

from this point on, the code is specifically meant for x86, so I recommend creating a x86 namespace in this file and include a GetControlFlowInstructionKind method along with the instruction_decode method there. That way we organize the code in a more cleaner manner

683

add a comment explaining what these variables are

694

add a comment explaining what this prefix handling is actually doing

717

you can move this to the beginning of the function and assume that this mapping is x86 only, which is how it should be

775

you can also mention here how this mapping is actually generated and were you got inspiration from, like libipt

949

should you remove this?

952

unknown

lldb/source/Plugins/Trace/intel-pt/DecodedThread.cpp

63 ↗

(On Diff #440808)

remove this, because we won't use it anymore

[persona0220]

• Modify function name instruction_decode into DecodeInstructionOpcode
• explicit naming for flag show_kind -> show_control_flow_kind
• Convert InstructionControlFlowType FLAG_ENUM into simple enum
• Create x86 namespace in Disassembler.cpp to decode instruction.

[persona0220]

nit

[wallace]

much better! Thanks for doing this.

There are two main things to do.

1. The algorithm you are using to classify the instructions uses too many acronyms and it's very well documented. Try to make it understandable enough so that anyone with little familiarity can have an idea of what is happening
2. write a unit test. For this, you can follow any of the tests in lldb/unittests/Disassembler/. In order to run it, you'll need to do ninja DisassemblerTests and then run the output path printed by that command. It uses gtest. You can see the tests in that folder for inspiration.

lldb/include/lldb/Core/Disassembler.h

82

better this

84

Rename this to

GetControlFlowKind

because we are already inside the Instruction

lldb/include/lldb/lldb-enumerations.h

976

lldb/source/API/SBInstruction.cpp

244–245

the llvm style requires a =

279–280

same here

lldb/source/API/SBInstructionList.cpp

169

ditto

lldb/source/Commands/Options.td

306

1161

copy the changes from above

lldb/source/Core/Disassembler.cpp

575

add documentation mentioning what a PTI_MAP is. Try to make the documentation clear enough for anyone without knowledge of this matter. Also, mention what modrm is why it's important here.
Also, it's better if don't use the PTI acronym but instead use the full name. It'd make it easier to read.
Also, this is an enum and not a map, so better use an identifier different than a map

584–586

let's be more specific

695–696

another reference to opcode, modrm, and map bytes. I recommend writing extensive documentation in PTI_MAP and then mention here that the full documentation can be found in the PTI_MAP definition

703–704

this comment is not useful because this method is in the x86 namespace

710–713

789–790

you use exe_ctx->GetTargetRef().GetArchitecture().GetMachine() != llvm::Triple::ArchType::x86_64 a lot. What about creating a variable that holds this comparison?

847–848

use { } in this else, because the if already used it

[persona0220]

• Terms ‘control flow kind’ and ‘control flow type’ was mixed across source codes -> Unify into ‘control flow kind’
• Divide the ‘GetControlFlowKind’ function into two functions:
  • InstructionLengthDecode: Decode raw instruction bytes into opcode, modrm and map.
  • MapOpcodeIntoControlFlowKind: Get control flow find from opcode, modrm and map.
• Add detailed comments for each new functions.

[persona0220]

Add some more documentation

[wallace]

let's try to have tests soon. It seems that the code can be simplified and tests will be very handy

lldb/include/lldb/lldb-enumerations.h

976

lldb/source/Core/Disassembler.cpp

730–740

I'm noticing that MapOpcodeIntoControlFlowKind only uses PTI_MAP_0 and PTI_MAP_1, which are opcodes of 1 and 2 bytes. Any opcode of 3 bytes and even amd3dnow is not used at all. That means that you don't need that enum, so please delete it. Instead, use the length of the opcode throughout the code.

882

does this mean that all x86 and x86_64 instructions are categorized as Opcode::Type::eTypeBytes?
I'm asking because after reading GetOpcodeBytes, it only returns data if the type is eTypeBytes. Did you check that?

885

you don't need to copy GetOpcodeBytes, you can just pass it directly to InstructionLengthDecode

[persona0220]

• Delete PTI_MAP enum and use opcode_len instead.
• Add a unit test
  • Divide existing Disassembler test into x86 / ARM subdirectory
  • Unittests/Disassembler/x86/TestGetControlFlowKindx86.cpp tests categorizing x86_64 instructions
• Modify GetControlFlowKind function to get ArchSpec instead of exe_ctx

[wallace]

almost there! I like the tests btw :)

lldb/source/Commands/Options.td

304

1159

same

lldb/source/Core/Disassembler.cpp

578

588

592–594

705

734–736

We try not to use out parameters this way. Instead, create a new struct InstructionOpcodeAndModrm with the three values that are important to you. Then, change this function to return Optional<InstructionOpcodeAndModrm>, where the None case means that decoding failed

lldb/unittests/Disassembler/x86/TestGetControlFlowKindx86.cpp

29–30

delete if not used

[persona0220]

Added a struct InstructionOpcodeAndModrm, which contains primary_opcode, opcode_len and modrm bytes decoded from InstructionLengthDecode function.

[wallace]

I'll commit this for you

lldb/include/lldb/Core/Disassembler.h

const char *GetOperands(const ExecutionContext *exe_ctx) {
     return m_mnemonics.c_str();
   }
 
   const char *GetComment(const ExecutionContext *exe_ctx) {
     CalculateMnemonicOperandsAndCommentIfNeeded(exe_ctx);
     return m_comment.c_str();
   }
 
+  /// \return
+  ///    The control flow kind of this instruction, or
+  ///    eInstructionControlFlowKindUnknown if the instruction
+  ///    can't be classified.
+  lldb::InstructionControlFlowKind GetControlFlowKind(const ArchSpec &arch);
+
   virtual void
   CalculateMnemonicOperandsAndComment(const ExecutionContext *exe_ctx) = 0;
 
   AddressClass GetAddressClass();
 
   void SetAddress(const Address &addr) {
     // Invalidate the address class to lazily discover it if we need to.
     m_address_class = AddressClass::eInvalid;
public:
   ///
   /// \param[in] show_address
   ///     Whether the address (using disassembly_addr_format_spec formatting)
   ///     should be printed.
   ///
   /// \param[in] show_bytes
   ///     Whether the bytes of the assembly instruction should be printed.
   ///
+  /// \param[in] show_control_flow_kind
+  ///     Whether the control flow kind of the instruction should be printed.
+  ///
   /// \param[in] max_opcode_byte_size
   ///     The size (in bytes) of the largest instruction in the list that
   ///     we are printing (for text justification/alignment purposes)
   ///     Only needed if show_bytes is true.
   ///
   /// \param[in] exe_ctx
   ///     The current execution context, if available.  May be used in
   ///     the assembling of the operands+comments for this instruction.
public:
   ///
   /// \param[in] max_address_text_size
   ///     The length of the longest address string at the start of the
   ///     disassembly line that will be printed (the
   ///     Debugger::FormatDisassemblerAddress() string)
   ///     so this method can properly align the instruction opcodes.
   ///     May be 0 to indicate no indentation/alignment of the opcodes.
   virtual void Dump(Stream *s, uint32_t max_opcode_byte_size, bool show_address,
-                    bool show_bytes, const ExecutionContext *exe_ctx,
+                    bool show_bytes, bool show_control_flow_kind,
+                    const ExecutionContext *exe_ctx,
                     const SymbolContext *sym_ctx,
                     const SymbolContext *prev_sym_ctx,
                     const FormatEntity::Entry *disassembly_addr_format,
                     size_t max_address_text_size);
 
   virtual bool DoesBranch() = 0;
 
   virtual bool HasDelaySlot();
public:
   };
 
   virtual bool ParseOperands(llvm::SmallVectorImpl<Operand> &operands) {
     return false;
   }
 
   virtual bool IsCall() { return false; }
 
 protected:
   Address m_address; // The section offset address of this instruction
                      // We include an address class in the Instruction class to
                      // allow the instruction specify the
                      // AddressClass::eCodeAlternateISA (currently used for
                      // thumb), and also to specify data (AddressClass::eData).
                      // The usual value will be AddressClass::eCode, but often
                      // when disassembling memory, you might run into data.
                      // This can help us to disassemble appropriately.
 private:
   AddressClass m_address_class; // Use GetAddressClass () accessor function!
 
 protected:
   Opcode m_opcode; // The opcode for this instruction
   std::string m_opcode_name;
   std::string m_mnemonics;
uint32_t GetIndexOfInstructionAtLoadAddress(lldb::addr_t load_addr,
                                               Target &target);
 
   uint32_t GetIndexOfInstructionAtAddress(const Address &addr);
 
   void Clear();
 
   void Append(lldb::InstructionSP &inst_sp);
 
   void Dump(Stream *s, bool show_address, bool show_bytes,
-            const ExecutionContext *exe_ctx);
+            bool show_control_flow_kind, const ExecutionContext *exe_ctx);
 
 private:
   typedef std::vector<lldb::InstructionSP> collection;
   typedef collection::iterator iterator;
   typedef collection::const_iterator const_iterator;
 
   collection m_instructions;
 };

 public:
   enum {
     eOptionNone = 0u,
     eOptionShowBytes = (1u << 0),
     eOptionRawOuput = (1u << 1),
     eOptionMarkPCSourceLine = (1u << 2), // Mark the source line that contains
                                          // the current PC (mixed mode only)
     eOptionMarkPCAddress =
-        (1u << 3) // Mark the disassembly line the contains the PC
+        (1u << 3), // Mark the disassembly line the contains the PC
+    eOptionShowControlFlowKind = (1u << 4),
   };
 
   enum HexImmediateStyle {
     eHexStyleC,
     eHexStyleAsm,
   };
 
   // FindPlugin should be lax about the flavor string (it is too annoying to

lldb/include/lldb/Target/TraceDumper.h

struct TraceDumperOptions {
   bool json = false;
   /// When dumping in JSON format, pretty print the output.
   bool pretty_print_json = false;
   /// For each instruction, print the corresponding timestamp counter if
   /// available.
   bool show_tsc = false;
   /// Dump the events that happened between instructions.
   bool show_events = false;
+  /// For each instruction, print the instruction kind.
+  bool show_control_flow_kind = false;
   /// Optional custom id to start traversing from.
   llvm::Optional<uint64_t> id = llvm::None;
   /// Optional number of instructions to skip from the starting position
   /// of the cursor.
   llvm::Optional<size_t> skip = llvm::None;
 };
 
 /// Class used to dump the instructions of a \a TraceCursor using its current

lldb/include/lldb/lldb-enumerations.h

enum ExpressionEvaluationPhase {
   eExpressionEvaluationExecution,
   eExpressionEvaluationComplete
 };
 
 /// Architecture-agnostic categorization of instructions for traversing the
 /// control flow of a trace.
 ///
 /// A single instruction can match one or more of these categories.
-FLAGS_ENUM(TraceInstructionControlFlowType){
-    /// Any instruction.
-    eTraceInstructionControlFlowTypeInstruction = (1u << 1),
-    /// A conditional or unconditional branch/jump.
-    eTraceInstructionControlFlowTypeBranch = (1u << 2),
-    /// A conditional or unconditional branch/jump that changed
-    /// the control flow of the program.
-    eTraceInstructionControlFlowTypeTakenBranch = (1u << 3),
-    /// A call to a function.
-    eTraceInstructionControlFlowTypeCall = (1u << 4),
-    /// A return from a function.
-    eTraceInstructionControlFlowTypeReturn = (1u << 5)};
-
-LLDB_MARK_AS_BITMASK_ENUM(TraceInstructionControlFlowType)
+enum InstructionControlFlowKind {
+  /// The instruction could not be classified.
+  eInstructionControlFlowKindUnknown = 0,
+  /// The instruction is something not listed below, i.e. it's a sequential
+  /// instruction that doesn't affect the control flow of the program.
+  eInstructionControlFlowKindOther,
+  /// The instruction is a near (function) call.
+  eInstructionControlFlowKindCall,
+  /// The instruction is a near (function) return.
+  eInstructionControlFlowKindReturn,
+  /// The instruction is a near unconditional jump.
+  eInstructionControlFlowKindJump,
+  /// The instruction is a near conditional jump.
+  eInstructionControlFlowKindCondJump,
+  /// The instruction is a call-like far transfer.
+  /// E.g. SYSCALL, SYSENTER, or FAR CALL.
+  eInstructionControlFlowKindFarCall,
+  /// The instruction is a return-like far transfer.
+  /// E.g. SYSRET, SYSEXIT, IRET, or FAR RET.
+  eInstructionControlFlowKindFarReturn,
+  /// The instruction is a jump-like far transfer.
+  /// E.g. FAR JMP.
+  eInstructionControlFlowKindFarJump
+};
 
 /// Watchpoint Kind.
 ///
 /// Indicates what types of events cause the watchpoint to fire. Used by Native
 /// *Protocol-related classes.
 FLAGS_ENUM(WatchpointKind){eWatchpointKindWrite = (1u << 0),
                            eWatchpointKindRead = (1u << 1)};
 

lldb/source/API/SBInstruction.cpp

if (inst_sp) {
     ModuleSP module_sp(addr.GetModule());
     if (module_sp)
       module_sp->ResolveSymbolContextForAddress(addr, eSymbolContextEverything,
                                                 sc);
     // Use the "ref()" instead of the "get()" accessor in case the SBStream
     // didn't have a stream already created, one will get created...
     FormatEntity::Entry format;
     FormatEntity::Parse("${addr}: ", format);
-    inst_sp->Dump(&s.ref(), 0, true, false, nullptr, &sc, nullptr, &format, 0);
+    inst_sp->Dump(&s.ref(), 0, true, false, /*show_control_flow_kind=*/false,
+                  nullptr, &sc, nullptr, &format, 0);
     return true;
   }
   return false;
 }
 
 void SBInstruction::Print(FILE *outp) {
   LLDB_INSTRUMENT_VA(this, outp);
   FileSP out = std::make_shared<NativeFile>(outp, /*take_ownership=*/false);
if (inst_sp) {
     const Address &addr = inst_sp->GetAddress();
     ModuleSP module_sp(addr.GetModule());
     if (module_sp)
       module_sp->ResolveSymbolContextForAddress(addr, eSymbolContextEverything,
                                                 sc);
     StreamFile out_stream(out_sp);
     FormatEntity::Entry format;
     FormatEntity::Parse("${addr}: ", format);
-    inst_sp->Dump(&out_stream, 0, true, false, nullptr, &sc, nullptr, &format,
-                  0);
+    inst_sp->Dump(&out_stream, 0, true, false, /*show_control_flow_kind=*/false,
+                  nullptr, &sc, nullptr, &format, 0);
   }
 }
 
 bool SBInstruction::EmulateWithFrame(lldb::SBFrame &frame,
                                      uint32_t evaluate_options) {
   LLDB_INSTRUMENT_VA(this, frame, evaluate_options);
 
   lldb::InstructionSP inst_sp(GetOpaque());

lldb/source/API/SBInstructionList.cpp

if (num_instructions) {
         const Address &addr = inst->GetAddress();
         prev_sc = sc;
         ModuleSP module_sp(addr.GetModule());
         if (module_sp) {
           module_sp->ResolveSymbolContextForAddress(
               addr, eSymbolContextEverything, sc);
         }
 
-        inst->Dump(&sref, max_opcode_byte_size, true, false, nullptr, &sc,
-                   &prev_sc, &format, 0);
+        inst->Dump(&sref, max_opcode_byte_size, true, false,
+                   /*show_control_flow_kind=*/false, nullptr, &sc, &prev_sc,
+                   &format, 0);
         sref.EOL();
       }
       return true;
     }
   }
   return false;
 }
 

lldb/source/Commands/CommandObjectDisassemble.h

const char *GetFlavorString() {
         return nullptr;
       return flavor_string.c_str();
     }
 
     Status OptionParsingFinished(ExecutionContext *execution_context) override;
 
     bool show_mixed; // Show mixed source/assembly
     bool show_bytes;
+    bool show_control_flow_kind;
     uint32_t num_lines_context = 0;
     uint32_t num_instructions = 0;
     bool raw;
     std::string func_name;
     bool current_function = false;
     lldb::addr_t start_addr = 0;
     lldb::addr_t end_addr = 0;
     bool at_pc = false;

lldb/source/Commands/CommandObjectDisassemble.cpp

if (option_arg.getAsInteger(0, num_instructions))
           "invalid num of instructions string: \"%s\"",
           option_arg.str().c_str());
     break;
 
   case 'b':
     show_bytes = true;
     break;
 
+  case 'k':
+    show_control_flow_kind = true;
+    break;
+
   case 's': {
     start_addr = OptionArgParser::ToAddress(execution_context, option_arg,
                                             LLDB_INVALID_ADDRESS, &error);
     if (start_addr != LLDB_INVALID_ADDRESS)
       some_location_specified = true;
   } break;
   case 'e': {
     end_addr = OptionArgParser::ToAddress(execution_context, option_arg,
Status CommandObjectDisassemble::CommandOptions::SetOptionValue(
 
   return error;
 }
 
 void CommandObjectDisassemble::CommandOptions::OptionParsingStarting(
     ExecutionContext *execution_context) {
   show_mixed = false;
   show_bytes = false;
+  show_control_flow_kind = false;
   num_lines_context = 0;
   num_instructions = 0;
   func_name.clear();
   current_function = false;
   at_pc = false;
   frame_line = false;
   start_addr = LLDB_INVALID_ADDRESS;
   end_addr = LLDB_INVALID_ADDRESS;
bool CommandObjectDisassemble::DoExecute(Args &command,
   // Mark the source line for the current PC only if we are doing mixed source
   // and assembly
   if (m_options.show_mixed)
     options |= Disassembler::eOptionMarkPCSourceLine;
 
   if (m_options.show_bytes)
     options |= Disassembler::eOptionShowBytes;
 
+  if (m_options.show_control_flow_kind)
+    options |= Disassembler::eOptionShowControlFlowKind;
+
   if (m_options.raw)
     options |= Disassembler::eOptionRawOuput;
 
   llvm::Expected<std::vector<AddressRange>> ranges =
       GetRangesForSelectedMode(result);
   if (!ranges) {
     result.AppendError(toString(ranges.takeError()));
     return result.Succeeded();

lldb/source/Commands/CommandObjectThread.cpp

Status SetOptionValue(uint32_t option_idx, llvm::StringRef option_arg,
       case 'r': {
         m_dumper_options.raw = true;
         break;
       }
       case 'f': {
         m_dumper_options.forwards = true;
         break;
       }
+      case 'k': {
+        m_dumper_options.show_control_flow_kind = true;
+        break;
+      }
       case 't': {
         m_dumper_options.show_tsc = true;
         break;
       }
       case 'e': {
         m_dumper_options.show_events = true;
         break;
       }

lldb/source/Commands/Options.td

def breakpoint_command_delete_dummy_breakpoints :
     Option<"dummy-breakpoints", "D">, Group<1>,
     Desc<"Delete commands from Dummy breakpoints - i.e. breakpoints set before "
     "a file is provided, which prime new targets.">;
 }
 
 let Command = "disassemble" in {
   def disassemble_options_bytes : Option<"bytes", "b">,
     Desc<"Show opcode bytes when disassembling.">;
+  def disassemble_options_kind : Option<"kind", "k">,
+    Desc<"Show instruction control flow kind. Refer to the enum "
+    "`InstructionControlFlowKind` for a list of control flow kind. "
+    "As an important note, far jumps, far calls and far returns often indicate "
+    "calls to and from kernel.">;
   def disassemble_options_context : Option<"context", "C">, Arg<"NumLines">,
     Desc<"Number of context lines of source to show.">;
   def disassemble_options_mixed : Option<"mixed", "m">,
     Desc<"Enable mixed source and assembly display.">;
   def disassemble_options_raw : Option<"raw", "r">,
     Desc<"Print raw disassembly with no symbol information.">;
   def disassemble_options_plugin : Option<"plugin", "P">, Arg<"Plugin">,
     Desc<"Name of the disassembler plugin you want to use.">;

 
 let Command = "thread trace dump instructions" in {
   def thread_trace_dump_instructions_forwards: Option<"forwards", "f">,
     Group<1>,
     Desc<"If specified, the trace is traversed forwards chronologically "
     "starting at the oldest instruction. Otherwise, it starts at the most "
     "recent one and the traversal is backwards.">;
   def thread_trace_dump_instructions_count : Option<"count", "c">, Group<1>,
     Arg<"Count">,
     Desc<"The number of instructions to display starting at the most recent "
     "instruction, or the oldest if --forwards is provided.">;
   def thread_trace_dump_instructions_all : Option<"all", "a">, Group<1>,
     Desc<"From the starting point of the trace, dump all instructions "
     "available.">;
   def thread_trace_dump_instructions_id: Option<"id", "i">, Group<1>,
     Arg<"Index">,
     Desc<"Custom starting instruction id from where to start traversing. This "
def thread_trace_dump_instructions_file : Option<"file", "F">, Group<1>,
     Arg<"Filename">,
     Desc<"Dump the instruction to a file instead of the standard output.">;
   def thread_trace_dump_instructions_json: Option<"json", "j">,
     Group<1>,
     Desc<"Dump in simple JSON format.">;
   def thread_trace_dump_instructions_pretty_print: Option<"pretty-json", "J">,
     Group<1>,
     Desc<"Dump in JSON format but pretty printing the output for easier readability.">;
+  def thread_trace_dump_instructions_show_kind : Option<"kind", "k">, Group<1>,
+    Desc<"Show instruction control flow kind. Refer to the enum "
+    "`InstructionControlFlowKind` for a list of control flow kind. "
+    "As an important note, far jumps, far calls and far returns often indicate "
+    "calls to and from kernel.">;
   def thread_trace_dump_instructions_show_tsc : Option<"tsc", "t">, Group<1>,
     Desc<"For each instruction, print the corresponding timestamp counter if "
     "available.">;
   def thread_trace_dump_instructions_show_events : Option<"events", "e">,
     Group<1>,
     Desc<"Dump the events that happened during the execution of the target.">;
   def thread_trace_dump_instructions_continue: Option<"continue", "C">,
     Group<1>,

lldb/source/Core/Disassembler.cpp

if (inst) {
           source_manager.DisplaySourceLinesWithLineNumbers(
               ln.file, ln.line, ln.column, 0, 0, line_highlight, &strm);
         }
         if (source_lines_to_display.print_source_context_end_eol)
           strm.EOL();
       }
 
       const bool show_bytes = (options & eOptionShowBytes) != 0;
-      inst->Dump(&strm, max_opcode_byte_size, true, show_bytes, &exe_ctx, &sc,
-                 &prev_sc, nullptr, address_text_size);
+      const bool show_control_flow_kind =
+          (options & eOptionShowControlFlowKind) != 0;
+      inst->Dump(&strm, max_opcode_byte_size, true, show_bytes,
+                 show_control_flow_kind, &exe_ctx, &sc, &prev_sc, nullptr,
+                 address_text_size);
       strm.EOL();
     } else {
       break;
     }
   }
 }
 
 bool Disassembler::Disassemble(Debugger &debugger, const ArchSpec &arch,

 }
 
 Instruction::Instruction(const Address &address, AddressClass addr_class)
     : m_address(address), m_address_class(addr_class), m_opcode(),
       m_calculated_strings(false) {}
 
 Instruction::~Instruction() = default;
 
+namespace x86 {
+
+/// These are the three values deciding instruction control flow kind.
+/// InstructionLengthDecode function decodes an instruction and get this struct.
+///
+/// primary_opcode
+///    Primary opcode of the instruction.
+///    For one-byte opcode instruction, it's the first byte after prefix.
+///    For two- and three-byte opcodes, it's the second byte.
+///
+/// opcode_len
+///    The length of opcode in bytes. Valid opcode lengths are 1, 2, or 3.
+///
+/// modrm
+///    ModR/M byte of the instruction.
+///    Bits[7:6] indicate MOD. Bits[5:3] specify a register and R/M bits[2:0]
+///    may contain a register or specify an addressing mode, depending on MOD.
+struct InstructionOpcodeAndModrm {
+  uint8_t primary_opcode;
+  uint8_t opcode_len;
+  uint8_t modrm;
+};
+
+/// Determine the InstructionControlFlowKind based on opcode and modrm bytes.
+/// Refer to http://ref.x86asm.net/coder.html for the full list of opcode and
+/// instruction set.
+///
+/// \param[in] opcode_and_modrm
+///    Contains primary_opcode byte, its length, and ModR/M byte.
+///    Refer to the struct InstructionOpcodeAndModrm for details.
+///
+/// \return
+///   The control flow kind of the instruction or
+///   eInstructionControlFlowKindOther if the instruction doesn't affect
+///   the control flow of the program.
+lldb::InstructionControlFlowKind
+MapOpcodeIntoControlFlowKind(InstructionOpcodeAndModrm opcode_and_modrm) {
+  uint8_t opcode = opcode_and_modrm.primary_opcode;
+  uint8_t opcode_len = opcode_and_modrm.opcode_len;
+  uint8_t modrm = opcode_and_modrm.modrm;
+
+  if (opcode_len > 2)
+    return lldb::eInstructionControlFlowKindOther;
+
+  if (opcode >= 0x70 && opcode <= 0x7F) {
+    if (opcode_len == 1)
+      return lldb::eInstructionControlFlowKindCondJump;
+    else
+      return lldb::eInstructionControlFlowKindOther;
+  }
+
+  if (opcode >= 0x80 && opcode <= 0x8F) {
+    if (opcode_len == 2)
+      return lldb::eInstructionControlFlowKindCondJump;
+    else
+      return lldb::eInstructionControlFlowKindOther;
+  }
+
+  switch (opcode) {
+  case 0x9A:
+    if (opcode_len == 1)
+      return lldb::eInstructionControlFlowKindFarCall;
+    break;
+  case 0xFF:
+    if (opcode_len == 1) {
+      uint8_t modrm_reg = (modrm >> 3) & 7;
+      if (modrm_reg == 2)
+        return lldb::eInstructionControlFlowKindCall;
+      else if (modrm_reg == 3)
+        return lldb::eInstructionControlFlowKindFarCall;
+      else if (modrm_reg == 4)
+        return lldb::eInstructionControlFlowKindJump;
+      else if (modrm_reg == 5)
+        return lldb::eInstructionControlFlowKindFarJump;
+    }
+    break;
+  case 0xE8:
+    if (opcode_len == 1)
+      return lldb::eInstructionControlFlowKindCall;
+    break;
+  case 0xCD:
+  case 0xCC:
+  case 0xCE:
+  case 0xF1:
+    if (opcode_len == 1)
+      return lldb::eInstructionControlFlowKindFarCall;
+    break;
+  case 0xCF:
+    if (opcode_len == 1)
+      return lldb::eInstructionControlFlowKindFarReturn;
+    break;
+  case 0xE9:
+  case 0xEB:
+    if (opcode_len == 1)
+      return lldb::eInstructionControlFlowKindJump;
+    break;
+  case 0xEA:
+    if (opcode_len == 1)
+      return lldb::eInstructionControlFlowKindFarJump;
+    break;
+  case 0xE3:
+  case 0xE0:
+  case 0xE1:
+  case 0xE2:
+    if (opcode_len == 1)
+      return lldb::eInstructionControlFlowKindCondJump;
+    break;
+  case 0xC3:
+  case 0xC2:
+    if (opcode_len == 1)
+      return lldb::eInstructionControlFlowKindReturn;
+    break;
+  case 0xCB:
+  case 0xCA:
+    if (opcode_len == 1)
+      return lldb::eInstructionControlFlowKindFarReturn;
+    break;
+  case 0x05:
+  case 0x34:
+    if (opcode_len == 2)
+      return lldb::eInstructionControlFlowKindFarCall;
+    break;
+  case 0x35:
+  case 0x07:
+    if (opcode_len == 2)
+      return lldb::eInstructionControlFlowKindFarReturn;
+    break;
+  case 0x01:
+    if (opcode_len == 2) {
+      switch (modrm) {
+      case 0xc1:
+        return lldb::eInstructionControlFlowKindFarCall;
+      case 0xc2:
+      case 0xc3:
+        return lldb::eInstructionControlFlowKindFarReturn;
+      default:
+        break;
+      }
+    }
+    break;
+  default:
+    break;
+  }
+
+  return lldb::eInstructionControlFlowKindOther;
+}
+
+/// Decode an instruction into opcode, modrm and opcode_len.
+/// Refer to http://ref.x86asm.net/coder.html for the instruction bytes layout.
+/// Opcodes in x86 are generally the first byte of instruction, though two-byte
+/// instructions and prefixes exist. ModR/M is the byte following the opcode
+/// and adds additional information for how the instruction is executed.
+///
+/// \param[in] inst_bytes
+///    Raw bytes of the instruction
+///
+///
+/// \param[in] bytes_len
+///    The length of the inst_bytes array.
+///
+/// \param[in] is_exec_mode_64b
+///    If true, the execution mode is 64 bit.
+///
+/// \return
+///    Returns decoded instruction as struct InstructionOpcodeAndModrm, holding
+///    primary_opcode, opcode_len and modrm byte. Refer to the struct definition
+///    for more details.
+///    Otherwise if the given instruction is invalid, returns None.
+llvm::Optional<InstructionOpcodeAndModrm>
+InstructionLengthDecode(const uint8_t *inst_bytes, int bytes_len,
+                        bool is_exec_mode_64b) {
+  int op_idx = 0;
+  bool prefix_done = false;
+  InstructionOpcodeAndModrm ret = {0, 0, 0};
+
+  // In most cases, the primary_opcode is the first byte of the instruction
+  // but some instructions have a prefix to be skipped for these calculations.
+  // The following mapping is inspired from libipt's instruction decoding logic
+  // in `src/pt_ild.c`
+  while (!prefix_done) {
+    if (op_idx >= bytes_len)
+      return llvm::None;
+
+    ret.primary_opcode = inst_bytes[op_idx];
+    switch (ret.primary_opcode) {
+    // prefix_ignore
+    case 0x26:
+    case 0x2e:
+    case 0x36:
+    case 0x3e:
+    case 0x64:
+    case 0x65:
+    // prefix_osz, prefix_asz
+    case 0x66:
+    case 0x67:
+    // prefix_lock, prefix_f2, prefix_f3
+    case 0xf0:
+    case 0xf2:
+    case 0xf3:
+      op_idx++;
+      break;
+
+    // prefix_rex
+    case 0x40:
+    case 0x41:
+    case 0x42:
+    case 0x43:
+    case 0x44:
+    case 0x45:
+    case 0x46:
+    case 0x47:
+    case 0x48:
+    case 0x49:
+    case 0x4a:
+    case 0x4b:
+    case 0x4c:
+    case 0x4d:
+    case 0x4e:
+    case 0x4f:
+      if (is_exec_mode_64b)
+        op_idx++;
+      else
+        prefix_done = true;
+      break;
+
+    // prefix_vex_c4, c5
+    case 0xc5:
+      if (!is_exec_mode_64b && (inst_bytes[op_idx + 1] & 0xc0) != 0xc0) {
+        prefix_done = true;
+        break;
+      }
+
+      ret.opcode_len = 2;
+      ret.primary_opcode = inst_bytes[op_idx + 2];
+      ret.modrm = inst_bytes[op_idx + 3];
+      return ret;
+
+    case 0xc4:
+      if (!is_exec_mode_64b && (inst_bytes[op_idx + 1] & 0xc0) != 0xc0) {
+        prefix_done = true;
+        break;
+      }
+      ret.opcode_len = inst_bytes[op_idx + 1] & 0x1f;
+      ret.primary_opcode = inst_bytes[op_idx + 3];
+      ret.modrm = inst_bytes[op_idx + 4];
+      return ret;
+
+    // prefix_evex
+    case 0x62:
+      if (!is_exec_mode_64b && (inst_bytes[op_idx + 1] & 0xc0) != 0xc0) {
+        prefix_done = true;
+        break;
+      }
+      ret.opcode_len = inst_bytes[op_idx + 1] & 0x03;
+      ret.primary_opcode = inst_bytes[op_idx + 4];
+      ret.modrm = inst_bytes[op_idx + 5];
+      return ret;
+
+    default:
+      prefix_done = true;
+      break;
+    }
+  } // prefix done
+
+  ret.primary_opcode = inst_bytes[op_idx];
+  ret.modrm = inst_bytes[op_idx + 1];
+  ret.opcode_len = 1;
+
+  // If the first opcode is 0F, it's two- or three- byte opcodes.
+  if (ret.primary_opcode == 0x0F) {
+    ret.primary_opcode = inst_bytes[++op_idx]; // get the next byte
+
+    if (ret.primary_opcode == 0x38) {
+      ret.opcode_len = 3;
+      ret.primary_opcode = inst_bytes[++op_idx]; // get the next byte
+      ret.modrm = inst_bytes[op_idx + 1];
+    } else if (ret.primary_opcode == 0x3A) {
+      ret.opcode_len = 3;
+      ret.primary_opcode = inst_bytes[++op_idx];
+      ret.modrm = inst_bytes[op_idx + 1];
+    } else if ((ret.primary_opcode & 0xf8) == 0x38) {
+      ret.opcode_len = 0;
+      ret.primary_opcode = inst_bytes[++op_idx];
+      ret.modrm = inst_bytes[op_idx + 1];
+    } else if (ret.primary_opcode == 0x0F) {
+      ret.opcode_len = 3;
+      // opcode is 0x0F, no needs to update
+      ret.modrm = inst_bytes[op_idx + 1];
+    } else {
+      ret.opcode_len = 2;
+      ret.modrm = inst_bytes[op_idx + 1];
+    }
+  }
+
+  return ret;
+}
+
+lldb::InstructionControlFlowKind GetControlFlowKind(bool is_exec_mode_64b,
+                                                    Opcode m_opcode) {
+  llvm::Optional<InstructionOpcodeAndModrm> ret = llvm::None;
+
+  if (m_opcode.GetOpcodeBytes() == nullptr || m_opcode.GetByteSize() <= 0) {
+    // x86_64 and i386 instructions are categorized as Opcode::Type::eTypeBytes
+    return lldb::eInstructionControlFlowKindUnknown;
+  }
+
+  // Opcode bytes will be decoded into primary_opcode, modrm and opcode length.
+  // These are the three values deciding instruction control flow kind.
+  ret = InstructionLengthDecode((const uint8_t *)m_opcode.GetOpcodeBytes(),
+                                m_opcode.GetByteSize(), is_exec_mode_64b);
+  if (!ret)
+    return lldb::eInstructionControlFlowKindUnknown;
+  else
+    return MapOpcodeIntoControlFlowKind(ret.value());
+}
+
+} // namespace x86
+
+lldb::InstructionControlFlowKind
+Instruction::GetControlFlowKind(const ArchSpec &arch) {
+  if (arch.GetTriple().getArch() == llvm::Triple::x86)
+    return x86::GetControlFlowKind(/*is_exec_mode_64b=*/false, m_opcode);
+  else if (arch.GetTriple().getArch() == llvm::Triple::x86_64)
+    return x86::GetControlFlowKind(/*is_exec_mode_64b=*/true, m_opcode);
+  else
+    return eInstructionControlFlowKindUnknown; // not implemented
+}
+
 AddressClass Instruction::GetAddressClass() {
   if (m_address_class == AddressClass::eInvalid)
     m_address_class = m_address.GetAddressClass();
   return m_address_class;
 }
 
 void Instruction::Dump(lldb_private::Stream *s, uint32_t max_opcode_byte_size,
                        bool show_address, bool show_bytes,
+                       bool show_control_flow_kind,
                        const ExecutionContext *exe_ctx,
                        const SymbolContext *sym_ctx,
                        const SymbolContext *prev_sym_ctx,
                        const FormatEntity::Entry *disassembly_addr_format,
                        size_t max_address_text_size) {
   size_t opcode_column_width = 7;
   const size_t operand_column_width = 25;
 
if (m_opcode.GetType() == Opcode::eTypeBytes) {
       // (10 spaces) plus two for padding...
       if (max_opcode_byte_size > 0)
         m_opcode.Dump(&ss, max_opcode_byte_size * 3 + 1);
       else
         m_opcode.Dump(&ss, 12);
     }
   }
 
+  if (show_control_flow_kind) {
+    switch (GetControlFlowKind(exe_ctx->GetTargetRef().GetArchitecture())) {
+    case eInstructionControlFlowKindUnknown:
+      ss.Printf("%-12s", "unknown");
+      break;
+    case eInstructionControlFlowKindOther:
+      ss.Printf("%-12s", "other");
+      break;
+    case eInstructionControlFlowKindCall:
+      ss.Printf("%-12s", "call");
+      break;
+    case eInstructionControlFlowKindReturn:
+      ss.Printf("%-12s", "return");
+      break;
+    case eInstructionControlFlowKindJump:
+      ss.Printf("%-12s", "jump");
+      break;
+    case eInstructionControlFlowKindCondJump:
+      ss.Printf("%-12s", "cond jump");
+      break;
+    case eInstructionControlFlowKindFarCall:
+      ss.Printf("%-12s", "far call");
+      break;
+    case eInstructionControlFlowKindFarReturn:
+      ss.Printf("%-12s", "far return");
+      break;
+    case eInstructionControlFlowKindFarJump:
+      ss.Printf("%-12s", "far jump");
+      break;
+    }
+  }
+
   const size_t opcode_pos = ss.GetSizeOfLastLine();
 
   // The default opcode size of 7 characters is plenty for most architectures
   // but some like arm can pull out the occasional vqrshrun.s16.  We won't get
   // consistent column spacing in these cases, unfortunately.
   if (m_opcode_name.length() >= opcode_column_width) {
     opcode_column_width = m_opcode_name.length() + 1;
   }

 InstructionSP InstructionList::GetInstructionAtAddress(const Address &address) {
   uint32_t index = GetIndexOfInstructionAtAddress(address);
   if (index != UINT32_MAX)
     return GetInstructionAtIndex(index);
   return nullptr;
 }
 
 void InstructionList::Dump(Stream *s, bool show_address, bool show_bytes,
+                           bool show_control_flow_kind,
                            const ExecutionContext *exe_ctx) {
   const uint32_t max_opcode_byte_size = GetMaxOpcocdeByteSize();
   collection::const_iterator pos, begin, end;
 
   const FormatEntity::Entry *disassembly_format = nullptr;
   FormatEntity::Entry format;
   if (exe_ctx && exe_ctx->HasTargetScope()) {
     disassembly_format =
         exe_ctx->GetTargetRef().GetDebugger().GetDisassemblyFormat();
   } else {
     FormatEntity::Parse("${addr}: ", format);
     disassembly_format = &format;
   }
 
   for (begin = m_instructions.begin(), end = m_instructions.end(), pos = begin;
        pos != end; ++pos) {
     if (pos != begin)
       s->EOL();
-    (*pos)->Dump(s, max_opcode_byte_size, show_address, show_bytes, exe_ctx,
-                 nullptr, nullptr, disassembly_format, 0);
+    (*pos)->Dump(s, max_opcode_byte_size, show_address, show_bytes,
+                 show_control_flow_kind, exe_ctx, nullptr, nullptr,
+                 disassembly_format, 0);
   }
 }
 
 void InstructionList::Clear() { m_instructions.clear(); }
 
 void InstructionList::Append(lldb::InstructionSP &inst_sp) {
   if (inst_sp)
     m_instructions.push_back(inst_sp);
 }
 
 uint32_t
 InstructionList::GetIndexOfNextBranchInstruction(uint32_t start,
                                                  bool ignore_calls,
                                                  bool *found_calls) const {
   size_t num_instructions = m_instructions.size();
 
   uint32_t next_branch = UINT32_MAX;
-  
   if (found_calls)
     *found_calls = false;
   for (size_t i = start; i < num_instructions; i++) {
     if (m_instructions[i]->DoesBranch()) {
       if (ignore_calls && m_instructions[i]->IsCall()) {
         if (found_calls)
           *found_calls = true;
         continue;

lldb/source/Core/DumpDataExtractor.cpp

if (disassembler_sp) {
       size_t bytes_consumed = disassembler_sp->DecodeInstructions(
           so_addr, DE, start_offset, number_of_instructions, false,
           data_from_file);
 
       if (bytes_consumed) {
         offset += bytes_consumed;
         const bool show_address = base_addr != LLDB_INVALID_ADDRESS;
         const bool show_bytes = true;
+        const bool show_control_flow_kind = true;
         ExecutionContext exe_ctx;
         exe_scope->CalculateExecutionContext(exe_ctx);
-        disassembler_sp->GetInstructionList().Dump(s, show_address, show_bytes,
-                                                   &exe_ctx);
+        disassembler_sp->GetInstructionList().Dump(
+            s, show_address, show_bytes, show_control_flow_kind, &exe_ctx);
       }
     }
   } else
     s->Printf("invalid target");
 
   return offset;
 }
 

lldb/source/Expression/IRExecutionUnit.cpp

if (log) {
     extractor.PutToLog(log, 0, extractor.GetByteSize(), func_remote_addr, 16,
                        DataExtractor::TypeUInt8);
   }
 
   disassembler_sp->DecodeInstructions(Address(func_remote_addr), extractor, 0,
                                       UINT32_MAX, false, false);
 
   InstructionList &instruction_list = disassembler_sp->GetInstructionList();
-  instruction_list.Dump(&stream, true, true, &exe_ctx);
+  instruction_list.Dump(&stream, true, true, /*show_control_flow_kind=*/true,
+                        &exe_ctx);
+
   return ret;
 }
 
 namespace {
 struct IRExecDiagnosticHandler : public llvm::DiagnosticHandler {
   Status *err;
   IRExecDiagnosticHandler(Status *err) : err(err) {}
   bool handleDiagnostics(const llvm::DiagnosticInfo &DI) override {

lldb/source/Plugins/TraceExporter/common/TraceHTR.cpp

while (cursor.HasValue()) { if (cursor.IsError()) {
       // TODO: Make distinction between errors by storing the error messages.
       // Currently, all errors are treated the same.
       m_instruction_layer_up->AppendInstruction(0);
       cursor.Next();
     } else if (cursor.IsEvent()) {
       cursor.Next();
     } else {
       lldb::addr_t current_instruction_load_address = cursor.GetLoadAddress();
-      lldb::TraceInstructionControlFlowType current_instruction_type =
-          cursor.GetInstructionControlFlowType();
+      lldb::InstructionControlFlowKind current_instruction_type =
+          cursor.GetInstructionControlFlowKind();
 
       m_instruction_layer_up->AppendInstruction(
           current_instruction_load_address);
       cursor.Next();
       bool more_data_in_trace = cursor.HasValue();
       if (current_instruction_type &
-          lldb::eTraceInstructionControlFlowTypeCall) {
+          lldb::eInstructionControlFlowKindCall) {
         if (more_data_in_trace && !cursor.IsError()) {
           m_instruction_layer_up->AddCallInstructionMetadata(
               current_instruction_load_address,
               function_name_from_load_address(cursor.GetLoadAddress()));
         } else {
           // Next instruction is not known - pass None to indicate the name
           // of the function being called is not known
           m_instruction_layer_up->AddCallInstructionMetadata(

lldb/source/Plugins/UnwindAssembly/InstEmulation/UnwindAssemblyInstEmulation.cpp

if (range.GetByteSize() > 0 && range.GetBaseAddress().IsValid() &&
     if (disasm_sp) {
 
       m_range_ptr = ⦥
       m_unwind_plan_ptr = &unwind_plan;
 
       const uint32_t addr_byte_size = m_arch.GetAddressByteSize();
       const bool show_address = true;
       const bool show_bytes = true;
+      const bool show_control_flow_kind = true;
       m_inst_emulator_up->GetRegisterInfo(unwind_plan.GetRegisterKind(),
                                           unwind_plan.GetInitialCFARegister(),
                                           m_cfa_reg_info);
 
       m_fp_is_cfa = false;
       m_register_values.clear();
       m_pushed_regs.clear();
 
if (disasm_sp) {
               condition_block_start_offset = current_offset;
             }
 
             if (log && log->GetVerbose()) {
               StreamString strm;
               lldb_private::FormatEntity::Entry format;
               FormatEntity::Parse("${frame.pc}: ", format);
               inst->Dump(&strm, inst_list.GetMaxOpcocdeByteSize(), show_address,
-                         show_bytes, nullptr, nullptr, nullptr, &format, 0);
+                         show_bytes, show_control_flow_kind, nullptr, nullptr,
+                         nullptr, &format, 0);
               log->PutString(strm.GetString());
             }
 
             last_condition = m_inst_emulator_up->GetInstructionCondition();
 
             m_inst_emulator_up->EvaluateInstruction(
                 eEmulateInstructionOptionIgnoreConditions);
 

lldb/source/Symbol/Function.cpp

 bool Function::GetDisassembly(const ExecutionContext &exe_ctx,
                               const char *flavor, Stream &strm,
                               bool prefer_file_cache) {
   lldb::DisassemblerSP disassembler_sp =
       GetInstructions(exe_ctx, flavor, prefer_file_cache);
   if (disassembler_sp) {
     const bool show_address = true;
     const bool show_bytes = false;
-    disassembler_sp->GetInstructionList().Dump(&strm, show_address, show_bytes,
-                                               &exe_ctx);
+    const bool show_control_flow_kind = false;
+    disassembler_sp->GetInstructionList().Dump(
+        &strm, show_address, show_bytes, show_control_flow_kind, &exe_ctx);
     return true;
   }
   return false;
 }
 
 // Symbol *
 // Function::CalculateSymbolContextSymbol ()
 //{

lldb/source/Symbol/Symbol.cpp

 
 bool Symbol::GetDisassembly(const ExecutionContext &exe_ctx, const char *flavor,
                             bool prefer_file_cache, Stream &strm) {
   lldb::DisassemblerSP disassembler_sp =
       GetInstructions(exe_ctx, flavor, prefer_file_cache);
   if (disassembler_sp) {
     const bool show_address = true;
     const bool show_bytes = false;
-    disassembler_sp->GetInstructionList().Dump(&strm, show_address, show_bytes,
-                                               &exe_ctx);
+    const bool show_control_flow_kind = false;
+    disassembler_sp->GetInstructionList().Dump(
+        &strm, show_address, show_bytes, show_control_flow_kind, &exe_ctx);
     return true;
   }
   return false;
 }
 
 bool Symbol::ContainsFileAddress(lldb::addr_t file_addr) const {
   return m_addr_range.ContainsFileAddress(file_addr);
 }

lldb/source/Target/ThreadPlanTracer.cpp

if (err.Success()) {
 
       InstructionList &instruction_list = disassembler->GetInstructionList();
       const uint32_t max_opcode_byte_size =
           instruction_list.GetMaxOpcocdeByteSize();
 
       if (instruction_list.GetSize()) {
         const bool show_bytes = true;
         const bool show_address = true;
+        const bool show_control_flow_kind = true;
         Instruction *instruction =
             instruction_list.GetInstructionAtIndex(0).get();
         const FormatEntity::Entry *disassemble_format =
             m_process.GetTarget().GetDebugger().GetDisassemblyFormat();
         instruction->Dump(stream, max_opcode_byte_size, show_address,
-                          show_bytes, nullptr, nullptr, nullptr,
-                          disassemble_format, 0);
+                          show_bytes, show_control_flow_kind, nullptr, nullptr,
+                          nullptr, disassemble_format, 0);
       }
     }
   }
 
   const ABI *abi = m_process.GetABI().get();
   TypeFromUser intptr_type = GetIntPointerType();
 
   if (abi && intptr_type.IsValid()) {

lldb/source/Target/TraceDumper.cpp

void TraceItem(const TraceDumper::TraceItem &item) override {
     if (item.event) {
       m_s << "(event) " << TraceCursor::EventKindToString(*item.event);
     } else if (item.error) {
       m_s << "(error) " << *item.error;
     } else {
       m_s.Format("{0:x+16}", item.load_address);
       if (item.symbol_info) {
         m_s << "    ";
-        item.symbol_info->instruction->Dump(&m_s, /*max_opcode_byte_size=*/0,
-                                            /*show_address=*/false,
-                                            /*show_bytes=*/false,
-                                            &item.symbol_info->exe_ctx,
-                                            &item.symbol_info->sc,
-                                            /*prev_sym_ctx=*/nullptr,
-                                            /*disassembly_addr_format=*/nullptr,
-                                            /*max_address_text_size=*/0);
+        item.symbol_info->instruction->Dump(
+            &m_s, /*max_opcode_byte_size=*/0,
+            /*show_bytes=*/false, m_options.show_control_flow_kind,
+            &item.symbol_info->exe_ctx, &item.symbol_info->sc,
       }
     }
 
     m_was_prev_instruction_an_error = (bool)item.error;
     m_s << "\n";
   }
 
 private:

lldb/unittests/Disassembler/ARM/CMakeLists.txt

+add_lldb_unittest(DisassemblerTests
+  TestArm64Disassembly.cpp
+  TestArmv7Disassembly.cpp
+  LINK_LIBS
+    lldbCore
+    lldbSymbol
+    lldbTarget
+    lldbPluginDisassemblerLLVMC
+    lldbPluginProcessUtility
+  LINK_COMPONENTS
+    Support
+    ${LLVM_TARGETS_TO_BUILD})

lldb/unittests/Disassembler/CMakeLists.txt

 if("ARM" IN_LIST LLVM_TARGETS_TO_BUILD)
-  add_lldb_unittest(DisassemblerTests
-    TestArm64Disassembly.cpp
-    TestArmv7Disassembly.cpp
-    LINK_LIBS
-      lldbCore
-      lldbSymbol
-      lldbTarget
-      lldbPluginDisassemblerLLVMC
-      lldbPluginProcessUtility
-    LINK_COMPONENTS
-      Support
-      ${LLVM_TARGETS_TO_BUILD})
+  add_subdirectory(ARM)
+endif()
+
+if("X86" IN_LIST LLVM_TARGETS_TO_BUILD)
+  add_subdirectory(x86)
 endif()

lldb/unittests/Disassembler/x86/CMakeLists.txt

+add_lldb_unittest(GetControlFlowKindx86Tests
+    TestGetControlFlowKindx86.cpp
+    LINK_LIBS
+      lldbCore
+      lldbSymbol
+      lldbTarget
+      lldbPluginDisassemblerLLVMC
+      lldbPluginProcessUtility
+    LINK_COMPONENTS
+      Support
+      ${LLVM_TARGETS_TO_BUILD}
+  )

lldb/unittests/Disassembler/x86/TestGetControlFlowKindx86.cpp

+//===-- TextX86GetControlFlowKind.cpp ------------------------------------------===//
+
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "llvm/Support/TargetSelect.h"
+#include "gtest/gtest.h"
+
+#include "lldb/Core/Address.h"
+#include "lldb/Core/Disassembler.h"
+#include "lldb/Target/ExecutionContext.h"
+#include "lldb/Utility/ArchSpec.h"
+
+#include "Plugins/Disassembler/LLVMC/DisassemblerLLVMC.h"
+
+using namespace lldb;
+using namespace lldb_private;
+
+class TestGetControlFlowKindx86 : public testing::Test {
+public:
+  static void SetUpTestCase();
+  static void TearDownTestCase();
+
+protected:
+};
+
+void TestGetControlFlowKindx86::SetUpTestCase() {
+  llvm::InitializeAllTargets();
+  llvm::InitializeAllAsmPrinters();
+  llvm::InitializeAllTargetMCs();
+  llvm::InitializeAllDisassemblers();
+  DisassemblerLLVMC::Initialize();
+}
+
+void TestGetControlFlowKindx86::TearDownTestCase() {
+  DisassemblerLLVMC::Terminate();
+}
+
+TEST_F(TestGetControlFlowKindx86, TestX86_64Instruction) {
+  ArchSpec arch("x86_64-*-linux");
+
+  const unsigned num_of_instructions = 29;
+  uint8_t data[] = {
+      0x55,                               // other -- pushq %rbp
+      0x48, 0x89, 0xe5,                   // other -- movq %rsp, %rbp
+
+      0xe8, 0xfc, 0xfe, 0xff, 0xff,       // call -- callq 0x4004c0
+      0x41, 0xff, 0x14, 0xdc,             // call -- callq *(%r12,%rbx,8)
+      0xff, 0x50, 0x18,                   // call -- callq *0x18(%rax)
+      0xe8, 0x48, 0x0d, 0x00, 0x00,       // call -- callq 0x94fe0
+
+      0xc3,                               // return -- retq
+
+      0xeb, 0xd3,                         // jump -- jmp 0x92dab
+      0xe9, 0x22, 0xff, 0xff, 0xff,       // jump -- jmp 0x933ae
+      0xff, 0xe0,                         // jump -- jmpq *%rax
+      0xf2, 0xff, 0x25, 0x75, 0xe7, 0x39, 0x00, // jump -- repne jmpq *0x39e775
+
+      0x73, 0xc2,                         // cond jump -- jae 0x9515c
+      0x74, 0x1f,                         // cond jump -- je 0x400626
+      0x75, 0xea,                         // cond jump -- jne 0x400610
+      0x76, 0x10,                         // cond jump -- jbe 0x94d10
+      0x77, 0x58,                         // cond jump -- ja 0x1208c8
+      0x7e, 0x67,                         // cond jump -- jle 0x92180
+      0x78, 0x0b,                         // cond jump -- js 0x92dc3
+      0x0f, 0x82, 0x17, 0x01, 0x00, 0x00, // cond jump -- jb 0x9c7b0
+      0x0f, 0x83, 0xa7, 0x00, 0x00, 0x00, // cond jump -- jae 0x895c8
+      0x0f, 0x84, 0x8c, 0x00, 0x00, 0x00, // cond jump -- je 0x941f0
+      0x0f, 0x85, 0x51, 0xff, 0xff, 0xff, // cond jump -- jne 0x8952c
+      0x0f, 0x86, 0xa3, 0x02, 0x00, 0x00, // cond jump -- jbe 0x9ae10
+      0x0f, 0x87, 0xff, 0x00, 0x00, 0x00, // cond jump -- ja 0x9ab60
+      0x0f, 0x8e, 0x7e, 0x00, 0x00, 0x00, // cond jump -- jle 0x92dd8
+      0x0f, 0x86, 0xdf, 0x00, 0x00, 0x00, // cond jump -- jbe 0x921b0
+
+      0x0f, 0x05,                         // far call -- syscall
+
+      0x0f, 0x07,                         // far return -- sysret
+      0xcf,                               // far return -- interrupt ret
+  };
+
+  InstructionControlFlowKind result[] = {
+      eInstructionControlFlowKindOther,
+      eInstructionControlFlowKindOther,
+
+      eInstructionControlFlowKindCall,
+      eInstructionControlFlowKindCall,
+      eInstructionControlFlowKindCall,
+      eInstructionControlFlowKindCall,
+
+      eInstructionControlFlowKindReturn,
+
+      eInstructionControlFlowKindJump,
+      eInstructionControlFlowKindJump,
+      eInstructionControlFlowKindJump,
+      eInstructionControlFlowKindJump,
+
+      eInstructionControlFlowKindCondJump,
+      eInstructionControlFlowKindCondJump,
+      eInstructionControlFlowKindCondJump,
+      eInstructionControlFlowKindCondJump,
+      eInstructionControlFlowKindCondJump,
+      eInstructionControlFlowKindCondJump,
+      eInstructionControlFlowKindCondJump,
+      eInstructionControlFlowKindCondJump,
+      eInstructionControlFlowKindCondJump,
+      eInstructionControlFlowKindCondJump,
+      eInstructionControlFlowKindCondJump,
+      eInstructionControlFlowKindCondJump,
+      eInstructionControlFlowKindCondJump,
+      eInstructionControlFlowKindCondJump,
+      eInstructionControlFlowKindCondJump,
+
+      eInstructionControlFlowKindFarCall,
+
+      eInstructionControlFlowKindFarReturn,
+      eInstructionControlFlowKindFarReturn,
+  };
+
+  DisassemblerSP disass_sp;
+  Address start_addr(0x100);
+  disass_sp =
+      Disassembler::DisassembleBytes(arch, nullptr, nullptr, start_addr, &data,
+                                    sizeof (data), num_of_instructions, false);
+
+  // If we failed to get a disassembler, we can assume it is because
+  // the llvm we linked against was not built with the i386 target,
+  // and we should skip these tests without marking anything as failing.
+
+  if (disass_sp) {
+    const InstructionList inst_list(disass_sp->GetInstructionList());
+    EXPECT_EQ(num_of_instructions, inst_list.GetSize());
+
+    for (size_t i = 0; i < num_of_instructions; ++i) {
+      InstructionSP inst_sp;
+      inst_sp = inst_list.GetInstructionAtIndex(i);
+      InstructionControlFlowKind kind = inst_sp->GetControlFlowKind(arch);
+      EXPECT_EQ(kind, result[i]);
+    }
+  }
+}