[mlir][spirv] Fix bitcast input order for UnifyAliasedResourcePass

[antiagainst]

Summary

spv.bitcast from a vector to a scalar expects the lower-numbered
components of the the vector to map to the lower-ordered bits of
the scalar. That actually already matches how little endian stores
data in the memory. So we just need to read and push to the back
of the vector sequentially.

mlir/lib/Dialect/SPIRV/Transforms/UnifyAliasedResourcePass.cpp

matchAndRewrite(spirv::LoadOp loadOp, OpAdaptor adaptor,
     Value oneValue = spirv::ConstantOp::getOne(i32Type, loc, rewriter);
     auto indices = llvm::to_vector<4>(acOp.indices());
     for (int i = 1; i < ratio; ++i) {
       // Load all subsequent components belonging to this element.
       indices.back() = rewriter.create<spirv::IAddOp>(loc, i32Type,
                                                       indices.back(), oneValue);
       auto componentAcOp =
           rewriter.create<spirv::AccessChainOp>(loc, acOp.base_ptr(), indices);
+      // Assuming little endian, this reads lower-ordered bits of the number to
+      // lower-numbered components of the vector.
       components.push_back(rewriter.create<spirv::LoadOp>(loc, componentAcOp));
     }
-    std::reverse(components.begin(), components.end()); // For little endian..
 
     // Create a vector of the components and then cast back to the larger
-    // bitwidth element type.
+    // bitwidth element type. For spv.bitcast, the lower-numbered components of
+    // the vector map to lower-ordered bits of the larger bitwidth element type.
     auto vectorType = VectorType::get({ratio}, dstElemType);
     Value vectorValue = rewriter.create<spirv::CompositeConstructOp>(
         loc, vectorType, components);
     rewriter.replaceOpWithNewOp<spirv::BitcastOp>(loadOp, srcElemType,
                                                   vectorValue);
     return success();
   }
 };

mlir/test/Dialect/SPIRV/Transforms/unify-aliased-resource.mlir

 //     CHECK:   %[[AC0:.+]] = spv.AccessChain %[[ADDR]][%[[ZERO]], %[[BASE]]]
 //     CHECK:   %[[LOAD0:.+]] = spv.Load "StorageBuffer" %[[AC0]] : f32
 
 //     CHECK:   %[[ONE:.+]] = spv.Constant 1 : i32
 //     CHECK:   %[[ADD:.+]] = spv.IAdd %[[BASE]], %[[ONE]] : i32
 //     CHECK:   %[[AC1:.+]] = spv.AccessChain %[[ADDR]][%[[ZERO]], %[[ADD]]]
 //     CHECK:   %[[LOAD1:.+]] = spv.Load "StorageBuffer" %[[AC1]] : f32
 
-//     CHECK:   %[[CC:.+]] = spv.CompositeConstruct %[[LOAD1]], %[[LOAD0]]
+//     CHECK:   %[[CC:.+]] = spv.CompositeConstruct %[[LOAD0]], %[[LOAD1]]
 //     CHECK:   %[[CAST:.+]] = spv.Bitcast %[[CC]] : vector<2xf32> to i64
 //     CHECK:   spv.ReturnValue %[[CAST]]
 
 // -----
 
 spv.module Logical GLSL450 {
   spv.GlobalVariable @var01s_i64 bind(0, 1) {aliased} : !spv.ptr<!spv.struct<(!spv.rtarray<i64, stride=4> [0])>, StorageBuffer>
   spv.GlobalVariable @var01s_f32 bind(0, 1) {aliased} : !spv.ptr<!spv.struct<(!spv.rtarray<f32, stride=4> [0])>, StorageBuffer>