[SPARC] Don't do leaf optimization on procedures with inline assembly

[koakuma]

Summary

On SPARC, leaf function optimization omits the register window sliding (and the associated register name changes). This might result in miscompilation of procedures containing inline assembly, as some of the register constraints used may interfere with the register usage of optimized functions, so we disable leaf procedure optimization on those procedures to prevent it from happening.

This is a continuation of patch D102342 by @LemonBoy, the original comment is reproduced below:

Leaf functions allow the compiler to omit the setup and teardown of a frame pointer, therefore avoiding the exchange of the in/out register. According to the SPARC architecture manual every reference to %i0-%i5 should be replaced with %o0-o5, if the target register is already in use a further remapping step to %g1-%g7 is required to free the output register.

Add a simple check to make sure not to stomp on any output register that's already in use.

[koakuma]

Also update other inline asm-related SPARC tests.

llvm/lib/Target/Sparc/SparcFrameLowering.cpp

 }
 
 bool SparcFrameLowering::isLeafProc(MachineFunction &MF) const
 {
 
   MachineRegisterInfo &MRI = MF.getRegInfo();
   MachineFrameInfo    &MFI = MF.getFrameInfo();
 
-  return !(MFI.hasCalls()                  // has calls
-           || MRI.isPhysRegUsed(SP::L0)    // Too many registers needed
-           || MRI.isPhysRegUsed(SP::O6)    // %sp is used
-           || hasFP(MF));                  // need %fp
+  return !(MFI.hasCalls()               // has calls
+           || MRI.isPhysRegUsed(SP::L0) // Too many registers needed
+           || MRI.isPhysRegUsed(SP::O6) // %sp is used
+           || hasFP(MF)                 // need %fp
+           || MF.hasInlineAsm());       // has inline assembly
 }
 
 void SparcFrameLowering::remapRegsForLeafProc(MachineFunction &MF) const {
   MachineRegisterInfo &MRI = MF.getRegInfo();
   // Remap %i[0-7] to %o[0-7].
   for (unsigned reg = SP::I0; reg <= SP::I7; ++reg) {
     if (!MRI.isPhysRegUsed(reg))
       continue;

llvm/test/CodeGen/SPARC/LeonSMACUMACInstructionUT.ll

 ; RUN: llc %s -O0 -march=sparc -mcpu=leon2 -o - | FileCheck %s
 ; RUN: llc %s -O0 -march=sparc -mcpu=leon3 -o - | FileCheck %s
 ; RUN: llc %s -O0 -march=sparc -mcpu=leon4 -o - | FileCheck %s
 
 ; CHECK-LABEL: smac_test:
-; CHECK:       smac %o1, %o0, %o0
+; CHECK:       smac %i1, %i0, %i0
 define i32 @smac_test(i16* %a, i16* %b) {
 entry:
 ;  %0 = tail call i32 asm sideeffect "smac $2, $1, $0", "={r2},{r3},{r4}"(i16* %a, i16* %b)
   %0 = tail call i32 asm sideeffect "smac $2, $1, $0", "=r,rI,r"(i16* %a, i16* %b)
   ret i32 %0
 }
 
 ; CHECK-LABEL: umac_test:
-; CHECK:       umac %o1, %o0, %o0
+; CHECK:       umac %i1, %i0, %i0
 define i32 @umac_test(i16* %a, i16* %b) {
 entry:
   %0 = tail call i32 asm sideeffect "umac $2, $1, $0", "=r,rI,r"(i16* %a, i16* %b)
   ret i32 %0
 }

llvm/test/CodeGen/SPARC/inlineasm-v9.ll

entry:
   tail call void asm sideeffect "fadds $0,$1,$2", "{f20},{f20},{f20}"(float 6.0, float 7.0, float 8.0)
   tail call void asm sideeffect "faddd $0,$1,$2", "{f20},{f20},{f20}"(double 9.0, double 10.0, double 11.0)
   tail call void asm sideeffect "faddq $0,$1,$2", "{f40},{f40},{f40}"(fp128 0xL0, fp128 0xL0, fp128 0xL0)
   ret void
 }
 
 ;; Ensure that 64-bit immediates aren't truncated
 ; CHECK-LABEL: test_large_immediate
-; CHECK: or %o0, %lo(4294967296), %o0
+; CHECK: or %i0, %lo(4294967296), %i0
 define i64 @test_large_immediate(i64) {
 entry:
   %1 = tail call i64 asm "or $0, %lo($1), $0", "=r,i,r"(i64 4294967296, i64 %0)
   ret i64 %1
 }
 
 ; Ensure that the input register value is not truncated to 32bit.
 ; CHECK-LABEL: test_constraint_input_type
-; CHECK: ldx [%o0], %o0
+; CHECK: ldx [%i0], %o0
 define void @test_constraint_input_type(i64* %arg1) {
 Entry:
   %val = load i64, i64* %arg1
   tail call void asm sideeffect "", "{o0}"(i64 %val)
   ret void
 }

llvm/test/CodeGen/SPARC/inlineasm.ll

 ; RUN: llc -march=sparc <%s | FileCheck %s
 
 ; CHECK-LABEL: test_constraint_r
-; CHECK:       add %o1, %o0, %o0
+; CHECK:       add %i1, %i0, %i0
 define i32 @test_constraint_r(i32 %a, i32 %b) {
 entry:
   %0 = tail call i32 asm sideeffect "add $2, $1, $0", "=r,r,r"(i32 %a, i32 %b)
   ret i32 %0
 }
 
 ;; Check tests only that the constraints are accepted without a compiler failure.
 ; CHECK-LABEL: test_constraints_nro:
 %struct.anon = type { i32, i32 }
 @v = external global %struct.anon, align 4
 define void @test_constraints_nro() {
 entry:
   %0 = load i32, i32* getelementptr inbounds (%struct.anon, %struct.anon* @v, i32 0, i32 0);
   %1 = load i32, i32* getelementptr inbounds (%struct.anon, %struct.anon* @v, i32 0, i32 1);
   tail call void asm sideeffect "", "nro,nro"(i32 %0, i32 %1)
   ret void
 }
 
 ; CHECK-LABEL: test_constraint_I:
-; CHECK:       add %o0, 1023, %o0
+; CHECK:       add %i0, 1023, %i0
 define i32 @test_constraint_I(i32 %a) {
 entry:
   %0 = tail call i32 asm sideeffect "add $1, $2, $0", "=r,r,rI"(i32 %a, i32 1023)
   ret i32 %0
 }
 
 ; CHECK-LABEL: test_constraint_I_neg:
-; CHECK:       add %o0, -4096, %o0
+; CHECK:       add %i0, -4096, %i0
 define i32 @test_constraint_I_neg(i32 %a) {
 entry:
   %0 = tail call i32 asm sideeffect "add $1, $2, $0", "=r,r,rI"(i32 %a, i32 -4096)
   ret i32 %0
 }
 
 ; CHECK-LABEL: test_constraint_I_largeimm:
 ; CHECK:       sethi 9, [[R0:%[gilo][0-7]]]
 ; CHECK:       or [[R0]], 784, [[R1:%[gilo][0-7]]]
-; CHECK:       add %o0, [[R1]], %o0
+; CHECK:       add %i0, [[R1]], %i0
 define i32 @test_constraint_I_largeimm(i32 %a) {
 entry:
   %0 = tail call i32 asm sideeffect "add $1, $2, $0", "=r,r,rI"(i32 %a, i32 10000)
   ret i32 %0
 }
 
 ; CHECK-LABEL: test_constraint_reg:
-; CHECK:       ldda [%o1] 43, %g2
-; CHECK:       ldda [%o1] 43, %g4
+; CHECK:       ldda [%i1] 43, %g2
+; CHECK:       ldda [%i1] 43, %g4
 define void @test_constraint_reg(i32 %s, i32* %ptr) {
 entry:
   %0 = tail call i64 asm sideeffect "ldda [$1] $2, $0", "={r2},r,n"(i32* %ptr, i32 43)
   %1 = tail call i64 asm sideeffect "ldda [$1] $2, $0", "={g4},r,n"(i32* %ptr, i32 43)
   ret void
 }
 
 ;; Ensure that i64 args to asm are allocated to the IntPair register class.
-;; Also checks that register renaming for leaf proc works.
+;; Also checks that there's no register renaming for leaf proc if it has inline asm.
 ; CHECK-LABEL: test_constraint_r_i64:
-; CHECK: mov %o0, %o5
-; CHECK: sra %o5, 31, %o4
-; CHECK: std %o4, [%o1]
+; CHECK: mov %i0, %i5
+; CHECK: sra %i5, 31, %i4
+; CHECK: std %i4, [%i1]
 define i32 @test_constraint_r_i64(i32 %foo, i64* %out, i32 %o) {
 entry:
   %conv = sext i32 %foo to i64
   tail call void asm sideeffect "std $0, [$1]", "r,r,~{memory}"(i64 %conv, i64* %out)
   ret i32 %o
 }
 
 ;; Same test without leaf-proc opt
 ; CHECK-LABEL: test_constraint_r_i64_noleaf:
 ; CHECK: mov %i0, %i5
 ; CHECK: sra %i5, 31, %i4
 ; CHECK: std %i4, [%i1]
 define i32 @test_constraint_r_i64_noleaf(i32 %foo, i64* %out, i32 %o) #0 {
 entry:
   %conv = sext i32 %foo to i64
   tail call void asm sideeffect "std $0, [$1]", "r,r,~{memory}"(i64 %conv, i64* %out)
   ret i32 %o
 }
 attributes #0 = { "frame-pointer"="all" }
 
 ;; Ensures that tied in and out gets allocated properly.
 ; CHECK-LABEL: test_i64_inout:
-; CHECK: mov %g0, %o2
-; CHECK: mov 5, %o3
-; CHECK: xor %o2, %g0, %o2
-; CHECK: mov %o2, %o0
+; CHECK: mov %g0, %i2
+; CHECK: mov 5, %i3
+; CHECK: xor %i2, %g0, %i2
+; CHECK: mov %i2, %i0
 ; CHECK: ret
 define i64 @test_i64_inout() {
 entry:
   %0 = call i64 asm sideeffect "xor $1, %g0, $0", "=r,0,~{i1}"(i64 5);
   ret i64 %0
 }
 
 

 ; CHECK: faddd  %f0, %f2, %f0
 define double @faddd(double, double) local_unnamed_addr #2 {
 entry:
   %2 = tail call double asm sideeffect "faddd  $1, $2, $0;", "=f,f,e"(double %0, double %1) #7
   ret double %2
 }
 
 ; CHECK-LABEL: test_addressing_mode_i64:
-; CHECK: std %l0, [%o0]
+; CHECK: std %l0, [%i0]
 define void @test_addressing_mode_i64(i64* %out) {
 entry:
   call void asm "std %l0, $0", "=*m,r"(i64* elementtype(i64) nonnull %out, i64 0)
   ret void
 }
 
 ; CHECK-LABEL: test_constraint_float_reg:
 ; CHECK: fadds %f20, %f20, %f20
 ; CHECK: faddd %f20, %f20, %f20
 define void @test_constraint_float_reg() {
 entry:
   tail call void asm sideeffect "fadds $0,$1,$2", "{f20},{f20},{f20}"(float 6.0, float 7.0, float 8.0)
   tail call void asm sideeffect "faddd $0,$1,$2", "{f20},{f20},{f20}"(double 9.0, double 10.0, double 11.0)
   ret void
 }
 
 ; CHECK-LABEL: test_constraint_f_e_i32_i64:
-; CHECK: ld [%o0+%lo(.LCPI13_0)], %f0
-; CHECK: ldd [%o0+%lo(.LCPI13_1)], %f2
+; CHECK: ld [%i0+%lo(.LCPI13_0)], %f0
+; CHECK: ldd [%i0+%lo(.LCPI13_1)], %f2
 ; CHECK: fadds %f0, %f0, %f0
 ; CHECK: faddd %f2, %f2, %f0
 
 define void @test_constraint_f_e_i32_i64() {
 entry:
   %0 = call float asm sideeffect "fadds $1, $2, $0", "=f,f,e"(i32 0, i32 0)
   %1 = call double asm sideeffect "faddd $1, $2, $0", "=f,f,e"(i64 0, i64 0)
   ret void
 }

llvm/test/CodeGen/SPARC/leafproc.ll

entry:
   %1 = getelementptr inbounds [2 x i32], [2 x i32]* %array, i32 0, i32 0
   store i32 1, i32* %1, align 4
   %2 = getelementptr inbounds [2 x i32], [2 x i32]* %array, i32 0, i32 1
   store i32 2, i32* %2, align 4
   %3 = getelementptr inbounds [2 x i32], [2 x i32]* %array, i32 0, i32 %a
   %4 = load i32, i32* %3, align 4
   ret i32 %4
 }
+
+; Here we have a leaf function where it contains inline assembly, which means
+; that register renumbering might interfere with the register constraints.
+; As a result the function is not marked as being a leaf one.
+
+; CHECK-LABEL: leaf_proc_give_up
+; CHECK: save %sp, -96, %sp
+; CHECK: ld [%fp+92], %o5
+; CHECK: mov %i0, %g1
+; CHECK: mov %i1, %o0
+; CHECK: mov %i2, %o1
+; CHECK: mov %i3, %o2
+; CHECK: mov %i4, %o3
+; CHECK: mov %i5, %o4
+; CHECK: ret
+; CHECK-NEXT: restore %g0, %o0, %o0
+
+define i32 @leaf_proc_give_up(i32 %0, i32 %1, i32 %2, i32 %3, i32 %4, i32 %5, i32 %6) {
+Entry:
+  %g = call i32 asm sideeffect "", "={o0},{g1},{o0},{o1},{o2},{o3},{o4},{o5}"(i32 %0, i32 %1, i32 %2, i32 %3, i32 %4, i32 %5, i32 %6)
+  ret i32 %g
+}