[PowerPC] Fix llvm.ppc.cfence on float point types

[lkail]

Summary

Handle llvm.ppc.cfence on f64 and f32 values bitcasted from integer values.

[shchenz]

Looks great! Thanks.

[lkail]

Already covered by https://reviews.llvm.org/D127609.

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

case Intrinsic::ppc_cfence: {
     assert(ArgStart == 1 && "llvm.ppc.cfence must carry a chain argument.");
     assert(Subtarget.isPPC64() && "Only 64-bit is supported for now.");
     SDValue Val = Op.getOperand(ArgStart + 1);
     EVT Ty = Val.getValueType();
     if (Ty == MVT::i128) {
       // FIXME: Testing one of two paired registers is sufficient to guarantee
       // ordering?
       Val = DAG.getNode(ISD::TRUNCATE, DL, MVT::i64, Val);
-    }
+    } else if (Ty == MVT::f32 || Ty == MVT::f64) {
+      assert(Val.getOpcode() == ISD::BITCAST &&
+             "Expect the float point value is bitcasted from another value.");
+      Val = Val.getOperand(0);
+      assert(Val.getValueType().isInteger() &&
+             "Expect the float point value is bitcasted from a integer value");
+    } else if (!Ty.isInteger())
+      llvm_unreachable("Unhandled type in llvm.ppc.cfence");
     return SDValue(
         DAG.getMachineNode(PPC::CFENCE8, DL, MVT::Other,
                            DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Val),
                            Op.getOperand(0)),
         0);
   }
   default:
     break;

llvm/test/CodeGen/PowerPC/cfence-double.ll

-; REQUIRES: asserts
-; RUN: not --crash llc -opaque-pointers -mtriple=powerpc64le-unknown-unknown \
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -opaque-pointers -mtriple=powerpc64le-unknown-unknown \
 ; RUN:   < %s 2>&1 | FileCheck %s
-; RUN: not --crash llc -opaque-pointers -mtriple=powerpc64-unknown-unknown \
+; RUN: llc -opaque-pointers -mtriple=powerpc64-unknown-unknown \
 ; RUN:   < %s 2>&1 | FileCheck %s
 
-; CHECK: Assertion `VT.isInteger() && Operand.getValueType().isInteger() && "Invalid ANY_EXTEND!"' failed
 define void @foo() {
+; CHECK-LABEL: foo:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    ld 3, 0(3)
+; CHECK-NEXT:    cmpd 7, 3, 3
+; CHECK-NEXT:    bne- 7, .+4
+; CHECK-NEXT:    isync
+; CHECK-NEXT:    blr
 entry:
   %0 = load atomic double, double* undef acquire, align 8
   ret void
 }

llvm/test/CodeGen/PowerPC/cfence-float.ll

-; REQUIRES: asserts
-; RUN: not --crash llc -opaque-pointers -mtriple=powerpc64le-unknown-unknown \
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -opaque-pointers -mtriple=powerpc64le-unknown-unknown \
 ; RUN:   < %s 2>&1 | FileCheck %s
-; RUN: not --crash llc -opaque-pointers -mtriple=powerpc64-unknown-unknown \
+; RUN: llc -opaque-pointers -mtriple=powerpc64-unknown-unknown \
 ; RUN:   < %s 2>&1 | FileCheck %s
 
-; CHECK: Assertion `VT.isInteger() && Operand.getValueType().isInteger() && "Invalid ANY_EXTEND!"' failed
 define void @bar() {
+; CHECK-LABEL: bar:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    lwz 3, 0(3)
+; CHECK-NEXT:    cmpd 7, 3, 3
+; CHECK-NEXT:    bne- 7, .+4
+; CHECK-NEXT:    isync
+; CHECK-NEXT:    blr
 entry:
   %0 = load atomic float, float* undef acquire, align 8
   ret void
 }

llvm/test/Transforms/AtomicExpand/PowerPC/cfence-float.ll

+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt -opaque-pointers -atomic-expand -S -mtriple=powerpc64le-unknown-unknown \
+; RUN:   %s | FileCheck %s
+; RUN: opt -opaque-pointers -atomic-expand -S -mtriple=powerpc64-unknown-unknown \
+; RUN:   %s | FileCheck %s
+
+define void @bar() {
+; CHECK-LABEL: @bar(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[TMP0:%.*]] = load atomic i32, ptr undef monotonic, align 8
+; CHECK-NEXT:    [[TMP1:%.*]] = bitcast i32 [[TMP0]] to float
+; CHECK-NEXT:    call void @llvm.ppc.cfence.f32(float [[TMP1]])
+; CHECK-NEXT:    ret void
+;
+entry:
+  %0 = load atomic float, float* undef acquire, align 8
+  ret void
+}
+
+define void @foo() {
+; CHECK-LABEL: @foo(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[TMP0:%.*]] = load atomic i64, ptr undef monotonic, align 8
+; CHECK-NEXT:    [[TMP1:%.*]] = bitcast i64 [[TMP0]] to double
+; CHECK-NEXT:    call void @llvm.ppc.cfence.f64(double [[TMP1]])
+; CHECK-NEXT:    ret void
+;
+entry:
+  %0 = load atomic double, double* undef acquire, align 8
+  ret void
+}