[AMDGPU] Basic implementation of isExtractSubvectorCheap

[foad]

Summary

Add a basic implementation of isExtractSubvectorCheap that only
considers extracts at offset 0.

[foad]

This doesn't affect any current lit tests but does fix a code quality regression in D127115.

[foad]

llvm/lib/Target/AMDGPU/SIISelLowering.cpp

1589

For VGPRs I think any extract starting at a dword boundary should be cheap, but for SGPRs it would need to start at a suitably aligned register number. So I don't know how to implement this.

[deadalnix]

I can confirm that this works.

[deadalnix]

@foad do you have commit rights? Do you need me to push this for you?

[foad]

@foad do you have commit rights? Do you need me to push this for you?

Yes. No. I was just waiting for further comments.

llvm/lib/Target/AMDGPU/SIISelLowering.h

public:
   bool isFreeAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override;
 
   TargetLoweringBase::LegalizeTypeAction
   getPreferredVectorAction(MVT VT) const override;
 
   bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
                                         Type *Ty) const override;
 
+  bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
+                               unsigned Index) const override;
+
   bool isTypeDesirableForOp(unsigned Op, EVT VT) const override;
 
   bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
 
   bool supportSplitCSR(MachineFunction *MF) const override;
   void initializeSplitCSR(MachineBasicBlock *Entry) const override;
   void insertCopiesSplitCSR(
     MachineBasicBlock *Entry,

llvm/lib/Target/AMDGPU/SIISelLowering.cpp

 }
 
 bool SITargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
                                                          Type *Ty) const {
   // FIXME: Could be smarter if called for vector constants.
   return true;
 }
 
+bool SITargetLowering::isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
+                                               unsigned Index) const {
+  if (!isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, ResVT))
+    return false;
+
+  // TODO: Add more cases that are cheap.
+  return Index == 0;
+}
+
 bool SITargetLowering::isTypeDesirableForOp(unsigned Op, EVT VT) const {
   if (Subtarget->has16BitInsts() && VT == MVT::i16) {
     switch (Op) {
     case ISD::LOAD:
     case ISD::STORE:
 
     // These operations are done with 32-bit instructions anyway.
     case ISD::AND: