[SelectionDAG] Remove invalid TypeSize conversion from WidenVecOp_BITCAST.

[paulwalker-arm]

For full disclosure, I'm not 100% sure but believe the nxv1#64 output is possibly wrong. This is true for the existing and new tests. I don't think this is the fault of this or previous bitcast work but rather an issue with how we're lowering ISD::INSERT_SUBVECTOR for these types. It looks suspiciously like we're treating ISD::INSERT_SUBVECTOR nxv2i64 undef, nxv1i64 data, i32 0 as a NOP.

This is certainly at odds with how we handle the other "unpacked" types but I don't think we've ever really agreed how <vscale x 1 x should be represented at the register level.

[efriedma]

LGTM

This is certainly at odds with how we handle the other "unpacked" types but I don't think we've ever really agreed how <vscale x 1 x should be represented at the register level.

In memory, `<vscale x 1 x is tightly packed. There are no legal <vscale x 1 x types on AArch64, so target-independent legalization will eliminate them.

So the question you're asking is really how <vscale x 1 x are passed across functions, and in SelectionDAG, across basic blocks. That's entirely determined by getCopyFromPartsVector()/getCopyToPartsVector() in SelectionDAGBuilder, I think. I'm fine with the current state, but if you want to mess with it, we can, I guess. I don't think it directly interacts with anything else.

[paulwalker-arm]

Thanks for the information @efriedma. I'll likely need to do a fuller <vscale x 1 x investigation to close out the remaining legalisation issues as I think the current strategy may well not be a good fit.

llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp

 
 SDValue DAGTypeLegalizer::WidenVecOp_BITCAST(SDNode *N) {
   EVT VT = N->getValueType(0);
   SDValue InOp = GetWidenedVector(N->getOperand(0));
   EVT InWidenVT = InOp.getValueType();
   SDLoc dl(N);
 
   // Check if we can convert between two legal vector types and extract.
-  unsigned InWidenSize = InWidenVT.getSizeInBits();
-  unsigned Size = VT.getSizeInBits();
+  TypeSize InWidenSize = InWidenVT.getSizeInBits();
+  TypeSize Size = VT.getSizeInBits();
   // x86mmx is not an acceptable vector element type, so don't try.
-  if (InWidenSize % Size == 0 && !VT.isVector() && VT != MVT::x86mmx) {
-    unsigned NewNumElts = InWidenSize / Size;
+  if (!VT.isVector() && VT != MVT::x86mmx &&
+      InWidenSize.hasKnownScalarFactor(Size)) {
+    unsigned NewNumElts = InWidenSize.getKnownScalarFactor(Size);
     EVT NewVT = EVT::getVectorVT(*DAG.getContext(), VT, NewNumElts);
     if (TLI.isTypeLegal(NewVT)) {
       SDValue BitOp = DAG.getNode(ISD::BITCAST, dl, NewVT, InOp);
       return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, BitOp,
                          DAG.getVectorIdxConstant(0, dl));
     }
   }
 
   // Handle a case like bitcast v12i8 -> v3i32. Normally that would get widened
   // to v16i8 -> v4i32, but for a target where v3i32 is legal but v12i8 is not,
   // we end up here. Handling the case here with EXTRACT_SUBVECTOR avoids
   // having to copy via memory.
   if (VT.isVector()) {
     EVT EltVT = VT.getVectorElementType();
-    unsigned EltSize = EltVT.getSizeInBits();
-    if (InWidenSize % EltSize == 0) {
-      unsigned NewNumElts = InWidenSize / EltSize;
+    unsigned EltSize = EltVT.getFixedSizeInBits();
+    if (InWidenSize.isKnownMultipleOf(EltSize)) {
+      ElementCount NewNumElts =
+          (InWidenVT.getVectorElementCount() * InWidenVT.getScalarSizeInBits())
+              .divideCoefficientBy(EltSize);
       EVT NewVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NewNumElts);
       if (TLI.isTypeLegal(NewVT)) {
         SDValue BitOp = DAG.getNode(ISD::BITCAST, dl, NewVT, InOp);
         return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, BitOp,
                            DAG.getVectorIdxConstant(0, dl));
       }
     }
   }

llvm/test/CodeGen/AArch64/sve-bitcast.ll

 ; CHECK-NEXT:    ld1h { z0.s }, p0/z, [sp, #1, mul vl]
 ; CHECK-NEXT:    addvl sp, sp, #1
 ; CHECK-NEXT:    ldr x29, [sp], #16 // 8-byte Folded Reload
 ; CHECK-NEXT:    ret
   %bc = bitcast <vscale x 2 x i32> %v to <vscale x 4 x half>
   ret <vscale x 4 x half> %bc
 }
 
-; @bitcast_nxv1i64_to_nxv4f16 is missing
+define <vscale x 4 x half> @bitcast_nxv1i64_to_nxv4f16(<vscale x 1 x i64> %v) #0 {
+; CHECK-LABEL: bitcast_nxv1i64_to_nxv4f16:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    uunpklo z0.s, z0.h
+; CHECK-NEXT:    ret
+  %bc = bitcast <vscale x 1 x i64> %v to <vscale x 4 x half>
+  ret <vscale x 4 x half> %bc
+}
 
 define <vscale x 4 x half> @bitcast_nxv2f32_to_nxv4f16(<vscale x 2 x float> %v) #0 {
 ; CHECK-LABEL: bitcast_nxv2f32_to_nxv4f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    str x29, [sp, #-16]! // 8-byte Folded Spill
 ; CHECK-NEXT:    addvl sp, sp, #-1
 ; CHECK-NEXT:    ptrue p0.d
 ; CHECK-NEXT:    st1w { z0.d }, p0, [sp, #1, mul vl]
 ; CHECK-NEXT:    ptrue p0.s
 ; CHECK-NEXT:    ld1h { z0.s }, p0/z, [sp, #1, mul vl]
 ; CHECK-NEXT:    addvl sp, sp, #1
 ; CHECK-NEXT:    ldr x29, [sp], #16 // 8-byte Folded Reload
 ; CHECK-NEXT:    ret
   %bc = bitcast <vscale x 2 x float> %v to <vscale x 4 x half>
   ret <vscale x 4 x half> %bc
 }
 
-; @bitcast_nxv1f64_to_nxv4f16 is missing
+define <vscale x 4 x half> @bitcast_nxv1f64_to_nxv4f16(<vscale x 1 x double> %v) #0 {
+; CHECK-LABEL: bitcast_nxv1f64_to_nxv4f16:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    uunpklo z0.s, z0.h
+; CHECK-NEXT:    ret
+  %bc = bitcast <vscale x 1 x double> %v to <vscale x 4 x half>
+  ret <vscale x 4 x half> %bc
+}
 
 define <vscale x 4 x half> @bitcast_nxv4bf16_to_nxv4f16(<vscale x 4 x bfloat> %v) #0 {
 ; CHECK-LABEL: bitcast_nxv4bf16_to_nxv4f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ret
   %bc = bitcast <vscale x 4 x bfloat> %v to <vscale x 4 x half>
   ret <vscale x 4 x half> %bc
 }

 define <vscale x 2 x float> @bitcast_nxv2i32_to_nxv2f32(<vscale x 2 x i32> %v) #0 {
 ; CHECK-LABEL: bitcast_nxv2i32_to_nxv2f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ret
   %bc = bitcast <vscale x 2 x i32> %v to <vscale x 2 x float>
   ret <vscale x 2 x float> %bc
 }
 
-; @bitcast_nxv1i64_to_nxv2f32 is missing
+define <vscale x 2 x float> @bitcast_nxv1i64_to_nxv2f32(<vscale x 1 x i64> %v) #0 {
+; CHECK-LABEL: bitcast_nxv1i64_to_nxv2f32:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    uunpklo z0.d, z0.s
+; CHECK-NEXT:    ret
+  %bc = bitcast <vscale x 1 x i64> %v to <vscale x 2 x float>
+  ret <vscale x 2 x float> %bc
+}
 
 define <vscale x 2 x float> @bitcast_nxv4f16_to_nxv2f32(<vscale x 4 x half> %v) #0 {
 ; CHECK-LABEL: bitcast_nxv4f16_to_nxv2f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    str x29, [sp, #-16]! // 8-byte Folded Spill
 ; CHECK-NEXT:    addvl sp, sp, #-1
 ; CHECK-NEXT:    ptrue p0.s
 ; CHECK-NEXT:    st1h { z0.s }, p0, [sp, #1, mul vl]
 ; CHECK-NEXT:    ptrue p0.d
 ; CHECK-NEXT:    ld1w { z0.d }, p0/z, [sp, #1, mul vl]
 ; CHECK-NEXT:    addvl sp, sp, #1
 ; CHECK-NEXT:    ldr x29, [sp], #16 // 8-byte Folded Reload
 ; CHECK-NEXT:    ret
   %bc = bitcast <vscale x 4 x half> %v to <vscale x 2 x float>
   ret <vscale x 2 x float> %bc
 }
 
-; @bitcast_nxv1f64_to_nxv2f32 is missing
+define <vscale x 2 x float> @bitcast_nxv1f64_to_nxv2f32(<vscale x 1 x double> %v) #0 {
+; CHECK-LABEL: bitcast_nxv1f64_to_nxv2f32:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    uunpklo z0.d, z0.s
+; CHECK-NEXT:    ret
+  %bc = bitcast <vscale x 1 x double> %v to <vscale x 2 x float>
+  ret <vscale x 2 x float> %bc
+}
 
 define <vscale x 2 x float> @bitcast_nxv4bf16_to_nxv2f32(<vscale x 4 x bfloat> %v) #0 {
 ; CHECK-LABEL: bitcast_nxv4bf16_to_nxv2f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    str x29, [sp, #-16]! // 8-byte Folded Spill
 ; CHECK-NEXT:    addvl sp, sp, #-1
 ; CHECK-NEXT:    ptrue p0.s
 ; CHECK-NEXT:    st1h { z0.s }, p0, [sp, #1, mul vl]
 ; CHECK-NEXT:    ptrue p0.d
 ; CHECK-NEXT:    ld1w { z0.d }, p0/z, [sp, #1, mul vl]
 ; CHECK-NEXT:    addvl sp, sp, #1
 ; CHECK-NEXT:    ldr x29, [sp], #16 // 8-byte Folded Reload
 ; CHECK-NEXT:    ret
   %bc = bitcast <vscale x 4 x bfloat> %v to <vscale x 2 x float>
   ret <vscale x 2 x float> %bc
 }
 
 ;
 ; bitcast to nxv1f64
 ;
 
-; @bitcast_nxv8i8_to_nxv1f64 is missing
-; @bitcast_nxv4i16_to_nxv1f64 is missing
-; @bitcast_nxv2i32_to_nxv1f64 is missing
-; @bitcast_nxv1i64_to_nxv1f64 is missing
-; @bitcast_nxv4f16_to_nxv1f64 is missing
-; @bitcast_nxv2f32_to_nxv1f64 is missing
-; @bitcast_nxv4bf16_to_nxv1f64 is missing
+define <vscale x 1 x double> @bitcast_nxv8i8_to_nxv1f64(<vscale x 8 x i8> %v) #0 {
+; CHECK-LABEL: bitcast_nxv8i8_to_nxv1f64:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    uzp1 z0.b, z0.b, z0.b
+; CHECK-NEXT:    ret
+  %bc = bitcast <vscale x 8 x i8> %v to <vscale x 1 x double>
+  ret <vscale x 1 x double> %bc
+}
+
+define <vscale x 1 x double> @bitcast_nxv4i16_to_nxv1f64(<vscale x 4 x i16> %v) #0 {
+; CHECK-LABEL: bitcast_nxv4i16_to_nxv1f64:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    uzp1 z0.h, z0.h, z0.h
+; CHECK-NEXT:    ret
+  %bc = bitcast <vscale x 4 x i16> %v to <vscale x 1 x double>
+  ret <vscale x 1 x double> %bc
+}
+
+define <vscale x 1 x double> @bitcast_nxv2i32_to_nxv1f64(<vscale x 2 x i32> %v) #0 {
+; CHECK-LABEL: bitcast_nxv2i32_to_nxv1f64:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    uzp1 z0.s, z0.s, z0.s
+; CHECK-NEXT:    ret
+  %bc = bitcast <vscale x 2 x i32> %v to <vscale x 1 x double>
+  ret <vscale x 1 x double> %bc
+}
+
+define <vscale x 1 x double> @bitcast_nxv1i64_to_nxv1f64(<vscale x 1 x i64> %v) #0 {
+; CHECK-LABEL: bitcast_nxv1i64_to_nxv1f64:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ret
+  %bc = bitcast <vscale x 1 x i64> %v to <vscale x 1 x double>
+  ret <vscale x 1 x double> %bc
+}
+
+define <vscale x 1 x double> @bitcast_nxv4f16_to_nxv1f64(<vscale x 4 x half> %v) #0 {
+; CHECK-LABEL: bitcast_nxv4f16_to_nxv1f64:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    uzp1 z0.h, z0.h, z0.h
+; CHECK-NEXT:    ret
+  %bc = bitcast <vscale x 4 x half> %v to <vscale x 1 x double>
+  ret <vscale x 1 x double> %bc
+}
+
+define <vscale x 1 x double> @bitcast_nxv2f32_to_nxv1f64(<vscale x 2 x float> %v) #0 {
+; CHECK-LABEL: bitcast_nxv2f32_to_nxv1f64:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    uzp1 z0.s, z0.s, z0.s
+; CHECK-NEXT:    ret
+  %bc = bitcast <vscale x 2 x float> %v to <vscale x 1 x double>
+  ret <vscale x 1 x double> %bc
+}
+
+define <vscale x 1 x double> @bitcast_nxv4bf16_to_nxv1f64(<vscale x 4 x bfloat> %v) #0 {
+; CHECK-LABEL: bitcast_nxv4bf16_to_nxv1f64:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    uzp1 z0.h, z0.h, z0.h
+; CHECK-NEXT:    ret
+  %bc = bitcast <vscale x 4 x bfloat> %v to <vscale x 1 x double>
+  ret <vscale x 1 x double> %bc
+}
 
 ;
 ; bitcast to nxv4bf16
 ;
 
 define <vscale x 4 x bfloat> @bitcast_nxv8i8_to_nxv4bf16(<vscale x 8 x i8> %v) #0 {
 ; CHECK-LABEL: bitcast_nxv8i8_to_nxv4bf16:
 ; CHECK:       // %bb.0:

 ; CHECK-NEXT:    ld1h { z0.s }, p0/z, [sp, #1, mul vl]
 ; CHECK-NEXT:    addvl sp, sp, #1
 ; CHECK-NEXT:    ldr x29, [sp], #16 // 8-byte Folded Reload
 ; CHECK-NEXT:    ret
   %bc = bitcast <vscale x 2 x i32> %v to <vscale x 4 x bfloat>
   ret <vscale x 4 x bfloat> %bc
 }
 
-; @bitcast_nxv1i64_to_nxv4bf16 is missing
+define <vscale x 4 x bfloat> @bitcast_nxv1i64_to_nxv4bf16(<vscale x 1 x i64> %v) #0 {
+; CHECK-LABEL: bitcast_nxv1i64_to_nxv4bf16:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    uunpklo z0.s, z0.h
+; CHECK-NEXT:    ret
+  %bc = bitcast <vscale x 1 x i64> %v to <vscale x 4 x bfloat>
+  ret <vscale x 4 x bfloat> %bc
+}
 
 define <vscale x 4 x bfloat> @bitcast_nxv4f16_to_nxv4bf16(<vscale x 4 x half> %v) #0 {
 ; CHECK-LABEL: bitcast_nxv4f16_to_nxv4bf16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ret
   %bc = bitcast <vscale x 4 x half> %v to <vscale x 4 x bfloat>
   ret <vscale x 4 x bfloat> %bc
 }

 ; CHECK-NEXT:    ld1h { z0.s }, p0/z, [sp, #1, mul vl]
 ; CHECK-NEXT:    addvl sp, sp, #1
 ; CHECK-NEXT:    ldr x29, [sp], #16 // 8-byte Folded Reload
 ; CHECK-NEXT:    ret
   %bc = bitcast <vscale x 2 x float> %v to <vscale x 4 x bfloat>
   ret <vscale x 4 x bfloat> %bc
 }
 
-; @bitcast_nxv1f64_to_nxv4bf16 is missing
+define <vscale x 4 x bfloat> @bitcast_nxv1f64_to_nxv4bf16(<vscale x 1 x double> %v) #0 {
+; CHECK-LABEL: bitcast_nxv1f64_to_nxv4bf16:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    uunpklo z0.s, z0.h
+; CHECK-NEXT:    ret
+  %bc = bitcast <vscale x 1 x double> %v to <vscale x 4 x bfloat>
+  ret <vscale x 4 x bfloat> %bc
+}
 
 ;
 ; bitcast to nxv4i8
 ;
 
 define <vscale x 4 x i8> @bitcast_nxv2i16_to_nxv4i8(<vscale x 2 x i16> %v) #0 {
 ; CHECK-LABEL: bitcast_nxv2i16_to_nxv4i8:
 ; CHECK:       // %bb.0:

 ; CHECK-LABEL: bitcast_nxv2bf16_to_nxv2f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ret
   %bc = bitcast <vscale x 2 x bfloat> %v to <vscale x 2 x half>
   ret <vscale x 2 x half> %bc
 }
 
 ;
+; bitcast to nxv1f32
+;
+
+; @bitcast_nxv4i8_to_nxv1f32 is missing
+; @bitcast_nxv2i16_to_nxv1f32 is missing
+; @bitcast_nxv1i32_to_nxv1f32 is missing
+; @bitcast_nxv2f16_to_nxv1f32 is missing
+; @bitcast_nxv2bf16_to_nxv1f32 is missing
+
+;
 ; bitcast to nxv2bf16
 ;
 
 define <vscale x 2 x bfloat> @bitcast_nxv4i8_to_nxv2bf16(<vscale x 4 x i8> %v) #0 {
 ; CHECK-LABEL: bitcast_nxv4i8_to_nxv2bf16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    str x29, [sp, #-16]! // 8-byte Folded Spill
 ; CHECK-NEXT:    addvl sp, sp, #-1
; CHECK-NEXT:    ret
   %bc = bitcast <vscale x 2 x i8> %v to <vscale x 1 x i16>
   ret <vscale x 1 x i16> %bc
 }
 
 ; @bitcast_nxv1f16_to_nxv1i16 is missing
 ; @bitcast_nxv1bf16_to_nxv1i16 is missing
 
 ;
+; bitcast to nxv1f16
+;
+
+; @bitcast_nxv2i8_to_nxv1f16 is missing
+; @bitcast_nxv1i16_to_nxv1f16 is missing
+; @bitcast_nxv1bf16_to_nxv1f16 is missing
+
+;
+; bitcast to nxv1bf16
+;
+
+; @bitcast_nxv2i8_to_nxv1bf16 is missing
+; @bitcast_nxv1i16_to_nxv1bf16 is missing
+; @bitcast_nxv1f16_to_nxv1bf16 is missing
+
+;
 ; Other
 ;
 
 define <vscale x 2 x i32> @bitcast_short_float_to_i32(<vscale x 2 x double> %v) #0 {
 ; CHECK-LABEL: bitcast_short_float_to_i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ptrue p0.d
 ; CHECK-NEXT:    fcvt z0.s, p0/m, z0.d