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Differential D127309

[PowerPC] emit VSX instructions instead of VMX instructions for vector loads and stores
ClosedPublic

Authored by quinnp on Jun 8 2022, 7:56 AM.

Details

Reviewers
nemanjai
lei
stefanp
Group Reviewers
Restricted Project
Commits
rG335e8bf1008f: [PowerPC] emit VSX instructions instead of VMX instructions for vector loads…
Summary

This patch changes the PowerPC backend to generate VSX load/store instructions
for all vector loads/stores on Power8 and earlier (LE) instead of VMX
load/store instructions. The reason for this change is because VMX instructions
require the vector to be 16-byte aligned. So, a vector load/store will fail with
VMX instructions if the vector is misaligned. Also, gcc generates VSX
instructions in this situation which allow for unaligned access but require a
swap instruction after loading/before storing. This is not an issue for BE
because we already emit VSX instructions since no swap is required. And this is
not an issue on Power9 and up since we have access to lxv[x]/stxv[x] which
allow for unaligned access and do not require swaps.

This patch also delays the VSX load/store for LE combines until after
LegalizeOps to prioritize other load/store combines.

Diff Detail

Event Timeline

quinnp created this revision.Jun 8 2022, 7:56 AM
Herald added a project: Restricted Project. · View Herald TranscriptJun 8 2022, 7:56 AM
Herald added subscribers: steven.zhang, shchenz, kbarton and 2 others. · View Herald Transcript
quinnp requested review of this revision.Jun 8 2022, 7:56 AM
Herald added a project: Restricted Project. · View Herald TranscriptJun 8 2022, 7:57 AM
Herald added a subscriber: llvm-commits. · View Herald Transcript
quinnp added reviewers: nemanjai, lei, Restricted Project.Jun 8 2022, 7:58 AM
Harbormaster completed remote builds in B168576: Diff 435163.Jun 8 2022, 9:48 AM
quinnp updated this revision to Diff 435961.Jun 10 2022, 10:11 AM

Rebasing with main.

Harbormaster completed remote builds in B169107: Diff 435961.Jun 10 2022, 11:46 AM
quinnp edited the summary of this revision. (Show Details)Jun 13 2022, 11:55 AM
quinnp edited the summary of this revision. (Show Details)Jun 13 2022, 11:57 AM
quinnp updated this revision to Diff 437131.Jun 15 2022, 6:21 AM

Updating patch to delay SVX load and store combine until after legalization.

quinnp updated this revision to Diff 437149.Jun 15 2022, 7:12 AM

Adding a comments to the early exits in expandVSXLoadForLE and expandVSXStoreForLE.

quinnp edited the summary of this revision. (Show Details)Jun 15 2022, 7:13 AM
quinnp added a reviewer: stefanp.
Harbormaster completed remote builds in B169979: Diff 437149.Jun 15 2022, 8:09 AM
stefanp accepted this revision.Jun 15 2022, 9:24 AM

LGTM

This revision is now accepted and ready to land.Jun 15 2022, 9:24 AM
This revision was landed with ongoing or failed builds.Jun 15 2022, 10:06 AM
Closed by commit rG335e8bf1008f: [PowerPC] emit VSX instructions instead of VMX instructions for vector loads… (authored by quinnp). · Explain Why
This revision was automatically updated to reflect the committed changes.
quinnp added a commit: rG335e8bf1008f: [PowerPC] emit VSX instructions instead of VMX instructions for vector loads….

Revision Contents

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lib/
Target/
PowerPC/
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Diff 437229

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 14,546 Lines • ▼ Show 20 LinesSDValue PPCTargetLowering::combineFPToIntToFP(SDNode *N,
return SDValue(); return SDValue();
} }
// expandVSXLoadForLE - Convert VSX loads (which may be intrinsics for // expandVSXLoadForLE - Convert VSX loads (which may be intrinsics for
// builtins) into loads with swaps. // builtins) into loads with swaps.
SDValue PPCTargetLowering::expandVSXLoadForLE(SDNode *N, SDValue PPCTargetLowering::expandVSXLoadForLE(SDNode *N,
DAGCombinerInfo &DCI) const { DAGCombinerInfo &DCI) const {
// Delay VSX load for LE combine until after LegalizeOps to prioritize other
// load combines.
if (DCI.isBeforeLegalizeOps())
return SDValue();
SelectionDAG &DAG = DCI.DAG; SelectionDAG &DAG = DCI.DAG;
SDLoc dl(N); SDLoc dl(N);
SDValue Chain; SDValue Chain;
SDValue Base; SDValue Base;
MachineMemOperand *MMO; MachineMemOperand *MMO;
switch (N->getOpcode()) { switch (N->getOpcode()) {
default: default:
Show All 18 Lines case ISD::INTRINSIC_W_CHAIN: {
Base = Intrin->getOperand(2); Base = Intrin->getOperand(2);
MMO = Intrin->getMemOperand(); MMO = Intrin->getMemOperand();
break; break;
} }
} }
MVT VecTy = N->getValueType(0).getSimpleVT(); MVT VecTy = N->getValueType(0).getSimpleVT();
// Do not expand to PPCISD::LXVD2X + PPCISD::XXSWAPD when the load is
// aligned and the type is a vector with elements up to 4 bytes
if (Subtarget.needsSwapsForVSXMemOps() && MMO->getAlign() >= Align(16) &&
VecTy.getScalarSizeInBits() <= 32) {
return SDValue();
}
SDValue LoadOps[] = { Chain, Base }; SDValue LoadOps[] = { Chain, Base };
SDValue Load = DAG.getMemIntrinsicNode(PPCISD::LXVD2X, dl, SDValue Load = DAG.getMemIntrinsicNode(PPCISD::LXVD2X, dl,
DAG.getVTList(MVT::v2f64, MVT::Other), DAG.getVTList(MVT::v2f64, MVT::Other),
LoadOps, MVT::v2f64, MMO); LoadOps, MVT::v2f64, MMO);
DCI.AddToWorklist(Load.getNode()); DCI.AddToWorklist(Load.getNode());
Chain = Load.getValue(1); Chain = Load.getValue(1);
SDValue Swap = DAG.getNode( SDValue Swap = DAG.getNode(
Show All 11 LinesSDValue PPCTargetLowering::expandVSXLoadForLE(SDNode *N,
return Swap; return Swap;
} }
// expandVSXStoreForLE - Convert VSX stores (which may be intrinsics for // expandVSXStoreForLE - Convert VSX stores (which may be intrinsics for
// builtins) into stores with swaps. // builtins) into stores with swaps.
SDValue PPCTargetLowering::expandVSXStoreForLE(SDNode *N, SDValue PPCTargetLowering::expandVSXStoreForLE(SDNode *N,
DAGCombinerInfo &DCI) const { DAGCombinerInfo &DCI) const {
// Delay VSX store for LE combine until after LegalizeOps to prioritize other
// store combines.
if (DCI.isBeforeLegalizeOps())
return SDValue();
SelectionDAG &DAG = DCI.DAG; SelectionDAG &DAG = DCI.DAG;
SDLoc dl(N); SDLoc dl(N);
SDValue Chain; SDValue Chain;
SDValue Base; SDValue Base;
unsigned SrcOpnd; unsigned SrcOpnd;
MachineMemOperand *MMO; MachineMemOperand *MMO;
switch (N->getOpcode()) { switch (N->getOpcode()) {
Show All 21 Lines case ISD::INTRINSIC_VOID: {
SrcOpnd = 2; SrcOpnd = 2;
break; break;
} }
} }
SDValue Src = N->getOperand(SrcOpnd); SDValue Src = N->getOperand(SrcOpnd);
MVT VecTy = Src.getValueType().getSimpleVT(); MVT VecTy = Src.getValueType().getSimpleVT();
// Do not expand to PPCISD::XXSWAPD and PPCISD::STXVD2X when the load is
// aligned and the type is a vector with elements up to 4 bytes
if (Subtarget.needsSwapsForVSXMemOps() && MMO->getAlign() >= Align(16) &&
VecTy.getScalarSizeInBits() <= 32) {
return SDValue();
}
// All stores are done as v2f64 and possible bit cast. // All stores are done as v2f64 and possible bit cast.
if (VecTy != MVT::v2f64) { if (VecTy != MVT::v2f64) {
Src = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Src); Src = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Src);
DCI.AddToWorklist(Src.getNode()); DCI.AddToWorklist(Src.getNode());
} }
SDValue Swap = DAG.getNode(PPCISD::XXSWAPD, dl, SDValue Swap = DAG.getNode(PPCISD::XXSWAPD, dl,
DAG.getVTList(MVT::v2f64, MVT::Other), Chain, Src); DAG.getVTList(MVT::v2f64, MVT::Other), Chain, Src);
▲ Show 20 Lines • Show All 3,508 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/P10-stack-alignment.ll

Show All 19 Lines
; CHECK-LE-NEXT: std r0, 16(r1) ; CHECK-LE-NEXT: std r0, 16(r1)
; CHECK-LE-NEXT: clrldi r0, r1, 59 ; CHECK-LE-NEXT: clrldi r0, r1, 59
; CHECK-LE-NEXT: subfic r0, r0, -96 ; CHECK-LE-NEXT: subfic r0, r0, -96
; CHECK-LE-NEXT: stdux r1, r1, r0 ; CHECK-LE-NEXT: stdux r1, r1, r0
; CHECK-LE-NEXT: addis r3, r2, .LCPI0_0@toc@ha ; CHECK-LE-NEXT: addis r3, r2, .LCPI0_0@toc@ha
; CHECK-LE-NEXT: addis r4, r2, .LCPI0_1@toc@ha ; CHECK-LE-NEXT: addis r4, r2, .LCPI0_1@toc@ha
; CHECK-LE-NEXT: addi r3, r3, .LCPI0_0@toc@l ; CHECK-LE-NEXT: addi r3, r3, .LCPI0_0@toc@l
; CHECK-LE-NEXT: addi r4, r4, .LCPI0_1@toc@l ; CHECK-LE-NEXT: addi r4, r4, .LCPI0_1@toc@l
; CHECK-LE-NEXT: lvx v2, 0, r3 ; CHECK-LE-NEXT: lxvd2x vs0, 0, r3
; CHECK-LE-NEXT: lvx v3, 0, r4 ; CHECK-LE-NEXT: lxvd2x vs1, 0, r4
; CHECK-LE-NEXT: addi r4, r1, 48 ; CHECK-LE-NEXT: addi r4, r1, 48
; CHECK-LE-NEXT: addi r3, r1, 32 ; CHECK-LE-NEXT: addi r3, r1, 32
; CHECK-LE-NEXT: stvx v2, 0, r4 ; CHECK-LE-NEXT: stxvd2x vs0, 0, r4
; CHECK-LE-NEXT: stvx v3, 0, r3 ; CHECK-LE-NEXT: stxvd2x vs1, 0, r3
; CHECK-LE-NEXT: bl test ; CHECK-LE-NEXT: bl test
; CHECK-LE-NEXT: nop ; CHECK-LE-NEXT: nop
; CHECK-LE-NEXT: lwa r3, 32(r1) ; CHECK-LE-NEXT: lwa r3, 32(r1)
; CHECK-LE-NEXT: mr r1, r30 ; CHECK-LE-NEXT: mr r1, r30
; CHECK-LE-NEXT: ld r0, 16(r1) ; CHECK-LE-NEXT: ld r0, 16(r1)
; CHECK-LE-NEXT: ld r30, -16(r1) ; CHECK-LE-NEXT: ld r30, -16(r1)
; CHECK-LE-NEXT: mtlr r0 ; CHECK-LE-NEXT: mtlr r0
; CHECK-LE-NEXT: blr ; CHECK-LE-NEXT: blr
▲ Show 20 Lines • Show All 52 Lines • ▼ Show 20 Lines
; CHECK-LE-NEXT: std r30, -16(r1) ; CHECK-LE-NEXT: std r30, -16(r1)
; CHECK-LE-NEXT: mr r30, r1 ; CHECK-LE-NEXT: mr r30, r1
; CHECK-LE-NEXT: std r0, 16(r1) ; CHECK-LE-NEXT: std r0, 16(r1)
; CHECK-LE-NEXT: clrldi r0, r1, 59 ; CHECK-LE-NEXT: clrldi r0, r1, 59
; CHECK-LE-NEXT: subfic r0, r0, -64 ; CHECK-LE-NEXT: subfic r0, r0, -64
; CHECK-LE-NEXT: stdux r1, r1, r0 ; CHECK-LE-NEXT: stdux r1, r1, r0
; CHECK-LE-NEXT: addis r3, r2, .LCPI1_0@toc@ha ; CHECK-LE-NEXT: addis r3, r2, .LCPI1_0@toc@ha
; CHECK-LE-NEXT: addi r3, r3, .LCPI1_0@toc@l ; CHECK-LE-NEXT: addi r3, r3, .LCPI1_0@toc@l
; CHECK-LE-NEXT: lvx v2, 0, r3 ; CHECK-LE-NEXT: lxvd2x vs0, 0, r3
; CHECK-LE-NEXT: addi r3, r1, 32 ; CHECK-LE-NEXT: addi r3, r1, 32
; CHECK-LE-NEXT: stvx v2, 0, r3 ; CHECK-LE-NEXT: stxvd2x vs0, 0, r3
; CHECK-LE-NEXT: bl test1 ; CHECK-LE-NEXT: bl test1
; CHECK-LE-NEXT: nop ; CHECK-LE-NEXT: nop
; CHECK-LE-NEXT: lwa r3, 32(r1) ; CHECK-LE-NEXT: lwa r3, 32(r1)
; CHECK-LE-NEXT: mr r1, r30 ; CHECK-LE-NEXT: mr r1, r30
; CHECK-LE-NEXT: ld r0, 16(r1) ; CHECK-LE-NEXT: ld r0, 16(r1)
; CHECK-LE-NEXT: ld r30, -16(r1) ; CHECK-LE-NEXT: ld r30, -16(r1)
; CHECK-LE-NEXT: mtlr r0 ; CHECK-LE-NEXT: mtlr r0
; CHECK-LE-NEXT: blr ; CHECK-LE-NEXT: blr
Show All 40 Lines
@Arr1 = dso_local global [64 x i8] zeroinitializer, align 1 @Arr1 = dso_local global [64 x i8] zeroinitializer, align 1
define dso_local void @test_Array() nounwind { define dso_local void @test_Array() nounwind {
; CHECK-OPT-LABEL: @test_Array( ; CHECK-OPT-LABEL: @test_Array(
; CHECK-OPT-NEXT: entry: ; CHECK-OPT-NEXT: entry:
; CHECK-OPT-NEXT: %Arr2 = alloca [64 x i16], align 2 ; CHECK-OPT-NEXT: %Arr2 = alloca [64 x i16], align 2
; CHECK-OPT: store <16 x i16> [[TMP0:%.*]], <16 x i16>* [[TMP0:%.*]], align 2 ; CHECK-OPT: store <16 x i16> [[TMP0:%.*]], <16 x i16>* [[TMP0:%.*]], align 2
; CHECK-LE-LABEL: test_Array:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: mflr r0
; CHECK-LE-NEXT: std r0, 16(r1)
; CHECK-LE-NEXT: stdu r1, -176(r1)
; CHECK-LE-NEXT: addis r4, r2, Arr1@toc@ha
; CHECK-LE-NEXT: li r3, 0
; CHECK-LE-NEXT: li r6, 65
; CHECK-LE-NEXT: addi r5, r1, 46
; CHECK-LE-NEXT: addi r4, r4, Arr1@toc@l
; CHECK-LE-NEXT: stw r3, 44(r1)
; CHECK-LE-NEXT: addi r4, r4, -1
; CHECK-LE-NEXT: mtctr r6
; CHECK-LE-NEXT: bdz .LBB2_2
; CHECK-LE-NEXT: .p2align 5
; CHECK-LE-NEXT: .LBB2_1: # %for.body
; CHECK-LE-NEXT: #
; CHECK-LE-NEXT: lbz r6, 1(r4)
; CHECK-LE-NEXT: addi r7, r5, 2
; CHECK-LE-NEXT: addi r4, r4, 1
; CHECK-LE-NEXT: addi r3, r3, 1
; CHECK-LE-NEXT: sth r6, 2(r5)
; CHECK-LE-NEXT: mr r5, r7
; CHECK-LE-NEXT: bdnz .LBB2_1
; CHECK-LE-NEXT: .LBB2_2: # %for.cond.cleanup
; CHECK-LE-NEXT: addi r3, r1, 48
; CHECK-LE-NEXT: bl test_arr
; CHECK-LE-NEXT: nop
; CHECK-LE-NEXT: addi r1, r1, 176
; CHECK-LE-NEXT: ld r0, 16(r1)
; CHECK-LE-NEXT: mtlr r0
; CHECK-LE-NEXT: blr
;
; CHECK-BE-LABEL: test_Array:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: mflr r0
; CHECK-BE-NEXT: std r0, 16(r1)
; CHECK-BE-NEXT: stdu r1, -256(r1)
; CHECK-BE-NEXT: addis r5, r2, Arr1@toc@ha
; CHECK-BE-NEXT: li r3, 0
; CHECK-BE-NEXT: addi r5, r5, Arr1@toc@l
; CHECK-BE-NEXT: addi r4, r1, 126
; CHECK-BE-NEXT: li r6, 65
; CHECK-BE-NEXT: stw r3, 124(r1)
; CHECK-BE-NEXT: addi r5, r5, -1
; CHECK-BE-NEXT: mtctr r6
; CHECK-BE-NEXT: bdz .LBB2_2
; CHECK-BE-NEXT: .LBB2_1: # %for.body
; CHECK-BE-NEXT: #
; CHECK-BE-NEXT: lbz r6, 1(r5)
; CHECK-BE-NEXT: addi r5, r5, 1
; CHECK-BE-NEXT: addi r3, r3, 1
; CHECK-BE-NEXT: sth r6, 2(r4)
; CHECK-BE-NEXT: addi r4, r4, 2
; CHECK-BE-NEXT: bdnz .LBB2_1
; CHECK-BE-NEXT: .LBB2_2: # %for.cond.cleanup
; CHECK-BE-NEXT: addi r3, r1, 128
; CHECK-BE-NEXT: bl test_arr
; CHECK-BE-NEXT: nop
; CHECK-BE-NEXT: addi r1, r1, 256
; CHECK-BE-NEXT: ld r0, 16(r1)
; CHECK-BE-NEXT: mtlr r0
; CHECK-BE-NEXT: blr
entry: entry:
%Arr2 = alloca [64 x i16], align 2 %Arr2 = alloca [64 x i16], align 2
%i = alloca i32, align 4 %i = alloca i32, align 4
%0 = bitcast [64 x i16]* %Arr2 to i8* %0 = bitcast [64 x i16]* %Arr2 to i8*
call void @llvm.lifetime.start.p0i8(i64 128, i8* %0) call void @llvm.lifetime.start.p0i8(i64 128, i8* %0)
%1 = bitcast i32* %i to i8* %1 = bitcast i32* %i to i8*
call void @llvm.lifetime.start.p0i8(i64 4, i8* %1) call void @llvm.lifetime.start.p0i8(i64 4, i8* %1)
store i32 0, i32* %i, align 4 store i32 0, i32* %i, align 4
▲ Show 20 Lines • Show All 45 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/VSX-XForm-Scalars.ll

; RUN: llc < %s -mcpu=pwr8 -mtriple=powerpc64le-unknown-unknown \ ; RUN: llc < %s -mcpu=pwr8 -mtriple=powerpc64le-unknown-unknown \
; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names -verify-machineinstrs \ ; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names -verify-machineinstrs \
; RUN: | FileCheck %s --check-prefix=CHECK-P8 ; RUN: | FileCheck %s --check-prefix=CHECK-P8
; RUN: llc < %s -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown \ ; RUN: llc < %s -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown \
; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names -verify-machineinstrs \ ; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names -verify-machineinstrs \
; RUN: | FileCheck %s --check-prefix=CHECK-P9 ; RUN: | FileCheck %s --check-prefix=CHECK-P9
@a = external local_unnamed_addr global <4 x i32>, align 16 @a = external local_unnamed_addr global <4 x i32>, align 16
@pb = external local_unnamed_addr global float*, align 8 @pb = external local_unnamed_addr global float*, align 8
define void @testExpandPostRAPseudo(i32* nocapture readonly %ptr) { define void @testExpandPostRAPseudo(i32* nocapture readonly %ptr) {
; CHECK-P8-LABEL: testExpandPostRAPseudo: ; CHECK-P8-LABEL: testExpandPostRAPseudo:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8: lfiwzx f0, 0, r3 ; CHECK-P8: lfiwzx f0, 0, r3
; CHECK-P8: ld r4, .LC0@toc@l(r4) ; CHECK-P8: ld r4, .LC0@toc@l(r4)
; CHECK-P8: xxspltw v2, vs0, 1 ; CHECK-P8: xxspltw vs0, vs0, 1
; CHECK-P8: stvx v2, 0, r4 ; CHECK-P8: xxswapd vs0, vs0
; CHECK-P8; stxvd2x vs0, 0, r4
; CHECK-P8: lis r4, 1024 ; CHECK-P8: lis r4, 1024
; CHECK-P8: lfiwax f0, 0, r3 ; CHECK-P8: lfiwax f0, 0, r3
; CHECK-P8: addis r3, r2, .LC1@toc@ha ; CHECK-P8: addis r3, r2, .LC1@toc@ha
; CHECK-P8: ld r3, .LC1@toc@l(r3) ; CHECK-P8: ld r3, .LC1@toc@l(r3)
; CHECK-P8: xscvsxdsp f0, f0 ; CHECK-P8: xscvsxdsp f0, f0
; CHECK-P8: ld r3, 0(r3) ; CHECK-P8: ld r3, 0(r3)
; CHECK-P8: stfsx f0, r3, r4 ; CHECK-P8: stfsx f0, r3, r4
; CHECK-P8: blr ; CHECK-P8: blr
Show All 28 Lines

llvm/test/CodeGen/PowerPC/aix-vsx-splatimm.ll

Show First 20 Lines • Show All 41 Lines • ▼ Show 20 Lines
; CHECK-NEXT: lwz 5, 0(3) ; CHECK-NEXT: lwz 5, 0(3)
; CHECK-NEXT: slwi 3, 3, 8 ; CHECK-NEXT: slwi 3, 3, 8
; CHECK-NEXT: neg 3, 3 ; CHECK-NEXT: neg 3, 3
; CHECK-NEXT: srwi 5, 5, 1 ; CHECK-NEXT: srwi 5, 5, 1
; CHECK-NEXT: mtvsrd 34, 3 ; CHECK-NEXT: mtvsrd 34, 3
; CHECK-NEXT: li 3, 0 ; CHECK-NEXT: li 3, 0
; CHECK-NEXT: mullw 4, 4, 5 ; CHECK-NEXT: mullw 4, 4, 5
; CHECK-NEXT: vsplth 2, 2, 3 ; CHECK-NEXT: vsplth 2, 2, 3
; CHECK-NEXT: stvx 2, 0, 3 ; CHECK-NEXT: xxswapd 0, 34
; CHECK-NEXT: neg 4, 4 ; CHECK-NEXT: neg 4, 4
; CHECK-NEXT: mtvsrd 35, 4 ; CHECK-NEXT: mtvsrd 35, 4
; CHECK-NEXT: stxvd2x 0, 0, 3
; CHECK-NEXT: vsplth 3, 3, 3 ; CHECK-NEXT: vsplth 3, 3, 3
; CHECK-NEXT: stvx 3, 0, 3 ; CHECK-NEXT: xxswapd 1, 35
; CHECK-NEXT: stxvd2x 1, 0, 3
bb: bb:
br i1 undef, label %bb22, label %bb3 br i1 undef, label %bb22, label %bb3
bb3: ; preds = %bb bb3: ; preds = %bb
%i = insertelement <8 x i16> undef, i16 0, i32 0 %i = insertelement <8 x i16> undef, i16 0, i32 0
%i4 = trunc i32 %arg to i16 %i4 = trunc i32 %arg to i16
%i5 = mul i16 %i4, -256 %i5 = mul i16 %i4, -256
%i6 = insertelement <8 x i16> %i, i16 %i5, i32 1 %i6 = insertelement <8 x i16> %i, i16 %i5, i32 1
Show All 22 Lines

llvm/test/CodeGen/PowerPC/build-vector-tests.ll

Show First 20 Lines • Show All 873 Lines • ▼ Show 20 Lines
; P8BE-NEXT: addi r3, r3, .LCPI5_0@toc@l ; P8BE-NEXT: addi r3, r3, .LCPI5_0@toc@l
; P8BE-NEXT: lxvw4x v2, 0, r3 ; P8BE-NEXT: lxvw4x v2, 0, r3
; P8BE-NEXT: blr ; P8BE-NEXT: blr
; ;
; P8LE-LABEL: fromDiffConstsi: ; P8LE-LABEL: fromDiffConstsi:
; P8LE: # %bb.0: # %entry ; P8LE: # %bb.0: # %entry
; P8LE-NEXT: addis r3, r2, .LCPI5_0@toc@ha ; P8LE-NEXT: addis r3, r2, .LCPI5_0@toc@ha
; P8LE-NEXT: addi r3, r3, .LCPI5_0@toc@l ; P8LE-NEXT: addi r3, r3, .LCPI5_0@toc@l
; P8LE-NEXT: lvx v2, 0, r3 ; P8LE-NEXT: lxvd2x vs0, 0, r3
; P8LE-NEXT: xxswapd v2, vs0
; P8LE-NEXT: blr ; P8LE-NEXT: blr
entry: entry:
ret <4 x i32> <i32 242, i32 -113, i32 889, i32 19> ret <4 x i32> <i32 242, i32 -113, i32 889, i32 19>
} }
define <4 x i32> @fromDiffMemConsAi(i32* nocapture readonly %arr) { define <4 x i32> @fromDiffMemConsAi(i32* nocapture readonly %arr) {
; P9BE-LABEL: fromDiffMemConsAi: ; P9BE-LABEL: fromDiffMemConsAi:
; P9BE: # %bb.0: # %entry ; P9BE: # %bb.0: # %entry
▲ Show 20 Lines • Show All 51 Lines • ▼ Show 20 Lines
; P8BE-NEXT: lxvw4x v2, 0, r3 ; P8BE-NEXT: lxvw4x v2, 0, r3
; P8BE-NEXT: addi r4, r4, .LCPI7_0@toc@l ; P8BE-NEXT: addi r4, r4, .LCPI7_0@toc@l
; P8BE-NEXT: lxvw4x v3, 0, r4 ; P8BE-NEXT: lxvw4x v3, 0, r4
; P8BE-NEXT: vperm v2, v2, v2, v3 ; P8BE-NEXT: vperm v2, v2, v2, v3
; P8BE-NEXT: blr ; P8BE-NEXT: blr
; ;
; P8LE-LABEL: fromDiffMemConsDi: ; P8LE-LABEL: fromDiffMemConsDi:
; P8LE: # %bb.0: # %entry ; P8LE: # %bb.0: # %entry
; P8LE-NEXT: lxvd2x vs0, 0, r3
; P8LE-NEXT: addis r4, r2, .LCPI7_0@toc@ha ; P8LE-NEXT: addis r4, r2, .LCPI7_0@toc@ha
; P8LE-NEXT: addi r3, r4, .LCPI7_0@toc@l ; P8LE-NEXT: lxvd2x vs0, 0, r3
; P8LE-NEXT: lvx v2, 0, r3 ; P8LE-NEXT: addi r4, r4, .LCPI7_0@toc@l
; P8LE-NEXT: xxswapd v3, vs0 ; P8LE-NEXT: lxvd2x vs1, 0, r4
; P8LE-NEXT: vperm v2, v3, v3, v2 ; P8LE-NEXT: xxswapd v2, vs0
; P8LE-NEXT: xxswapd v3, vs1
; P8LE-NEXT: vperm v2, v2, v2, v3
; P8LE-NEXT: blr ; P8LE-NEXT: blr
entry: entry:
%arrayidx = getelementptr inbounds i32, i32* %arr, i64 3 %arrayidx = getelementptr inbounds i32, i32* %arr, i64 3
%0 = load i32, i32* %arrayidx, align 4 %0 = load i32, i32* %arrayidx, align 4
%vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0
%arrayidx1 = getelementptr inbounds i32, i32* %arr, i64 2 %arrayidx1 = getelementptr inbounds i32, i32* %arr, i64 2
%1 = load i32, i32* %arrayidx1, align 4 %1 = load i32, i32* %arrayidx1, align 4
%vecinit2 = insertelement <4 x i32> %vecinit, i32 %1, i32 1 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %1, i32 1
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; P8BE-NEXT: vperm v2, v2, v2, v3 ; P8BE-NEXT: vperm v2, v2, v2, v3
; P8BE-NEXT: blr ; P8BE-NEXT: blr
; ;
; P8LE-LABEL: fromDiffMemVarDi: ; P8LE-LABEL: fromDiffMemVarDi:
; P8LE: # %bb.0: # %entry ; P8LE: # %bb.0: # %entry
; P8LE-NEXT: sldi r4, r4, 2 ; P8LE-NEXT: sldi r4, r4, 2
; P8LE-NEXT: addis r5, r2, .LCPI9_0@toc@ha ; P8LE-NEXT: addis r5, r2, .LCPI9_0@toc@ha
; P8LE-NEXT: add r3, r3, r4 ; P8LE-NEXT: add r3, r3, r4
; P8LE-NEXT: addi r4, r5, .LCPI9_0@toc@l
; P8LE-NEXT: addi r3, r3, -12 ; P8LE-NEXT: addi r3, r3, -12
; P8LE-NEXT: lxvd2x vs1, 0, r4
; P8LE-NEXT: lxvd2x vs0, 0, r3 ; P8LE-NEXT: lxvd2x vs0, 0, r3
; P8LE-NEXT: addi r3, r5, .LCPI9_0@toc@l ; P8LE-NEXT: xxswapd v3, vs1
; P8LE-NEXT: lvx v3, 0, r3
; P8LE-NEXT: xxswapd v2, vs0 ; P8LE-NEXT: xxswapd v2, vs0
; P8LE-NEXT: vperm v2, v2, v2, v3 ; P8LE-NEXT: vperm v2, v2, v2, v3
; P8LE-NEXT: blr ; P8LE-NEXT: blr
entry: entry:
%idxprom = sext i32 %elem to i64 %idxprom = sext i32 %elem to i64
%arrayidx = getelementptr inbounds i32, i32* %arr, i64 %idxprom %arrayidx = getelementptr inbounds i32, i32* %arr, i64 %idxprom
%0 = load i32, i32* %arrayidx, align 4 %0 = load i32, i32* %arrayidx, align 4
%vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0
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; P8BE-NEXT: addi r3, r3, .LCPI16_0@toc@l ; P8BE-NEXT: addi r3, r3, .LCPI16_0@toc@l
; P8BE-NEXT: lxvw4x v2, 0, r3 ; P8BE-NEXT: lxvw4x v2, 0, r3
; P8BE-NEXT: blr ; P8BE-NEXT: blr
; ;
; P8LE-LABEL: fromDiffConstsConvftoi: ; P8LE-LABEL: fromDiffConstsConvftoi:
; P8LE: # %bb.0: # %entry ; P8LE: # %bb.0: # %entry
; P8LE-NEXT: addis r3, r2, .LCPI16_0@toc@ha ; P8LE-NEXT: addis r3, r2, .LCPI16_0@toc@ha
; P8LE-NEXT: addi r3, r3, .LCPI16_0@toc@l ; P8LE-NEXT: addi r3, r3, .LCPI16_0@toc@l
; P8LE-NEXT: lvx v2, 0, r3 ; P8LE-NEXT: lxvd2x vs0, 0, r3
; P8LE-NEXT: xxswapd v2, vs0
; P8LE-NEXT: blr ; P8LE-NEXT: blr
entry: entry:
ret <4 x i32> <i32 24, i32 234, i32 988, i32 422> ret <4 x i32> <i32 24, i32 234, i32 988, i32 422>
} }
define <4 x i32> @fromDiffMemConsAConvftoi(float* nocapture readonly %ptr) { define <4 x i32> @fromDiffMemConsAConvftoi(float* nocapture readonly %ptr) {
; P9BE-LABEL: fromDiffMemConsAConvftoi: ; P9BE-LABEL: fromDiffMemConsAConvftoi:
; P9BE: # %bb.0: # %entry ; P9BE: # %bb.0: # %entry
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; P8BE-NEXT: addi r4, r4, .LCPI18_0@toc@l ; P8BE-NEXT: addi r4, r4, .LCPI18_0@toc@l
; P8BE-NEXT: lxvw4x v3, 0, r4 ; P8BE-NEXT: lxvw4x v3, 0, r4
; P8BE-NEXT: vperm v2, v2, v2, v3 ; P8BE-NEXT: vperm v2, v2, v2, v3
; P8BE-NEXT: xvcvspsxws v2, v2 ; P8BE-NEXT: xvcvspsxws v2, v2
; P8BE-NEXT: blr ; P8BE-NEXT: blr
; ;
; P8LE-LABEL: fromDiffMemConsDConvftoi: ; P8LE-LABEL: fromDiffMemConsDConvftoi:
; P8LE: # %bb.0: # %entry ; P8LE: # %bb.0: # %entry
; P8LE-NEXT: lxvd2x vs0, 0, r3
; P8LE-NEXT: addis r4, r2, .LCPI18_0@toc@ha ; P8LE-NEXT: addis r4, r2, .LCPI18_0@toc@ha
; P8LE-NEXT: addi r3, r4, .LCPI18_0@toc@l ; P8LE-NEXT: lxvd2x vs0, 0, r3
; P8LE-NEXT: lvx v2, 0, r3 ; P8LE-NEXT: addi r4, r4, .LCPI18_0@toc@l
; P8LE-NEXT: xxswapd v3, vs0 ; P8LE-NEXT: lxvd2x vs1, 0, r4
; P8LE-NEXT: vperm v2, v3, v3, v2 ; P8LE-NEXT: xxswapd v2, vs0
; P8LE-NEXT: xxswapd v3, vs1
; P8LE-NEXT: vperm v2, v2, v2, v3
; P8LE-NEXT: xvcvspsxws v2, v2 ; P8LE-NEXT: xvcvspsxws v2, v2
; P8LE-NEXT: blr ; P8LE-NEXT: blr
entry: entry:
%arrayidx = getelementptr inbounds float, float* %ptr, i64 3 %arrayidx = getelementptr inbounds float, float* %ptr, i64 3
%0 = load float, float* %arrayidx, align 4 %0 = load float, float* %arrayidx, align 4
%conv = fptosi float %0 to i32 %conv = fptosi float %0 to i32
%vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0
%arrayidx1 = getelementptr inbounds float, float* %ptr, i64 2 %arrayidx1 = getelementptr inbounds float, float* %ptr, i64 2
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; P8BE-NEXT: addi r3, r3, .LCPI25_0@toc@l ; P8BE-NEXT: addi r3, r3, .LCPI25_0@toc@l
; P8BE-NEXT: lxvw4x v2, 0, r3 ; P8BE-NEXT: lxvw4x v2, 0, r3
; P8BE-NEXT: blr ; P8BE-NEXT: blr
; ;
; P8LE-LABEL: fromDiffConstsConvdtoi: ; P8LE-LABEL: fromDiffConstsConvdtoi:
; P8LE: # %bb.0: # %entry ; P8LE: # %bb.0: # %entry
; P8LE-NEXT: addis r3, r2, .LCPI25_0@toc@ha ; P8LE-NEXT: addis r3, r2, .LCPI25_0@toc@ha
; P8LE-NEXT: addi r3, r3, .LCPI25_0@toc@l ; P8LE-NEXT: addi r3, r3, .LCPI25_0@toc@l
; P8LE-NEXT: lvx v2, 0, r3 ; P8LE-NEXT: lxvd2x vs0, 0, r3
; P8LE-NEXT: xxswapd v2, vs0
; P8LE-NEXT: blr ; P8LE-NEXT: blr
entry: entry:
ret <4 x i32> <i32 24, i32 234, i32 988, i32 422> ret <4 x i32> <i32 24, i32 234, i32 988, i32 422>
} }
define <4 x i32> @fromDiffMemConsAConvdtoi(double* nocapture readonly %ptr) { define <4 x i32> @fromDiffMemConsAConvdtoi(double* nocapture readonly %ptr) {
; P9BE-LABEL: fromDiffMemConsAConvdtoi: ; P9BE-LABEL: fromDiffMemConsAConvdtoi:
; P9BE: # %bb.0: # %entry ; P9BE: # %bb.0: # %entry
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; P8BE-NEXT: addi r3, r3, .LCPI37_0@toc@l ; P8BE-NEXT: addi r3, r3, .LCPI37_0@toc@l
; P8BE-NEXT: lxvw4x v2, 0, r3 ; P8BE-NEXT: lxvw4x v2, 0, r3
; P8BE-NEXT: blr ; P8BE-NEXT: blr
; ;
; P8LE-LABEL: fromDiffConstsui: ; P8LE-LABEL: fromDiffConstsui:
; P8LE: # %bb.0: # %entry ; P8LE: # %bb.0: # %entry
; P8LE-NEXT: addis r3, r2, .LCPI37_0@toc@ha ; P8LE-NEXT: addis r3, r2, .LCPI37_0@toc@ha
; P8LE-NEXT: addi r3, r3, .LCPI37_0@toc@l ; P8LE-NEXT: addi r3, r3, .LCPI37_0@toc@l
; P8LE-NEXT: lvx v2, 0, r3 ; P8LE-NEXT: lxvd2x vs0, 0, r3
; P8LE-NEXT: xxswapd v2, vs0
; P8LE-NEXT: blr ; P8LE-NEXT: blr
entry: entry:
ret <4 x i32> <i32 242, i32 -113, i32 889, i32 19> ret <4 x i32> <i32 242, i32 -113, i32 889, i32 19>
} }
define <4 x i32> @fromDiffMemConsAui(i32* nocapture readonly %arr) { define <4 x i32> @fromDiffMemConsAui(i32* nocapture readonly %arr) {
; P9BE-LABEL: fromDiffMemConsAui: ; P9BE-LABEL: fromDiffMemConsAui:
; P9BE: # %bb.0: # %entry ; P9BE: # %bb.0: # %entry
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; P8BE-NEXT: lxvw4x v2, 0, r3 ; P8BE-NEXT: lxvw4x v2, 0, r3
; P8BE-NEXT: addi r4, r4, .LCPI39_0@toc@l ; P8BE-NEXT: addi r4, r4, .LCPI39_0@toc@l
; P8BE-NEXT: lxvw4x v3, 0, r4 ; P8BE-NEXT: lxvw4x v3, 0, r4
; P8BE-NEXT: vperm v2, v2, v2, v3 ; P8BE-NEXT: vperm v2, v2, v2, v3
; P8BE-NEXT: blr ; P8BE-NEXT: blr
; ;
; P8LE-LABEL: fromDiffMemConsDui: ; P8LE-LABEL: fromDiffMemConsDui:
; P8LE: # %bb.0: # %entry ; P8LE: # %bb.0: # %entry
; P8LE-NEXT: lxvd2x vs0, 0, r3
; P8LE-NEXT: addis r4, r2, .LCPI39_0@toc@ha ; P8LE-NEXT: addis r4, r2, .LCPI39_0@toc@ha
; P8LE-NEXT: addi r3, r4, .LCPI39_0@toc@l ; P8LE-NEXT: lxvd2x vs0, 0, r3
; P8LE-NEXT: lvx v2, 0, r3 ; P8LE-NEXT: addi r4, r4, .LCPI39_0@toc@l
; P8LE-NEXT: xxswapd v3, vs0 ; P8LE-NEXT: lxvd2x vs1, 0, r4
; P8LE-NEXT: vperm v2, v3, v3, v2 ; P8LE-NEXT: xxswapd v2, vs0
; P8LE-NEXT: xxswapd v3, vs1
; P8LE-NEXT: vperm v2, v2, v2, v3
; P8LE-NEXT: blr ; P8LE-NEXT: blr
entry: entry:
%arrayidx = getelementptr inbounds i32, i32* %arr, i64 3 %arrayidx = getelementptr inbounds i32, i32* %arr, i64 3
%0 = load i32, i32* %arrayidx, align 4 %0 = load i32, i32* %arrayidx, align 4
%vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0
%arrayidx1 = getelementptr inbounds i32, i32* %arr, i64 2 %arrayidx1 = getelementptr inbounds i32, i32* %arr, i64 2
%1 = load i32, i32* %arrayidx1, align 4 %1 = load i32, i32* %arrayidx1, align 4
%vecinit2 = insertelement <4 x i32> %vecinit, i32 %1, i32 1 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %1, i32 1
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; P8BE-NEXT: vperm v2, v2, v2, v3 ; P8BE-NEXT: vperm v2, v2, v2, v3
; P8BE-NEXT: blr ; P8BE-NEXT: blr
; ;
; P8LE-LABEL: fromDiffMemVarDui: ; P8LE-LABEL: fromDiffMemVarDui:
; P8LE: # %bb.0: # %entry ; P8LE: # %bb.0: # %entry
; P8LE-NEXT: sldi r4, r4, 2 ; P8LE-NEXT: sldi r4, r4, 2
; P8LE-NEXT: addis r5, r2, .LCPI41_0@toc@ha ; P8LE-NEXT: addis r5, r2, .LCPI41_0@toc@ha
; P8LE-NEXT: add r3, r3, r4 ; P8LE-NEXT: add r3, r3, r4
; P8LE-NEXT: addi r4, r5, .LCPI41_0@toc@l
; P8LE-NEXT: addi r3, r3, -12 ; P8LE-NEXT: addi r3, r3, -12
; P8LE-NEXT: lxvd2x vs1, 0, r4
; P8LE-NEXT: lxvd2x vs0, 0, r3 ; P8LE-NEXT: lxvd2x vs0, 0, r3
; P8LE-NEXT: addi r3, r5, .LCPI41_0@toc@l ; P8LE-NEXT: xxswapd v3, vs1
; P8LE-NEXT: lvx v3, 0, r3
; P8LE-NEXT: xxswapd v2, vs0 ; P8LE-NEXT: xxswapd v2, vs0
; P8LE-NEXT: vperm v2, v2, v2, v3 ; P8LE-NEXT: vperm v2, v2, v2, v3
; P8LE-NEXT: blr ; P8LE-NEXT: blr
entry: entry:
%idxprom = sext i32 %elem to i64 %idxprom = sext i32 %elem to i64
%arrayidx = getelementptr inbounds i32, i32* %arr, i64 %idxprom %arrayidx = getelementptr inbounds i32, i32* %arr, i64 %idxprom
%0 = load i32, i32* %arrayidx, align 4 %0 = load i32, i32* %arrayidx, align 4
%vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0
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; P8BE-NEXT: addi r3, r3, .LCPI48_0@toc@l ; P8BE-NEXT: addi r3, r3, .LCPI48_0@toc@l
; P8BE-NEXT: lxvw4x v2, 0, r3 ; P8BE-NEXT: lxvw4x v2, 0, r3
; P8BE-NEXT: blr ; P8BE-NEXT: blr
; ;
; P8LE-LABEL: fromDiffConstsConvftoui: ; P8LE-LABEL: fromDiffConstsConvftoui:
; P8LE: # %bb.0: # %entry ; P8LE: # %bb.0: # %entry
; P8LE-NEXT: addis r3, r2, .LCPI48_0@toc@ha ; P8LE-NEXT: addis r3, r2, .LCPI48_0@toc@ha
; P8LE-NEXT: addi r3, r3, .LCPI48_0@toc@l ; P8LE-NEXT: addi r3, r3, .LCPI48_0@toc@l
; P8LE-NEXT: lvx v2, 0, r3 ; P8LE-NEXT: lxvd2x vs0, 0, r3
; P8LE-NEXT: xxswapd v2, vs0
; P8LE-NEXT: blr ; P8LE-NEXT: blr
entry: entry:
ret <4 x i32> <i32 24, i32 234, i32 988, i32 422> ret <4 x i32> <i32 24, i32 234, i32 988, i32 422>
} }
define <4 x i32> @fromDiffMemConsAConvftoui(float* nocapture readonly %ptr) { define <4 x i32> @fromDiffMemConsAConvftoui(float* nocapture readonly %ptr) {
; P9BE-LABEL: fromDiffMemConsAConvftoui: ; P9BE-LABEL: fromDiffMemConsAConvftoui:
; P9BE: # %bb.0: # %entry ; P9BE: # %bb.0: # %entry
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; P8BE-NEXT: addi r4, r4, .LCPI50_0@toc@l ; P8BE-NEXT: addi r4, r4, .LCPI50_0@toc@l
; P8BE-NEXT: lxvw4x v3, 0, r4 ; P8BE-NEXT: lxvw4x v3, 0, r4
; P8BE-NEXT: vperm v2, v2, v2, v3 ; P8BE-NEXT: vperm v2, v2, v2, v3
; P8BE-NEXT: xvcvspuxws v2, v2 ; P8BE-NEXT: xvcvspuxws v2, v2
; P8BE-NEXT: blr ; P8BE-NEXT: blr
; ;
; P8LE-LABEL: fromDiffMemConsDConvftoui: ; P8LE-LABEL: fromDiffMemConsDConvftoui:
; P8LE: # %bb.0: # %entry ; P8LE: # %bb.0: # %entry
; P8LE-NEXT: lxvd2x vs0, 0, r3
; P8LE-NEXT: addis r4, r2, .LCPI50_0@toc@ha ; P8LE-NEXT: addis r4, r2, .LCPI50_0@toc@ha
; P8LE-NEXT: addi r3, r4, .LCPI50_0@toc@l ; P8LE-NEXT: lxvd2x vs0, 0, r3
; P8LE-NEXT: lvx v2, 0, r3 ; P8LE-NEXT: addi r4, r4, .LCPI50_0@toc@l
; P8LE-NEXT: xxswapd v3, vs0 ; P8LE-NEXT: lxvd2x vs1, 0, r4
; P8LE-NEXT: vperm v2, v3, v3, v2 ; P8LE-NEXT: xxswapd v2, vs0
; P8LE-NEXT: xxswapd v3, vs1
; P8LE-NEXT: vperm v2, v2, v2, v3
; P8LE-NEXT: xvcvspuxws v2, v2 ; P8LE-NEXT: xvcvspuxws v2, v2
; P8LE-NEXT: blr ; P8LE-NEXT: blr
entry: entry:
%arrayidx = getelementptr inbounds float, float* %ptr, i64 3 %arrayidx = getelementptr inbounds float, float* %ptr, i64 3
%0 = load float, float* %arrayidx, align 4 %0 = load float, float* %arrayidx, align 4
%conv = fptoui float %0 to i32 %conv = fptoui float %0 to i32
%vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0
%arrayidx1 = getelementptr inbounds float, float* %ptr, i64 2 %arrayidx1 = getelementptr inbounds float, float* %ptr, i64 2
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; P8BE-NEXT: addi r3, r3, .LCPI57_0@toc@l ; P8BE-NEXT: addi r3, r3, .LCPI57_0@toc@l
; P8BE-NEXT: lxvw4x v2, 0, r3 ; P8BE-NEXT: lxvw4x v2, 0, r3
; P8BE-NEXT: blr ; P8BE-NEXT: blr
; ;
; P8LE-LABEL: fromDiffConstsConvdtoui: ; P8LE-LABEL: fromDiffConstsConvdtoui:
; P8LE: # %bb.0: # %entry ; P8LE: # %bb.0: # %entry
; P8LE-NEXT: addis r3, r2, .LCPI57_0@toc@ha ; P8LE-NEXT: addis r3, r2, .LCPI57_0@toc@ha
; P8LE-NEXT: addi r3, r3, .LCPI57_0@toc@l ; P8LE-NEXT: addi r3, r3, .LCPI57_0@toc@l
; P8LE-NEXT: lvx v2, 0, r3 ; P8LE-NEXT: lxvd2x vs0, 0, r3
; P8LE-NEXT: xxswapd v2, vs0
; P8LE-NEXT: blr ; P8LE-NEXT: blr
entry: entry:
ret <4 x i32> <i32 24, i32 234, i32 988, i32 422> ret <4 x i32> <i32 24, i32 234, i32 988, i32 422>
} }
define <4 x i32> @fromDiffMemConsAConvdtoui(double* nocapture readonly %ptr) { define <4 x i32> @fromDiffMemConsAConvdtoui(double* nocapture readonly %ptr) {
; P9BE-LABEL: fromDiffMemConsAConvdtoui: ; P9BE-LABEL: fromDiffMemConsAConvdtoui:
; P9BE: # %bb.0: # %entry ; P9BE: # %bb.0: # %entry
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llvm/test/CodeGen/PowerPC/canonical-merge-shuffles.ll

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; CHECK-NOVSX-NEXT: lvx v4, 0, r3 ; CHECK-NOVSX-NEXT: lvx v4, 0, r3
; CHECK-NOVSX-NEXT: vperm v2, v3, v2, v4 ; CHECK-NOVSX-NEXT: vperm v2, v3, v2, v4
; CHECK-NOVSX-NEXT: blr ; CHECK-NOVSX-NEXT: blr
; ;
; CHECK-P7-LABEL: testmrghb2: ; CHECK-P7-LABEL: testmrghb2:
; CHECK-P7: # %bb.0: # %entry ; CHECK-P7: # %bb.0: # %entry
; CHECK-P7-NEXT: addis r3, r2, .LCPI1_0@toc@ha ; CHECK-P7-NEXT: addis r3, r2, .LCPI1_0@toc@ha
; CHECK-P7-NEXT: addi r3, r3, .LCPI1_0@toc@l ; CHECK-P7-NEXT: addi r3, r3, .LCPI1_0@toc@l
; CHECK-P7-NEXT: lvx v4, 0, r3 ; CHECK-P7-NEXT: lxvd2x vs0, 0, r3
; CHECK-P7-NEXT: xxswapd v4, vs0
; CHECK-P7-NEXT: vperm v2, v3, v2, v4 ; CHECK-P7-NEXT: vperm v2, v3, v2, v4
; CHECK-P7-NEXT: blr ; CHECK-P7-NEXT: blr
; ;
; P8-AIX-LABEL: testmrghb2: ; P8-AIX-LABEL: testmrghb2:
; P8-AIX: # %bb.0: # %entry ; P8-AIX: # %bb.0: # %entry
; P8-AIX-NEXT: vmrglb v2, v3, v2 ; P8-AIX-NEXT: vmrglb v2, v3, v2
; P8-AIX-NEXT: blr ; P8-AIX-NEXT: blr
entry: entry:
▲ Show 20 Lines • Show All 57 Lines • ▼ Show 20 Lines
; CHECK-NOVSX-NEXT: lvx v4, 0, r3 ; CHECK-NOVSX-NEXT: lvx v4, 0, r3
; CHECK-NOVSX-NEXT: vperm v2, v3, v2, v4 ; CHECK-NOVSX-NEXT: vperm v2, v3, v2, v4
; CHECK-NOVSX-NEXT: blr ; CHECK-NOVSX-NEXT: blr
; ;
; CHECK-P7-LABEL: testmrghh2: ; CHECK-P7-LABEL: testmrghh2:
; CHECK-P7: # %bb.0: # %entry ; CHECK-P7: # %bb.0: # %entry
; CHECK-P7-NEXT: addis r3, r2, .LCPI3_0@toc@ha ; CHECK-P7-NEXT: addis r3, r2, .LCPI3_0@toc@ha
; CHECK-P7-NEXT: addi r3, r3, .LCPI3_0@toc@l ; CHECK-P7-NEXT: addi r3, r3, .LCPI3_0@toc@l
; CHECK-P7-NEXT: lvx v4, 0, r3 ; CHECK-P7-NEXT: lxvd2x vs0, 0, r3
; CHECK-P7-NEXT: xxswapd v4, vs0
; CHECK-P7-NEXT: vperm v2, v3, v2, v4 ; CHECK-P7-NEXT: vperm v2, v3, v2, v4
; CHECK-P7-NEXT: blr ; CHECK-P7-NEXT: blr
; ;
; P8-AIX-LABEL: testmrghh2: ; P8-AIX-LABEL: testmrghh2:
; P8-AIX: # %bb.0: # %entry ; P8-AIX: # %bb.0: # %entry
; P8-AIX-NEXT: vmrglh v2, v3, v2 ; P8-AIX-NEXT: vmrglh v2, v3, v2
; P8-AIX-NEXT: blr ; P8-AIX-NEXT: blr
entry: entry:
▲ Show 20 Lines • Show All 57 Lines • ▼ Show 20 Lines
; CHECK-NOVSX-NEXT: lvx v4, 0, r3 ; CHECK-NOVSX-NEXT: lvx v4, 0, r3
; CHECK-NOVSX-NEXT: vperm v2, v3, v2, v4 ; CHECK-NOVSX-NEXT: vperm v2, v3, v2, v4
; CHECK-NOVSX-NEXT: blr ; CHECK-NOVSX-NEXT: blr
; ;
; CHECK-P7-LABEL: testmrglb2: ; CHECK-P7-LABEL: testmrglb2:
; CHECK-P7: # %bb.0: # %entry ; CHECK-P7: # %bb.0: # %entry
; CHECK-P7-NEXT: addis r3, r2, .LCPI5_0@toc@ha ; CHECK-P7-NEXT: addis r3, r2, .LCPI5_0@toc@ha
; CHECK-P7-NEXT: addi r3, r3, .LCPI5_0@toc@l ; CHECK-P7-NEXT: addi r3, r3, .LCPI5_0@toc@l
; CHECK-P7-NEXT: lvx v4, 0, r3 ; CHECK-P7-NEXT: lxvd2x vs0, 0, r3
; CHECK-P7-NEXT: xxswapd v4, vs0
; CHECK-P7-NEXT: vperm v2, v3, v2, v4 ; CHECK-P7-NEXT: vperm v2, v3, v2, v4
; CHECK-P7-NEXT: blr ; CHECK-P7-NEXT: blr
; ;
; P8-AIX-LABEL: testmrglb2: ; P8-AIX-LABEL: testmrglb2:
; P8-AIX: # %bb.0: # %entry ; P8-AIX: # %bb.0: # %entry
; P8-AIX-NEXT: vmrghb v2, v3, v2 ; P8-AIX-NEXT: vmrghb v2, v3, v2
; P8-AIX-NEXT: blr ; P8-AIX-NEXT: blr
entry: entry:
▲ Show 20 Lines • Show All 57 Lines • ▼ Show 20 Lines
; CHECK-NOVSX-NEXT: lvx v4, 0, r3 ; CHECK-NOVSX-NEXT: lvx v4, 0, r3
; CHECK-NOVSX-NEXT: vperm v2, v3, v2, v4 ; CHECK-NOVSX-NEXT: vperm v2, v3, v2, v4
; CHECK-NOVSX-NEXT: blr ; CHECK-NOVSX-NEXT: blr
; ;
; CHECK-P7-LABEL: testmrglh2: ; CHECK-P7-LABEL: testmrglh2:
; CHECK-P7: # %bb.0: # %entry ; CHECK-P7: # %bb.0: # %entry
; CHECK-P7-NEXT: addis r3, r2, .LCPI7_0@toc@ha ; CHECK-P7-NEXT: addis r3, r2, .LCPI7_0@toc@ha
; CHECK-P7-NEXT: addi r3, r3, .LCPI7_0@toc@l ; CHECK-P7-NEXT: addi r3, r3, .LCPI7_0@toc@l
; CHECK-P7-NEXT: lvx v4, 0, r3 ; CHECK-P7-NEXT: lxvd2x vs0, 0, r3
; CHECK-P7-NEXT: xxswapd v4, vs0
; CHECK-P7-NEXT: vperm v2, v3, v2, v4 ; CHECK-P7-NEXT: vperm v2, v3, v2, v4
; CHECK-P7-NEXT: blr ; CHECK-P7-NEXT: blr
; ;
; P8-AIX-LABEL: testmrglh2: ; P8-AIX-LABEL: testmrglh2:
; P8-AIX: # %bb.0: # %entry ; P8-AIX: # %bb.0: # %entry
; P8-AIX-NEXT: vmrghh v2, v3, v2 ; P8-AIX-NEXT: vmrghh v2, v3, v2
; P8-AIX-NEXT: blr ; P8-AIX-NEXT: blr
entry: entry:
▲ Show 20 Lines • Show All 57 Lines • ▼ Show 20 Lines
; CHECK-NOVSX-NEXT: lvx v4, 0, r3 ; CHECK-NOVSX-NEXT: lvx v4, 0, r3
; CHECK-NOVSX-NEXT: vperm v2, v3, v2, v4 ; CHECK-NOVSX-NEXT: vperm v2, v3, v2, v4
; CHECK-NOVSX-NEXT: blr ; CHECK-NOVSX-NEXT: blr
; ;
; CHECK-P7-LABEL: testmrghw2: ; CHECK-P7-LABEL: testmrghw2:
; CHECK-P7: # %bb.0: # %entry ; CHECK-P7: # %bb.0: # %entry
; CHECK-P7-NEXT: addis r3, r2, .LCPI9_0@toc@ha ; CHECK-P7-NEXT: addis r3, r2, .LCPI9_0@toc@ha
; CHECK-P7-NEXT: addi r3, r3, .LCPI9_0@toc@l ; CHECK-P7-NEXT: addi r3, r3, .LCPI9_0@toc@l
; CHECK-P7-NEXT: lvx v4, 0, r3 ; CHECK-P7-NEXT: lxvd2x vs0, 0, r3
; CHECK-P7-NEXT: xxswapd v4, vs0
; CHECK-P7-NEXT: vperm v2, v3, v2, v4 ; CHECK-P7-NEXT: vperm v2, v3, v2, v4
; CHECK-P7-NEXT: blr ; CHECK-P7-NEXT: blr
; ;
; P8-AIX-LABEL: testmrghw2: ; P8-AIX-LABEL: testmrghw2:
; P8-AIX: # %bb.0: # %entry ; P8-AIX: # %bb.0: # %entry
; P8-AIX-NEXT: xxmrglw v2, v3, v2 ; P8-AIX-NEXT: xxmrglw v2, v3, v2
; P8-AIX-NEXT: blr ; P8-AIX-NEXT: blr
entry: entry:
▲ Show 20 Lines • Show All 57 Lines • ▼ Show 20 Lines
; CHECK-NOVSX-NEXT: lvx v4, 0, r3 ; CHECK-NOVSX-NEXT: lvx v4, 0, r3
; CHECK-NOVSX-NEXT: vperm v2, v3, v2, v4 ; CHECK-NOVSX-NEXT: vperm v2, v3, v2, v4
; CHECK-NOVSX-NEXT: blr ; CHECK-NOVSX-NEXT: blr
; ;
; CHECK-P7-LABEL: testmrglw2: ; CHECK-P7-LABEL: testmrglw2:
; CHECK-P7: # %bb.0: # %entry ; CHECK-P7: # %bb.0: # %entry
; CHECK-P7-NEXT: addis r3, r2, .LCPI11_0@toc@ha ; CHECK-P7-NEXT: addis r3, r2, .LCPI11_0@toc@ha
; CHECK-P7-NEXT: addi r3, r3, .LCPI11_0@toc@l ; CHECK-P7-NEXT: addi r3, r3, .LCPI11_0@toc@l
; CHECK-P7-NEXT: lvx v4, 0, r3 ; CHECK-P7-NEXT: lxvd2x vs0, 0, r3
; CHECK-P7-NEXT: xxswapd v4, vs0
; CHECK-P7-NEXT: vperm v2, v3, v2, v4 ; CHECK-P7-NEXT: vperm v2, v3, v2, v4
; CHECK-P7-NEXT: blr ; CHECK-P7-NEXT: blr
; ;
; P8-AIX-LABEL: testmrglw2: ; P8-AIX-LABEL: testmrglw2:
; P8-AIX: # %bb.0: # %entry ; P8-AIX: # %bb.0: # %entry
; P8-AIX-NEXT: xxmrghw v2, v3, v2 ; P8-AIX-NEXT: xxmrghw v2, v3, v2
; P8-AIX-NEXT: blr ; P8-AIX-NEXT: blr
entry: entry:
▲ Show 20 Lines • Show All 41 Lines • ▼ Show 20 Lines
; ;
; CHECK-P7-LABEL: testmrglb3: ; CHECK-P7-LABEL: testmrglb3:
; CHECK-P7: # %bb.0: # %entry ; CHECK-P7: # %bb.0: # %entry
; CHECK-P7-NEXT: ld r3, 0(r3) ; CHECK-P7-NEXT: ld r3, 0(r3)
; CHECK-P7-NEXT: addi r4, r1, -16 ; CHECK-P7-NEXT: addi r4, r1, -16
; CHECK-P7-NEXT: xxlxor v4, v4, v4 ; CHECK-P7-NEXT: xxlxor v4, v4, v4
; CHECK-P7-NEXT: std r3, -16(r1) ; CHECK-P7-NEXT: std r3, -16(r1)
; CHECK-P7-NEXT: addis r3, r2, .LCPI12_0@toc@ha ; CHECK-P7-NEXT: addis r3, r2, .LCPI12_0@toc@ha
; CHECK-P7-NEXT: lxvd2x vs0, 0, r4
; CHECK-P7-NEXT: addi r3, r3, .LCPI12_0@toc@l ; CHECK-P7-NEXT: addi r3, r3, .LCPI12_0@toc@l
; CHECK-P7-NEXT: lvx v3, 0, r3 ; CHECK-P7-NEXT: lxvd2x vs0, 0, r4
; CHECK-P7-NEXT: lxvd2x vs1, 0, r3
; CHECK-P7-NEXT: xxswapd v2, vs0 ; CHECK-P7-NEXT: xxswapd v2, vs0
; CHECK-P7-NEXT: xxswapd v3, vs1
; CHECK-P7-NEXT: vperm v2, v2, v4, v3 ; CHECK-P7-NEXT: vperm v2, v2, v4, v3
; CHECK-P7-NEXT: blr ; CHECK-P7-NEXT: blr
; ;
; P8-AIX-64-LABEL: testmrglb3: ; P8-AIX-64-LABEL: testmrglb3:
; P8-AIX-64: # %bb.0: # %entry ; P8-AIX-64: # %bb.0: # %entry
; P8-AIX-64-NEXT: ld r4, L..C0(r2) # %const.0 ; P8-AIX-64-NEXT: ld r4, L..C0(r2) # %const.0
; P8-AIX-64-NEXT: lxsdx v2, 0, r3 ; P8-AIX-64-NEXT: lxsdx v2, 0, r3
; P8-AIX-64-NEXT: xxlxor v4, v4, v4 ; P8-AIX-64-NEXT: xxlxor v4, v4, v4
▲ Show 20 Lines • Show All 160 Lines • ▼ Show 20 Lines
; CHECK-NOVSX-NEXT: blr ; CHECK-NOVSX-NEXT: blr
; ;
; CHECK-P7-LABEL: no_crash_bitcast: ; CHECK-P7-LABEL: no_crash_bitcast:
; CHECK-P7: # %bb.0: # %entry ; CHECK-P7: # %bb.0: # %entry
; CHECK-P7-NEXT: addis r4, r2, .LCPI14_0@toc@ha ; CHECK-P7-NEXT: addis r4, r2, .LCPI14_0@toc@ha
; CHECK-P7-NEXT: stw r3, -16(r1) ; CHECK-P7-NEXT: stw r3, -16(r1)
; CHECK-P7-NEXT: addi r3, r1, -16 ; CHECK-P7-NEXT: addi r3, r1, -16
; CHECK-P7-NEXT: addi r4, r4, .LCPI14_0@toc@l ; CHECK-P7-NEXT: addi r4, r4, .LCPI14_0@toc@l
; CHECK-P7-NEXT: lvx v3, 0, r3 ; CHECK-P7-NEXT: lxvd2x vs1, 0, r3
; CHECK-P7-NEXT: lvx v2, 0, r4 ; CHECK-P7-NEXT: lxvd2x vs0, 0, r4
; CHECK-P7-NEXT: xxswapd v3, vs1
; CHECK-P7-NEXT: xxswapd v2, vs0
; CHECK-P7-NEXT: vperm v2, v3, v3, v2 ; CHECK-P7-NEXT: vperm v2, v3, v3, v2
; CHECK-P7-NEXT: blr ; CHECK-P7-NEXT: blr
; ;
; P8-AIX-64-LABEL: no_crash_bitcast: ; P8-AIX-64-LABEL: no_crash_bitcast:
; P8-AIX-64: # %bb.0: # %entry ; P8-AIX-64: # %bb.0: # %entry
; P8-AIX-64-NEXT: mtfprwz f0, r3 ; P8-AIX-64-NEXT: mtfprwz f0, r3
; P8-AIX-64-NEXT: xxmrghw v2, vs0, vs0 ; P8-AIX-64-NEXT: xxmrghw v2, vs0, vs0
; P8-AIX-64-NEXT: blr ; P8-AIX-64-NEXT: blr
Show All 13 Linesentry:
ret <16 x i8> %ret ret <16 x i8> %ret
} }
define dso_local <4 x i32> @replace_undefs_in_splat(<4 x i32> %a) local_unnamed_addr #0 { define dso_local <4 x i32> @replace_undefs_in_splat(<4 x i32> %a) local_unnamed_addr #0 {
; CHECK-P8-LABEL: replace_undefs_in_splat: ; CHECK-P8-LABEL: replace_undefs_in_splat:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: addis r3, r2, .LCPI15_0@toc@ha ; CHECK-P8-NEXT: addis r3, r2, .LCPI15_0@toc@ha
; CHECK-P8-NEXT: addi r3, r3, .LCPI15_0@toc@l ; CHECK-P8-NEXT: addi r3, r3, .LCPI15_0@toc@l
; CHECK-P8-NEXT: lvx v3, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: xxswapd v3, vs0
; CHECK-P8-NEXT: vmrgow v2, v3, v2 ; CHECK-P8-NEXT: vmrgow v2, v3, v2
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: replace_undefs_in_splat: ; CHECK-P9-LABEL: replace_undefs_in_splat:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: addis r3, r2, .LCPI15_0@toc@ha ; CHECK-P9-NEXT: addis r3, r2, .LCPI15_0@toc@ha
; CHECK-P9-NEXT: addi r3, r3, .LCPI15_0@toc@l ; CHECK-P9-NEXT: addi r3, r3, .LCPI15_0@toc@l
; CHECK-P9-NEXT: lxv v3, 0(r3) ; CHECK-P9-NEXT: lxv v3, 0(r3)
Show All 22 Lines
; CHECK-NOVSX-NEXT: vperm v2, v4, v2, v3 ; CHECK-NOVSX-NEXT: vperm v2, v4, v2, v3
; CHECK-NOVSX-NEXT: blr ; CHECK-NOVSX-NEXT: blr
; ;
; CHECK-P7-LABEL: replace_undefs_in_splat: ; CHECK-P7-LABEL: replace_undefs_in_splat:
; CHECK-P7: # %bb.0: # %entry ; CHECK-P7: # %bb.0: # %entry
; CHECK-P7-NEXT: addis r3, r2, .LCPI15_0@toc@ha ; CHECK-P7-NEXT: addis r3, r2, .LCPI15_0@toc@ha
; CHECK-P7-NEXT: addis r4, r2, .LCPI15_1@toc@ha ; CHECK-P7-NEXT: addis r4, r2, .LCPI15_1@toc@ha
; CHECK-P7-NEXT: addi r3, r3, .LCPI15_0@toc@l ; CHECK-P7-NEXT: addi r3, r3, .LCPI15_0@toc@l
; CHECK-P7-NEXT: lvx v3, 0, r3 ; CHECK-P7-NEXT: lxvd2x vs0, 0, r3
; CHECK-P7-NEXT: addi r3, r4, .LCPI15_1@toc@l ; CHECK-P7-NEXT: addi r3, r4, .LCPI15_1@toc@l
; CHECK-P7-NEXT: lvx v4, 0, r3 ; CHECK-P7-NEXT: lxvd2x vs1, 0, r3
; CHECK-P7-NEXT: xxswapd v3, vs0
; CHECK-P7-NEXT: xxswapd v4, vs1
; CHECK-P7-NEXT: vperm v2, v4, v2, v3 ; CHECK-P7-NEXT: vperm v2, v4, v2, v3
; CHECK-P7-NEXT: blr ; CHECK-P7-NEXT: blr
; ;
; P8-AIX-64-LABEL: replace_undefs_in_splat: ; P8-AIX-64-LABEL: replace_undefs_in_splat:
; P8-AIX-64: # %bb.0: # %entry ; P8-AIX-64: # %bb.0: # %entry
; P8-AIX-64-NEXT: ld r3, L..C1(r2) # %const.0 ; P8-AIX-64-NEXT: ld r3, L..C1(r2) # %const.0
; P8-AIX-64-NEXT: ld r4, L..C2(r2) # %const.1 ; P8-AIX-64-NEXT: ld r4, L..C2(r2) # %const.1
; P8-AIX-64-NEXT: lxvw4x v3, 0, r3 ; P8-AIX-64-NEXT: lxvw4x v3, 0, r3
▲ Show 20 Lines • Show All 316 Lines • ▼ Show 20 Linesentry:
%0 = load <1 x i64>, <1 x i64>* %ptr, align 8 %0 = load <1 x i64>, <1 x i64>* %ptr, align 8
%1 = shufflevector <1 x i64> %0, <1 x i64> undef, <2 x i32> <i32 0, i32 0> %1 = shufflevector <1 x i64> %0, <1 x i64> undef, <2 x i32> <i32 0, i32 0>
ret <2 x i64> %1 ret <2 x i64> %1
} }
define <2 x i64> @testSplati64_1(<2 x i64>* nocapture readonly %ptr) #0 { define <2 x i64> @testSplati64_1(<2 x i64>* nocapture readonly %ptr) #0 {
; CHECK-P8-LABEL: testSplati64_1: ; CHECK-P8-LABEL: testSplati64_1:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: lxvd2x vs0, 0, r3 ; CHECK-P8-NEXT: addi r3, r3, 8
; CHECK-P8-NEXT: xxspltd v2, vs0, 1 ; CHECK-P8-NEXT: lxvdsx v2, 0, r3
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: testSplati64_1: ; CHECK-P9-LABEL: testSplati64_1:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: addi r3, r3, 8 ; CHECK-P9-NEXT: addi r3, r3, 8
; CHECK-P9-NEXT: lxvdsx v2, 0, r3 ; CHECK-P9-NEXT: lxvdsx v2, 0, r3
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
Show All 14 Lines
; CHECK-NOVSX-NEXT: std r3, -16(r1) ; CHECK-NOVSX-NEXT: std r3, -16(r1)
; CHECK-NOVSX-NEXT: addi r3, r1, -16 ; CHECK-NOVSX-NEXT: addi r3, r1, -16
; CHECK-NOVSX-NEXT: lvx v3, 0, r3 ; CHECK-NOVSX-NEXT: lvx v3, 0, r3
; CHECK-NOVSX-NEXT: vperm v2, v3, v3, v2 ; CHECK-NOVSX-NEXT: vperm v2, v3, v3, v2
; CHECK-NOVSX-NEXT: blr ; CHECK-NOVSX-NEXT: blr
; ;
; CHECK-P7-LABEL: testSplati64_1: ; CHECK-P7-LABEL: testSplati64_1:
; CHECK-P7: # %bb.0: # %entry ; CHECK-P7: # %bb.0: # %entry
; CHECK-P7-NEXT: lxvd2x vs0, 0, r3 ; CHECK-P7-NEXT: addi r3, r3, 8
; CHECK-P7-NEXT: xxspltd v2, vs0, 1 ; CHECK-P7-NEXT: lxvdsx v2, 0, r3
; CHECK-P7-NEXT: blr ; CHECK-P7-NEXT: blr
; ;
; P8-AIX-LABEL: testSplati64_1: ; P8-AIX-LABEL: testSplati64_1:
; P8-AIX: # %bb.0: # %entry ; P8-AIX: # %bb.0: # %entry
; P8-AIX-NEXT: addi r3, r3, 8 ; P8-AIX-NEXT: addi r3, r3, 8
; P8-AIX-NEXT: lxvdsx v2, 0, r3 ; P8-AIX-NEXT: lxvdsx v2, 0, r3
; P8-AIX-NEXT: blr ; P8-AIX-NEXT: blr
entry: entry:
%0 = load <2 x i64>, <2 x i64>* %ptr, align 8 %0 = load <2 x i64>, <2 x i64>* %ptr, align 8
%1 = shufflevector <2 x i64> %0, <2 x i64> undef, <2 x i32> <i32 1, i32 1> %1 = shufflevector <2 x i64> %0, <2 x i64> undef, <2 x i32> <i32 1, i32 1>
ret <2 x i64> %1 ret <2 x i64> %1
} }
define dso_local void @testByteSplat() #0 { define dso_local void @testByteSplat() #0 {
; CHECK-P8-LABEL: testByteSplat: ; CHECK-P8-LABEL: testByteSplat:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: lbzx r3, 0, r3 ; CHECK-P8-NEXT: lbzx r3, 0, r3
; CHECK-P8-NEXT: mtvsrwz v2, r3 ; CHECK-P8-NEXT: mtvsrwz v2, r3
; CHECK-P8-NEXT: vspltb v2, v2, 7 ; CHECK-P8-NEXT: vspltb v2, v2, 7
; CHECK-P8-NEXT: stvx v2, 0, r3 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: stxvd2x vs0, 0, r3
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: testByteSplat: ; CHECK-P9-LABEL: testByteSplat:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lxsibzx v2, 0, r3 ; CHECK-P9-NEXT: lxsibzx v2, 0, r3
; CHECK-P9-NEXT: vspltb v2, v2, 7 ; CHECK-P9-NEXT: vspltb v2, v2, 7
; CHECK-P9-NEXT: stxv v2, 0(r3) ; CHECK-P9-NEXT: stxv v2, 0(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
Show All 16 Lines
; CHECK-NOVSX-NEXT: blr ; CHECK-NOVSX-NEXT: blr
; ;
; CHECK-P7-LABEL: testByteSplat: ; CHECK-P7-LABEL: testByteSplat:
; CHECK-P7: # %bb.0: # %entry ; CHECK-P7: # %bb.0: # %entry
; CHECK-P7-NEXT: lvsr v2, 0, r3 ; CHECK-P7-NEXT: lvsr v2, 0, r3
; CHECK-P7-NEXT: lvx v3, 0, r3 ; CHECK-P7-NEXT: lvx v3, 0, r3
; CHECK-P7-NEXT: vperm v2, v3, v3, v2 ; CHECK-P7-NEXT: vperm v2, v3, v3, v2
; CHECK-P7-NEXT: vspltb v2, v2, 15 ; CHECK-P7-NEXT: vspltb v2, v2, 15
; CHECK-P7-NEXT: stvx v2, 0, r3 ; CHECK-P7-NEXT: xxswapd vs0, v2
; CHECK-P7-NEXT: stxvd2x vs0, 0, r3
; CHECK-P7-NEXT: blr ; CHECK-P7-NEXT: blr
; ;
; P8-AIX-LABEL: testByteSplat: ; P8-AIX-LABEL: testByteSplat:
; P8-AIX: # %bb.0: # %entry ; P8-AIX: # %bb.0: # %entry
; P8-AIX-NEXT: lbzx r3, 0, r3 ; P8-AIX-NEXT: lbzx r3, 0, r3
; P8-AIX-NEXT: mtvsrwz v2, r3 ; P8-AIX-NEXT: mtvsrwz v2, r3
; P8-AIX-NEXT: vspltb v2, v2, 7 ; P8-AIX-NEXT: vspltb v2, v2, 7
; P8-AIX-NEXT: stxvw4x v2, 0, r3 ; P8-AIX-NEXT: stxvw4x v2, 0, r3
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llvm/test/CodeGen/PowerPC/crypto_bifs_be.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: -mcpu=pwr8 < %s | FileCheck %s --check-prefixes=CHECK-LE-P8 ; RUN: -mcpu=pwr8 < %s | FileCheck %s --check-prefixes=CHECK-LE-P8
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: -mcpu=pwr9 < %s | FileCheck %s --check-prefixes=CHECK-P9 ; RUN: -mcpu=pwr9 < %s | FileCheck %s --check-prefixes=CHECK-P9
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
; RUN: -mcpu=pwr8 < %s | FileCheck %s --check-prefixes=CHECK-BE-P8 ; RUN: -mcpu=pwr8 < %s | FileCheck %s --check-prefixes=CHECK-BE-P8
define <16 x i8> @test_vpermxorb() local_unnamed_addr { define <16 x i8> @test_vpermxorb() local_unnamed_addr {
; CHECK-LE-P8-LABEL: test_vpermxorb: ; CHECK-LE-P8-LABEL: test_vpermxorb:
; CHECK-LE-P8: # %bb.0: # %entry ; CHECK-LE-P8: # %bb.0: # %entry
; CHECK-LE-P8-NEXT: addis 3, 2, .LCPI0_0@toc@ha ; CHECK-LE-P8-NEXT: addis 3, 2, .LCPI0_0@toc@ha
; CHECK-LE-P8-NEXT: addis 4, 2, .LCPI0_1@toc@ha ; CHECK-LE-P8-NEXT: addis 4, 2, .LCPI0_1@toc@ha
; CHECK-LE-P8-NEXT: addi 3, 3, .LCPI0_0@toc@l ; CHECK-LE-P8-NEXT: addi 3, 3, .LCPI0_0@toc@l
; CHECK-LE-P8-NEXT: lvx 2, 0, 3 ; CHECK-LE-P8-NEXT: addi 4, 4, .LCPI0_1@toc@l
; CHECK-LE-P8-NEXT: addi 3, 4, .LCPI0_1@toc@l ; CHECK-LE-P8-NEXT: lxvd2x 0, 0, 3
; CHECK-LE-P8-NEXT: lvx 3, 0, 3 ; CHECK-LE-P8-NEXT: lxvd2x 1, 0, 4
; CHECK-LE-P8-NEXT: xxswapd 34, 0
; CHECK-LE-P8-NEXT: xxswapd 35, 1
; CHECK-LE-P8-NEXT: vpermxor 2, 3, 2, 2 ; CHECK-LE-P8-NEXT: vpermxor 2, 3, 2, 2
; CHECK-LE-P8-NEXT: blr ; CHECK-LE-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test_vpermxorb: ; CHECK-P9-LABEL: test_vpermxorb:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: addis 3, 2, .LCPI0_0@toc@ha ; CHECK-P9-NEXT: addis 3, 2, .LCPI0_0@toc@ha
; CHECK-P9-NEXT: addi 3, 3, .LCPI0_0@toc@l ; CHECK-P9-NEXT: addi 3, 3, .LCPI0_0@toc@l
; CHECK-P9-NEXT: lxv 34, 0(3) ; CHECK-P9-NEXT: lxv 34, 0(3)
Show All 21 Lines
declare <16 x i8> @llvm.ppc.altivec.crypto.vpermxor.be(<16 x i8>, <16 x i8>, <16 x i8>) declare <16 x i8> @llvm.ppc.altivec.crypto.vpermxor.be(<16 x i8>, <16 x i8>, <16 x i8>)
define <8 x i16> @test_vpermxorh() local_unnamed_addr { define <8 x i16> @test_vpermxorh() local_unnamed_addr {
; CHECK-LE-P8-LABEL: test_vpermxorh: ; CHECK-LE-P8-LABEL: test_vpermxorh:
; CHECK-LE-P8: # %bb.0: # %entry ; CHECK-LE-P8: # %bb.0: # %entry
; CHECK-LE-P8-NEXT: addis 3, 2, .LCPI1_0@toc@ha ; CHECK-LE-P8-NEXT: addis 3, 2, .LCPI1_0@toc@ha
; CHECK-LE-P8-NEXT: addis 4, 2, .LCPI1_1@toc@ha ; CHECK-LE-P8-NEXT: addis 4, 2, .LCPI1_1@toc@ha
; CHECK-LE-P8-NEXT: addi 3, 3, .LCPI1_0@toc@l ; CHECK-LE-P8-NEXT: addi 3, 3, .LCPI1_0@toc@l
; CHECK-LE-P8-NEXT: lvx 2, 0, 3 ; CHECK-LE-P8-NEXT: addi 4, 4, .LCPI1_1@toc@l
; CHECK-LE-P8-NEXT: addi 3, 4, .LCPI1_1@toc@l ; CHECK-LE-P8-NEXT: lxvd2x 0, 0, 3
; CHECK-LE-P8-NEXT: lvx 3, 0, 3 ; CHECK-LE-P8-NEXT: lxvd2x 1, 0, 4
; CHECK-LE-P8-NEXT: xxswapd 34, 0
; CHECK-LE-P8-NEXT: xxswapd 35, 1
; CHECK-LE-P8-NEXT: vpermxor 2, 3, 2, 2 ; CHECK-LE-P8-NEXT: vpermxor 2, 3, 2, 2
; CHECK-LE-P8-NEXT: blr ; CHECK-LE-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test_vpermxorh: ; CHECK-P9-LABEL: test_vpermxorh:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: addis 3, 2, .LCPI1_0@toc@ha ; CHECK-P9-NEXT: addis 3, 2, .LCPI1_0@toc@ha
; CHECK-P9-NEXT: addi 3, 3, .LCPI1_0@toc@l ; CHECK-P9-NEXT: addi 3, 3, .LCPI1_0@toc@l
; CHECK-P9-NEXT: lxv 34, 0(3) ; CHECK-P9-NEXT: lxv 34, 0(3)
Show All 20 Lines
} }
define <4 x i32> @test_vpermxorw() local_unnamed_addr { define <4 x i32> @test_vpermxorw() local_unnamed_addr {
; CHECK-LE-P8-LABEL: test_vpermxorw: ; CHECK-LE-P8-LABEL: test_vpermxorw:
; CHECK-LE-P8: # %bb.0: # %entry ; CHECK-LE-P8: # %bb.0: # %entry
; CHECK-LE-P8-NEXT: addis 3, 2, .LCPI2_0@toc@ha ; CHECK-LE-P8-NEXT: addis 3, 2, .LCPI2_0@toc@ha
; CHECK-LE-P8-NEXT: addis 4, 2, .LCPI2_1@toc@ha ; CHECK-LE-P8-NEXT: addis 4, 2, .LCPI2_1@toc@ha
; CHECK-LE-P8-NEXT: addi 3, 3, .LCPI2_0@toc@l ; CHECK-LE-P8-NEXT: addi 3, 3, .LCPI2_0@toc@l
; CHECK-LE-P8-NEXT: lvx 2, 0, 3 ; CHECK-LE-P8-NEXT: addi 4, 4, .LCPI2_1@toc@l
; CHECK-LE-P8-NEXT: addi 3, 4, .LCPI2_1@toc@l ; CHECK-LE-P8-NEXT: lxvd2x 0, 0, 3
; CHECK-LE-P8-NEXT: lvx 3, 0, 3 ; CHECK-LE-P8-NEXT: lxvd2x 1, 0, 4
; CHECK-LE-P8-NEXT: xxswapd 34, 0
; CHECK-LE-P8-NEXT: xxswapd 35, 1
; CHECK-LE-P8-NEXT: vpermxor 2, 3, 2, 2 ; CHECK-LE-P8-NEXT: vpermxor 2, 3, 2, 2
; CHECK-LE-P8-NEXT: blr ; CHECK-LE-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test_vpermxorw: ; CHECK-P9-LABEL: test_vpermxorw:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: addis 3, 2, .LCPI2_0@toc@ha ; CHECK-P9-NEXT: addis 3, 2, .LCPI2_0@toc@ha
; CHECK-P9-NEXT: addi 3, 3, .LCPI2_0@toc@l ; CHECK-P9-NEXT: addi 3, 3, .LCPI2_0@toc@l
; CHECK-P9-NEXT: lxv 34, 0(3) ; CHECK-P9-NEXT: lxv 34, 0(3)
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} }
define <2 x i64> @test_vpermxord() local_unnamed_addr { define <2 x i64> @test_vpermxord() local_unnamed_addr {
; CHECK-LE-P8-LABEL: test_vpermxord: ; CHECK-LE-P8-LABEL: test_vpermxord:
; CHECK-LE-P8: # %bb.0: # %entry ; CHECK-LE-P8: # %bb.0: # %entry
; CHECK-LE-P8-NEXT: addis 3, 2, .LCPI3_0@toc@ha ; CHECK-LE-P8-NEXT: addis 3, 2, .LCPI3_0@toc@ha
; CHECK-LE-P8-NEXT: addis 4, 2, .LCPI3_1@toc@ha ; CHECK-LE-P8-NEXT: addis 4, 2, .LCPI3_1@toc@ha
; CHECK-LE-P8-NEXT: addi 3, 3, .LCPI3_0@toc@l ; CHECK-LE-P8-NEXT: addi 3, 3, .LCPI3_0@toc@l
; CHECK-LE-P8-NEXT: lvx 2, 0, 3 ; CHECK-LE-P8-NEXT: addi 4, 4, .LCPI3_1@toc@l
; CHECK-LE-P8-NEXT: addi 3, 4, .LCPI3_1@toc@l ; CHECK-LE-P8-NEXT: lxvd2x 0, 0, 3
; CHECK-LE-P8-NEXT: lvx 3, 0, 3 ; CHECK-LE-P8-NEXT: lxvd2x 1, 0, 4
; CHECK-LE-P8-NEXT: xxswapd 34, 0
; CHECK-LE-P8-NEXT: xxswapd 35, 1
; CHECK-LE-P8-NEXT: vpermxor 2, 3, 2, 2 ; CHECK-LE-P8-NEXT: vpermxor 2, 3, 2, 2
; CHECK-LE-P8-NEXT: blr ; CHECK-LE-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test_vpermxord: ; CHECK-P9-LABEL: test_vpermxord:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: addis 3, 2, .LCPI3_0@toc@ha ; CHECK-P9-NEXT: addis 3, 2, .LCPI3_0@toc@ha
; CHECK-P9-NEXT: addi 3, 3, .LCPI3_0@toc@l ; CHECK-P9-NEXT: addi 3, 3, .LCPI3_0@toc@l
; CHECK-P9-NEXT: lxv 34, 0(3) ; CHECK-P9-NEXT: lxv 34, 0(3)
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llvm/test/CodeGen/PowerPC/extract-and-store.ll

Show First 20 Lines • Show All 567 Lines • ▼ Show 20 Lines
define dso_local void @test_stores_exceed_vec_size(<4 x i32> %a, i32* nocapture %b) local_unnamed_addr #0 { define dso_local void @test_stores_exceed_vec_size(<4 x i32> %a, i32* nocapture %b) local_unnamed_addr #0 {
; CHECK-LABEL: test_stores_exceed_vec_size: ; CHECK-LABEL: test_stores_exceed_vec_size:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r3, r2, .LCPI16_0@toc@ha ; CHECK-NEXT: addis r3, r2, .LCPI16_0@toc@ha
; CHECK-NEXT: xxsldwi vs1, vs34, vs34, 1 ; CHECK-NEXT: xxsldwi vs1, vs34, vs34, 1
; CHECK-NEXT: li r4, 20 ; CHECK-NEXT: li r4, 20
; CHECK-NEXT: addi r3, r3, .LCPI16_0@toc@l ; CHECK-NEXT: addi r3, r3, .LCPI16_0@toc@l
; CHECK-NEXT: lvx v3, 0, r3 ; CHECK-NEXT: lxvd2x vs0, 0, r3
; CHECK-NEXT: li r3, 16 ; CHECK-NEXT: li r3, 16
; CHECK-NEXT: xxswapd vs35, vs0
; CHECK-NEXT: vperm v3, v2, v2, v3 ; CHECK-NEXT: vperm v3, v2, v2, v3
; CHECK-NEXT: xxswapd vs0, vs35 ; CHECK-NEXT: xxswapd vs0, vs35
; CHECK-NEXT: stxvd2x vs0, 0, r5 ; CHECK-NEXT: stxvd2x vs0, 0, r5
; CHECK-NEXT: stfiwx f1, r5, r3 ; CHECK-NEXT: stfiwx f1, r5, r3
; CHECK-NEXT: stxsiwx vs34, r5, r4 ; CHECK-NEXT: stxsiwx vs34, r5, r4
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-BE-LABEL: test_stores_exceed_vec_size: ; CHECK-BE-LABEL: test_stores_exceed_vec_size:
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llvm/test/CodeGen/PowerPC/f128-aggregates.ll

Show All 25 Lines
; CHECK-BE-LABEL: testArray_01: ; CHECK-BE-LABEL: testArray_01:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxv v2, 32(r3) ; CHECK-BE-NEXT: lxv v2, 32(r3)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
; ;
; CHECK-P8-LABEL: testArray_01: ; CHECK-P8-LABEL: testArray_01:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: addi r3, r3, 32 ; CHECK-P8-NEXT: addi r3, r3, 32
; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
entry: entry:
%arrayidx = getelementptr inbounds fp128, fp128* %sa, i64 2 %arrayidx = getelementptr inbounds fp128, fp128* %sa, i64 2
%0 = load fp128, fp128* %arrayidx, align 16 %0 = load fp128, fp128* %arrayidx, align 16
ret fp128 %0 ret fp128 %0
} }
Show All 13 Lines
; CHECK-BE-NEXT: lxv v2, 32(r3) ; CHECK-BE-NEXT: lxv v2, 32(r3)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
; ;
; CHECK-P8-LABEL: testArray_02: ; CHECK-P8-LABEL: testArray_02:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: addis r3, r2, .LC0@toc@ha ; CHECK-P8-NEXT: addis r3, r2, .LC0@toc@ha
; CHECK-P8-NEXT: ld r3, .LC0@toc@l(r3) ; CHECK-P8-NEXT: ld r3, .LC0@toc@l(r3)
; CHECK-P8-NEXT: addi r3, r3, 32 ; CHECK-P8-NEXT: addi r3, r3, 32
; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
entry: entry:
%0 = load fp128, fp128* getelementptr inbounds ([3 x fp128], [3 x fp128]* @a1, %0 = load fp128, fp128* getelementptr inbounds ([3 x fp128], [3 x fp128]* @a1,
i64 0, i64 2), align 16 i64 0, i64 2), align 16
ret fp128 %0 ret fp128 %0
} }
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; CHECK-P8-LABEL: testStruct_03: ; CHECK-P8-LABEL: testStruct_03:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: li r11, 96 ; CHECK-P8-NEXT: li r11, 96
; CHECK-P8-NEXT: addi r12, r1, 32 ; CHECK-P8-NEXT: addi r12, r1, 32
; CHECK-P8-NEXT: std r3, 32(r1) ; CHECK-P8-NEXT: std r3, 32(r1)
; CHECK-P8-NEXT: std r4, 40(r1) ; CHECK-P8-NEXT: std r4, 40(r1)
; CHECK-P8-NEXT: std r5, 48(r1) ; CHECK-P8-NEXT: std r5, 48(r1)
; CHECK-P8-NEXT: std r6, 56(r1) ; CHECK-P8-NEXT: std r6, 56(r1)
; CHECK-P8-NEXT: lvx v2, r12, r11 ; CHECK-P8-NEXT: lxvd2x vs0, r12, r11
; CHECK-P8-NEXT: std r7, 64(r1) ; CHECK-P8-NEXT: std r7, 64(r1)
; CHECK-P8-NEXT: std r8, 72(r1) ; CHECK-P8-NEXT: std r8, 72(r1)
; CHECK-P8-NEXT: std r9, 80(r1) ; CHECK-P8-NEXT: std r9, 80(r1)
; CHECK-P8-NEXT: std r10, 88(r1) ; CHECK-P8-NEXT: std r10, 88(r1)
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
entry: entry:
%a7 = getelementptr inbounds %struct.With9fp128params, %a7 = getelementptr inbounds %struct.With9fp128params,
%struct.With9fp128params* %a, i64 0, i32 6 %struct.With9fp128params* %a, i64 0, i32 6
%0 = load fp128, fp128* %a7, align 16 %0 = load fp128, fp128* %a7, align 16
ret fp128 %0 ret fp128 %0
} }
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; CHECK-BE-NEXT: mtvsrdd v2, r8, r7 ; CHECK-BE-NEXT: mtvsrdd v2, r8, r7
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
; ;
; CHECK-P8-LABEL: testMixedAggregate: ; CHECK-P8-LABEL: testMixedAggregate:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: addi r3, r1, -16 ; CHECK-P8-NEXT: addi r3, r1, -16
; CHECK-P8-NEXT: std r8, -8(r1) ; CHECK-P8-NEXT: std r8, -8(r1)
; CHECK-P8-NEXT: std r7, -16(r1) ; CHECK-P8-NEXT: std r7, -16(r1)
; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
entry: entry:
%a.coerce.fca.2.extract = extractvalue [3 x i128] %a.coerce, 2 %a.coerce.fca.2.extract = extractvalue [3 x i128] %a.coerce, 2
%0 = bitcast i128 %a.coerce.fca.2.extract to fp128 %0 = bitcast i128 %a.coerce.fca.2.extract to fp128
ret fp128 %0 ret fp128 %0
} }
Show All 9 Lines
; CHECK-BE-NEXT: mtvsrdd v2, r6, r5 ; CHECK-BE-NEXT: mtvsrdd v2, r6, r5
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
; ;
; CHECK-P8-LABEL: testMixedAggregate_02: ; CHECK-P8-LABEL: testMixedAggregate_02:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: addi r3, r1, -16 ; CHECK-P8-NEXT: addi r3, r1, -16
; CHECK-P8-NEXT: std r6, -8(r1) ; CHECK-P8-NEXT: std r6, -8(r1)
; CHECK-P8-NEXT: std r5, -16(r1) ; CHECK-P8-NEXT: std r5, -16(r1)
; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
entry: entry:
%a.coerce.fca.1.extract = extractvalue [4 x i128] %a.coerce, 1 %a.coerce.fca.1.extract = extractvalue [4 x i128] %a.coerce, 1
%0 = bitcast i128 %a.coerce.fca.1.extract to fp128 %0 = bitcast i128 %a.coerce.fca.1.extract to fp128
ret fp128 %0 ret fp128 %0
} }
Show All 33 Lines
; CHECK-P8-NEXT: li r4, 64 ; CHECK-P8-NEXT: li r4, 64
; CHECK-P8-NEXT: std r30, 80(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, 80(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: extsw r3, r3 ; CHECK-P8-NEXT: extsw r3, r3
; CHECK-P8-NEXT: mr r30, r10 ; CHECK-P8-NEXT: mr r30, r10
; CHECK-P8-NEXT: stvx v31, r1, r4 # 16-byte Folded Spill ; CHECK-P8-NEXT: stvx v31, r1, r4 # 16-byte Folded Spill
; CHECK-P8-NEXT: addi r4, r1, 48 ; CHECK-P8-NEXT: addi r4, r1, 48
; CHECK-P8-NEXT: std r6, 56(r1) ; CHECK-P8-NEXT: std r6, 56(r1)
; CHECK-P8-NEXT: std r5, 48(r1) ; CHECK-P8-NEXT: std r5, 48(r1)
; CHECK-P8-NEXT: lvx v31, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r4
; CHECK-P8-NEXT: xxswapd v31, vs0
; CHECK-P8-NEXT: bl __floatsikf ; CHECK-P8-NEXT: bl __floatsikf
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: vmr v3, v2 ; CHECK-P8-NEXT: vmr v3, v2
; CHECK-P8-NEXT: vmr v2, v31 ; CHECK-P8-NEXT: vmr v2, v31
; CHECK-P8-NEXT: bl __addkf3 ; CHECK-P8-NEXT: bl __addkf3
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: mr r3, r30 ; CHECK-P8-NEXT: mr r3, r30
; CHECK-P8-NEXT: vmr v31, v2 ; CHECK-P8-NEXT: vmr v31, v2
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; CHECK-P8-LABEL: testNestedAggregate: ; CHECK-P8-LABEL: testNestedAggregate:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: li r11, 32 ; CHECK-P8-NEXT: li r11, 32
; CHECK-P8-NEXT: std r8, 72(r1) ; CHECK-P8-NEXT: std r8, 72(r1)
; CHECK-P8-NEXT: std r7, 64(r1) ; CHECK-P8-NEXT: std r7, 64(r1)
; CHECK-P8-NEXT: std r9, 80(r1) ; CHECK-P8-NEXT: std r9, 80(r1)
; CHECK-P8-NEXT: std r10, 88(r1) ; CHECK-P8-NEXT: std r10, 88(r1)
; CHECK-P8-NEXT: addi r7, r1, 32 ; CHECK-P8-NEXT: addi r7, r1, 32
; CHECK-P8-NEXT: lvx v2, r7, r11 ; CHECK-P8-NEXT: lxvd2x vs0, r7, r11
; CHECK-P8-NEXT: std r3, 32(r1) ; CHECK-P8-NEXT: std r3, 32(r1)
; CHECK-P8-NEXT: std r4, 40(r1) ; CHECK-P8-NEXT: std r4, 40(r1)
; CHECK-P8-NEXT: std r5, 48(r1) ; CHECK-P8-NEXT: std r5, 48(r1)
; CHECK-P8-NEXT: std r6, 56(r1) ; CHECK-P8-NEXT: std r6, 56(r1)
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
entry: entry:
%c = getelementptr inbounds %struct.MixedC, %struct.MixedC* %a, i64 0, i32 1, i32 1 %c = getelementptr inbounds %struct.MixedC, %struct.MixedC* %a, i64 0, i32 1, i32 1
%0 = load fp128, fp128* %c, align 16 %0 = load fp128, fp128* %c, align 16
ret fp128 %0 ret fp128 %0
} }
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; CHECK-BE-NEXT: mtvsrdd v2, r4, r3 ; CHECK-BE-NEXT: mtvsrdd v2, r4, r3
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
; ;
; CHECK-P8-LABEL: testUnion_01: ; CHECK-P8-LABEL: testUnion_01:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: addi r5, r1, -16 ; CHECK-P8-NEXT: addi r5, r1, -16
; CHECK-P8-NEXT: std r4, -8(r1) ; CHECK-P8-NEXT: std r4, -8(r1)
; CHECK-P8-NEXT: std r3, -16(r1) ; CHECK-P8-NEXT: std r3, -16(r1)
; CHECK-P8-NEXT: lvx v2, 0, r5 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r5
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
entry: entry:
%a.coerce.fca.0.extract = extractvalue [1 x i128] %a.coerce, 0 %a.coerce.fca.0.extract = extractvalue [1 x i128] %a.coerce, 0
%0 = bitcast i128 %a.coerce.fca.0.extract to fp128 %0 = bitcast i128 %a.coerce.fca.0.extract to fp128
ret fp128 %0 ret fp128 %0
} }
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; CHECK-BE-NEXT: mtvsrdd v2, r4, r3 ; CHECK-BE-NEXT: mtvsrdd v2, r4, r3
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
; ;
; CHECK-P8-LABEL: testUnion_02: ; CHECK-P8-LABEL: testUnion_02:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: addi r5, r1, -16 ; CHECK-P8-NEXT: addi r5, r1, -16
; CHECK-P8-NEXT: std r4, -8(r1) ; CHECK-P8-NEXT: std r4, -8(r1)
; CHECK-P8-NEXT: std r3, -16(r1) ; CHECK-P8-NEXT: std r3, -16(r1)
; CHECK-P8-NEXT: lvx v2, 0, r5 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r5
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
entry: entry:
%a.coerce.fca.0.extract = extractvalue [1 x i128] %a.coerce, 0 %a.coerce.fca.0.extract = extractvalue [1 x i128] %a.coerce, 0
%0 = bitcast i128 %a.coerce.fca.0.extract to fp128 %0 = bitcast i128 %a.coerce.fca.0.extract to fp128
ret fp128 %0 ret fp128 %0
} }
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; CHECK-BE-NEXT: mtvsrdd v2, r8, r7 ; CHECK-BE-NEXT: mtvsrdd v2, r8, r7
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
; ;
; CHECK-P8-LABEL: testUnion_03: ; CHECK-P8-LABEL: testUnion_03:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: addi r3, r1, -16 ; CHECK-P8-NEXT: addi r3, r1, -16
; CHECK-P8-NEXT: std r8, -8(r1) ; CHECK-P8-NEXT: std r8, -8(r1)
; CHECK-P8-NEXT: std r7, -16(r1) ; CHECK-P8-NEXT: std r7, -16(r1)
; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
entry: entry:
%a.coerce.fca.2.extract = extractvalue [4 x i128] %a.coerce, 2 %a.coerce.fca.2.extract = extractvalue [4 x i128] %a.coerce, 2
%0 = bitcast i128 %a.coerce.fca.2.extract to fp128 %0 = bitcast i128 %a.coerce.fca.2.extract to fp128
ret fp128 %0 ret fp128 %0
} }
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; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -64(r1) ; CHECK-P8-NEXT: stdu r1, -64(r1)
; CHECK-P8-NEXT: addis r11, r2, .LCPI17_0@toc@ha ; CHECK-P8-NEXT: addis r11, r2, .LCPI17_0@toc@ha
; CHECK-P8-NEXT: cmpwi r3, 1 ; CHECK-P8-NEXT: cmpwi r3, 1
; CHECK-P8-NEXT: std r4, 104(r1) ; CHECK-P8-NEXT: std r4, 104(r1)
; CHECK-P8-NEXT: std r5, 112(r1) ; CHECK-P8-NEXT: std r5, 112(r1)
; CHECK-P8-NEXT: std r6, 120(r1) ; CHECK-P8-NEXT: std r6, 120(r1)
; CHECK-P8-NEXT: std r7, 128(r1) ; CHECK-P8-NEXT: std r7, 128(r1)
; CHECK-P8-NEXT: addi r3, r11, .LCPI17_0@toc@l ; CHECK-P8-NEXT: addi r11, r11, .LCPI17_0@toc@l
; CHECK-P8-NEXT: lxvd2x vs0, 0, r11
; CHECK-P8-NEXT: std r8, 136(r1) ; CHECK-P8-NEXT: std r8, 136(r1)
; CHECK-P8-NEXT: std r9, 144(r1) ; CHECK-P8-NEXT: std r9, 144(r1)
; CHECK-P8-NEXT: std r10, 152(r1) ; CHECK-P8-NEXT: std r10, 152(r1)
; CHECK-P8-NEXT: xxswapd v3, vs0
; CHECK-P8-NEXT: blt cr0, .LBB17_2 ; CHECK-P8-NEXT: blt cr0, .LBB17_2
; CHECK-P8-NEXT: # %bb.1: # %if.end ; CHECK-P8-NEXT: # %bb.1: # %if.end
; CHECK-P8-NEXT: addi r30, r1, 104 ; CHECK-P8-NEXT: addi r30, r1, 104
; CHECK-P8-NEXT: lvx v3, 0, r3
; CHECK-P8-NEXT: lxvd2x vs0, 0, r30 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r30
; CHECK-P8-NEXT: xxswapd v2, vs0 ; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: bl __addkf3 ; CHECK-P8-NEXT: bl __addkf3
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: li r3, 16 ; CHECK-P8-NEXT: li r3, 16
; CHECK-P8-NEXT: lxvd2x vs0, r30, r3 ; CHECK-P8-NEXT: lxvd2x vs0, r30, r3
; CHECK-P8-NEXT: addi r3, r1, 136 ; CHECK-P8-NEXT: addi r3, r1, 136
; CHECK-P8-NEXT: std r3, 40(r1) ; CHECK-P8-NEXT: std r3, 40(r1)
; CHECK-P8-NEXT: xxswapd v3, vs0 ; CHECK-P8-NEXT: xxswapd v3, vs0
; CHECK-P8-NEXT: bl __addkf3 ; CHECK-P8-NEXT: bl __addkf3
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: b .LBB17_3 ; CHECK-P8-NEXT: vmr v3, v2
; CHECK-P8-NEXT: .LBB17_2: ; CHECK-P8-NEXT: .LBB17_2: # %cleanup
; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: vmr v2, v3
; CHECK-P8-NEXT: .LBB17_3: # %cleanup
; CHECK-P8-NEXT: addi r1, r1, 64 ; CHECK-P8-NEXT: addi r1, r1, 64
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
entry: entry:
%ap = alloca i8*, align 8 %ap = alloca i8*, align 8
%0 = bitcast i8** %ap to i8* %0 = bitcast i8** %ap to i8*
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llvm/test/CodeGen/PowerPC/f128-arith.ll

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; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: .cfi_def_cfa_offset 48 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 48
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: mr r30, r4 ; CHECK-P8-NEXT: mr r30, r4
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: vmr v3, v2 ; CHECK-P8-NEXT: vmr v3, v2
; CHECK-P8-NEXT: bl __addkf3 ; CHECK-P8-NEXT: bl __addkf3
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: stvx v2, 0, r30 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: stxvd2x vs0, 0, r30
; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: addi r1, r1, 48
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
entry: entry:
%0 = load fp128, fp128* %a, align 16 %0 = load fp128, fp128* %a, align 16
%add = fadd fp128 %0, %0 %add = fadd fp128 %0, %0
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; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: .cfi_def_cfa_offset 48 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 48
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: mr r30, r4 ; CHECK-P8-NEXT: mr r30, r4
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: vmr v3, v2 ; CHECK-P8-NEXT: vmr v3, v2
; CHECK-P8-NEXT: bl __subkf3 ; CHECK-P8-NEXT: bl __subkf3
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: stvx v2, 0, r30 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: stxvd2x vs0, 0, r30
; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: addi r1, r1, 48
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
entry: entry:
%0 = load fp128, fp128* %a, align 16 %0 = load fp128, fp128* %a, align 16
%sub = fsub fp128 %0, %0 %sub = fsub fp128 %0, %0
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; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: .cfi_def_cfa_offset 48 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 48
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: mr r30, r4 ; CHECK-P8-NEXT: mr r30, r4
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: vmr v3, v2 ; CHECK-P8-NEXT: vmr v3, v2
; CHECK-P8-NEXT: bl __mulkf3 ; CHECK-P8-NEXT: bl __mulkf3
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: stvx v2, 0, r30 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: stxvd2x vs0, 0, r30
; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: addi r1, r1, 48
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
entry: entry:
%0 = load fp128, fp128* %a, align 16 %0 = load fp128, fp128* %a, align 16
%mul = fmul fp128 %0, %0 %mul = fmul fp128 %0, %0
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; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: .cfi_def_cfa_offset 48 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 48
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: mr r30, r4 ; CHECK-P8-NEXT: mr r30, r4
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: vmr v3, v2 ; CHECK-P8-NEXT: vmr v3, v2
; CHECK-P8-NEXT: bl __divkf3 ; CHECK-P8-NEXT: bl __divkf3
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: stvx v2, 0, r30 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: stxvd2x vs0, 0, r30
; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: addi r1, r1, 48
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
entry: entry:
%0 = load fp128, fp128* %a, align 16 %0 = load fp128, fp128* %a, align 16
%div = fdiv fp128 %0, %0 %div = fdiv fp128 %0, %0
store fp128 %div, fp128* %res, align 16 store fp128 %div, fp128* %res, align 16
ret void ret void
} }
define dso_local void @testLdNSt(i8* nocapture readonly %PtrC, fp128* nocapture %PtrF) { define dso_local void @testLdNSt(i8* nocapture readonly %PtrC, fp128* nocapture %PtrF) {
; CHECK-LABEL: testLdNSt: ; CHECK-LABEL: testLdNSt:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: li r5, 4 ; CHECK-NEXT: li r5, 4
; CHECK-NEXT: lxvx vs0, r3, r5 ; CHECK-NEXT: lxvx vs0, r3, r5
; CHECK-NEXT: li r3, 8 ; CHECK-NEXT: li r3, 8
; CHECK-NEXT: stxvx vs0, r4, r3 ; CHECK-NEXT: stxvx vs0, r4, r3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LABEL: testLdNSt: ; CHECK-P8-LABEL: testLdNSt:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: addi r3, r3, 4 ; CHECK-P8-NEXT: addi r3, r3, 4
; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: addi r3, r4, 8 ; CHECK-P8-NEXT: addi r3, r4, 8
; CHECK-P8-NEXT: stvx v2, 0, r3 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r3
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
entry: entry:
%add.ptr = getelementptr inbounds i8, i8* %PtrC, i64 4 %add.ptr = getelementptr inbounds i8, i8* %PtrC, i64 4
%0 = bitcast i8* %add.ptr to fp128* %0 = bitcast i8* %add.ptr to fp128*
%1 = load fp128, fp128* %0, align 16 %1 = load fp128, fp128* %0, align 16
%2 = bitcast fp128* %PtrF to i8* %2 = bitcast fp128* %PtrF to i8*
%add.ptr1 = getelementptr inbounds i8, i8* %2, i64 8 %add.ptr1 = getelementptr inbounds i8, i8* %2, i64 8
%3 = bitcast i8* %add.ptr1 to fp128* %3 = bitcast i8* %add.ptr1 to fp128*
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; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: .cfi_def_cfa_offset 48 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 48
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: mr r30, r4 ; CHECK-P8-NEXT: mr r30, r4
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: bl sqrtf128 ; CHECK-P8-NEXT: bl sqrtf128
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: stvx v2, 0, r30 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: stxvd2x vs0, 0, r30
; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: addi r1, r1, 48
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
entry: entry:
%0 = load fp128, fp128* %a, align 16 %0 = load fp128, fp128* %a, align 16
%1 = tail call fp128 @llvm.sqrt.f128(fp128 %0) %1 = tail call fp128 @llvm.sqrt.f128(fp128 %0)
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; CHECK-NEXT: lxv v2, 0(r3) ; CHECK-NEXT: lxv v2, 0(r3)
; CHECK-NEXT: lxv v3, 0(r4) ; CHECK-NEXT: lxv v3, 0(r4)
; CHECK-NEXT: xscpsgnqp v2, v3, v2 ; CHECK-NEXT: xscpsgnqp v2, v3, v2
; CHECK-NEXT: stxv v2, 0(r5) ; CHECK-NEXT: stxv v2, 0(r5)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LABEL: qpCpsgn: ; CHECK-P8-LABEL: qpCpsgn:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r4
; CHECK-P8-NEXT: lvx v3, 0, r4 ; CHECK-P8-NEXT: addi r4, r1, -16
; CHECK-P8-NEXT: addi r3, r1, -16 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r4
; CHECK-P8-NEXT: addi r4, r1, -32 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: stvx v3, 0, r3 ; CHECK-P8-NEXT: addi r3, r1, -32
; CHECK-P8-NEXT: stvx v2, 0, r4 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r3
; CHECK-P8-NEXT: lbz r3, -1(r1) ; CHECK-P8-NEXT: lbz r4, -1(r1)
; CHECK-P8-NEXT: lbz r6, -17(r1) ; CHECK-P8-NEXT: lbz r6, -17(r1)
; CHECK-P8-NEXT: rlwimi r6, r3, 0, 0, 24 ; CHECK-P8-NEXT: rlwimi r6, r4, 0, 0, 24
; CHECK-P8-NEXT: stb r6, -17(r1) ; CHECK-P8-NEXT: stb r6, -17(r1)
; CHECK-P8-NEXT: lvx v2, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: stvx v2, 0, r5 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r5
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
fp128* nocapture %res) { fp128* nocapture %res) {
entry: entry:
%0 = load fp128, fp128* %a, align 16 %0 = load fp128, fp128* %a, align 16
%1 = load fp128, fp128* %b, align 16 %1 = load fp128, fp128* %b, align 16
%2 = tail call fp128 @llvm.copysign.f128(fp128 %0, fp128 %1) %2 = tail call fp128 @llvm.copysign.f128(fp128 %0, fp128 %1)
store fp128 %2, fp128* %res, align 16 store fp128 %2, fp128* %res, align 16
ret void ret void
} }
declare fp128 @llvm.copysign.f128(fp128 %Mag, fp128 %Sgn) declare fp128 @llvm.copysign.f128(fp128 %Mag, fp128 %Sgn)
define dso_local void @qpAbs(fp128* nocapture readonly %a, fp128* nocapture %res) { define dso_local void @qpAbs(fp128* nocapture readonly %a, fp128* nocapture %res) {
; CHECK-LABEL: qpAbs: ; CHECK-LABEL: qpAbs:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lxv v2, 0(r3) ; CHECK-NEXT: lxv v2, 0(r3)
; CHECK-NEXT: xsabsqp v2, v2 ; CHECK-NEXT: xsabsqp v2, v2
; CHECK-NEXT: stxv v2, 0(r4) ; CHECK-NEXT: stxv v2, 0(r4)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LABEL: qpAbs: ; CHECK-P8-LABEL: qpAbs:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: addi r3, r1, -16 ; CHECK-P8-NEXT: addi r3, r1, -16
; CHECK-P8-NEXT: stvx v2, 0, r3 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r3
; CHECK-P8-NEXT: lbz r5, -1(r1) ; CHECK-P8-NEXT: lbz r5, -1(r1)
; CHECK-P8-NEXT: clrlwi r5, r5, 25 ; CHECK-P8-NEXT: clrlwi r5, r5, 25
; CHECK-P8-NEXT: stb r5, -1(r1) ; CHECK-P8-NEXT: stb r5, -1(r1)
; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: stvx v2, 0, r4 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r4
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
entry: entry:
%0 = load fp128, fp128* %a, align 16 %0 = load fp128, fp128* %a, align 16
%1 = tail call fp128 @llvm.fabs.f128(fp128 %0) %1 = tail call fp128 @llvm.fabs.f128(fp128 %0)
store fp128 %1, fp128* %res, align 16 store fp128 %1, fp128* %res, align 16
ret void ret void
} }
declare fp128 @llvm.fabs.f128(fp128 %Val) declare fp128 @llvm.fabs.f128(fp128 %Val)
define dso_local void @qpNAbs(fp128* nocapture readonly %a, fp128* nocapture %res) { define dso_local void @qpNAbs(fp128* nocapture readonly %a, fp128* nocapture %res) {
; CHECK-LABEL: qpNAbs: ; CHECK-LABEL: qpNAbs:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lxv v2, 0(r3) ; CHECK-NEXT: lxv v2, 0(r3)
; CHECK-NEXT: xsnabsqp v2, v2 ; CHECK-NEXT: xsnabsqp v2, v2
; CHECK-NEXT: stxv v2, 0(r4) ; CHECK-NEXT: stxv v2, 0(r4)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LABEL: qpNAbs: ; CHECK-P8-LABEL: qpNAbs:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: addi r3, r1, -32 ; CHECK-P8-NEXT: addi r3, r1, -32
; CHECK-P8-NEXT: stvx v2, 0, r3 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r3
; CHECK-P8-NEXT: lbz r5, -17(r1) ; CHECK-P8-NEXT: lbz r5, -17(r1)
; CHECK-P8-NEXT: clrlwi r5, r5, 25 ; CHECK-P8-NEXT: clrlwi r5, r5, 25
; CHECK-P8-NEXT: stb r5, -17(r1) ; CHECK-P8-NEXT: stb r5, -17(r1)
; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: addi r3, r1, -16 ; CHECK-P8-NEXT: addi r3, r1, -16
; CHECK-P8-NEXT: stvx v2, 0, r3 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r3
; CHECK-P8-NEXT: lbz r5, -1(r1) ; CHECK-P8-NEXT: lbz r5, -1(r1)
; CHECK-P8-NEXT: xori r5, r5, 128 ; CHECK-P8-NEXT: xori r5, r5, 128
; CHECK-P8-NEXT: stb r5, -1(r1) ; CHECK-P8-NEXT: stb r5, -1(r1)
; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: stvx v2, 0, r4 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r4
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
entry: entry:
%0 = load fp128, fp128* %a, align 16 %0 = load fp128, fp128* %a, align 16
%1 = tail call fp128 @llvm.fabs.f128(fp128 %0) %1 = tail call fp128 @llvm.fabs.f128(fp128 %0)
%neg = fsub fp128 0xL00000000000000008000000000000000, %1 %neg = fsub fp128 0xL00000000000000008000000000000000, %1
store fp128 %neg, fp128* %res, align 16 store fp128 %neg, fp128* %res, align 16
ret void ret void
} }
define dso_local void @qpNeg(fp128* nocapture readonly %a, fp128* nocapture %res) { define dso_local void @qpNeg(fp128* nocapture readonly %a, fp128* nocapture %res) {
; CHECK-LABEL: qpNeg: ; CHECK-LABEL: qpNeg:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lxv v2, 0(r3) ; CHECK-NEXT: lxv v2, 0(r3)
; CHECK-NEXT: xsnegqp v2, v2 ; CHECK-NEXT: xsnegqp v2, v2
; CHECK-NEXT: stxv v2, 0(r4) ; CHECK-NEXT: stxv v2, 0(r4)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LABEL: qpNeg: ; CHECK-P8-LABEL: qpNeg:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: addi r3, r1, -16 ; CHECK-P8-NEXT: addi r3, r1, -16
; CHECK-P8-NEXT: stvx v2, 0, r3 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r3
; CHECK-P8-NEXT: lbz r5, -1(r1) ; CHECK-P8-NEXT: lbz r5, -1(r1)
; CHECK-P8-NEXT: xori r5, r5, 128 ; CHECK-P8-NEXT: xori r5, r5, 128
; CHECK-P8-NEXT: stb r5, -1(r1) ; CHECK-P8-NEXT: stb r5, -1(r1)
; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: stvx v2, 0, r4 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r4
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
entry: entry:
%0 = load fp128, fp128* %a, align 16 %0 = load fp128, fp128* %a, align 16
%sub = fsub fp128 0xL00000000000000008000000000000000, %0 %sub = fsub fp128 0xL00000000000000008000000000000000, %0
store fp128 %sub, fp128* %res, align 16 store fp128 %sub, fp128* %res, align 16
ret void ret void
} }
Show All 16 Lines
; ;
; CHECK-P8-LABEL: qp_sin: ; CHECK-P8-LABEL: qp_sin:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -32(r1) ; CHECK-P8-NEXT: stdu r1, -32(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 32 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 32
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: bl sinf128 ; CHECK-P8-NEXT: bl sinf128
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: addi r1, r1, 32 ; CHECK-P8-NEXT: addi r1, r1, 32
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
entry: entry:
%0 = load fp128, fp128* %a, align 16 %0 = load fp128, fp128* %a, align 16
Show All 20 Lines
; ;
; CHECK-P8-LABEL: qp_cos: ; CHECK-P8-LABEL: qp_cos:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -32(r1) ; CHECK-P8-NEXT: stdu r1, -32(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 32 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 32
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: bl cosf128 ; CHECK-P8-NEXT: bl cosf128
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: addi r1, r1, 32 ; CHECK-P8-NEXT: addi r1, r1, 32
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
entry: entry:
%0 = load fp128, fp128* %a, align 16 %0 = load fp128, fp128* %a, align 16
Show All 20 Lines
; ;
; CHECK-P8-LABEL: qp_log: ; CHECK-P8-LABEL: qp_log:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -32(r1) ; CHECK-P8-NEXT: stdu r1, -32(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 32 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 32
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: bl logf128 ; CHECK-P8-NEXT: bl logf128
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: addi r1, r1, 32 ; CHECK-P8-NEXT: addi r1, r1, 32
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
entry: entry:
%0 = load fp128, fp128* %a, align 16 %0 = load fp128, fp128* %a, align 16
Show All 20 Lines
; ;
; CHECK-P8-LABEL: qp_log10: ; CHECK-P8-LABEL: qp_log10:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -32(r1) ; CHECK-P8-NEXT: stdu r1, -32(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 32 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 32
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: bl log10f128 ; CHECK-P8-NEXT: bl log10f128
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: addi r1, r1, 32 ; CHECK-P8-NEXT: addi r1, r1, 32
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
entry: entry:
%0 = load fp128, fp128* %a, align 16 %0 = load fp128, fp128* %a, align 16
Show All 20 Lines
; ;
; CHECK-P8-LABEL: qp_log2: ; CHECK-P8-LABEL: qp_log2:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -32(r1) ; CHECK-P8-NEXT: stdu r1, -32(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 32 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 32
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: bl log2f128 ; CHECK-P8-NEXT: bl log2f128
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: addi r1, r1, 32 ; CHECK-P8-NEXT: addi r1, r1, 32
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
entry: entry:
%0 = load fp128, fp128* %a, align 16 %0 = load fp128, fp128* %a, align 16
Show All 21 Lines
; ;
; CHECK-P8-LABEL: qp_minnum: ; CHECK-P8-LABEL: qp_minnum:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -32(r1) ; CHECK-P8-NEXT: stdu r1, -32(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 32 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 32
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: lvx v3, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs1, 0, r4
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: xxswapd v3, vs1
; CHECK-P8-NEXT: bl fminf128 ; CHECK-P8-NEXT: bl fminf128
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: addi r1, r1, 32 ; CHECK-P8-NEXT: addi r1, r1, 32
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
fp128* nocapture readonly %b) { fp128* nocapture readonly %b) {
entry: entry:
Show All 23 Lines
; ;
; CHECK-P8-LABEL: qp_maxnum: ; CHECK-P8-LABEL: qp_maxnum:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -32(r1) ; CHECK-P8-NEXT: stdu r1, -32(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 32 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 32
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: lvx v3, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs1, 0, r4
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: xxswapd v3, vs1
; CHECK-P8-NEXT: bl fmaxf128 ; CHECK-P8-NEXT: bl fmaxf128
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: addi r1, r1, 32 ; CHECK-P8-NEXT: addi r1, r1, 32
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
fp128* nocapture readonly %b) { fp128* nocapture readonly %b) {
entry: entry:
Show All 23 Lines
; ;
; CHECK-P8-LABEL: qp_pow: ; CHECK-P8-LABEL: qp_pow:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -32(r1) ; CHECK-P8-NEXT: stdu r1, -32(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 32 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 32
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: lvx v3, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs1, 0, r4
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: xxswapd v3, vs1
; CHECK-P8-NEXT: bl powf128 ; CHECK-P8-NEXT: bl powf128
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: addi r1, r1, 32 ; CHECK-P8-NEXT: addi r1, r1, 32
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
fp128* nocapture readonly %b) { fp128* nocapture readonly %b) {
entry: entry:
Show All 22 Lines
; ;
; CHECK-P8-LABEL: qp_exp: ; CHECK-P8-LABEL: qp_exp:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -32(r1) ; CHECK-P8-NEXT: stdu r1, -32(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 32 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 32
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: bl expf128 ; CHECK-P8-NEXT: bl expf128
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: addi r1, r1, 32 ; CHECK-P8-NEXT: addi r1, r1, 32
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
entry: entry:
%0 = load fp128, fp128* %a, align 16 %0 = load fp128, fp128* %a, align 16
Show All 20 Lines
; ;
; CHECK-P8-LABEL: qp_exp2: ; CHECK-P8-LABEL: qp_exp2:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -32(r1) ; CHECK-P8-NEXT: stdu r1, -32(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 32 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 32
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: bl exp2f128 ; CHECK-P8-NEXT: bl exp2f128
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: addi r1, r1, 32 ; CHECK-P8-NEXT: addi r1, r1, 32
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
entry: entry:
%0 = load fp128, fp128* %a, align 16 %0 = load fp128, fp128* %a, align 16
Show All 28 Lines
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: .cfi_def_cfa_offset 48 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 48
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: lwz r3, 0(r4) ; CHECK-P8-NEXT: lwz r3, 0(r4)
; CHECK-P8-NEXT: mr r30, r5 ; CHECK-P8-NEXT: mr r30, r5
; CHECK-P8-NEXT: mr r5, r3 ; CHECK-P8-NEXT: mr r5, r3
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: bl __powikf2 ; CHECK-P8-NEXT: bl __powikf2
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: stvx v2, 0, r30 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: stxvd2x vs0, 0, r30
; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: addi r1, r1, 48
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
fp128* nocapture %res) { fp128* nocapture %res) {
entry: entry:
%0 = load fp128, fp128* %a, align 16 %0 = load fp128, fp128* %a, align 16
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; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -32(r1) ; CHECK-P8-NEXT: stdu r1, -32(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 32 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 32
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: addis r3, r2, a@toc@ha ; CHECK-P8-NEXT: addis r3, r2, a@toc@ha
; CHECK-P8-NEXT: addis r4, r2, b@toc@ha ; CHECK-P8-NEXT: addis r4, r2, b@toc@ha
; CHECK-P8-NEXT: addi r3, r3, a@toc@l ; CHECK-P8-NEXT: addi r3, r3, a@toc@l
; CHECK-P8-NEXT: addi r4, r4, b@toc@l ; CHECK-P8-NEXT: addi r4, r4, b@toc@l
; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: lvx v3, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs1, 0, r4
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: xxswapd v3, vs1
; CHECK-P8-NEXT: bl fmodf128 ; CHECK-P8-NEXT: bl fmodf128
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: addi r1, r1, 32 ; CHECK-P8-NEXT: addi r1, r1, 32
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
entry: entry:
%0 = load fp128, fp128* @a, align 16 %0 = load fp128, fp128* @a, align 16
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; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: .cfi_def_cfa_offset 48 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 48
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: mr r30, r4 ; CHECK-P8-NEXT: mr r30, r4
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: bl ceilf128 ; CHECK-P8-NEXT: bl ceilf128
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: stvx v2, 0, r30 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: stxvd2x vs0, 0, r30
; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: addi r1, r1, 48
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
entry: entry:
%0 = load fp128, fp128* %a, align 16 %0 = load fp128, fp128* %a, align 16
%1 = tail call fp128 @llvm.ceil.f128(fp128 %0) %1 = tail call fp128 @llvm.ceil.f128(fp128 %0)
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; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: .cfi_def_cfa_offset 48 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 48
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: mr r30, r4 ; CHECK-P8-NEXT: mr r30, r4
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: bl floorf128 ; CHECK-P8-NEXT: bl floorf128
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: stvx v2, 0, r30 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: stxvd2x vs0, 0, r30
; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: addi r1, r1, 48
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
entry: entry:
%0 = load fp128, fp128* %a, align 16 %0 = load fp128, fp128* %a, align 16
%1 = tail call fp128 @llvm.floor.f128(fp128 %0) %1 = tail call fp128 @llvm.floor.f128(fp128 %0)
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; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: .cfi_def_cfa_offset 48 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 48
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: mr r30, r4 ; CHECK-P8-NEXT: mr r30, r4
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: bl truncf128 ; CHECK-P8-NEXT: bl truncf128
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: stvx v2, 0, r30 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: stxvd2x vs0, 0, r30
; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: addi r1, r1, 48
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
entry: entry:
%0 = load fp128, fp128* %a, align 16 %0 = load fp128, fp128* %a, align 16
%1 = tail call fp128 @llvm.trunc.f128(fp128 %0) %1 = tail call fp128 @llvm.trunc.f128(fp128 %0)
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; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: .cfi_def_cfa_offset 48 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 48
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: mr r30, r4 ; CHECK-P8-NEXT: mr r30, r4
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: bl roundf128 ; CHECK-P8-NEXT: bl roundf128
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: stvx v2, 0, r30 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: stxvd2x vs0, 0, r30
; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: addi r1, r1, 48
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
entry: entry:
%0 = load fp128, fp128* %a, align 16 %0 = load fp128, fp128* %a, align 16
%1 = tail call fp128 @llvm.round.f128(fp128 %0) %1 = tail call fp128 @llvm.round.f128(fp128 %0)
Show All 27 Lines
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: .cfi_def_cfa_offset 48 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 48
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: mr r30, r4 ; CHECK-P8-NEXT: mr r30, r4
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: bl lroundf128 ; CHECK-P8-NEXT: bl lroundf128
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: stw r3, 0(r30) ; CHECK-P8-NEXT: stw r3, 0(r30)
; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: addi r1, r1, 48
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
Show All 30 Lines
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: .cfi_def_cfa_offset 48 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 48
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: mr r30, r4 ; CHECK-P8-NEXT: mr r30, r4
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: bl llroundf128 ; CHECK-P8-NEXT: bl llroundf128
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: std r3, 0(r30) ; CHECK-P8-NEXT: std r3, 0(r30)
; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: addi r1, r1, 48
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
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; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: .cfi_def_cfa_offset 48 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 48
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: mr r30, r4 ; CHECK-P8-NEXT: mr r30, r4
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: bl rintf128 ; CHECK-P8-NEXT: bl rintf128
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: stvx v2, 0, r30 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: stxvd2x vs0, 0, r30
; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: addi r1, r1, 48
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
entry: entry:
%0 = load fp128, fp128* %a, align 16 %0 = load fp128, fp128* %a, align 16
%1 = tail call fp128 @llvm.rint.f128(fp128 %0) %1 = tail call fp128 @llvm.rint.f128(fp128 %0)
Show All 27 Lines
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: .cfi_def_cfa_offset 48 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 48
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: mr r30, r4 ; CHECK-P8-NEXT: mr r30, r4
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: bl lrintf128 ; CHECK-P8-NEXT: bl lrintf128
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: stw r3, 0(r30) ; CHECK-P8-NEXT: stw r3, 0(r30)
; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: addi r1, r1, 48
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
Show All 30 Lines
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: .cfi_def_cfa_offset 48 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 48
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: mr r30, r4 ; CHECK-P8-NEXT: mr r30, r4
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: bl llrintf128 ; CHECK-P8-NEXT: bl llrintf128
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: std r3, 0(r30) ; CHECK-P8-NEXT: std r3, 0(r30)
; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: addi r1, r1, 48
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
Show All 17 Lines
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: .cfi_def_cfa_offset 48 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 48
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: mr r30, r4 ; CHECK-P8-NEXT: mr r30, r4
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: bl nearbyintf128 ; CHECK-P8-NEXT: bl nearbyintf128
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: stvx v2, 0, r30 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: stxvd2x vs0, 0, r30
; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: addi r1, r1, 48
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
entry: entry:
%0 = load fp128, fp128* %a, align 16 %0 = load fp128, fp128* %a, align 16
%1 = tail call fp128 @llvm.nearbyint.f128(fp128 %0) %1 = tail call fp128 @llvm.nearbyint.f128(fp128 %0)
Show All 16 Lines
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: .cfi_def_cfa_offset 48 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 48
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: lvx v3, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs1, 0, r4
; CHECK-P8-NEXT: lvx v4, 0, r5
; CHECK-P8-NEXT: mr r30, r6 ; CHECK-P8-NEXT: mr r30, r6
; CHECK-P8-NEXT: lxvd2x vs2, 0, r5
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: xxswapd v3, vs1
; CHECK-P8-NEXT: xxswapd v4, vs2
; CHECK-P8-NEXT: bl fmaf128 ; CHECK-P8-NEXT: bl fmaf128
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: stvx v2, 0, r30 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: stxvd2x vs0, 0, r30
; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: addi r1, r1, 48
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
entry: entry:
%0 = load fp128, fp128* %a, align 16 %0 = load fp128, fp128* %a, align 16
%1 = load fp128, fp128* %b, align 16 %1 = load fp128, fp128* %b, align 16
%2 = load fp128, fp128* %c, align 16 %2 = load fp128, fp128* %c, align 16
%3 = tail call fp128 @llvm.fma.f128(fp128 %0, fp128 %1, fp128 %2) %3 = tail call fp128 @llvm.fma.f128(fp128 %0, fp128 %1, fp128 %2)
store fp128 %3, fp128* %res, align 16 store fp128 %3, fp128* %res, align 16
ret void ret void
} }
declare fp128 @llvm.fma.f128(fp128, fp128, fp128) declare fp128 @llvm.fma.f128(fp128, fp128, fp128)

llvm/test/CodeGen/PowerPC/f128-compare.ll

Show All 29 Lines
; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -32(r1) ; CHECK-P8-NEXT: stdu r1, -32(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 32 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 32
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: addis r3, r2, a_qp@toc@ha ; CHECK-P8-NEXT: addis r3, r2, a_qp@toc@ha
; CHECK-P8-NEXT: addis r4, r2, b_qp@toc@ha ; CHECK-P8-NEXT: addis r4, r2, b_qp@toc@ha
; CHECK-P8-NEXT: addi r3, r3, a_qp@toc@l ; CHECK-P8-NEXT: addi r3, r3, a_qp@toc@l
; CHECK-P8-NEXT: addi r4, r4, b_qp@toc@l ; CHECK-P8-NEXT: addi r4, r4, b_qp@toc@l
; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: lvx v3, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs1, 0, r4
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: xxswapd v3, vs1
; CHECK-P8-NEXT: bl __gtkf2 ; CHECK-P8-NEXT: bl __gtkf2
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: extsw r3, r3 ; CHECK-P8-NEXT: extsw r3, r3
; CHECK-P8-NEXT: neg r3, r3 ; CHECK-P8-NEXT: neg r3, r3
; CHECK-P8-NEXT: rldicl r3, r3, 1, 63 ; CHECK-P8-NEXT: rldicl r3, r3, 1, 63
; CHECK-P8-NEXT: addi r1, r1, 32 ; CHECK-P8-NEXT: addi r1, r1, 32
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
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; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -32(r1) ; CHECK-P8-NEXT: stdu r1, -32(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 32 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 32
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: addis r3, r2, a_qp@toc@ha ; CHECK-P8-NEXT: addis r3, r2, a_qp@toc@ha
; CHECK-P8-NEXT: addis r4, r2, b_qp@toc@ha ; CHECK-P8-NEXT: addis r4, r2, b_qp@toc@ha
; CHECK-P8-NEXT: addi r3, r3, a_qp@toc@l ; CHECK-P8-NEXT: addi r3, r3, a_qp@toc@l
; CHECK-P8-NEXT: addi r4, r4, b_qp@toc@l ; CHECK-P8-NEXT: addi r4, r4, b_qp@toc@l
; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: lvx v3, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs1, 0, r4
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: xxswapd v3, vs1
; CHECK-P8-NEXT: bl __ltkf2 ; CHECK-P8-NEXT: bl __ltkf2
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: rlwinm r3, r3, 1, 31, 31 ; CHECK-P8-NEXT: rlwinm r3, r3, 1, 31, 31
; CHECK-P8-NEXT: addi r1, r1, 32 ; CHECK-P8-NEXT: addi r1, r1, 32
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
entry: entry:
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; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -32(r1) ; CHECK-P8-NEXT: stdu r1, -32(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 32 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 32
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: addis r3, r2, a_qp@toc@ha ; CHECK-P8-NEXT: addis r3, r2, a_qp@toc@ha
; CHECK-P8-NEXT: addis r4, r2, b_qp@toc@ha ; CHECK-P8-NEXT: addis r4, r2, b_qp@toc@ha
; CHECK-P8-NEXT: addi r3, r3, a_qp@toc@l ; CHECK-P8-NEXT: addi r3, r3, a_qp@toc@l
; CHECK-P8-NEXT: addi r4, r4, b_qp@toc@l ; CHECK-P8-NEXT: addi r4, r4, b_qp@toc@l
; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: lvx v3, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs1, 0, r4
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: xxswapd v3, vs1
; CHECK-P8-NEXT: bl __gekf2 ; CHECK-P8-NEXT: bl __gekf2
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: rlwinm r3, r3, 1, 31, 31 ; CHECK-P8-NEXT: rlwinm r3, r3, 1, 31, 31
; CHECK-P8-NEXT: xori r3, r3, 1 ; CHECK-P8-NEXT: xori r3, r3, 1
; CHECK-P8-NEXT: addi r1, r1, 32 ; CHECK-P8-NEXT: addi r1, r1, 32
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
Show All 27 Lines
; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -32(r1) ; CHECK-P8-NEXT: stdu r1, -32(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 32 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 32
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: addis r3, r2, a_qp@toc@ha ; CHECK-P8-NEXT: addis r3, r2, a_qp@toc@ha
; CHECK-P8-NEXT: addis r4, r2, b_qp@toc@ha ; CHECK-P8-NEXT: addis r4, r2, b_qp@toc@ha
; CHECK-P8-NEXT: addi r3, r3, a_qp@toc@l ; CHECK-P8-NEXT: addi r3, r3, a_qp@toc@l
; CHECK-P8-NEXT: addi r4, r4, b_qp@toc@l ; CHECK-P8-NEXT: addi r4, r4, b_qp@toc@l
; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: lvx v3, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs1, 0, r4
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: xxswapd v3, vs1
; CHECK-P8-NEXT: bl __lekf2 ; CHECK-P8-NEXT: bl __lekf2
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: extsw r3, r3 ; CHECK-P8-NEXT: extsw r3, r3
; CHECK-P8-NEXT: neg r3, r3 ; CHECK-P8-NEXT: neg r3, r3
; CHECK-P8-NEXT: rldicl r3, r3, 1, 63 ; CHECK-P8-NEXT: rldicl r3, r3, 1, 63
; CHECK-P8-NEXT: xori r3, r3, 1 ; CHECK-P8-NEXT: xori r3, r3, 1
; CHECK-P8-NEXT: addi r1, r1, 32 ; CHECK-P8-NEXT: addi r1, r1, 32
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
Show All 29 Lines
; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -32(r1) ; CHECK-P8-NEXT: stdu r1, -32(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 32 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 32
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: addis r3, r2, a_qp@toc@ha ; CHECK-P8-NEXT: addis r3, r2, a_qp@toc@ha
; CHECK-P8-NEXT: addis r4, r2, b_qp@toc@ha ; CHECK-P8-NEXT: addis r4, r2, b_qp@toc@ha
; CHECK-P8-NEXT: addi r3, r3, a_qp@toc@l ; CHECK-P8-NEXT: addi r3, r3, a_qp@toc@l
; CHECK-P8-NEXT: addi r4, r4, b_qp@toc@l ; CHECK-P8-NEXT: addi r4, r4, b_qp@toc@l
; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: lvx v3, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs1, 0, r4
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: xxswapd v3, vs1
; CHECK-P8-NEXT: bl __eqkf2 ; CHECK-P8-NEXT: bl __eqkf2
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: cntlzw r3, r3 ; CHECK-P8-NEXT: cntlzw r3, r3
; CHECK-P8-NEXT: srwi r3, r3, 5 ; CHECK-P8-NEXT: srwi r3, r3, 5
; CHECK-P8-NEXT: addi r1, r1, 32 ; CHECK-P8-NEXT: addi r1, r1, 32
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
Show All 26 Lines
; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -32(r1) ; CHECK-P8-NEXT: stdu r1, -32(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 32 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 32
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: addis r3, r2, a_qp@toc@ha ; CHECK-P8-NEXT: addis r3, r2, a_qp@toc@ha
; CHECK-P8-NEXT: addis r4, r2, b_qp@toc@ha ; CHECK-P8-NEXT: addis r4, r2, b_qp@toc@ha
; CHECK-P8-NEXT: addi r3, r3, a_qp@toc@l ; CHECK-P8-NEXT: addi r3, r3, a_qp@toc@l
; CHECK-P8-NEXT: addi r4, r4, b_qp@toc@l ; CHECK-P8-NEXT: addi r4, r4, b_qp@toc@l
; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: lvx v3, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs1, 0, r4
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: xxswapd v3, vs1
; CHECK-P8-NEXT: bl __gtkf2 ; CHECK-P8-NEXT: bl __gtkf2
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: extsw r3, r3 ; CHECK-P8-NEXT: extsw r3, r3
; CHECK-P8-NEXT: neg r3, r3 ; CHECK-P8-NEXT: neg r3, r3
; CHECK-P8-NEXT: rldicl r3, r3, 1, 63 ; CHECK-P8-NEXT: rldicl r3, r3, 1, 63
; CHECK-P8-NEXT: xori r3, r3, 1 ; CHECK-P8-NEXT: xori r3, r3, 1
; CHECK-P8-NEXT: addi r1, r1, 32 ; CHECK-P8-NEXT: addi r1, r1, 32
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
Show All 29 Lines
; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -32(r1) ; CHECK-P8-NEXT: stdu r1, -32(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 32 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 32
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: addis r3, r2, a_qp@toc@ha ; CHECK-P8-NEXT: addis r3, r2, a_qp@toc@ha
; CHECK-P8-NEXT: addis r4, r2, b_qp@toc@ha ; CHECK-P8-NEXT: addis r4, r2, b_qp@toc@ha
; CHECK-P8-NEXT: addi r3, r3, a_qp@toc@l ; CHECK-P8-NEXT: addi r3, r3, a_qp@toc@l
; CHECK-P8-NEXT: addi r4, r4, b_qp@toc@l ; CHECK-P8-NEXT: addi r4, r4, b_qp@toc@l
; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: lvx v3, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs1, 0, r4
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: xxswapd v3, vs1
; CHECK-P8-NEXT: bl __ltkf2 ; CHECK-P8-NEXT: bl __ltkf2
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: rlwinm r3, r3, 1, 31, 31 ; CHECK-P8-NEXT: rlwinm r3, r3, 1, 31, 31
; CHECK-P8-NEXT: xori r3, r3, 1 ; CHECK-P8-NEXT: xori r3, r3, 1
; CHECK-P8-NEXT: addi r1, r1, 32 ; CHECK-P8-NEXT: addi r1, r1, 32
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
Show All 28 Lines
; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -32(r1) ; CHECK-P8-NEXT: stdu r1, -32(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 32 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 32
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: addis r3, r2, a_qp@toc@ha ; CHECK-P8-NEXT: addis r3, r2, a_qp@toc@ha
; CHECK-P8-NEXT: addis r4, r2, b_qp@toc@ha ; CHECK-P8-NEXT: addis r4, r2, b_qp@toc@ha
; CHECK-P8-NEXT: addi r3, r3, a_qp@toc@l ; CHECK-P8-NEXT: addi r3, r3, a_qp@toc@l
; CHECK-P8-NEXT: addi r4, r4, b_qp@toc@l ; CHECK-P8-NEXT: addi r4, r4, b_qp@toc@l
; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: lvx v3, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs1, 0, r4
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: xxswapd v3, vs1
; CHECK-P8-NEXT: bl __gekf2 ; CHECK-P8-NEXT: bl __gekf2
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: rlwinm r3, r3, 1, 31, 31 ; CHECK-P8-NEXT: rlwinm r3, r3, 1, 31, 31
; CHECK-P8-NEXT: addi r1, r1, 32 ; CHECK-P8-NEXT: addi r1, r1, 32
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
entry: entry:
Show All 27 Lines
; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -32(r1) ; CHECK-P8-NEXT: stdu r1, -32(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 32 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 32
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: addis r3, r2, a_qp@toc@ha ; CHECK-P8-NEXT: addis r3, r2, a_qp@toc@ha
; CHECK-P8-NEXT: addis r4, r2, b_qp@toc@ha ; CHECK-P8-NEXT: addis r4, r2, b_qp@toc@ha
; CHECK-P8-NEXT: addi r3, r3, a_qp@toc@l ; CHECK-P8-NEXT: addi r3, r3, a_qp@toc@l
; CHECK-P8-NEXT: addi r4, r4, b_qp@toc@l ; CHECK-P8-NEXT: addi r4, r4, b_qp@toc@l
; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: lvx v3, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs1, 0, r4
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: xxswapd v3, vs1
; CHECK-P8-NEXT: bl __lekf2 ; CHECK-P8-NEXT: bl __lekf2
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: extsw r3, r3 ; CHECK-P8-NEXT: extsw r3, r3
; CHECK-P8-NEXT: neg r3, r3 ; CHECK-P8-NEXT: neg r3, r3
; CHECK-P8-NEXT: rldicl r3, r3, 1, 63 ; CHECK-P8-NEXT: rldicl r3, r3, 1, 63
; CHECK-P8-NEXT: addi r1, r1, 32 ; CHECK-P8-NEXT: addi r1, r1, 32
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
Show All 28 Lines
; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -32(r1) ; CHECK-P8-NEXT: stdu r1, -32(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 32 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 32
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: addis r3, r2, a_qp@toc@ha ; CHECK-P8-NEXT: addis r3, r2, a_qp@toc@ha
; CHECK-P8-NEXT: addis r4, r2, b_qp@toc@ha ; CHECK-P8-NEXT: addis r4, r2, b_qp@toc@ha
; CHECK-P8-NEXT: addi r3, r3, a_qp@toc@l ; CHECK-P8-NEXT: addi r3, r3, a_qp@toc@l
; CHECK-P8-NEXT: addi r4, r4, b_qp@toc@l ; CHECK-P8-NEXT: addi r4, r4, b_qp@toc@l
; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: lvx v3, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs1, 0, r4
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: xxswapd v3, vs1
; CHECK-P8-NEXT: bl __nekf2 ; CHECK-P8-NEXT: bl __nekf2
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: cntlzw r3, r3 ; CHECK-P8-NEXT: cntlzw r3, r3
; CHECK-P8-NEXT: srwi r3, r3, 5 ; CHECK-P8-NEXT: srwi r3, r3, 5
; CHECK-P8-NEXT: xori r3, r3, 1 ; CHECK-P8-NEXT: xori r3, r3, 1
; CHECK-P8-NEXT: addi r1, r1, 32 ; CHECK-P8-NEXT: addi r1, r1, 32
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
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; CHECK-P8-NEXT: .cfi_offset v31, -16 ; CHECK-P8-NEXT: .cfi_offset v31, -16
; CHECK-P8-NEXT: li r3, 48 ; CHECK-P8-NEXT: li r3, 48
; CHECK-P8-NEXT: addis r4, r2, b_qp@toc@ha ; CHECK-P8-NEXT: addis r4, r2, b_qp@toc@ha
; CHECK-P8-NEXT: stvx v30, r1, r3 # 16-byte Folded Spill ; CHECK-P8-NEXT: stvx v30, r1, r3 # 16-byte Folded Spill
; CHECK-P8-NEXT: li r3, 64 ; CHECK-P8-NEXT: li r3, 64
; CHECK-P8-NEXT: addi r4, r4, b_qp@toc@l ; CHECK-P8-NEXT: addi r4, r4, b_qp@toc@l
; CHECK-P8-NEXT: stvx v31, r1, r3 # 16-byte Folded Spill ; CHECK-P8-NEXT: stvx v31, r1, r3 # 16-byte Folded Spill
; CHECK-P8-NEXT: addis r3, r2, a_qp@toc@ha ; CHECK-P8-NEXT: addis r3, r2, a_qp@toc@ha
; CHECK-P8-NEXT: lvx v30, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs1, 0, r4
; CHECK-P8-NEXT: addi r3, r3, a_qp@toc@l ; CHECK-P8-NEXT: addi r3, r3, a_qp@toc@l
; CHECK-P8-NEXT: lvx v31, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: xxswapd v30, vs1
; CHECK-P8-NEXT: xxswapd v31, vs0
; CHECK-P8-NEXT: vmr v3, v30 ; CHECK-P8-NEXT: vmr v3, v30
; CHECK-P8-NEXT: vmr v2, v31 ; CHECK-P8-NEXT: vmr v2, v31
; CHECK-P8-NEXT: bl __gtkf2 ; CHECK-P8-NEXT: bl __gtkf2
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: cmpwi r3, 0 ; CHECK-P8-NEXT: cmpwi r3, 0
; CHECK-P8-NEXT: bgt cr0, .LBB10_2 ; CHECK-P8-NEXT: bgt cr0, .LBB10_2
; CHECK-P8-NEXT: # %bb.1: # %entry ; CHECK-P8-NEXT: # %bb.1: # %entry
; CHECK-P8-NEXT: vmr v31, v30 ; CHECK-P8-NEXT: vmr v31, v30
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; CHECK-P8-NEXT: .cfi_offset v31, -16 ; CHECK-P8-NEXT: .cfi_offset v31, -16
; CHECK-P8-NEXT: li r3, 48 ; CHECK-P8-NEXT: li r3, 48
; CHECK-P8-NEXT: addis r4, r2, b_qp@toc@ha ; CHECK-P8-NEXT: addis r4, r2, b_qp@toc@ha
; CHECK-P8-NEXT: stvx v30, r1, r3 # 16-byte Folded Spill ; CHECK-P8-NEXT: stvx v30, r1, r3 # 16-byte Folded Spill
; CHECK-P8-NEXT: li r3, 64 ; CHECK-P8-NEXT: li r3, 64
; CHECK-P8-NEXT: addi r4, r4, b_qp@toc@l ; CHECK-P8-NEXT: addi r4, r4, b_qp@toc@l
; CHECK-P8-NEXT: stvx v31, r1, r3 # 16-byte Folded Spill ; CHECK-P8-NEXT: stvx v31, r1, r3 # 16-byte Folded Spill
; CHECK-P8-NEXT: addis r3, r2, a_qp@toc@ha ; CHECK-P8-NEXT: addis r3, r2, a_qp@toc@ha
; CHECK-P8-NEXT: lvx v30, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs1, 0, r4
; CHECK-P8-NEXT: addi r3, r3, a_qp@toc@l ; CHECK-P8-NEXT: addi r3, r3, a_qp@toc@l
; CHECK-P8-NEXT: lvx v31, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: xxswapd v30, vs1
; CHECK-P8-NEXT: xxswapd v31, vs0
; CHECK-P8-NEXT: vmr v3, v30 ; CHECK-P8-NEXT: vmr v3, v30
; CHECK-P8-NEXT: vmr v2, v31 ; CHECK-P8-NEXT: vmr v2, v31
; CHECK-P8-NEXT: bl __ltkf2 ; CHECK-P8-NEXT: bl __ltkf2
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: cmpwi r3, 0 ; CHECK-P8-NEXT: cmpwi r3, 0
; CHECK-P8-NEXT: blt cr0, .LBB11_2 ; CHECK-P8-NEXT: blt cr0, .LBB11_2
; CHECK-P8-NEXT: # %bb.1: # %entry ; CHECK-P8-NEXT: # %bb.1: # %entry
; CHECK-P8-NEXT: vmr v31, v30 ; CHECK-P8-NEXT: vmr v31, v30
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; CHECK-P8-NEXT: .cfi_offset v31, -16 ; CHECK-P8-NEXT: .cfi_offset v31, -16
; CHECK-P8-NEXT: li r3, 48 ; CHECK-P8-NEXT: li r3, 48
; CHECK-P8-NEXT: addis r4, r2, b_qp@toc@ha ; CHECK-P8-NEXT: addis r4, r2, b_qp@toc@ha
; CHECK-P8-NEXT: stvx v30, r1, r3 # 16-byte Folded Spill ; CHECK-P8-NEXT: stvx v30, r1, r3 # 16-byte Folded Spill
; CHECK-P8-NEXT: li r3, 64 ; CHECK-P8-NEXT: li r3, 64
; CHECK-P8-NEXT: addi r4, r4, b_qp@toc@l ; CHECK-P8-NEXT: addi r4, r4, b_qp@toc@l
; CHECK-P8-NEXT: stvx v31, r1, r3 # 16-byte Folded Spill ; CHECK-P8-NEXT: stvx v31, r1, r3 # 16-byte Folded Spill
; CHECK-P8-NEXT: addis r3, r2, a_qp@toc@ha ; CHECK-P8-NEXT: addis r3, r2, a_qp@toc@ha
; CHECK-P8-NEXT: lvx v30, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs1, 0, r4
; CHECK-P8-NEXT: addi r3, r3, a_qp@toc@l ; CHECK-P8-NEXT: addi r3, r3, a_qp@toc@l
; CHECK-P8-NEXT: lvx v31, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: xxswapd v30, vs1
; CHECK-P8-NEXT: xxswapd v31, vs0
; CHECK-P8-NEXT: vmr v3, v30 ; CHECK-P8-NEXT: vmr v3, v30
; CHECK-P8-NEXT: vmr v2, v31 ; CHECK-P8-NEXT: vmr v2, v31
; CHECK-P8-NEXT: bl __gekf2 ; CHECK-P8-NEXT: bl __gekf2
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: cmpwi r3, -1 ; CHECK-P8-NEXT: cmpwi r3, -1
; CHECK-P8-NEXT: bgt cr0, .LBB12_2 ; CHECK-P8-NEXT: bgt cr0, .LBB12_2
; CHECK-P8-NEXT: # %bb.1: # %entry ; CHECK-P8-NEXT: # %bb.1: # %entry
; CHECK-P8-NEXT: vmr v31, v30 ; CHECK-P8-NEXT: vmr v31, v30
▲ Show 20 Lines • Show All 43 Lines • ▼ Show 20 Lines
; CHECK-P8-NEXT: .cfi_offset v31, -16 ; CHECK-P8-NEXT: .cfi_offset v31, -16
; CHECK-P8-NEXT: li r3, 48 ; CHECK-P8-NEXT: li r3, 48
; CHECK-P8-NEXT: addis r4, r2, b_qp@toc@ha ; CHECK-P8-NEXT: addis r4, r2, b_qp@toc@ha
; CHECK-P8-NEXT: stvx v30, r1, r3 # 16-byte Folded Spill ; CHECK-P8-NEXT: stvx v30, r1, r3 # 16-byte Folded Spill
; CHECK-P8-NEXT: li r3, 64 ; CHECK-P8-NEXT: li r3, 64
; CHECK-P8-NEXT: addi r4, r4, b_qp@toc@l ; CHECK-P8-NEXT: addi r4, r4, b_qp@toc@l
; CHECK-P8-NEXT: stvx v31, r1, r3 # 16-byte Folded Spill ; CHECK-P8-NEXT: stvx v31, r1, r3 # 16-byte Folded Spill
; CHECK-P8-NEXT: addis r3, r2, a_qp@toc@ha ; CHECK-P8-NEXT: addis r3, r2, a_qp@toc@ha
; CHECK-P8-NEXT: lvx v30, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs1, 0, r4
; CHECK-P8-NEXT: addi r3, r3, a_qp@toc@l ; CHECK-P8-NEXT: addi r3, r3, a_qp@toc@l
; CHECK-P8-NEXT: lvx v31, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: xxswapd v30, vs1
; CHECK-P8-NEXT: xxswapd v31, vs0
; CHECK-P8-NEXT: vmr v3, v30 ; CHECK-P8-NEXT: vmr v3, v30
; CHECK-P8-NEXT: vmr v2, v31 ; CHECK-P8-NEXT: vmr v2, v31
; CHECK-P8-NEXT: bl __lekf2 ; CHECK-P8-NEXT: bl __lekf2
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: cmpwi r3, 1 ; CHECK-P8-NEXT: cmpwi r3, 1
; CHECK-P8-NEXT: blt cr0, .LBB13_2 ; CHECK-P8-NEXT: blt cr0, .LBB13_2
; CHECK-P8-NEXT: # %bb.1: # %entry ; CHECK-P8-NEXT: # %bb.1: # %entry
; CHECK-P8-NEXT: vmr v31, v30 ; CHECK-P8-NEXT: vmr v31, v30
▲ Show 20 Lines • Show All 42 Lines • ▼ Show 20 Lines
; CHECK-P8-NEXT: .cfi_offset v31, -16 ; CHECK-P8-NEXT: .cfi_offset v31, -16
; CHECK-P8-NEXT: li r3, 48 ; CHECK-P8-NEXT: li r3, 48
; CHECK-P8-NEXT: addis r4, r2, b_qp@toc@ha ; CHECK-P8-NEXT: addis r4, r2, b_qp@toc@ha
; CHECK-P8-NEXT: stvx v30, r1, r3 # 16-byte Folded Spill ; CHECK-P8-NEXT: stvx v30, r1, r3 # 16-byte Folded Spill
; CHECK-P8-NEXT: li r3, 64 ; CHECK-P8-NEXT: li r3, 64
; CHECK-P8-NEXT: addi r4, r4, b_qp@toc@l ; CHECK-P8-NEXT: addi r4, r4, b_qp@toc@l
; CHECK-P8-NEXT: stvx v31, r1, r3 # 16-byte Folded Spill ; CHECK-P8-NEXT: stvx v31, r1, r3 # 16-byte Folded Spill
; CHECK-P8-NEXT: addis r3, r2, a_qp@toc@ha ; CHECK-P8-NEXT: addis r3, r2, a_qp@toc@ha
; CHECK-P8-NEXT: lvx v30, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs1, 0, r4
; CHECK-P8-NEXT: addi r3, r3, a_qp@toc@l ; CHECK-P8-NEXT: addi r3, r3, a_qp@toc@l
; CHECK-P8-NEXT: lvx v31, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: xxswapd v30, vs1
; CHECK-P8-NEXT: xxswapd v31, vs0
; CHECK-P8-NEXT: vmr v3, v30 ; CHECK-P8-NEXT: vmr v3, v30
; CHECK-P8-NEXT: vmr v2, v31 ; CHECK-P8-NEXT: vmr v2, v31
; CHECK-P8-NEXT: bl __eqkf2 ; CHECK-P8-NEXT: bl __eqkf2
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: cmplwi r3, 0 ; CHECK-P8-NEXT: cmplwi r3, 0
; CHECK-P8-NEXT: beq cr0, .LBB14_2 ; CHECK-P8-NEXT: beq cr0, .LBB14_2
; CHECK-P8-NEXT: # %bb.1: # %entry ; CHECK-P8-NEXT: # %bb.1: # %entry
; CHECK-P8-NEXT: vmr v31, v30 ; CHECK-P8-NEXT: vmr v31, v30
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llvm/test/CodeGen/PowerPC/f128-conv.ll

Show All 29 Lines
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: mr r30, r3 ; CHECK-P8-NEXT: mr r30, r3
; CHECK-P8-NEXT: mr r3, r4 ; CHECK-P8-NEXT: mr r3, r4
; CHECK-P8-NEXT: bl __floatdikf ; CHECK-P8-NEXT: bl __floatdikf
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: stvx v2, 0, r30 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: stxvd2x vs0, 0, r30
; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: addi r1, r1, 48
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
entry: entry:
%conv = sitofp i64 %b to fp128 %conv = sitofp i64 %b to fp128
store fp128 %conv, fp128* %a, align 16 store fp128 %conv, fp128* %a, align 16
Show All 33 Lines
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: mr r30, r3 ; CHECK-P8-NEXT: mr r30, r3
; CHECK-P8-NEXT: mr r3, r4 ; CHECK-P8-NEXT: mr r3, r4
; CHECK-P8-NEXT: mr r4, r5 ; CHECK-P8-NEXT: mr r4, r5
; CHECK-P8-NEXT: bl __floattikf ; CHECK-P8-NEXT: bl __floattikf
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: stvx v2, 0, r30 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: stxvd2x vs0, 0, r30
; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: addi r1, r1, 48
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
entry: entry:
%conv = sitofp i128 %b to fp128 %conv = sitofp i128 %b to fp128
store fp128 %conv, fp128* %a, align 16 store fp128 %conv, fp128* %a, align 16
Show All 23 Lines
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-P8-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-P8-NEXT: mr r30, r3 ; CHECK-P8-NEXT: mr r30, r3
; CHECK-P8-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-P8-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-P8-NEXT: ld r4, 16(r4) ; CHECK-P8-NEXT: ld r4, 16(r4)
; CHECK-P8-NEXT: mr r3, r4 ; CHECK-P8-NEXT: mr r3, r4
; CHECK-P8-NEXT: bl __floatdikf ; CHECK-P8-NEXT: bl __floatdikf
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: stvx v2, 0, r30 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: stxvd2x vs0, 0, r30
; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: addi r1, r1, 48
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
entry: entry:
%0 = load i64, i64* getelementptr inbounds %0 = load i64, i64* getelementptr inbounds
([5 x i64], [5 x i64]* @mem, i64 0, i64 2), align 8 ([5 x i64], [5 x i64]* @mem, i64 0, i64 2), align 8
Show All 21 Lines
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: ld r4, 0(r4) ; CHECK-P8-NEXT: ld r4, 0(r4)
; CHECK-P8-NEXT: mr r30, r3 ; CHECK-P8-NEXT: mr r30, r3
; CHECK-P8-NEXT: mr r3, r4 ; CHECK-P8-NEXT: mr r3, r4
; CHECK-P8-NEXT: bl __floatdikf ; CHECK-P8-NEXT: bl __floatdikf
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: stvx v2, 0, r30 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: stxvd2x vs0, 0, r30
; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: addi r1, r1, 48
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
entry: entry:
%0 = load i64, i64* %b, align 8 %0 = load i64, i64* %b, align 8
%conv = sitofp i64 %0 to fp128 %conv = sitofp i64 %0 to fp128
Show All 26 Lines
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: mr r30, r3 ; CHECK-P8-NEXT: mr r30, r3
; CHECK-P8-NEXT: andi. r3, r4, 1 ; CHECK-P8-NEXT: andi. r3, r4, 1
; CHECK-P8-NEXT: li r4, -1 ; CHECK-P8-NEXT: li r4, -1
; CHECK-P8-NEXT: li r3, 0 ; CHECK-P8-NEXT: li r3, 0
; CHECK-P8-NEXT: iselgt r3, r4, r3 ; CHECK-P8-NEXT: iselgt r3, r4, r3
; CHECK-P8-NEXT: bl __floatsikf ; CHECK-P8-NEXT: bl __floatsikf
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: stvx v2, 0, r30 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: stxvd2x vs0, 0, r30
; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: addi r1, r1, 48
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
entry: entry:
%conv = sitofp i1 %b to fp128 %conv = sitofp i1 %b to fp128
store fp128 %conv, fp128* %a, align 16 store fp128 %conv, fp128* %a, align 16
Show All 18 Lines
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: mr r30, r3 ; CHECK-P8-NEXT: mr r30, r3
; CHECK-P8-NEXT: mr r3, r4 ; CHECK-P8-NEXT: mr r3, r4
; CHECK-P8-NEXT: bl __floatundikf ; CHECK-P8-NEXT: bl __floatundikf
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: stvx v2, 0, r30 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: stxvd2x vs0, 0, r30
; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: addi r1, r1, 48
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
entry: entry:
%conv = uitofp i64 %b to fp128 %conv = uitofp i64 %b to fp128
store fp128 %conv, fp128* %a, align 16 store fp128 %conv, fp128* %a, align 16
Show All 33 Lines
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: mr r30, r3 ; CHECK-P8-NEXT: mr r30, r3
; CHECK-P8-NEXT: mr r3, r4 ; CHECK-P8-NEXT: mr r3, r4
; CHECK-P8-NEXT: mr r4, r5 ; CHECK-P8-NEXT: mr r4, r5
; CHECK-P8-NEXT: bl __floatuntikf ; CHECK-P8-NEXT: bl __floatuntikf
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: stvx v2, 0, r30 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: stxvd2x vs0, 0, r30
; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: addi r1, r1, 48
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
entry: entry:
%conv = uitofp i128 %b to fp128 %conv = uitofp i128 %b to fp128
store fp128 %conv, fp128* %a, align 16 store fp128 %conv, fp128* %a, align 16
Show All 23 Lines
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: addis r4, r2, .LC1@toc@ha ; CHECK-P8-NEXT: addis r4, r2, .LC1@toc@ha
; CHECK-P8-NEXT: mr r30, r3 ; CHECK-P8-NEXT: mr r30, r3
; CHECK-P8-NEXT: ld r4, .LC1@toc@l(r4) ; CHECK-P8-NEXT: ld r4, .LC1@toc@l(r4)
; CHECK-P8-NEXT: ld r4, 32(r4) ; CHECK-P8-NEXT: ld r4, 32(r4)
; CHECK-P8-NEXT: mr r3, r4 ; CHECK-P8-NEXT: mr r3, r4
; CHECK-P8-NEXT: bl __floatundikf ; CHECK-P8-NEXT: bl __floatundikf
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: stvx v2, 0, r30 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: stxvd2x vs0, 0, r30
; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: addi r1, r1, 48
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
entry: entry:
%0 = load i64, i64* getelementptr inbounds %0 = load i64, i64* getelementptr inbounds
([5 x i64], [5 x i64]* @umem, i64 0, i64 4), align 8 ([5 x i64], [5 x i64]* @umem, i64 0, i64 4), align 8
Show All 21 Lines
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: ld r4, 0(r4) ; CHECK-P8-NEXT: ld r4, 0(r4)
; CHECK-P8-NEXT: mr r30, r3 ; CHECK-P8-NEXT: mr r30, r3
; CHECK-P8-NEXT: mr r3, r4 ; CHECK-P8-NEXT: mr r3, r4
; CHECK-P8-NEXT: bl __floatundikf ; CHECK-P8-NEXT: bl __floatundikf
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: stvx v2, 0, r30 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: stxvd2x vs0, 0, r30
; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: addi r1, r1, 48
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
entry: entry:
%0 = load i64, i64* %b, align 8 %0 = load i64, i64* %b, align 8
%conv = uitofp i64 %0 to fp128 %conv = uitofp i64 %0 to fp128
Show All 20 Lines
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: mr r30, r3 ; CHECK-P8-NEXT: mr r30, r3
; CHECK-P8-NEXT: clrldi r3, r4, 63 ; CHECK-P8-NEXT: clrldi r3, r4, 63
; CHECK-P8-NEXT: bl __floatsikf ; CHECK-P8-NEXT: bl __floatsikf
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: stvx v2, 0, r30 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: stxvd2x vs0, 0, r30
; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: addi r1, r1, 48
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
entry: entry:
%conv = uitofp i1 %b to fp128 %conv = uitofp i1 %b to fp128
store fp128 %conv, fp128* %a, align 16 store fp128 %conv, fp128* %a, align 16
Show All 23 Lines
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: lis r5, 1 ; CHECK-P8-NEXT: lis r5, 1
; CHECK-P8-NEXT: mr r30, r3 ; CHECK-P8-NEXT: mr r30, r3
; CHECK-P8-NEXT: ori r5, r5, 7797 ; CHECK-P8-NEXT: ori r5, r5, 7797
; CHECK-P8-NEXT: ldx r4, r4, r5 ; CHECK-P8-NEXT: ldx r4, r4, r5
; CHECK-P8-NEXT: mr r3, r4 ; CHECK-P8-NEXT: mr r3, r4
; CHECK-P8-NEXT: bl __floatdikf ; CHECK-P8-NEXT: bl __floatdikf
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: mr r3, r30 ; CHECK-P8-NEXT: mr r3, r30
; CHECK-P8-NEXT: stvx v2, 0, r30 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r30
; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: addi r1, r1, 48
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
i8* nocapture readonly %a) { i8* nocapture readonly %a) {
entry: entry:
%add.ptr = getelementptr inbounds i8, i8* %a, i64 73333 %add.ptr = getelementptr inbounds i8, i8* %a, i64 73333
Show All 27 Lines
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: lis r5, 1 ; CHECK-P8-NEXT: lis r5, 1
; CHECK-P8-NEXT: mr r30, r3 ; CHECK-P8-NEXT: mr r30, r3
; CHECK-P8-NEXT: ori r5, r5, 7797 ; CHECK-P8-NEXT: ori r5, r5, 7797
; CHECK-P8-NEXT: ldx r4, r4, r5 ; CHECK-P8-NEXT: ldx r4, r4, r5
; CHECK-P8-NEXT: mr r3, r4 ; CHECK-P8-NEXT: mr r3, r4
; CHECK-P8-NEXT: bl __floatundikf ; CHECK-P8-NEXT: bl __floatundikf
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: mr r3, r30 ; CHECK-P8-NEXT: mr r3, r30
; CHECK-P8-NEXT: stvx v2, 0, r30 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r30
; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: addi r1, r1, 48
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
i8* nocapture readonly %a) { i8* nocapture readonly %a) {
entry: entry:
%add.ptr = getelementptr inbounds i8, i8* %a, i64 73333 %add.ptr = getelementptr inbounds i8, i8* %a, i64 73333
Show All 22 Lines
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: mr r30, r3 ; CHECK-P8-NEXT: mr r30, r3
; CHECK-P8-NEXT: mr r3, r4 ; CHECK-P8-NEXT: mr r3, r4
; CHECK-P8-NEXT: bl __floatsikf ; CHECK-P8-NEXT: bl __floatsikf
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: stvx v2, 0, r30 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: stxvd2x vs0, 0, r30
; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: addi r1, r1, 48
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
entry: entry:
%conv = sitofp i32 %b to fp128 %conv = sitofp i32 %b to fp128
store fp128 %conv, fp128* %a, align 16 store fp128 %conv, fp128* %a, align 16
Show All 19 Lines
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: lwa r4, 0(r4) ; CHECK-P8-NEXT: lwa r4, 0(r4)
; CHECK-P8-NEXT: mr r30, r3 ; CHECK-P8-NEXT: mr r30, r3
; CHECK-P8-NEXT: mr r3, r4 ; CHECK-P8-NEXT: mr r3, r4
; CHECK-P8-NEXT: bl __floatsikf ; CHECK-P8-NEXT: bl __floatsikf
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: stvx v2, 0, r30 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: stxvd2x vs0, 0, r30
; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: addi r1, r1, 48
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
entry: entry:
%0 = load i32, i32* %b, align 4 %0 = load i32, i32* %b, align 4
%conv = sitofp i32 %0 to fp128 %conv = sitofp i32 %0 to fp128
Show All 25 Lines
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: addis r4, r2, .LC2@toc@ha ; CHECK-P8-NEXT: addis r4, r2, .LC2@toc@ha
; CHECK-P8-NEXT: mr r30, r3 ; CHECK-P8-NEXT: mr r30, r3
; CHECK-P8-NEXT: ld r4, .LC2@toc@l(r4) ; CHECK-P8-NEXT: ld r4, .LC2@toc@l(r4)
; CHECK-P8-NEXT: lwa r4, 12(r4) ; CHECK-P8-NEXT: lwa r4, 12(r4)
; CHECK-P8-NEXT: mr r3, r4 ; CHECK-P8-NEXT: mr r3, r4
; CHECK-P8-NEXT: bl __floatsikf ; CHECK-P8-NEXT: bl __floatsikf
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: stvx v2, 0, r30 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: stxvd2x vs0, 0, r30
; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: addi r1, r1, 48
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
entry: entry:
%0 = load i32, i32* getelementptr inbounds %0 = load i32, i32* getelementptr inbounds
([5 x i32], [5 x i32]* @swMem, i64 0, i64 3), align 4 ([5 x i32], [5 x i32]* @swMem, i64 0, i64 3), align 4
Show All 20 Lines
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: mr r30, r3 ; CHECK-P8-NEXT: mr r30, r3
; CHECK-P8-NEXT: mr r3, r4 ; CHECK-P8-NEXT: mr r3, r4
; CHECK-P8-NEXT: bl __floatunsikf ; CHECK-P8-NEXT: bl __floatunsikf
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: stvx v2, 0, r30 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: stxvd2x vs0, 0, r30
; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: addi r1, r1, 48
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
entry: entry:
%conv = uitofp i32 %b to fp128 %conv = uitofp i32 %b to fp128
store fp128 %conv, fp128* %a, align 16 store fp128 %conv, fp128* %a, align 16
Show All 19 Lines
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: lwz r4, 0(r4) ; CHECK-P8-NEXT: lwz r4, 0(r4)
; CHECK-P8-NEXT: mr r30, r3 ; CHECK-P8-NEXT: mr r30, r3
; CHECK-P8-NEXT: mr r3, r4 ; CHECK-P8-NEXT: mr r3, r4
; CHECK-P8-NEXT: bl __floatunsikf ; CHECK-P8-NEXT: bl __floatunsikf
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: stvx v2, 0, r30 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: stxvd2x vs0, 0, r30
; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: addi r1, r1, 48
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
entry: entry:
%0 = load i32, i32* %b, align 4 %0 = load i32, i32* %b, align 4
%conv = uitofp i32 %0 to fp128 %conv = uitofp i32 %0 to fp128
Show All 25 Lines
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: addis r4, r2, .LC3@toc@ha ; CHECK-P8-NEXT: addis r4, r2, .LC3@toc@ha
; CHECK-P8-NEXT: mr r30, r3 ; CHECK-P8-NEXT: mr r30, r3
; CHECK-P8-NEXT: ld r4, .LC3@toc@l(r4) ; CHECK-P8-NEXT: ld r4, .LC3@toc@l(r4)
; CHECK-P8-NEXT: lwz r4, 12(r4) ; CHECK-P8-NEXT: lwz r4, 12(r4)
; CHECK-P8-NEXT: mr r3, r4 ; CHECK-P8-NEXT: mr r3, r4
; CHECK-P8-NEXT: bl __floatunsikf ; CHECK-P8-NEXT: bl __floatunsikf
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: stvx v2, 0, r30 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: stxvd2x vs0, 0, r30
; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: addi r1, r1, 48
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
entry: entry:
%0 = load i32, i32* getelementptr inbounds %0 = load i32, i32* getelementptr inbounds
([5 x i32], [5 x i32]* @uwMem, i64 0, i64 3), align 4 ([5 x i32], [5 x i32]* @uwMem, i64 0, i64 3), align 4
Show All 24 Lines
; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: mr r30, r3 ; CHECK-P8-NEXT: mr r30, r3
; CHECK-P8-NEXT: lwz r3, 0(r5) ; CHECK-P8-NEXT: lwz r3, 0(r5)
; CHECK-P8-NEXT: add r3, r3, r4 ; CHECK-P8-NEXT: add r3, r3, r4
; CHECK-P8-NEXT: clrldi r3, r3, 32 ; CHECK-P8-NEXT: clrldi r3, r3, 32
; CHECK-P8-NEXT: bl __floatunsikf ; CHECK-P8-NEXT: bl __floatunsikf
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: stvx v2, 0, r30 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: stxvd2x vs0, 0, r30
; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: addi r1, r1, 48
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
i32 zeroext %b, i32* nocapture readonly %c) { i32 zeroext %b, i32* nocapture readonly %c) {
entry: entry:
%0 = load i32, i32* %c, align 4 %0 = load i32, i32* %c, align 4
Show All 21 Lines
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: mr r30, r3 ; CHECK-P8-NEXT: mr r30, r3
; CHECK-P8-NEXT: mr r3, r4 ; CHECK-P8-NEXT: mr r3, r4
; CHECK-P8-NEXT: bl __floatunsikf ; CHECK-P8-NEXT: bl __floatunsikf
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: stvx v2, 0, r30 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: stxvd2x vs0, 0, r30
; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: addi r1, r1, 48
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
entry: entry:
%conv = uitofp i16 %b to fp128 %conv = uitofp i16 %b to fp128
store fp128 %conv, fp128* %a, align 16 store fp128 %conv, fp128* %a, align 16
Show All 20 Lines
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: lhz r4, 0(r4) ; CHECK-P8-NEXT: lhz r4, 0(r4)
; CHECK-P8-NEXT: mr r30, r3 ; CHECK-P8-NEXT: mr r30, r3
; CHECK-P8-NEXT: mr r3, r4 ; CHECK-P8-NEXT: mr r3, r4
; CHECK-P8-NEXT: bl __floatunsikf ; CHECK-P8-NEXT: bl __floatunsikf
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: stvx v2, 0, r30 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: stxvd2x vs0, 0, r30
; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: addi r1, r1, 48
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
entry: entry:
%0 = load i16, i16* %b, align 2 %0 = load i16, i16* %b, align 2
%conv = uitofp i16 %0 to fp128 %conv = uitofp i16 %0 to fp128
Show All 25 Lines
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: addis r4, r2, .LC4@toc@ha ; CHECK-P8-NEXT: addis r4, r2, .LC4@toc@ha
; CHECK-P8-NEXT: mr r30, r3 ; CHECK-P8-NEXT: mr r30, r3
; CHECK-P8-NEXT: ld r4, .LC4@toc@l(r4) ; CHECK-P8-NEXT: ld r4, .LC4@toc@l(r4)
; CHECK-P8-NEXT: lhz r4, 6(r4) ; CHECK-P8-NEXT: lhz r4, 6(r4)
; CHECK-P8-NEXT: mr r3, r4 ; CHECK-P8-NEXT: mr r3, r4
; CHECK-P8-NEXT: bl __floatunsikf ; CHECK-P8-NEXT: bl __floatunsikf
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: stvx v2, 0, r30 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: stxvd2x vs0, 0, r30
; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: addi r1, r1, 48
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
entry: entry:
%0 = load i16, i16* getelementptr inbounds %0 = load i16, i16* getelementptr inbounds
([5 x i16], [5 x i16]* @uhwMem, i64 0, i64 3), align 2 ([5 x i16], [5 x i16]* @uhwMem, i64 0, i64 3), align 2
Show All 24 Lines
; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: mr r30, r3 ; CHECK-P8-NEXT: mr r30, r3
; CHECK-P8-NEXT: lhz r3, 0(r5) ; CHECK-P8-NEXT: lhz r3, 0(r5)
; CHECK-P8-NEXT: add r3, r3, r4 ; CHECK-P8-NEXT: add r3, r3, r4
; CHECK-P8-NEXT: clrldi r3, r3, 32 ; CHECK-P8-NEXT: clrldi r3, r3, 32
; CHECK-P8-NEXT: bl __floatsikf ; CHECK-P8-NEXT: bl __floatsikf
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: stvx v2, 0, r30 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: stxvd2x vs0, 0, r30
; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: addi r1, r1, 48
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
i16* nocapture readonly %c) { i16* nocapture readonly %c) {
entry: entry:
%conv = zext i16 %b to i32 %conv = zext i16 %b to i32
Show All 23 Lines
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: mr r30, r3 ; CHECK-P8-NEXT: mr r30, r3
; CHECK-P8-NEXT: mr r3, r4 ; CHECK-P8-NEXT: mr r3, r4
; CHECK-P8-NEXT: bl __floatunsikf ; CHECK-P8-NEXT: bl __floatunsikf
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: stvx v2, 0, r30 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: stxvd2x vs0, 0, r30
; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: addi r1, r1, 48
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
entry: entry:
%conv = uitofp i8 %b to fp128 %conv = uitofp i8 %b to fp128
store fp128 %conv, fp128* %a, align 16 store fp128 %conv, fp128* %a, align 16
Show All 19 Lines
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: lbz r4, 0(r4) ; CHECK-P8-NEXT: lbz r4, 0(r4)
; CHECK-P8-NEXT: mr r30, r3 ; CHECK-P8-NEXT: mr r30, r3
; CHECK-P8-NEXT: mr r3, r4 ; CHECK-P8-NEXT: mr r3, r4
; CHECK-P8-NEXT: bl __floatunsikf ; CHECK-P8-NEXT: bl __floatunsikf
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: stvx v2, 0, r30 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: stxvd2x vs0, 0, r30
; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: addi r1, r1, 48
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
entry: entry:
%0 = load i8, i8* %b, align 1 %0 = load i8, i8* %b, align 1
%conv = uitofp i8 %0 to fp128 %conv = uitofp i8 %0 to fp128
Show All 25 Lines
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: addis r4, r2, .LC5@toc@ha ; CHECK-P8-NEXT: addis r4, r2, .LC5@toc@ha
; CHECK-P8-NEXT: mr r30, r3 ; CHECK-P8-NEXT: mr r30, r3
; CHECK-P8-NEXT: ld r4, .LC5@toc@l(r4) ; CHECK-P8-NEXT: ld r4, .LC5@toc@l(r4)
; CHECK-P8-NEXT: lbz r4, 2(r4) ; CHECK-P8-NEXT: lbz r4, 2(r4)
; CHECK-P8-NEXT: mr r3, r4 ; CHECK-P8-NEXT: mr r3, r4
; CHECK-P8-NEXT: bl __floatunsikf ; CHECK-P8-NEXT: bl __floatunsikf
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: stvx v2, 0, r30 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: stxvd2x vs0, 0, r30
; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: addi r1, r1, 48
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
entry: entry:
%0 = load i8, i8* getelementptr inbounds %0 = load i8, i8* getelementptr inbounds
([5 x i8], [5 x i8]* @ubMem, i64 0, i64 2), align 1 ([5 x i8], [5 x i8]* @ubMem, i64 0, i64 2), align 1
Show All 24 Lines
; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: mr r30, r3 ; CHECK-P8-NEXT: mr r30, r3
; CHECK-P8-NEXT: lbz r3, 0(r5) ; CHECK-P8-NEXT: lbz r3, 0(r5)
; CHECK-P8-NEXT: add r3, r3, r4 ; CHECK-P8-NEXT: add r3, r3, r4
; CHECK-P8-NEXT: clrldi r3, r3, 32 ; CHECK-P8-NEXT: clrldi r3, r3, 32
; CHECK-P8-NEXT: bl __floatsikf ; CHECK-P8-NEXT: bl __floatsikf
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: stvx v2, 0, r30 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: stxvd2x vs0, 0, r30
; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: addi r1, r1, 48
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
i8* nocapture readonly %c) { i8* nocapture readonly %c) {
entry: entry:
%conv = zext i8 %b to i32 %conv = zext i8 %b to i32
Show All 26 Lines
; ;
; CHECK-P8-LABEL: qpConv2dp: ; CHECK-P8-LABEL: qpConv2dp:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -32(r1) ; CHECK-P8-NEXT: stdu r1, -32(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 32 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 32
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: bl __trunckfdf2 ; CHECK-P8-NEXT: bl __trunckfdf2
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: addi r1, r1, 32 ; CHECK-P8-NEXT: addi r1, r1, 32
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
entry: entry:
%0 = load fp128, fp128* %a, align 16 %0 = load fp128, fp128* %a, align 16
Show All 19 Lines
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: addis r4, r2, .LC6@toc@ha ; CHECK-P8-NEXT: addis r4, r2, .LC6@toc@ha
; CHECK-P8-NEXT: mr r30, r3 ; CHECK-P8-NEXT: mr r30, r3
; CHECK-P8-NEXT: ld r4, .LC6@toc@l(r4) ; CHECK-P8-NEXT: ld r4, .LC6@toc@l(r4)
; CHECK-P8-NEXT: lvx v2, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r4
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: bl __trunckfdf2 ; CHECK-P8-NEXT: bl __trunckfdf2
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: stfd f1, 0(r30) ; CHECK-P8-NEXT: stfd f1, 0(r30)
; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: addi r1, r1, 48
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
Show All 26 Lines
; CHECK-P8-NEXT: std r29, -24(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r29, -24(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -64(r1) ; CHECK-P8-NEXT: stdu r1, -64(r1)
; CHECK-P8-NEXT: mr r30, r4 ; CHECK-P8-NEXT: mr r30, r4
; CHECK-P8-NEXT: addis r4, r2, .LC7@toc@ha ; CHECK-P8-NEXT: addis r4, r2, .LC7@toc@ha
; CHECK-P8-NEXT: mr r29, r3 ; CHECK-P8-NEXT: mr r29, r3
; CHECK-P8-NEXT: ld r4, .LC7@toc@l(r4) ; CHECK-P8-NEXT: ld r4, .LC7@toc@l(r4)
; CHECK-P8-NEXT: lvx v2, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r4
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: bl __trunckfdf2 ; CHECK-P8-NEXT: bl __trunckfdf2
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: sldi r3, r30, 3 ; CHECK-P8-NEXT: sldi r3, r30, 3
; CHECK-P8-NEXT: stfdx f1, r29, r3 ; CHECK-P8-NEXT: stfdx f1, r29, r3
; CHECK-P8-NEXT: addi r1, r1, 64 ; CHECK-P8-NEXT: addi r1, r1, 64
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-P8-NEXT: ld r29, -24(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: ld r29, -24(r1) # 8-byte Folded Reload
Show All 23 Lines
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: .cfi_def_cfa_offset 48 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 48
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: lvx v3, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs1, 0, r4
; CHECK-P8-NEXT: mr r30, r5 ; CHECK-P8-NEXT: mr r30, r5
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: xxswapd v3, vs1
; CHECK-P8-NEXT: bl __addkf3 ; CHECK-P8-NEXT: bl __addkf3
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: bl __trunckfdf2 ; CHECK-P8-NEXT: bl __trunckfdf2
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: stfd f1, 0(r30) ; CHECK-P8-NEXT: stfd f1, 0(r30)
; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: addi r1, r1, 48
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
Show All 21 Lines
; ;
; CHECK-P8-LABEL: qpConv2sp: ; CHECK-P8-LABEL: qpConv2sp:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -32(r1) ; CHECK-P8-NEXT: stdu r1, -32(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 32 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 32
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: bl __trunckfsf2 ; CHECK-P8-NEXT: bl __trunckfsf2
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: addi r1, r1, 32 ; CHECK-P8-NEXT: addi r1, r1, 32
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
entry: entry:
%0 = load fp128, fp128* %a, align 16 %0 = load fp128, fp128* %a, align 16
Show All 20 Lines
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: addis r4, r2, .LC6@toc@ha ; CHECK-P8-NEXT: addis r4, r2, .LC6@toc@ha
; CHECK-P8-NEXT: mr r30, r3 ; CHECK-P8-NEXT: mr r30, r3
; CHECK-P8-NEXT: ld r4, .LC6@toc@l(r4) ; CHECK-P8-NEXT: ld r4, .LC6@toc@l(r4)
; CHECK-P8-NEXT: lvx v2, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r4
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: bl __trunckfsf2 ; CHECK-P8-NEXT: bl __trunckfsf2
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: stfs f1, 0(r30) ; CHECK-P8-NEXT: stfs f1, 0(r30)
; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: addi r1, r1, 48
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
Show All 28 Lines
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -64(r1) ; CHECK-P8-NEXT: stdu r1, -64(r1)
; CHECK-P8-NEXT: mr r30, r4 ; CHECK-P8-NEXT: mr r30, r4
; CHECK-P8-NEXT: addis r4, r2, .LC7@toc@ha ; CHECK-P8-NEXT: addis r4, r2, .LC7@toc@ha
; CHECK-P8-NEXT: mr r29, r3 ; CHECK-P8-NEXT: mr r29, r3
; CHECK-P8-NEXT: ld r4, .LC7@toc@l(r4) ; CHECK-P8-NEXT: ld r4, .LC7@toc@l(r4)
; CHECK-P8-NEXT: addi r4, r4, 48 ; CHECK-P8-NEXT: addi r4, r4, 48
; CHECK-P8-NEXT: lvx v2, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r4
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: bl __trunckfsf2 ; CHECK-P8-NEXT: bl __trunckfsf2
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: sldi r3, r30, 2 ; CHECK-P8-NEXT: sldi r3, r30, 2
; CHECK-P8-NEXT: stfsx f1, r29, r3 ; CHECK-P8-NEXT: stfsx f1, r29, r3
; CHECK-P8-NEXT: addi r1, r1, 64 ; CHECK-P8-NEXT: addi r1, r1, 64
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-P8-NEXT: ld r29, -24(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: ld r29, -24(r1) # 8-byte Folded Reload
Show All 24 Lines
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: .cfi_def_cfa_offset 48 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 48
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: lvx v3, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs1, 0, r4
; CHECK-P8-NEXT: mr r30, r5 ; CHECK-P8-NEXT: mr r30, r5
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: xxswapd v3, vs1
; CHECK-P8-NEXT: bl __addkf3 ; CHECK-P8-NEXT: bl __addkf3
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: bl __trunckfsf2 ; CHECK-P8-NEXT: bl __trunckfsf2
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: stfs f1, 0(r30) ; CHECK-P8-NEXT: stfs f1, 0(r30)
; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: addi r1, r1, 48
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
▲ Show 20 Lines • Show All 53 Lines • ▼ Show 20 Lines
; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -32(r1) ; CHECK-P8-NEXT: stdu r1, -32(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 32 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 32
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: lfd f1, 0(r3) ; CHECK-P8-NEXT: lfd f1, 0(r3)
; CHECK-P8-NEXT: bl __extenddfkf2 ; CHECK-P8-NEXT: bl __extenddfkf2
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: addis r3, r2, .LC8@toc@ha ; CHECK-P8-NEXT: addis r3, r2, .LC8@toc@ha
; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: ld r3, .LC8@toc@l(r3) ; CHECK-P8-NEXT: ld r3, .LC8@toc@l(r3)
; CHECK-P8-NEXT: stvx v2, 0, r3 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r3
; CHECK-P8-NEXT: addi r1, r1, 32 ; CHECK-P8-NEXT: addi r1, r1, 32
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
entry: entry:
%0 = load double, double* %a, align 8 %0 = load double, double* %a, align 8
%conv = fpext double %0 to fp128 %conv = fpext double %0 to fp128
store fp128 %conv, fp128* @f128Glob, align 16 store fp128 %conv, fp128* @f128Glob, align 16
Show All 19 Lines
; CHECK-P8-NEXT: stdu r1, -32(r1) ; CHECK-P8-NEXT: stdu r1, -32(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 32 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 32
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: sldi r4, r4, 3 ; CHECK-P8-NEXT: sldi r4, r4, 3
; CHECK-P8-NEXT: lfdx f1, r3, r4 ; CHECK-P8-NEXT: lfdx f1, r3, r4
; CHECK-P8-NEXT: bl __extenddfkf2 ; CHECK-P8-NEXT: bl __extenddfkf2
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: addis r3, r2, .LC8@toc@ha ; CHECK-P8-NEXT: addis r3, r2, .LC8@toc@ha
; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: ld r3, .LC8@toc@l(r3) ; CHECK-P8-NEXT: ld r3, .LC8@toc@l(r3)
; CHECK-P8-NEXT: stvx v2, 0, r3 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r3
; CHECK-P8-NEXT: addi r1, r1, 32 ; CHECK-P8-NEXT: addi r1, r1, 32
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
entry: entry:
%idxprom = sext i32 %idx to i64 %idxprom = sext i32 %idx to i64
%arrayidx = getelementptr inbounds double, double* %a, i64 %idxprom %arrayidx = getelementptr inbounds double, double* %a, i64 %idxprom
%0 = load double, double* %arrayidx, align 8 %0 = load double, double* %arrayidx, align 8
Show All 22 Lines
; CHECK-P8-NEXT: std r29, -24(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r29, -24(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -64(r1) ; CHECK-P8-NEXT: stdu r1, -64(r1)
; CHECK-P8-NEXT: mr r30, r4 ; CHECK-P8-NEXT: mr r30, r4
; CHECK-P8-NEXT: mr r29, r3 ; CHECK-P8-NEXT: mr r29, r3
; CHECK-P8-NEXT: bl __extenddfkf2 ; CHECK-P8-NEXT: bl __extenddfkf2
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: sldi r3, r30, 4 ; CHECK-P8-NEXT: sldi r3, r30, 4
; CHECK-P8-NEXT: stvx v2, r29, r3 ; CHECK-P8-NEXT: stxvd2x vs0, r29, r3
; CHECK-P8-NEXT: addi r1, r1, 64 ; CHECK-P8-NEXT: addi r1, r1, 64
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-P8-NEXT: ld r29, -24(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: ld r29, -24(r1) # 8-byte Folded Reload
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
entry: entry:
%conv = fpext double %a to fp128 %conv = fpext double %a to fp128
Show All 19 Lines
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: mr r30, r4 ; CHECK-P8-NEXT: mr r30, r4
; CHECK-P8-NEXT: bl __extenddfkf2 ; CHECK-P8-NEXT: bl __extenddfkf2
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: stvx v2, 0, r30 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: stxvd2x vs0, 0, r30
; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: addi r1, r1, 48
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
entry: entry:
%conv = fpext double %a to fp128 %conv = fpext double %a to fp128
store fp128 %conv, fp128* %res, align 16 store fp128 %conv, fp128* %res, align 16
▲ Show 20 Lines • Show All 43 Lines • ▼ Show 20 Lines
; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -32(r1) ; CHECK-P8-NEXT: stdu r1, -32(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 32 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 32
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: lfs f1, 0(r3) ; CHECK-P8-NEXT: lfs f1, 0(r3)
; CHECK-P8-NEXT: bl __extendsfkf2 ; CHECK-P8-NEXT: bl __extendsfkf2
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: addis r3, r2, .LC8@toc@ha ; CHECK-P8-NEXT: addis r3, r2, .LC8@toc@ha
; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: ld r3, .LC8@toc@l(r3) ; CHECK-P8-NEXT: ld r3, .LC8@toc@l(r3)
; CHECK-P8-NEXT: stvx v2, 0, r3 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r3
; CHECK-P8-NEXT: addi r1, r1, 32 ; CHECK-P8-NEXT: addi r1, r1, 32
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
entry: entry:
%0 = load float, float* %a, align 4 %0 = load float, float* %a, align 4
%conv = fpext float %0 to fp128 %conv = fpext float %0 to fp128
store fp128 %conv, fp128* @f128Glob, align 16 store fp128 %conv, fp128* @f128Glob, align 16
Show All 19 Lines
; CHECK-P8-NEXT: stdu r1, -32(r1) ; CHECK-P8-NEXT: stdu r1, -32(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 32 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 32
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: sldi r4, r4, 2 ; CHECK-P8-NEXT: sldi r4, r4, 2
; CHECK-P8-NEXT: lfsx f1, r3, r4 ; CHECK-P8-NEXT: lfsx f1, r3, r4
; CHECK-P8-NEXT: bl __extendsfkf2 ; CHECK-P8-NEXT: bl __extendsfkf2
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: addis r3, r2, .LC8@toc@ha ; CHECK-P8-NEXT: addis r3, r2, .LC8@toc@ha
; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: ld r3, .LC8@toc@l(r3) ; CHECK-P8-NEXT: ld r3, .LC8@toc@l(r3)
; CHECK-P8-NEXT: stvx v2, 0, r3 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r3
; CHECK-P8-NEXT: addi r1, r1, 32 ; CHECK-P8-NEXT: addi r1, r1, 32
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
entry: entry:
%idxprom = sext i32 %idx to i64 %idxprom = sext i32 %idx to i64
%arrayidx = getelementptr inbounds float, float* %a, i64 %idxprom %arrayidx = getelementptr inbounds float, float* %a, i64 %idxprom
%0 = load float, float* %arrayidx, align 4 %0 = load float, float* %arrayidx, align 4
Show All 22 Lines
; CHECK-P8-NEXT: std r29, -24(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r29, -24(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -64(r1) ; CHECK-P8-NEXT: stdu r1, -64(r1)
; CHECK-P8-NEXT: mr r30, r4 ; CHECK-P8-NEXT: mr r30, r4
; CHECK-P8-NEXT: mr r29, r3 ; CHECK-P8-NEXT: mr r29, r3
; CHECK-P8-NEXT: bl __extendsfkf2 ; CHECK-P8-NEXT: bl __extendsfkf2
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: sldi r3, r30, 4 ; CHECK-P8-NEXT: sldi r3, r30, 4
; CHECK-P8-NEXT: stvx v2, r29, r3 ; CHECK-P8-NEXT: stxvd2x vs0, r29, r3
; CHECK-P8-NEXT: addi r1, r1, 64 ; CHECK-P8-NEXT: addi r1, r1, 64
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-P8-NEXT: ld r29, -24(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: ld r29, -24(r1) # 8-byte Folded Reload
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
entry: entry:
%conv = fpext float %a to fp128 %conv = fpext float %a to fp128
Show All 19 Lines
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: mr r30, r4 ; CHECK-P8-NEXT: mr r30, r4
; CHECK-P8-NEXT: bl __extendsfkf2 ; CHECK-P8-NEXT: bl __extendsfkf2
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: stvx v2, 0, r30 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: stxvd2x vs0, 0, r30
; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: addi r1, r1, 48
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
entry: entry:
%conv = fpext float %a to fp128 %conv = fpext float %a to fp128
store fp128 %conv, fp128* %res, align 16 store fp128 %conv, fp128* %res, align 16
Show All 21 Lines
; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: xscvdpsxws f0, f1 ; CHECK-P8-NEXT: xscvdpsxws f0, f1
; CHECK-P8-NEXT: mr r30, r4 ; CHECK-P8-NEXT: mr r30, r4
; CHECK-P8-NEXT: mffprwz r3, f0 ; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: extsw r3, r3 ; CHECK-P8-NEXT: extsw r3, r3
; CHECK-P8-NEXT: bl __floatsikf ; CHECK-P8-NEXT: bl __floatsikf
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: stvx v2, 0, r30 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: stxvd2x vs0, 0, r30
; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: addi r1, r1, 48
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
entry: entry:
%conv = fptosi double %val to i32 %conv = fptosi double %val to i32
%conv1 = sitofp i32 %conv to fp128 %conv1 = sitofp i32 %conv to fp128
Show All 19 Lines
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: xscvdpsxds f0, f1 ; CHECK-P8-NEXT: xscvdpsxds f0, f1
; CHECK-P8-NEXT: mr r30, r4 ; CHECK-P8-NEXT: mr r30, r4
; CHECK-P8-NEXT: mffprd r3, f0 ; CHECK-P8-NEXT: mffprd r3, f0
; CHECK-P8-NEXT: bl __floatdikf ; CHECK-P8-NEXT: bl __floatdikf
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: stvx v2, 0, r30 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: stxvd2x vs0, 0, r30
; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: addi r1, r1, 48
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
entry: entry:
%conv = fptosi double %val to i64 %conv = fptosi double %val to i64
%conv1 = sitofp i64 %conv to fp128 %conv1 = sitofp i64 %conv to fp128
Show All 21 Lines
; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: xscvdpsxws f0, f1 ; CHECK-P8-NEXT: xscvdpsxws f0, f1
; CHECK-P8-NEXT: mr r30, r4 ; CHECK-P8-NEXT: mr r30, r4
; CHECK-P8-NEXT: mffprwz r3, f0 ; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: extsw r3, r3 ; CHECK-P8-NEXT: extsw r3, r3
; CHECK-P8-NEXT: bl __floatsikf ; CHECK-P8-NEXT: bl __floatsikf
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: stvx v2, 0, r30 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: stxvd2x vs0, 0, r30
; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: addi r1, r1, 48
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
entry: entry:
%conv = fptosi float %val to i32 %conv = fptosi float %val to i32
%conv1 = sitofp i32 %conv to fp128 %conv1 = sitofp i32 %conv to fp128
Show All 19 Lines
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: xscvdpsxds f0, f1 ; CHECK-P8-NEXT: xscvdpsxds f0, f1
; CHECK-P8-NEXT: mr r30, r4 ; CHECK-P8-NEXT: mr r30, r4
; CHECK-P8-NEXT: mffprd r3, f0 ; CHECK-P8-NEXT: mffprd r3, f0
; CHECK-P8-NEXT: bl __floatdikf ; CHECK-P8-NEXT: bl __floatdikf
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: stvx v2, 0, r30 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: stxvd2x vs0, 0, r30
; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: addi r1, r1, 48
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
entry: entry:
%conv = fptosi float %val to i64 %conv = fptosi float %val to i64
%conv1 = sitofp i64 %conv to fp128 %conv1 = sitofp i64 %conv to fp128
Show All 21 Lines
; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: xscvdpuxws f0, f1 ; CHECK-P8-NEXT: xscvdpuxws f0, f1
; CHECK-P8-NEXT: mr r30, r4 ; CHECK-P8-NEXT: mr r30, r4
; CHECK-P8-NEXT: mffprwz r3, f0 ; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: clrldi r3, r3, 32 ; CHECK-P8-NEXT: clrldi r3, r3, 32
; CHECK-P8-NEXT: bl __floatunsikf ; CHECK-P8-NEXT: bl __floatunsikf
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: stvx v2, 0, r30 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: stxvd2x vs0, 0, r30
; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: addi r1, r1, 48
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
entry: entry:
%conv = fptoui double %val to i32 %conv = fptoui double %val to i32
%conv1 = uitofp i32 %conv to fp128 %conv1 = uitofp i32 %conv to fp128
Show All 19 Lines
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: xscvdpuxds f0, f1 ; CHECK-P8-NEXT: xscvdpuxds f0, f1
; CHECK-P8-NEXT: mr r30, r4 ; CHECK-P8-NEXT: mr r30, r4
; CHECK-P8-NEXT: mffprd r3, f0 ; CHECK-P8-NEXT: mffprd r3, f0
; CHECK-P8-NEXT: bl __floatundikf ; CHECK-P8-NEXT: bl __floatundikf
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: stvx v2, 0, r30 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: stxvd2x vs0, 0, r30
; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: addi r1, r1, 48
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
entry: entry:
%conv = fptoui double %val to i64 %conv = fptoui double %val to i64
%conv1 = uitofp i64 %conv to fp128 %conv1 = uitofp i64 %conv to fp128
Show All 21 Lines
; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: xscvdpuxws f0, f1 ; CHECK-P8-NEXT: xscvdpuxws f0, f1
; CHECK-P8-NEXT: mr r30, r4 ; CHECK-P8-NEXT: mr r30, r4
; CHECK-P8-NEXT: mffprwz r3, f0 ; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: clrldi r3, r3, 32 ; CHECK-P8-NEXT: clrldi r3, r3, 32
; CHECK-P8-NEXT: bl __floatunsikf ; CHECK-P8-NEXT: bl __floatunsikf
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: stvx v2, 0, r30 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: stxvd2x vs0, 0, r30
; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: addi r1, r1, 48
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
entry: entry:
%conv = fptoui float %val to i32 %conv = fptoui float %val to i32
%conv1 = uitofp i32 %conv to fp128 %conv1 = uitofp i32 %conv to fp128
Show All 19 Lines
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: xscvdpuxds f0, f1 ; CHECK-P8-NEXT: xscvdpuxds f0, f1
; CHECK-P8-NEXT: mr r30, r4 ; CHECK-P8-NEXT: mr r30, r4
; CHECK-P8-NEXT: mffprd r3, f0 ; CHECK-P8-NEXT: mffprd r3, f0
; CHECK-P8-NEXT: bl __floatundikf ; CHECK-P8-NEXT: bl __floatundikf
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: stvx v2, 0, r30 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: stxvd2x vs0, 0, r30
; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: addi r1, r1, 48
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
entry: entry:
%conv = fptoui float %val to i64 %conv = fptoui float %val to i64
%conv1 = uitofp i64 %conv to fp128 %conv1 = uitofp i64 %conv to fp128
Show All 20 Lines
; ;
; CHECK-P8-LABEL: qpConv2i128: ; CHECK-P8-LABEL: qpConv2i128:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -32(r1) ; CHECK-P8-NEXT: stdu r1, -32(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 32 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 32
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: bl __fixkfti ; CHECK-P8-NEXT: bl __fixkfti
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: addi r1, r1, 32 ; CHECK-P8-NEXT: addi r1, r1, 32
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
entry: entry:
%0 = load fp128, fp128* %a, align 16 %0 = load fp128, fp128* %a, align 16
Show All 20 Lines
; ;
; CHECK-P8-LABEL: qpConv2ui128: ; CHECK-P8-LABEL: qpConv2ui128:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -32(r1) ; CHECK-P8-NEXT: stdu r1, -32(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 32 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 32
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: bl __fixunskfti ; CHECK-P8-NEXT: bl __fixunskfti
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: addi r1, r1, 32 ; CHECK-P8-NEXT: addi r1, r1, 32
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
entry: entry:
%0 = load fp128, fp128* %a, align 16 %0 = load fp128, fp128* %a, align 16
Show All 12 Lines
; ;
; CHECK-P8-LABEL: qpConv2ui1: ; CHECK-P8-LABEL: qpConv2ui1:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -32(r1) ; CHECK-P8-NEXT: stdu r1, -32(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 32 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 32
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: bl __fixkfsi ; CHECK-P8-NEXT: bl __fixkfsi
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: addi r1, r1, 32 ; CHECK-P8-NEXT: addi r1, r1, 32
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
entry: entry:
%0 = load fp128, fp128* %a, align 16 %0 = load fp128, fp128* %a, align 16
Show All 12 Lines
; ;
; CHECK-P8-LABEL: qpConv2si1: ; CHECK-P8-LABEL: qpConv2si1:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -32(r1) ; CHECK-P8-NEXT: stdu r1, -32(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 32 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 32
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: bl __fixkfsi ; CHECK-P8-NEXT: bl __fixkfsi
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: addi r1, r1, 32 ; CHECK-P8-NEXT: addi r1, r1, 32
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
entry: entry:
%0 = load fp128, fp128* %a, align 16 %0 = load fp128, fp128* %a, align 16
%conv = fptosi fp128 %0 to i1 %conv = fptosi fp128 %0 to i1
ret i1 %conv ret i1 %conv
} }

llvm/test/CodeGen/PowerPC/f128-fma.ll

Show All 18 Lines
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -80(r1) ; CHECK-P8-NEXT: stdu r1, -80(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 80 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 80
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: .cfi_offset v31, -32 ; CHECK-P8-NEXT: .cfi_offset v31, -32
; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: lxvd2x vs1, 0, r4
; CHECK-P8-NEXT: li r7, 48 ; CHECK-P8-NEXT: li r7, 48
; CHECK-P8-NEXT: lvx v2, 0, r3
; CHECK-P8-NEXT: lvx v3, 0, r4
; CHECK-P8-NEXT: std r30, 64(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, 64(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: mr r30, r6 ; CHECK-P8-NEXT: mr r30, r6
; CHECK-P8-NEXT: lxvd2x vs2, 0, r5
; CHECK-P8-NEXT: stvx v31, r1, r7 # 16-byte Folded Spill ; CHECK-P8-NEXT: stvx v31, r1, r7 # 16-byte Folded Spill
; CHECK-P8-NEXT: lvx v31, 0, r5 ; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: xxswapd v3, vs1
; CHECK-P8-NEXT: xxswapd v31, vs2
; CHECK-P8-NEXT: bl __mulkf3 ; CHECK-P8-NEXT: bl __mulkf3
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: vmr v3, v31 ; CHECK-P8-NEXT: vmr v3, v31
; CHECK-P8-NEXT: bl __addkf3 ; CHECK-P8-NEXT: bl __addkf3
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: li r3, 48 ; CHECK-P8-NEXT: li r3, 48
; CHECK-P8-NEXT: stvx v2, 0, r30 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r30
; CHECK-P8-NEXT: ld r30, 64(r1) # 8-byte Folded Reload
; CHECK-P8-NEXT: lvx v31, r1, r3 # 16-byte Folded Reload ; CHECK-P8-NEXT: lvx v31, r1, r3 # 16-byte Folded Reload
; CHECK-P8-NEXT: ld r30, 64(r1) # 8-byte Folded Reload
; CHECK-P8-NEXT: addi r1, r1, 80 ; CHECK-P8-NEXT: addi r1, r1, 80
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
fp128* nocapture readonly %c, fp128* nocapture %res) { fp128* nocapture readonly %c, fp128* nocapture %res) {
entry: entry:
%0 = load fp128, fp128* %a, align 16 %0 = load fp128, fp128* %a, align 16
%1 = load fp128, fp128* %b, align 16 %1 = load fp128, fp128* %b, align 16
Show All 19 Lines
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -80(r1) ; CHECK-P8-NEXT: stdu r1, -80(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 80 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 80
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: .cfi_offset v31, -32 ; CHECK-P8-NEXT: .cfi_offset v31, -32
; CHECK-P8-NEXT: lxvd2x vs1, 0, r4
; CHECK-P8-NEXT: lxvd2x vs2, 0, r5
; CHECK-P8-NEXT: li r7, 48 ; CHECK-P8-NEXT: li r7, 48
; CHECK-P8-NEXT: lvx v2, 0, r4
; CHECK-P8-NEXT: lvx v3, 0, r5
; CHECK-P8-NEXT: std r30, 64(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, 64(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: mr r30, r6 ; CHECK-P8-NEXT: mr r30, r6
; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: stvx v31, r1, r7 # 16-byte Folded Spill ; CHECK-P8-NEXT: stvx v31, r1, r7 # 16-byte Folded Spill
; CHECK-P8-NEXT: lvx v31, 0, r3 ; CHECK-P8-NEXT: xxswapd v2, vs1
; CHECK-P8-NEXT: xxswapd v3, vs2
; CHECK-P8-NEXT: xxswapd v31, vs0
; CHECK-P8-NEXT: bl __mulkf3 ; CHECK-P8-NEXT: bl __mulkf3
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: vmr v3, v2 ; CHECK-P8-NEXT: vmr v3, v2
; CHECK-P8-NEXT: vmr v2, v31 ; CHECK-P8-NEXT: vmr v2, v31
; CHECK-P8-NEXT: bl __addkf3 ; CHECK-P8-NEXT: bl __addkf3
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: li r3, 48 ; CHECK-P8-NEXT: li r3, 48
; CHECK-P8-NEXT: stvx v2, 0, r30 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r30
; CHECK-P8-NEXT: ld r30, 64(r1) # 8-byte Folded Reload
; CHECK-P8-NEXT: lvx v31, r1, r3 # 16-byte Folded Reload ; CHECK-P8-NEXT: lvx v31, r1, r3 # 16-byte Folded Reload
; CHECK-P8-NEXT: ld r30, 64(r1) # 8-byte Folded Reload
; CHECK-P8-NEXT: addi r1, r1, 80 ; CHECK-P8-NEXT: addi r1, r1, 80
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
fp128* nocapture readonly %b, fp128* nocapture readonly %b,
fp128* nocapture readonly %c, fp128* nocapture %res) { fp128* nocapture readonly %c, fp128* nocapture %res) {
entry: entry:
%0 = load fp128, fp128* %a, align 16 %0 = load fp128, fp128* %a, align 16
Show All 22 Lines
; CHECK-P8-NEXT: .cfi_def_cfa_offset 64 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 64
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r29, -24 ; CHECK-P8-NEXT: .cfi_offset r29, -24
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r29, -24(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r29, -24(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -64(r1) ; CHECK-P8-NEXT: stdu r1, -64(r1)
; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: lvx v3, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs1, 0, r4
; CHECK-P8-NEXT: mr r30, r6 ; CHECK-P8-NEXT: mr r30, r6
; CHECK-P8-NEXT: mr r29, r5 ; CHECK-P8-NEXT: mr r29, r5
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: xxswapd v3, vs1
; CHECK-P8-NEXT: bl __mulkf3 ; CHECK-P8-NEXT: bl __mulkf3
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: lvx v3, 0, r29 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r29
; CHECK-P8-NEXT: xxswapd v3, vs0
; CHECK-P8-NEXT: bl __addkf3 ; CHECK-P8-NEXT: bl __addkf3
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: stvx v2, 0, r30 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: stxvd2x vs0, 0, r30
; CHECK-P8-NEXT: addi r1, r1, 64 ; CHECK-P8-NEXT: addi r1, r1, 64
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-P8-NEXT: ld r29, -24(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: ld r29, -24(r1) # 8-byte Folded Reload
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
fp128* nocapture readonly %b, fp128* nocapture readonly %b,
fp128* nocapture readonly %c, fp128* nocapture %res) { fp128* nocapture readonly %c, fp128* nocapture %res) {
Show All 22 Lines
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -96(r1) ; CHECK-P8-NEXT: stdu r1, -96(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 96 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 96
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: .cfi_offset v31, -32 ; CHECK-P8-NEXT: .cfi_offset v31, -32
; CHECK-P8-NEXT: lxvd2x vs1, 0, r4
; CHECK-P8-NEXT: lxvd2x vs2, 0, r5
; CHECK-P8-NEXT: li r7, 64 ; CHECK-P8-NEXT: li r7, 64
; CHECK-P8-NEXT: lvx v2, 0, r4
; CHECK-P8-NEXT: lvx v3, 0, r5
; CHECK-P8-NEXT: std r30, 80(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, 80(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: mr r30, r6 ; CHECK-P8-NEXT: mr r30, r6
; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: stvx v31, r1, r7 # 16-byte Folded Spill ; CHECK-P8-NEXT: stvx v31, r1, r7 # 16-byte Folded Spill
; CHECK-P8-NEXT: lvx v31, 0, r3 ; CHECK-P8-NEXT: xxswapd v2, vs1
; CHECK-P8-NEXT: xxswapd v3, vs2
; CHECK-P8-NEXT: xxswapd v31, vs0
; CHECK-P8-NEXT: bl __mulkf3 ; CHECK-P8-NEXT: bl __mulkf3
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: vmr v3, v2 ; CHECK-P8-NEXT: vmr v3, v2
; CHECK-P8-NEXT: vmr v2, v31 ; CHECK-P8-NEXT: vmr v2, v31
; CHECK-P8-NEXT: bl __addkf3 ; CHECK-P8-NEXT: bl __addkf3
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: addi r3, r1, 48 ; CHECK-P8-NEXT: addi r3, r1, 48
; CHECK-P8-NEXT: stvx v2, 0, r3 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r3
; CHECK-P8-NEXT: lbz r4, 63(r1) ; CHECK-P8-NEXT: lbz r4, 63(r1)
; CHECK-P8-NEXT: xori r4, r4, 128 ; CHECK-P8-NEXT: xori r4, r4, 128
; CHECK-P8-NEXT: stb r4, 63(r1) ; CHECK-P8-NEXT: stb r4, 63(r1)
; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: li r3, 64 ; CHECK-P8-NEXT: li r3, 64
; CHECK-P8-NEXT: stxvd2x vs0, 0, r30
; CHECK-P8-NEXT: lvx v31, r1, r3 # 16-byte Folded Reload ; CHECK-P8-NEXT: lvx v31, r1, r3 # 16-byte Folded Reload
; CHECK-P8-NEXT: stvx v2, 0, r30
; CHECK-P8-NEXT: ld r30, 80(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: ld r30, 80(r1) # 8-byte Folded Reload
; CHECK-P8-NEXT: addi r1, r1, 96 ; CHECK-P8-NEXT: addi r1, r1, 96
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
fp128* nocapture readonly %b, fp128* nocapture readonly %b,
fp128* nocapture readonly %c, fp128* nocapture %res) { fp128* nocapture readonly %c, fp128* nocapture %res) {
entry: entry:
Show All 24 Lines
; CHECK-P8-NEXT: .cfi_def_cfa_offset 80 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 80
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r29, -24 ; CHECK-P8-NEXT: .cfi_offset r29, -24
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r29, -24(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r29, -24(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -80(r1) ; CHECK-P8-NEXT: stdu r1, -80(r1)
; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: lvx v3, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs1, 0, r4
; CHECK-P8-NEXT: mr r30, r6 ; CHECK-P8-NEXT: mr r30, r6
; CHECK-P8-NEXT: mr r29, r5 ; CHECK-P8-NEXT: mr r29, r5
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: xxswapd v3, vs1
; CHECK-P8-NEXT: bl __mulkf3 ; CHECK-P8-NEXT: bl __mulkf3
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: lvx v3, 0, r29 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r29
; CHECK-P8-NEXT: xxswapd v3, vs0
; CHECK-P8-NEXT: bl __addkf3 ; CHECK-P8-NEXT: bl __addkf3
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: addi r3, r1, 32 ; CHECK-P8-NEXT: addi r3, r1, 32
; CHECK-P8-NEXT: stvx v2, 0, r3 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r3
; CHECK-P8-NEXT: lbz r4, 47(r1) ; CHECK-P8-NEXT: lbz r4, 47(r1)
; CHECK-P8-NEXT: xori r4, r4, 128 ; CHECK-P8-NEXT: xori r4, r4, 128
; CHECK-P8-NEXT: stb r4, 47(r1) ; CHECK-P8-NEXT: stb r4, 47(r1)
; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: stvx v2, 0, r30 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r30
; CHECK-P8-NEXT: addi r1, r1, 80 ; CHECK-P8-NEXT: addi r1, r1, 80
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-P8-NEXT: ld r29, -24(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: ld r29, -24(r1) # 8-byte Folded Reload
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
fp128* nocapture readonly %b, fp128* nocapture readonly %b,
fp128* nocapture readonly %c, fp128* nocapture %res) { fp128* nocapture readonly %c, fp128* nocapture %res) {
Show All 23 Lines
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -80(r1) ; CHECK-P8-NEXT: stdu r1, -80(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 80 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 80
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: .cfi_offset v31, -32 ; CHECK-P8-NEXT: .cfi_offset v31, -32
; CHECK-P8-NEXT: lxvd2x vs1, 0, r4
; CHECK-P8-NEXT: lxvd2x vs2, 0, r5
; CHECK-P8-NEXT: li r7, 48 ; CHECK-P8-NEXT: li r7, 48
; CHECK-P8-NEXT: lvx v2, 0, r4
; CHECK-P8-NEXT: lvx v3, 0, r5
; CHECK-P8-NEXT: std r30, 64(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, 64(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: mr r30, r6 ; CHECK-P8-NEXT: mr r30, r6
; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: stvx v31, r1, r7 # 16-byte Folded Spill ; CHECK-P8-NEXT: stvx v31, r1, r7 # 16-byte Folded Spill
; CHECK-P8-NEXT: lvx v31, 0, r3 ; CHECK-P8-NEXT: xxswapd v2, vs1
; CHECK-P8-NEXT: xxswapd v3, vs2
; CHECK-P8-NEXT: xxswapd v31, vs0
; CHECK-P8-NEXT: bl __mulkf3 ; CHECK-P8-NEXT: bl __mulkf3
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: vmr v3, v2 ; CHECK-P8-NEXT: vmr v3, v2
; CHECK-P8-NEXT: vmr v2, v31 ; CHECK-P8-NEXT: vmr v2, v31
; CHECK-P8-NEXT: bl __subkf3 ; CHECK-P8-NEXT: bl __subkf3
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: li r3, 48 ; CHECK-P8-NEXT: li r3, 48
; CHECK-P8-NEXT: stvx v2, 0, r30 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r30
; CHECK-P8-NEXT: ld r30, 64(r1) # 8-byte Folded Reload
; CHECK-P8-NEXT: lvx v31, r1, r3 # 16-byte Folded Reload ; CHECK-P8-NEXT: lvx v31, r1, r3 # 16-byte Folded Reload
; CHECK-P8-NEXT: ld r30, 64(r1) # 8-byte Folded Reload
; CHECK-P8-NEXT: addi r1, r1, 80 ; CHECK-P8-NEXT: addi r1, r1, 80
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
fp128* nocapture readonly %b, fp128* nocapture readonly %b,
fp128* nocapture readonly %c, fp128* nocapture %res) { fp128* nocapture readonly %c, fp128* nocapture %res) {
entry: entry:
%0 = load fp128, fp128* %a, align 16 %0 = load fp128, fp128* %a, align 16
Show All 22 Lines
; CHECK-P8-NEXT: .cfi_def_cfa_offset 64 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 64
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r29, -24 ; CHECK-P8-NEXT: .cfi_offset r29, -24
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r29, -24(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r29, -24(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -64(r1) ; CHECK-P8-NEXT: stdu r1, -64(r1)
; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: lvx v3, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs1, 0, r4
; CHECK-P8-NEXT: mr r30, r6 ; CHECK-P8-NEXT: mr r30, r6
; CHECK-P8-NEXT: mr r29, r5 ; CHECK-P8-NEXT: mr r29, r5
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: xxswapd v3, vs1
; CHECK-P8-NEXT: bl __mulkf3 ; CHECK-P8-NEXT: bl __mulkf3
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: lvx v3, 0, r29 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r29
; CHECK-P8-NEXT: xxswapd v3, vs0
; CHECK-P8-NEXT: bl __subkf3 ; CHECK-P8-NEXT: bl __subkf3
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: stvx v2, 0, r30 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: stxvd2x vs0, 0, r30
; CHECK-P8-NEXT: addi r1, r1, 64 ; CHECK-P8-NEXT: addi r1, r1, 64
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-P8-NEXT: ld r29, -24(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: ld r29, -24(r1) # 8-byte Folded Reload
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
fp128* nocapture readonly %b, fp128* nocapture readonly %b,
fp128* nocapture readonly %c, fp128* nocapture %res) { fp128* nocapture readonly %c, fp128* nocapture %res) {
Show All 23 Lines
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -96(r1) ; CHECK-P8-NEXT: stdu r1, -96(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 96 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 96
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: .cfi_offset v31, -32 ; CHECK-P8-NEXT: .cfi_offset v31, -32
; CHECK-P8-NEXT: lxvd2x vs1, 0, r4
; CHECK-P8-NEXT: lxvd2x vs2, 0, r5
; CHECK-P8-NEXT: li r7, 64 ; CHECK-P8-NEXT: li r7, 64
; CHECK-P8-NEXT: lvx v2, 0, r4
; CHECK-P8-NEXT: lvx v3, 0, r5
; CHECK-P8-NEXT: std r30, 80(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, 80(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: mr r30, r6 ; CHECK-P8-NEXT: mr r30, r6
; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: stvx v31, r1, r7 # 16-byte Folded Spill ; CHECK-P8-NEXT: stvx v31, r1, r7 # 16-byte Folded Spill
; CHECK-P8-NEXT: lvx v31, 0, r3 ; CHECK-P8-NEXT: xxswapd v2, vs1
; CHECK-P8-NEXT: xxswapd v3, vs2
; CHECK-P8-NEXT: xxswapd v31, vs0
; CHECK-P8-NEXT: bl __mulkf3 ; CHECK-P8-NEXT: bl __mulkf3
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: vmr v3, v2 ; CHECK-P8-NEXT: vmr v3, v2
; CHECK-P8-NEXT: vmr v2, v31 ; CHECK-P8-NEXT: vmr v2, v31
; CHECK-P8-NEXT: bl __subkf3 ; CHECK-P8-NEXT: bl __subkf3
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: addi r3, r1, 48 ; CHECK-P8-NEXT: addi r3, r1, 48
; CHECK-P8-NEXT: stvx v2, 0, r3 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r3
; CHECK-P8-NEXT: lbz r4, 63(r1) ; CHECK-P8-NEXT: lbz r4, 63(r1)
; CHECK-P8-NEXT: xori r4, r4, 128 ; CHECK-P8-NEXT: xori r4, r4, 128
; CHECK-P8-NEXT: stb r4, 63(r1) ; CHECK-P8-NEXT: stb r4, 63(r1)
; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: li r3, 64 ; CHECK-P8-NEXT: li r3, 64
; CHECK-P8-NEXT: stxvd2x vs0, 0, r30
; CHECK-P8-NEXT: lvx v31, r1, r3 # 16-byte Folded Reload ; CHECK-P8-NEXT: lvx v31, r1, r3 # 16-byte Folded Reload
; CHECK-P8-NEXT: stvx v2, 0, r30
; CHECK-P8-NEXT: ld r30, 80(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: ld r30, 80(r1) # 8-byte Folded Reload
; CHECK-P8-NEXT: addi r1, r1, 96 ; CHECK-P8-NEXT: addi r1, r1, 96
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
fp128* nocapture readonly %b, fp128* nocapture readonly %b,
fp128* nocapture readonly %c, fp128* nocapture %res) { fp128* nocapture readonly %c, fp128* nocapture %res) {
entry: entry:
Show All 24 Lines
; CHECK-P8-NEXT: .cfi_def_cfa_offset 80 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 80
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r29, -24 ; CHECK-P8-NEXT: .cfi_offset r29, -24
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r29, -24(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r29, -24(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -80(r1) ; CHECK-P8-NEXT: stdu r1, -80(r1)
; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: lvx v3, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs1, 0, r4
; CHECK-P8-NEXT: mr r30, r6 ; CHECK-P8-NEXT: mr r30, r6
; CHECK-P8-NEXT: mr r29, r5 ; CHECK-P8-NEXT: mr r29, r5
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: xxswapd v3, vs1
; CHECK-P8-NEXT: bl __mulkf3 ; CHECK-P8-NEXT: bl __mulkf3
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: lvx v3, 0, r29 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r29
; CHECK-P8-NEXT: xxswapd v3, vs0
; CHECK-P8-NEXT: bl __subkf3 ; CHECK-P8-NEXT: bl __subkf3
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: addi r3, r1, 32 ; CHECK-P8-NEXT: addi r3, r1, 32
; CHECK-P8-NEXT: stvx v2, 0, r3 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r3
; CHECK-P8-NEXT: lbz r4, 47(r1) ; CHECK-P8-NEXT: lbz r4, 47(r1)
; CHECK-P8-NEXT: xori r4, r4, 128 ; CHECK-P8-NEXT: xori r4, r4, 128
; CHECK-P8-NEXT: stb r4, 47(r1) ; CHECK-P8-NEXT: stb r4, 47(r1)
; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: stvx v2, 0, r30 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r30
; CHECK-P8-NEXT: addi r1, r1, 80 ; CHECK-P8-NEXT: addi r1, r1, 80
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-P8-NEXT: ld r29, -24(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: ld r29, -24(r1) # 8-byte Folded Reload
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
fp128* nocapture readonly %b, fp128* nocapture readonly %b,
fp128* nocapture readonly %c, fp128* nocapture %res) { fp128* nocapture readonly %c, fp128* nocapture %res) {
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llvm/test/CodeGen/PowerPC/f128-passByValue.ll

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; CHECK-NEXT: addi r3, r3, .LCPI0_0@toc@l ; CHECK-NEXT: addi r3, r3, .LCPI0_0@toc@l
; CHECK-NEXT: lxv v2, 0(r3) ; CHECK-NEXT: lxv v2, 0(r3)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LABEL: loadConstant: ; CHECK-P8-LABEL: loadConstant:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: addis r3, r2, .LCPI0_0@toc@ha ; CHECK-P8-NEXT: addis r3, r2, .LCPI0_0@toc@ha
; CHECK-P8-NEXT: addi r3, r3, .LCPI0_0@toc@l ; CHECK-P8-NEXT: addi r3, r3, .LCPI0_0@toc@l
; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
entry: entry:
ret fp128 0xL00000000000000004001400000000000 ret fp128 0xL00000000000000004001400000000000
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define fp128 @loadConstant2(fp128 %a, fp128 %b) { define fp128 @loadConstant2(fp128 %a, fp128 %b) {
; CHECK-LABEL: loadConstant2: ; CHECK-LABEL: loadConstant2:
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; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -32(r1) ; CHECK-P8-NEXT: stdu r1, -32(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 32 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 32
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: bl __addkf3 ; CHECK-P8-NEXT: bl __addkf3
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: addis r3, r2, .LCPI1_0@toc@ha ; CHECK-P8-NEXT: addis r3, r2, .LCPI1_0@toc@ha
; CHECK-P8-NEXT: addi r3, r3, .LCPI1_0@toc@l ; CHECK-P8-NEXT: addi r3, r3, .LCPI1_0@toc@l
; CHECK-P8-NEXT: lvx v3, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: xxswapd v3, vs0
; CHECK-P8-NEXT: bl __addkf3 ; CHECK-P8-NEXT: bl __addkf3
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: addi r1, r1, 32 ; CHECK-P8-NEXT: addi r1, r1, 32
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
entry: entry:
%add = fadd fp128 %a, %b %add = fadd fp128 %a, %b
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; CHECK-P8-LABEL: fp128Array: ; CHECK-P8-LABEL: fp128Array:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -32(r1) ; CHECK-P8-NEXT: stdu r1, -32(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 32 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 32
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: sldi r4, r4, 4 ; CHECK-P8-NEXT: sldi r4, r4, 4
; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: add r4, r3, r4 ; CHECK-P8-NEXT: add r4, r3, r4
; CHECK-P8-NEXT: addi r4, r4, -16 ; CHECK-P8-NEXT: addi r4, r4, -16
; CHECK-P8-NEXT: lvx v3, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs1, 0, r4
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: xxswapd v3, vs1
; CHECK-P8-NEXT: bl __addkf3 ; CHECK-P8-NEXT: bl __addkf3
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: addi r1, r1, 32 ; CHECK-P8-NEXT: addi r1, r1, 32
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
i32 signext %loopcnt, fp128* nocapture readnone %sum) { i32 signext %loopcnt, fp128* nocapture readnone %sum) {
entry: entry:
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; CHECK-P8-NEXT: .cfi_offset v27, -80 ; CHECK-P8-NEXT: .cfi_offset v27, -80
; CHECK-P8-NEXT: .cfi_offset v28, -64 ; CHECK-P8-NEXT: .cfi_offset v28, -64
; CHECK-P8-NEXT: .cfi_offset v29, -48 ; CHECK-P8-NEXT: .cfi_offset v29, -48
; CHECK-P8-NEXT: .cfi_offset v30, -32 ; CHECK-P8-NEXT: .cfi_offset v30, -32
; CHECK-P8-NEXT: .cfi_offset v31, -16 ; CHECK-P8-NEXT: .cfi_offset v31, -16
; CHECK-P8-NEXT: li r3, 48 ; CHECK-P8-NEXT: li r3, 48
; CHECK-P8-NEXT: stvx v21, r1, r3 # 16-byte Folded Spill ; CHECK-P8-NEXT: stvx v21, r1, r3 # 16-byte Folded Spill
; CHECK-P8-NEXT: li r3, 64 ; CHECK-P8-NEXT: li r3, 64
; CHECK-P8-NEXT: vmr v21, v4
; CHECK-P8-NEXT: stvx v22, r1, r3 # 16-byte Folded Spill ; CHECK-P8-NEXT: stvx v22, r1, r3 # 16-byte Folded Spill
; CHECK-P8-NEXT: li r3, 80 ; CHECK-P8-NEXT: li r3, 80
; CHECK-P8-NEXT: vmr v22, v5 ; CHECK-P8-NEXT: vmr v22, v4
; CHECK-P8-NEXT: stvx v23, r1, r3 # 16-byte Folded Spill ; CHECK-P8-NEXT: stvx v23, r1, r3 # 16-byte Folded Spill
; CHECK-P8-NEXT: li r3, 96 ; CHECK-P8-NEXT: li r3, 96
; CHECK-P8-NEXT: vmr v23, v6 ; CHECK-P8-NEXT: vmr v23, v5
; CHECK-P8-NEXT: stvx v24, r1, r3 # 16-byte Folded Spill ; CHECK-P8-NEXT: stvx v24, r1, r3 # 16-byte Folded Spill
; CHECK-P8-NEXT: li r3, 112 ; CHECK-P8-NEXT: li r3, 112
; CHECK-P8-NEXT: vmr v24, v7 ; CHECK-P8-NEXT: vmr v24, v6
; CHECK-P8-NEXT: stvx v25, r1, r3 # 16-byte Folded Spill ; CHECK-P8-NEXT: stvx v25, r1, r3 # 16-byte Folded Spill
; CHECK-P8-NEXT: li r3, 128 ; CHECK-P8-NEXT: li r3, 128
; CHECK-P8-NEXT: vmr v25, v8 ; CHECK-P8-NEXT: vmr v25, v7
; CHECK-P8-NEXT: stvx v26, r1, r3 # 16-byte Folded Spill ; CHECK-P8-NEXT: stvx v26, r1, r3 # 16-byte Folded Spill
; CHECK-P8-NEXT: li r3, 144 ; CHECK-P8-NEXT: li r3, 144
; CHECK-P8-NEXT: vmr v26, v9 ; CHECK-P8-NEXT: vmr v26, v8
; CHECK-P8-NEXT: stvx v27, r1, r3 # 16-byte Folded Spill ; CHECK-P8-NEXT: stvx v27, r1, r3 # 16-byte Folded Spill
; CHECK-P8-NEXT: li r3, 160 ; CHECK-P8-NEXT: li r3, 160
; CHECK-P8-NEXT: vmr v27, v10 ; CHECK-P8-NEXT: vmr v27, v9
; CHECK-P8-NEXT: stvx v28, r1, r3 # 16-byte Folded Spill ; CHECK-P8-NEXT: stvx v28, r1, r3 # 16-byte Folded Spill
; CHECK-P8-NEXT: li r3, 176 ; CHECK-P8-NEXT: li r3, 176
; CHECK-P8-NEXT: vmr v28, v11 ; CHECK-P8-NEXT: vmr v28, v10
; CHECK-P8-NEXT: stvx v29, r1, r3 # 16-byte Folded Spill ; CHECK-P8-NEXT: stvx v29, r1, r3 # 16-byte Folded Spill
; CHECK-P8-NEXT: li r3, 192 ; CHECK-P8-NEXT: li r3, 192
; CHECK-P8-NEXT: vmr v29, v11
; CHECK-P8-NEXT: stvx v30, r1, r3 # 16-byte Folded Spill ; CHECK-P8-NEXT: stvx v30, r1, r3 # 16-byte Folded Spill
; CHECK-P8-NEXT: li r3, 208 ; CHECK-P8-NEXT: li r3, 208
; CHECK-P8-NEXT: vmr v30, v12 ; CHECK-P8-NEXT: vmr v30, v12
; CHECK-P8-NEXT: stvx v31, r1, r3 # 16-byte Folded Spill ; CHECK-P8-NEXT: stvx v31, r1, r3 # 16-byte Folded Spill
; CHECK-P8-NEXT: addi r3, r1, 448 ; CHECK-P8-NEXT: addi r3, r1, 448
; CHECK-P8-NEXT: vmr v31, v13 ; CHECK-P8-NEXT: vmr v31, v13
; CHECK-P8-NEXT: lvx v29, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: bl __addkf3 ; CHECK-P8-NEXT: xxswapd v21, vs0
; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: vmr v3, v21
; CHECK-P8-NEXT: bl __addkf3 ; CHECK-P8-NEXT: bl __addkf3
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: vmr v3, v22 ; CHECK-P8-NEXT: vmr v3, v22
; CHECK-P8-NEXT: bl __addkf3 ; CHECK-P8-NEXT: bl __addkf3
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: vmr v3, v23 ; CHECK-P8-NEXT: vmr v3, v23
; CHECK-P8-NEXT: bl __addkf3 ; CHECK-P8-NEXT: bl __addkf3
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: vmr v3, v24 ; CHECK-P8-NEXT: vmr v3, v24
; CHECK-P8-NEXT: bl __addkf3 ; CHECK-P8-NEXT: bl __addkf3
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: vmr v3, v25 ; CHECK-P8-NEXT: vmr v3, v25
; CHECK-P8-NEXT: bl __addkf3 ; CHECK-P8-NEXT: bl __addkf3
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: vmr v3, v26 ; CHECK-P8-NEXT: vmr v3, v26
; CHECK-P8-NEXT: bl __addkf3 ; CHECK-P8-NEXT: bl __addkf3
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: vmr v3, v27 ; CHECK-P8-NEXT: vmr v3, v27
; CHECK-P8-NEXT: bl __addkf3 ; CHECK-P8-NEXT: bl __addkf3
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: vmr v3, v28 ; CHECK-P8-NEXT: vmr v3, v28
; CHECK-P8-NEXT: bl __addkf3 ; CHECK-P8-NEXT: bl __addkf3
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: vmr v3, v29
; CHECK-P8-NEXT: bl __addkf3
; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: vmr v3, v30 ; CHECK-P8-NEXT: vmr v3, v30
; CHECK-P8-NEXT: bl __addkf3 ; CHECK-P8-NEXT: bl __addkf3
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: vmr v3, v31 ; CHECK-P8-NEXT: vmr v3, v31
; CHECK-P8-NEXT: bl __addkf3 ; CHECK-P8-NEXT: bl __addkf3
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: vmr v3, v29 ; CHECK-P8-NEXT: vmr v3, v21
; CHECK-P8-NEXT: bl __subkf3 ; CHECK-P8-NEXT: bl __subkf3
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: li r3, 208 ; CHECK-P8-NEXT: li r3, 208
; CHECK-P8-NEXT: lvx v31, r1, r3 # 16-byte Folded Reload ; CHECK-P8-NEXT: lvx v31, r1, r3 # 16-byte Folded Reload
; CHECK-P8-NEXT: li r3, 192 ; CHECK-P8-NEXT: li r3, 192
; CHECK-P8-NEXT: lvx v30, r1, r3 # 16-byte Folded Reload ; CHECK-P8-NEXT: lvx v30, r1, r3 # 16-byte Folded Reload
; CHECK-P8-NEXT: li r3, 176 ; CHECK-P8-NEXT: li r3, 176
; CHECK-P8-NEXT: lvx v29, r1, r3 # 16-byte Folded Reload ; CHECK-P8-NEXT: lvx v29, r1, r3 # 16-byte Folded Reload
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; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -80(r1) ; CHECK-P8-NEXT: stdu r1, -80(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 80 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 80
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset f31, -8 ; CHECK-P8-NEXT: .cfi_offset f31, -8
; CHECK-P8-NEXT: .cfi_offset v31, -32 ; CHECK-P8-NEXT: .cfi_offset v31, -32
; CHECK-P8-NEXT: li r3, 48 ; CHECK-P8-NEXT: li r3, 48
; CHECK-P8-NEXT: add r4, r7, r9 ; CHECK-P8-NEXT: add r4, r7, r9
; CHECK-P8-NEXT: vmr v4, v2 ; CHECK-P8-NEXT: vmr v3, v2
; CHECK-P8-NEXT: stfd f31, 72(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: stfd f31, 72(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: stvx v31, r1, r3 # 16-byte Folded Spill ; CHECK-P8-NEXT: stvx v31, r1, r3 # 16-byte Folded Spill
; CHECK-P8-NEXT: lwz r3, 176(r1) ; CHECK-P8-NEXT: lwz r3, 176(r1)
; CHECK-P8-NEXT: add r4, r4, r10 ; CHECK-P8-NEXT: add r4, r4, r10
; CHECK-P8-NEXT: fmr f31, f1 ; CHECK-P8-NEXT: fmr f31, f1
; CHECK-P8-NEXT: add r3, r4, r3 ; CHECK-P8-NEXT: add r3, r4, r3
; CHECK-P8-NEXT: clrldi r3, r3, 32 ; CHECK-P8-NEXT: clrldi r3, r3, 32
; CHECK-P8-NEXT: std r3, 0(r6) ; CHECK-P8-NEXT: std r3, 0(r6)
; CHECK-P8-NEXT: lvx v3, 0, r8 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r8
; CHECK-P8-NEXT: vmr v2, v3 ; CHECK-P8-NEXT: xxswapd vs0, vs0
; CHECK-P8-NEXT: vmr v3, v4 ; CHECK-P8-NEXT: xxlor v2, vs0, vs0
; CHECK-P8-NEXT: bl __addkf3 ; CHECK-P8-NEXT: bl __addkf3
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: fmr f1, f31 ; CHECK-P8-NEXT: fmr f1, f31
; CHECK-P8-NEXT: vmr v31, v2 ; CHECK-P8-NEXT: vmr v31, v2
; CHECK-P8-NEXT: bl __extenddfkf2 ; CHECK-P8-NEXT: bl __extenddfkf2
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: vmr v3, v2 ; CHECK-P8-NEXT: vmr v3, v2
; CHECK-P8-NEXT: vmr v2, v31 ; CHECK-P8-NEXT: vmr v2, v31
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; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -80(r1) ; CHECK-P8-NEXT: stdu r1, -80(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 80 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 80
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset f31, -8 ; CHECK-P8-NEXT: .cfi_offset f31, -8
; CHECK-P8-NEXT: .cfi_offset v31, -32 ; CHECK-P8-NEXT: .cfi_offset v31, -32
; CHECK-P8-NEXT: add r4, r4, r6 ; CHECK-P8-NEXT: add r4, r4, r6
; CHECK-P8-NEXT: vmr v4, v2 ; CHECK-P8-NEXT: vmr v3, v2
; CHECK-P8-NEXT: li r9, 48 ; CHECK-P8-NEXT: li r9, 48
; CHECK-P8-NEXT: stfd f31, 72(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: stfd f31, 72(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: add r4, r4, r7 ; CHECK-P8-NEXT: add r4, r4, r7
; CHECK-P8-NEXT: stvx v31, r1, r9 # 16-byte Folded Spill ; CHECK-P8-NEXT: stvx v31, r1, r9 # 16-byte Folded Spill
; CHECK-P8-NEXT: fmr f31, f1 ; CHECK-P8-NEXT: fmr f31, f1
; CHECK-P8-NEXT: add r4, r4, r8 ; CHECK-P8-NEXT: add r4, r4, r8
; CHECK-P8-NEXT: clrldi r4, r4, 32 ; CHECK-P8-NEXT: clrldi r4, r4, 32
; CHECK-P8-NEXT: std r4, 0(r3) ; CHECK-P8-NEXT: std r4, 0(r3)
; CHECK-P8-NEXT: lvx v3, 0, r5 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r5
; CHECK-P8-NEXT: vmr v2, v3 ; CHECK-P8-NEXT: xxswapd vs0, vs0
; CHECK-P8-NEXT: vmr v3, v4 ; CHECK-P8-NEXT: xxlor v2, vs0, vs0
; CHECK-P8-NEXT: bl __addkf3 ; CHECK-P8-NEXT: bl __addkf3
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: fmr f1, f31 ; CHECK-P8-NEXT: fmr f1, f31
; CHECK-P8-NEXT: vmr v31, v2 ; CHECK-P8-NEXT: vmr v31, v2
; CHECK-P8-NEXT: bl __extenddfkf2 ; CHECK-P8-NEXT: bl __extenddfkf2
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: vmr v3, v2 ; CHECK-P8-NEXT: vmr v3, v2
; CHECK-P8-NEXT: vmr v2, v31 ; CHECK-P8-NEXT: vmr v2, v31
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; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -80(r1) ; CHECK-P8-NEXT: stdu r1, -80(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 80 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 80
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: .cfi_offset v31, -32 ; CHECK-P8-NEXT: .cfi_offset v31, -32
; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: xxswapd vs1, v3
; CHECK-P8-NEXT: ld r4, 184(r1) ; CHECK-P8-NEXT: ld r4, 184(r1)
; CHECK-P8-NEXT: li r3, 48 ; CHECK-P8-NEXT: li r3, 48
; CHECK-P8-NEXT: stvx v2, 0, r9
; CHECK-P8-NEXT: std r30, 64(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, 64(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: mr r30, r5 ; CHECK-P8-NEXT: mr r30, r5
; CHECK-P8-NEXT: stvx v31, r1, r3 # 16-byte Folded Spill ; CHECK-P8-NEXT: stvx v31, r1, r3 # 16-byte Folded Spill
; CHECK-P8-NEXT: mr r3, r10 ; CHECK-P8-NEXT: mr r3, r10
; CHECK-P8-NEXT: stvx v3, 0, r4 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r9
; CHECK-P8-NEXT: lvx v31, 0, r9 ; CHECK-P8-NEXT: stxvd2x vs1, 0, r4
; CHECK-P8-NEXT: lxvd2x vs0, 0, r9
; CHECK-P8-NEXT: xxswapd v31, vs0
; CHECK-P8-NEXT: bl __floatsikf ; CHECK-P8-NEXT: bl __floatsikf
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: vmr v3, v2 ; CHECK-P8-NEXT: vmr v3, v2
; CHECK-P8-NEXT: vmr v2, v31 ; CHECK-P8-NEXT: vmr v2, v31
; CHECK-P8-NEXT: bl __addkf3 ; CHECK-P8-NEXT: bl __addkf3
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: bl __trunckfdf2 ; CHECK-P8-NEXT: bl __trunckfdf2
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
Show All 36 Lines
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -80(r1) ; CHECK-P8-NEXT: stdu r1, -80(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 80 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 80
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: .cfi_offset v31, -32 ; CHECK-P8-NEXT: .cfi_offset v31, -32
; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: xxswapd vs1, v3
; CHECK-P8-NEXT: li r6, 48 ; CHECK-P8-NEXT: li r6, 48
; CHECK-P8-NEXT: stvx v2, 0, r4
; CHECK-P8-NEXT: stvx v3, 0, r7
; CHECK-P8-NEXT: std r30, 64(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, 64(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: mr r30, r3 ; CHECK-P8-NEXT: mr r30, r3
; CHECK-P8-NEXT: mr r3, r5 ; CHECK-P8-NEXT: mr r3, r5
; CHECK-P8-NEXT: stvx v31, r1, r6 # 16-byte Folded Spill ; CHECK-P8-NEXT: stvx v31, r1, r6 # 16-byte Folded Spill
; CHECK-P8-NEXT: lvx v31, 0, r4 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r4
; CHECK-P8-NEXT: stxvd2x vs1, 0, r7
; CHECK-P8-NEXT: lxvd2x vs0, 0, r4
; CHECK-P8-NEXT: xxswapd v31, vs0
; CHECK-P8-NEXT: bl __floatsikf ; CHECK-P8-NEXT: bl __floatsikf
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: vmr v3, v2 ; CHECK-P8-NEXT: vmr v3, v2
; CHECK-P8-NEXT: vmr v2, v31 ; CHECK-P8-NEXT: vmr v2, v31
; CHECK-P8-NEXT: bl __addkf3 ; CHECK-P8-NEXT: bl __addkf3
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: bl __trunckfdf2 ; CHECK-P8-NEXT: bl __trunckfdf2
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
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llvm/test/CodeGen/PowerPC/f128-rounding.ll

Show All 16 Lines
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: .cfi_def_cfa_offset 48 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 48
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: mr r30, r4 ; CHECK-P8-NEXT: mr r30, r4
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: bl truncf128 ; CHECK-P8-NEXT: bl truncf128
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: stvx v2, 0, r30 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: stxvd2x vs0, 0, r30
; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: addi r1, r1, 48
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
entry: entry:
%0 = load fp128, fp128* %a, align 16 %0 = load fp128, fp128* %a, align 16
%1 = tail call fp128 @llvm.trunc.f128(fp128 %0) %1 = tail call fp128 @llvm.trunc.f128(fp128 %0)
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; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: .cfi_def_cfa_offset 48 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 48
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: mr r30, r4 ; CHECK-P8-NEXT: mr r30, r4
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: bl rintf128 ; CHECK-P8-NEXT: bl rintf128
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: stvx v2, 0, r30 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: stxvd2x vs0, 0, r30
; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: addi r1, r1, 48
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
entry: entry:
%0 = load fp128, fp128* %a, align 16 %0 = load fp128, fp128* %a, align 16
%1 = tail call fp128 @llvm.rint.f128(fp128 %0) %1 = tail call fp128 @llvm.rint.f128(fp128 %0)
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; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: .cfi_def_cfa_offset 48 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 48
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: mr r30, r4 ; CHECK-P8-NEXT: mr r30, r4
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: bl nearbyintf128 ; CHECK-P8-NEXT: bl nearbyintf128
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: stvx v2, 0, r30 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: stxvd2x vs0, 0, r30
; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: addi r1, r1, 48
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
entry: entry:
%0 = load fp128, fp128* %a, align 16 %0 = load fp128, fp128* %a, align 16
%1 = tail call fp128 @llvm.nearbyint.f128(fp128 %0) %1 = tail call fp128 @llvm.nearbyint.f128(fp128 %0)
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; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: .cfi_def_cfa_offset 48 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 48
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: mr r30, r4 ; CHECK-P8-NEXT: mr r30, r4
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: bl roundf128 ; CHECK-P8-NEXT: bl roundf128
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: stvx v2, 0, r30 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: stxvd2x vs0, 0, r30
; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: addi r1, r1, 48
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
entry: entry:
%0 = load fp128, fp128* %a, align 16 %0 = load fp128, fp128* %a, align 16
%1 = tail call fp128 @llvm.round.f128(fp128 %0) %1 = tail call fp128 @llvm.round.f128(fp128 %0)
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; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: .cfi_def_cfa_offset 48 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 48
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: mr r30, r4 ; CHECK-P8-NEXT: mr r30, r4
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: bl floorf128 ; CHECK-P8-NEXT: bl floorf128
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: stvx v2, 0, r30 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: stxvd2x vs0, 0, r30
; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: addi r1, r1, 48
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
entry: entry:
%0 = load fp128, fp128* %a, align 16 %0 = load fp128, fp128* %a, align 16
%1 = tail call fp128 @llvm.floor.f128(fp128 %0) %1 = tail call fp128 @llvm.floor.f128(fp128 %0)
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; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: .cfi_def_cfa_offset 48 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 48
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: mr r30, r4 ; CHECK-P8-NEXT: mr r30, r4
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: bl ceilf128 ; CHECK-P8-NEXT: bl ceilf128
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: stvx v2, 0, r30 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: stxvd2x vs0, 0, r30
; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: addi r1, r1, 48
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
entry: entry:
%0 = load fp128, fp128* %a, align 16 %0 = load fp128, fp128* %a, align 16
%1 = tail call fp128 @llvm.ceil.f128(fp128 %0) %1 = tail call fp128 @llvm.ceil.f128(fp128 %0)
store fp128 %1, fp128* %res, align 16 store fp128 %1, fp128* %res, align 16
ret void ret void
} }
declare fp128 @llvm.ceil.f128(fp128 %Val) declare fp128 @llvm.ceil.f128(fp128 %Val)

llvm/test/CodeGen/PowerPC/f128-truncateNconv.ll

Show All 22 Lines
; ;
; CHECK-P8-LABEL: qpConv2sdw: ; CHECK-P8-LABEL: qpConv2sdw:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -32(r1) ; CHECK-P8-NEXT: stdu r1, -32(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 32 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 32
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: bl __fixkfdi ; CHECK-P8-NEXT: bl __fixkfdi
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: addi r1, r1, 32 ; CHECK-P8-NEXT: addi r1, r1, 32
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
entry: entry:
%0 = load fp128, fp128* %a, align 16 %0 = load fp128, fp128* %a, align 16
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; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-P8-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-P8-NEXT: mr r30, r3 ; CHECK-P8-NEXT: mr r30, r3
; CHECK-P8-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-P8-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-P8-NEXT: addi r4, r4, 32 ; CHECK-P8-NEXT: addi r4, r4, 32
; CHECK-P8-NEXT: lvx v2, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r4
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: bl __fixkfdi ; CHECK-P8-NEXT: bl __fixkfdi
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: std r3, 0(r30) ; CHECK-P8-NEXT: std r3, 0(r30)
; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: addi r1, r1, 48
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
Show All 23 Lines
; CHECK-P8-LABEL: qpConv2sdw_03: ; CHECK-P8-LABEL: qpConv2sdw_03:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -32(r1) ; CHECK-P8-NEXT: stdu r1, -32(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 32 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 32
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-P8-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-P8-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: addi r4, r4, 16 ; CHECK-P8-NEXT: addi r4, r4, 16
; CHECK-P8-NEXT: lvx v3, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs1, 0, r4
; CHECK-P8-NEXT: xxswapd v3, vs1
; CHECK-P8-NEXT: bl __addkf3 ; CHECK-P8-NEXT: bl __addkf3
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: bl __fixkfdi ; CHECK-P8-NEXT: bl __fixkfdi
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: addi r1, r1, 32 ; CHECK-P8-NEXT: addi r1, r1, 32
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
Show All 23 Lines
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: .cfi_def_cfa_offset 48 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 48
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: lvx v3, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs1, 0, r4
; CHECK-P8-NEXT: mr r30, r5 ; CHECK-P8-NEXT: mr r30, r5
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: xxswapd v3, vs1
; CHECK-P8-NEXT: bl __addkf3 ; CHECK-P8-NEXT: bl __addkf3
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: bl __fixkfdi ; CHECK-P8-NEXT: bl __fixkfdi
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: std r3, 0(r30) ; CHECK-P8-NEXT: std r3, 0(r30)
; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: addi r1, r1, 48
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
Show All 33 Lines
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -64(r1) ; CHECK-P8-NEXT: stdu r1, -64(r1)
; CHECK-P8-NEXT: mr r30, r4 ; CHECK-P8-NEXT: mr r30, r4
; CHECK-P8-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-P8-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-P8-NEXT: mr r29, r3 ; CHECK-P8-NEXT: mr r29, r3
; CHECK-P8-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-P8-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-P8-NEXT: addi r4, r4, 32 ; CHECK-P8-NEXT: addi r4, r4, 32
; CHECK-P8-NEXT: lvx v2, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r4
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: bl __fixkfdi ; CHECK-P8-NEXT: bl __fixkfdi
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: sldi r4, r30, 3 ; CHECK-P8-NEXT: sldi r4, r30, 3
; CHECK-P8-NEXT: stdx r3, r29, r4 ; CHECK-P8-NEXT: stdx r3, r29, r4
; CHECK-P8-NEXT: addi r1, r1, 64 ; CHECK-P8-NEXT: addi r1, r1, 64
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-P8-NEXT: ld r29, -24(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: ld r29, -24(r1) # 8-byte Folded Reload
Show All 22 Lines
; ;
; CHECK-P8-LABEL: qpConv2udw: ; CHECK-P8-LABEL: qpConv2udw:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -32(r1) ; CHECK-P8-NEXT: stdu r1, -32(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 32 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 32
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: bl __fixunskfdi ; CHECK-P8-NEXT: bl __fixunskfdi
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: addi r1, r1, 32 ; CHECK-P8-NEXT: addi r1, r1, 32
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
entry: entry:
%0 = load fp128, fp128* %a, align 16 %0 = load fp128, fp128* %a, align 16
Show All 21 Lines
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-P8-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-P8-NEXT: mr r30, r3 ; CHECK-P8-NEXT: mr r30, r3
; CHECK-P8-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-P8-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-P8-NEXT: addi r4, r4, 32 ; CHECK-P8-NEXT: addi r4, r4, 32
; CHECK-P8-NEXT: lvx v2, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r4
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: bl __fixunskfdi ; CHECK-P8-NEXT: bl __fixunskfdi
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: std r3, 0(r30) ; CHECK-P8-NEXT: std r3, 0(r30)
; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: addi r1, r1, 48
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
Show All 23 Lines
; CHECK-P8-LABEL: qpConv2udw_03: ; CHECK-P8-LABEL: qpConv2udw_03:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -32(r1) ; CHECK-P8-NEXT: stdu r1, -32(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 32 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 32
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-P8-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-P8-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: addi r4, r4, 16 ; CHECK-P8-NEXT: addi r4, r4, 16
; CHECK-P8-NEXT: lvx v3, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs1, 0, r4
; CHECK-P8-NEXT: xxswapd v3, vs1
; CHECK-P8-NEXT: bl __addkf3 ; CHECK-P8-NEXT: bl __addkf3
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: bl __fixunskfdi ; CHECK-P8-NEXT: bl __fixunskfdi
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: addi r1, r1, 32 ; CHECK-P8-NEXT: addi r1, r1, 32
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
Show All 23 Lines
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: .cfi_def_cfa_offset 48 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 48
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: lvx v3, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs1, 0, r4
; CHECK-P8-NEXT: mr r30, r5 ; CHECK-P8-NEXT: mr r30, r5
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: xxswapd v3, vs1
; CHECK-P8-NEXT: bl __addkf3 ; CHECK-P8-NEXT: bl __addkf3
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: bl __fixunskfdi ; CHECK-P8-NEXT: bl __fixunskfdi
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: std r3, 0(r30) ; CHECK-P8-NEXT: std r3, 0(r30)
; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: addi r1, r1, 48
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
Show All 32 Lines
; CHECK-P8-NEXT: std r29, -24(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r29, -24(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -64(r1) ; CHECK-P8-NEXT: stdu r1, -64(r1)
; CHECK-P8-NEXT: mr r30, r4 ; CHECK-P8-NEXT: mr r30, r4
; CHECK-P8-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-P8-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-P8-NEXT: mr r29, r3 ; CHECK-P8-NEXT: mr r29, r3
; CHECK-P8-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-P8-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-P8-NEXT: lvx v2, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r4
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: bl __fixunskfdi ; CHECK-P8-NEXT: bl __fixunskfdi
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: sldi r4, r30, 3 ; CHECK-P8-NEXT: sldi r4, r30, 3
; CHECK-P8-NEXT: stdx r3, r29, r4 ; CHECK-P8-NEXT: stdx r3, r29, r4
; CHECK-P8-NEXT: addi r1, r1, 64 ; CHECK-P8-NEXT: addi r1, r1, 64
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-P8-NEXT: ld r29, -24(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: ld r29, -24(r1) # 8-byte Folded Reload
Show All 23 Lines
; ;
; CHECK-P8-LABEL: qpConv2sw: ; CHECK-P8-LABEL: qpConv2sw:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -32(r1) ; CHECK-P8-NEXT: stdu r1, -32(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 32 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 32
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: bl __fixkfsi ; CHECK-P8-NEXT: bl __fixkfsi
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: extsw r3, r3 ; CHECK-P8-NEXT: extsw r3, r3
; CHECK-P8-NEXT: addi r1, r1, 32 ; CHECK-P8-NEXT: addi r1, r1, 32
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
entry: entry:
Show All 22 Lines
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-P8-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-P8-NEXT: mr r30, r3 ; CHECK-P8-NEXT: mr r30, r3
; CHECK-P8-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-P8-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-P8-NEXT: addi r4, r4, 32 ; CHECK-P8-NEXT: addi r4, r4, 32
; CHECK-P8-NEXT: lvx v2, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r4
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: bl __fixkfsi ; CHECK-P8-NEXT: bl __fixkfsi
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: stw r3, 0(r30) ; CHECK-P8-NEXT: stw r3, 0(r30)
; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: addi r1, r1, 48
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
Show All 24 Lines
; CHECK-P8-LABEL: qpConv2sw_03: ; CHECK-P8-LABEL: qpConv2sw_03:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -32(r1) ; CHECK-P8-NEXT: stdu r1, -32(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 32 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 32
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-P8-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-P8-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: addi r4, r4, 16 ; CHECK-P8-NEXT: addi r4, r4, 16
; CHECK-P8-NEXT: lvx v3, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs1, 0, r4
; CHECK-P8-NEXT: xxswapd v3, vs1
; CHECK-P8-NEXT: bl __addkf3 ; CHECK-P8-NEXT: bl __addkf3
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: bl __fixkfsi ; CHECK-P8-NEXT: bl __fixkfsi
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: extsw r3, r3 ; CHECK-P8-NEXT: extsw r3, r3
; CHECK-P8-NEXT: addi r1, r1, 32 ; CHECK-P8-NEXT: addi r1, r1, 32
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
Show All 24 Lines
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: .cfi_def_cfa_offset 48 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 48
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: lvx v3, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs1, 0, r4
; CHECK-P8-NEXT: mr r30, r5 ; CHECK-P8-NEXT: mr r30, r5
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: xxswapd v3, vs1
; CHECK-P8-NEXT: bl __addkf3 ; CHECK-P8-NEXT: bl __addkf3
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: bl __fixkfsi ; CHECK-P8-NEXT: bl __fixkfsi
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: stw r3, 0(r30) ; CHECK-P8-NEXT: stw r3, 0(r30)
; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: addi r1, r1, 48
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
Show All 22 Lines
; ;
; CHECK-P8-LABEL: qpConv2uw: ; CHECK-P8-LABEL: qpConv2uw:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -32(r1) ; CHECK-P8-NEXT: stdu r1, -32(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 32 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 32
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: bl __fixunskfsi ; CHECK-P8-NEXT: bl __fixunskfsi
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: addi r1, r1, 32 ; CHECK-P8-NEXT: addi r1, r1, 32
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
entry: entry:
%0 = load fp128, fp128* %a, align 16 %0 = load fp128, fp128* %a, align 16
Show All 21 Lines
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-P8-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-P8-NEXT: mr r30, r3 ; CHECK-P8-NEXT: mr r30, r3
; CHECK-P8-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-P8-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-P8-NEXT: addi r4, r4, 32 ; CHECK-P8-NEXT: addi r4, r4, 32
; CHECK-P8-NEXT: lvx v2, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r4
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: bl __fixunskfsi ; CHECK-P8-NEXT: bl __fixunskfsi
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: stw r3, 0(r30) ; CHECK-P8-NEXT: stw r3, 0(r30)
; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: addi r1, r1, 48
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
Show All 24 Lines
; CHECK-P8-LABEL: qpConv2uw_03: ; CHECK-P8-LABEL: qpConv2uw_03:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -32(r1) ; CHECK-P8-NEXT: stdu r1, -32(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 32 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 32
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-P8-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-P8-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: addi r4, r4, 16 ; CHECK-P8-NEXT: addi r4, r4, 16
; CHECK-P8-NEXT: lvx v3, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs1, 0, r4
; CHECK-P8-NEXT: xxswapd v3, vs1
; CHECK-P8-NEXT: bl __addkf3 ; CHECK-P8-NEXT: bl __addkf3
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: bl __fixunskfsi ; CHECK-P8-NEXT: bl __fixunskfsi
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: addi r1, r1, 32 ; CHECK-P8-NEXT: addi r1, r1, 32
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
Show All 23 Lines
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: .cfi_def_cfa_offset 48 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 48
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: lvx v3, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs1, 0, r4
; CHECK-P8-NEXT: mr r30, r5 ; CHECK-P8-NEXT: mr r30, r5
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: xxswapd v3, vs1
; CHECK-P8-NEXT: bl __addkf3 ; CHECK-P8-NEXT: bl __addkf3
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: bl __fixunskfsi ; CHECK-P8-NEXT: bl __fixunskfsi
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: stw r3, 0(r30) ; CHECK-P8-NEXT: stw r3, 0(r30)
; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: addi r1, r1, 48
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
Show All 23 Lines
; ;
; CHECK-P8-LABEL: qpConv2shw: ; CHECK-P8-LABEL: qpConv2shw:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -32(r1) ; CHECK-P8-NEXT: stdu r1, -32(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 32 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 32
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: bl __fixkfsi ; CHECK-P8-NEXT: bl __fixkfsi
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: extsw r3, r3 ; CHECK-P8-NEXT: extsw r3, r3
; CHECK-P8-NEXT: addi r1, r1, 32 ; CHECK-P8-NEXT: addi r1, r1, 32
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
entry: entry:
Show All 21 Lines
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-P8-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-P8-NEXT: mr r30, r3 ; CHECK-P8-NEXT: mr r30, r3
; CHECK-P8-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-P8-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-P8-NEXT: addi r4, r4, 32 ; CHECK-P8-NEXT: addi r4, r4, 32
; CHECK-P8-NEXT: lvx v2, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r4
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: bl __fixkfsi ; CHECK-P8-NEXT: bl __fixkfsi
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: sth r3, 0(r30) ; CHECK-P8-NEXT: sth r3, 0(r30)
; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: addi r1, r1, 48
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
Show All 23 Lines
; CHECK-P8-LABEL: qpConv2shw_03: ; CHECK-P8-LABEL: qpConv2shw_03:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -32(r1) ; CHECK-P8-NEXT: stdu r1, -32(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 32 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 32
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-P8-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-P8-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: addi r4, r4, 16 ; CHECK-P8-NEXT: addi r4, r4, 16
; CHECK-P8-NEXT: lvx v3, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs1, 0, r4
; CHECK-P8-NEXT: xxswapd v3, vs1
; CHECK-P8-NEXT: bl __addkf3 ; CHECK-P8-NEXT: bl __addkf3
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: bl __fixkfsi ; CHECK-P8-NEXT: bl __fixkfsi
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: extsw r3, r3 ; CHECK-P8-NEXT: extsw r3, r3
; CHECK-P8-NEXT: addi r1, r1, 32 ; CHECK-P8-NEXT: addi r1, r1, 32
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
Show All 23 Lines
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: .cfi_def_cfa_offset 48 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 48
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: lvx v3, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs1, 0, r4
; CHECK-P8-NEXT: mr r30, r5 ; CHECK-P8-NEXT: mr r30, r5
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: xxswapd v3, vs1
; CHECK-P8-NEXT: bl __addkf3 ; CHECK-P8-NEXT: bl __addkf3
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: bl __fixkfsi ; CHECK-P8-NEXT: bl __fixkfsi
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: sth r3, 0(r30) ; CHECK-P8-NEXT: sth r3, 0(r30)
; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: addi r1, r1, 48
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
Show All 21 Lines
; ;
; CHECK-P8-LABEL: qpConv2uhw: ; CHECK-P8-LABEL: qpConv2uhw:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -32(r1) ; CHECK-P8-NEXT: stdu r1, -32(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 32 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 32
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: bl __fixkfsi ; CHECK-P8-NEXT: bl __fixkfsi
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: addi r1, r1, 32 ; CHECK-P8-NEXT: addi r1, r1, 32
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
entry: entry:
%0 = load fp128, fp128* %a, align 16 %0 = load fp128, fp128* %a, align 16
Show All 20 Lines
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-P8-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-P8-NEXT: mr r30, r3 ; CHECK-P8-NEXT: mr r30, r3
; CHECK-P8-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-P8-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-P8-NEXT: addi r4, r4, 32 ; CHECK-P8-NEXT: addi r4, r4, 32
; CHECK-P8-NEXT: lvx v2, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r4
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: bl __fixkfsi ; CHECK-P8-NEXT: bl __fixkfsi
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: sth r3, 0(r30) ; CHECK-P8-NEXT: sth r3, 0(r30)
; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: addi r1, r1, 48
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
Show All 23 Lines
; CHECK-P8-LABEL: qpConv2uhw_03: ; CHECK-P8-LABEL: qpConv2uhw_03:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -32(r1) ; CHECK-P8-NEXT: stdu r1, -32(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 32 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 32
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-P8-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-P8-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: addi r4, r4, 16 ; CHECK-P8-NEXT: addi r4, r4, 16
; CHECK-P8-NEXT: lvx v3, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs1, 0, r4
; CHECK-P8-NEXT: xxswapd v3, vs1
; CHECK-P8-NEXT: bl __addkf3 ; CHECK-P8-NEXT: bl __addkf3
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: bl __fixkfsi ; CHECK-P8-NEXT: bl __fixkfsi
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: addi r1, r1, 32 ; CHECK-P8-NEXT: addi r1, r1, 32
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
Show All 22 Lines
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: .cfi_def_cfa_offset 48 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 48
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: lvx v3, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs1, 0, r4
; CHECK-P8-NEXT: mr r30, r5 ; CHECK-P8-NEXT: mr r30, r5
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: xxswapd v3, vs1
; CHECK-P8-NEXT: bl __addkf3 ; CHECK-P8-NEXT: bl __addkf3
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: bl __fixkfsi ; CHECK-P8-NEXT: bl __fixkfsi
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: sth r3, 0(r30) ; CHECK-P8-NEXT: sth r3, 0(r30)
; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: addi r1, r1, 48
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
Show All 21 Lines
; ;
; CHECK-P8-LABEL: qpConv2sb: ; CHECK-P8-LABEL: qpConv2sb:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -32(r1) ; CHECK-P8-NEXT: stdu r1, -32(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 32 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 32
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: bl __fixkfsi ; CHECK-P8-NEXT: bl __fixkfsi
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: extsw r3, r3 ; CHECK-P8-NEXT: extsw r3, r3
; CHECK-P8-NEXT: addi r1, r1, 32 ; CHECK-P8-NEXT: addi r1, r1, 32
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
entry: entry:
Show All 21 Lines
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-P8-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-P8-NEXT: mr r30, r3 ; CHECK-P8-NEXT: mr r30, r3
; CHECK-P8-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-P8-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-P8-NEXT: addi r4, r4, 32 ; CHECK-P8-NEXT: addi r4, r4, 32
; CHECK-P8-NEXT: lvx v2, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r4
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: bl __fixkfsi ; CHECK-P8-NEXT: bl __fixkfsi
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: stb r3, 0(r30) ; CHECK-P8-NEXT: stb r3, 0(r30)
; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: addi r1, r1, 48
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
Show All 23 Lines
; CHECK-P8-LABEL: qpConv2sb_03: ; CHECK-P8-LABEL: qpConv2sb_03:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -32(r1) ; CHECK-P8-NEXT: stdu r1, -32(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 32 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 32
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-P8-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-P8-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: addi r4, r4, 16 ; CHECK-P8-NEXT: addi r4, r4, 16
; CHECK-P8-NEXT: lvx v3, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs1, 0, r4
; CHECK-P8-NEXT: xxswapd v3, vs1
; CHECK-P8-NEXT: bl __addkf3 ; CHECK-P8-NEXT: bl __addkf3
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: bl __fixkfsi ; CHECK-P8-NEXT: bl __fixkfsi
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: extsw r3, r3 ; CHECK-P8-NEXT: extsw r3, r3
; CHECK-P8-NEXT: addi r1, r1, 32 ; CHECK-P8-NEXT: addi r1, r1, 32
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
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; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: .cfi_def_cfa_offset 48 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 48
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: lvx v3, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs1, 0, r4
; CHECK-P8-NEXT: mr r30, r5 ; CHECK-P8-NEXT: mr r30, r5
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: xxswapd v3, vs1
; CHECK-P8-NEXT: bl __addkf3 ; CHECK-P8-NEXT: bl __addkf3
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: bl __fixkfsi ; CHECK-P8-NEXT: bl __fixkfsi
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: stb r3, 0(r30) ; CHECK-P8-NEXT: stb r3, 0(r30)
; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: addi r1, r1, 48
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
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; ;
; CHECK-P8-LABEL: qpConv2ub: ; CHECK-P8-LABEL: qpConv2ub:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -32(r1) ; CHECK-P8-NEXT: stdu r1, -32(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 32 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 32
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: bl __fixkfsi ; CHECK-P8-NEXT: bl __fixkfsi
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: addi r1, r1, 32 ; CHECK-P8-NEXT: addi r1, r1, 32
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
entry: entry:
%0 = load fp128, fp128* %a, align 16 %0 = load fp128, fp128* %a, align 16
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; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-P8-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-P8-NEXT: mr r30, r3 ; CHECK-P8-NEXT: mr r30, r3
; CHECK-P8-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-P8-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-P8-NEXT: addi r4, r4, 32 ; CHECK-P8-NEXT: addi r4, r4, 32
; CHECK-P8-NEXT: lvx v2, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r4
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: bl __fixkfsi ; CHECK-P8-NEXT: bl __fixkfsi
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: stb r3, 0(r30) ; CHECK-P8-NEXT: stb r3, 0(r30)
; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: addi r1, r1, 48
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
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; CHECK-P8-LABEL: qpConv2ub_03: ; CHECK-P8-LABEL: qpConv2ub_03:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -32(r1) ; CHECK-P8-NEXT: stdu r1, -32(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 32 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 32
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-P8-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-P8-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: addi r4, r4, 16 ; CHECK-P8-NEXT: addi r4, r4, 16
; CHECK-P8-NEXT: lvx v3, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs1, 0, r4
; CHECK-P8-NEXT: xxswapd v3, vs1
; CHECK-P8-NEXT: bl __addkf3 ; CHECK-P8-NEXT: bl __addkf3
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: bl __fixkfsi ; CHECK-P8-NEXT: bl __fixkfsi
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: addi r1, r1, 32 ; CHECK-P8-NEXT: addi r1, r1, 32
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
Show All 22 Lines
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: .cfi_def_cfa_offset 48 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 48
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: lvx v3, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs1, 0, r4
; CHECK-P8-NEXT: mr r30, r5 ; CHECK-P8-NEXT: mr r30, r5
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: xxswapd v3, vs1
; CHECK-P8-NEXT: bl __addkf3 ; CHECK-P8-NEXT: bl __addkf3
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: bl __fixkfsi ; CHECK-P8-NEXT: bl __fixkfsi
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: stb r3, 0(r30) ; CHECK-P8-NEXT: stb r3, 0(r30)
; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: addi r1, r1, 48
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
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; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: mr r30, r5 ; CHECK-P8-NEXT: mr r30, r5
; CHECK-P8-NEXT: bl __trunctfkf2 ; CHECK-P8-NEXT: bl __trunctfkf2
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: stvx v2, 0, r30 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: stxvd2x vs0, 0, r30
; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: addi r1, r1, 48
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
entry: entry:
%res = call fp128 @llvm.ppc.convert.ppcf128.to.f128(ppc_fp128 %src) %res = call fp128 @llvm.ppc.convert.ppcf128.to.f128(ppc_fp128 %src)
store fp128 %res, fp128* %dst, align 16 store fp128 %res, fp128* %dst, align 16
ret void ret void
} }
declare ppc_fp128 @llvm.ppc.convert.f128.to.ppcf128(fp128) declare ppc_fp128 @llvm.ppc.convert.f128.to.ppcf128(fp128)
declare fp128 @llvm.ppc.convert.ppcf128.to.f128(ppc_fp128) declare fp128 @llvm.ppc.convert.ppcf128.to.f128(ppc_fp128)

llvm/test/CodeGen/PowerPC/float-logic-ops.ll

Show First 20 Lines • Show All 49 Lines • ▼ Show 20 Linesentry:
ret <4 x float> %conv1 ret <4 x float> %conv1
} }
define <4 x float> @absv4f32_invalid(<4 x float> %a) { define <4 x float> @absv4f32_invalid(<4 x float> %a) {
; CHECK-LABEL: absv4f32_invalid: ; CHECK-LABEL: absv4f32_invalid:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r3, r2, .LCPI4_0@toc@ha ; CHECK-NEXT: addis r3, r2, .LCPI4_0@toc@ha
; CHECK-NEXT: addi r3, r3, .LCPI4_0@toc@l ; CHECK-NEXT: addi r3, r3, .LCPI4_0@toc@l
; CHECK-NEXT: lvx v3, 0, r3 ; CHECK-NEXT: lxvd2x vs0, 0, r3
; CHECK-NEXT: xxswapd vs35, vs0
; CHECK-NEXT: xxland vs34, vs34, vs35 ; CHECK-NEXT: xxland vs34, vs34, vs35
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%conv = bitcast <4 x float> %a to <4 x i32> %conv = bitcast <4 x float> %a to <4 x i32>
%and = and <4 x i32> %conv, <i32 2147483646, i32 2147483647, i32 2147483647, i32 2147483647> %and = and <4 x i32> %conv, <i32 2147483646, i32 2147483647, i32 2147483647, i32 2147483647>
%conv1 = bitcast <4 x i32> %and to <4 x float> %conv1 = bitcast <4 x i32> %and to <4 x float>
ret <4 x float> %conv1 ret <4 x float> %conv1
} }
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llvm/test/CodeGen/PowerPC/fp-strict-f128.ll

Show First 20 Lines • Show All 151 Lines • ▼ Show 20 Lines
; ;
; CHECK-P8-LABEL: fmsub_f128: ; CHECK-P8-LABEL: fmsub_f128:
; CHECK-P8: # %bb.0: ; CHECK-P8: # %bb.0:
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 48 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 48
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: xxswapd vs0, v4
; CHECK-P8-NEXT: addi r3, r1, 32 ; CHECK-P8-NEXT: addi r3, r1, 32
; CHECK-P8-NEXT: stvx v4, 0, r3 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r3
; CHECK-P8-NEXT: lbz r4, 47(r1) ; CHECK-P8-NEXT: lbz r4, 47(r1)
; CHECK-P8-NEXT: xori r4, r4, 128 ; CHECK-P8-NEXT: xori r4, r4, 128
; CHECK-P8-NEXT: stb r4, 47(r1) ; CHECK-P8-NEXT: stb r4, 47(r1)
; CHECK-P8-NEXT: lvx v4, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: xxswapd v4, vs0
; CHECK-P8-NEXT: bl fmaf128 ; CHECK-P8-NEXT: bl fmaf128
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: addi r1, r1, 48
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
%neg = fneg fp128 %f2 %neg = fneg fp128 %f2
%res = call fp128 @llvm.experimental.constrained.fma.f128( %res = call fp128 @llvm.experimental.constrained.fma.f128(
Show All 14 Lines
; CHECK-P8: # %bb.0: ; CHECK-P8: # %bb.0:
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 48 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 48
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: bl fmaf128 ; CHECK-P8-NEXT: bl fmaf128
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: addi r3, r1, 32 ; CHECK-P8-NEXT: addi r3, r1, 32
; CHECK-P8-NEXT: stvx v2, 0, r3 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r3
; CHECK-P8-NEXT: lbz r4, 47(r1) ; CHECK-P8-NEXT: lbz r4, 47(r1)
; CHECK-P8-NEXT: xori r4, r4, 128 ; CHECK-P8-NEXT: xori r4, r4, 128
; CHECK-P8-NEXT: stb r4, 47(r1) ; CHECK-P8-NEXT: stb r4, 47(r1)
; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: addi r1, r1, 48
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
%fma = call fp128 @llvm.experimental.constrained.fma.f128( %fma = call fp128 @llvm.experimental.constrained.fma.f128(
fp128 %f0, fp128 %f1, fp128 %f2, fp128 %f0, fp128 %f1, fp128 %f2,
metadata !"round.dynamic", metadata !"round.dynamic",
metadata !"fpexcept.strict") #0 metadata !"fpexcept.strict") #0
Show All 10 Lines
; ;
; CHECK-P8-LABEL: fnmsub_f128: ; CHECK-P8-LABEL: fnmsub_f128:
; CHECK-P8: # %bb.0: ; CHECK-P8: # %bb.0:
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -64(r1) ; CHECK-P8-NEXT: stdu r1, -64(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 64 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 64
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: xxswapd vs0, v4
; CHECK-P8-NEXT: addi r3, r1, 32 ; CHECK-P8-NEXT: addi r3, r1, 32
; CHECK-P8-NEXT: stvx v4, 0, r3 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r3
; CHECK-P8-NEXT: lbz r4, 47(r1) ; CHECK-P8-NEXT: lbz r4, 47(r1)
; CHECK-P8-NEXT: xori r4, r4, 128 ; CHECK-P8-NEXT: xori r4, r4, 128
; CHECK-P8-NEXT: stb r4, 47(r1) ; CHECK-P8-NEXT: stb r4, 47(r1)
; CHECK-P8-NEXT: lvx v4, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: xxswapd v4, vs0
; CHECK-P8-NEXT: bl fmaf128 ; CHECK-P8-NEXT: bl fmaf128
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: addi r3, r1, 48 ; CHECK-P8-NEXT: addi r3, r1, 48
; CHECK-P8-NEXT: stvx v2, 0, r3 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r3
; CHECK-P8-NEXT: lbz r4, 63(r1) ; CHECK-P8-NEXT: lbz r4, 63(r1)
; CHECK-P8-NEXT: xori r4, r4, 128 ; CHECK-P8-NEXT: xori r4, r4, 128
; CHECK-P8-NEXT: stb r4, 63(r1) ; CHECK-P8-NEXT: stb r4, 63(r1)
; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: addi r1, r1, 64 ; CHECK-P8-NEXT: addi r1, r1, 64
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
%neg = fneg fp128 %f2 %neg = fneg fp128 %f2
%fma = call fp128 @llvm.experimental.constrained.fma.f128( %fma = call fp128 @llvm.experimental.constrained.fma.f128(
fp128 %f0, fp128 %f1, fp128 %neg, fp128 %f0, fp128 %f1, fp128 %neg,
metadata !"round.dynamic", metadata !"round.dynamic",
Show All 33 Lines

llvm/test/CodeGen/PowerPC/legalize-vaarg.ll

Show All 17 Lines
; BE-NEXT: lvx 3, 0, 4 ; BE-NEXT: lvx 3, 0, 4
; BE-NEXT: blr ; BE-NEXT: blr
; ;
; LE-LABEL: test_large_vec_vaarg: ; LE-LABEL: test_large_vec_vaarg:
; LE: # %bb.0: ; LE: # %bb.0:
; LE-NEXT: ld 3, -8(1) ; LE-NEXT: ld 3, -8(1)
; LE-NEXT: addi 3, 3, 15 ; LE-NEXT: addi 3, 3, 15
; LE-NEXT: rldicr 3, 3, 0, 59 ; LE-NEXT: rldicr 3, 3, 0, 59
; LE-NEXT: addi 4, 3, 31 ; LE-NEXT: addi 4, 3, 16
; LE-NEXT: addi 5, 3, 16 ; LE-NEXT: std 4, -8(1)
; LE-NEXT: ld 4, -8(1)
; LE-NEXT: lxvd2x 0, 0, 3
; LE-NEXT: addi 4, 4, 15
; LE-NEXT: rldicr 4, 4, 0, 59 ; LE-NEXT: rldicr 4, 4, 0, 59
; LE-NEXT: std 5, -8(1) ; LE-NEXT: xxswapd 34, 0
; LE-NEXT: addi 5, 4, 16 ; LE-NEXT: addi 5, 4, 16
; LE-NEXT: lvx 2, 0, 3
; LE-NEXT: std 5, -8(1) ; LE-NEXT: std 5, -8(1)
; LE-NEXT: lvx 3, 0, 4 ; LE-NEXT: lxvd2x 1, 0, 4
; LE-NEXT: xxswapd 35, 1
; LE-NEXT: blr ; LE-NEXT: blr
%args = alloca i8*, align 4 %args = alloca i8*, align 4
%x = va_arg i8** %args, <8 x i32> %x = va_arg i8** %args, <8 x i32>
ret <8 x i32> %x ret <8 x i32> %x
} }

llvm/test/CodeGen/PowerPC/load-and-splat.ll

Show First 20 Lines • Show All 77 Lines • ▼ Show 20 Lines
; P9-NEXT: lxvwsx vs0, 0, r4 ; P9-NEXT: lxvwsx vs0, 0, r4
; P9-NEXT: stxv vs0, 0(r3) ; P9-NEXT: stxv vs0, 0(r3)
; P9-NEXT: blr ; P9-NEXT: blr
; ;
; P8-LABEL: test2: ; P8-LABEL: test2:
; P8: # %bb.0: # %entry ; P8: # %bb.0: # %entry
; P8-NEXT: addi r4, r4, 12 ; P8-NEXT: addi r4, r4, 12
; P8-NEXT: lfiwzx f0, 0, r4 ; P8-NEXT: lfiwzx f0, 0, r4
; P8-NEXT: xxspltw v2, vs0, 1 ; P8-NEXT: xxspltw vs0, vs0, 1
; P8-NEXT: stvx v2, 0, r3 ; P8-NEXT: xxswapd vs0, vs0
; P8-NEXT: stxvd2x vs0, 0, r3
; P8-NEXT: blr ; P8-NEXT: blr
; ;
; P7-LABEL: test2: ; P7-LABEL: test2:
; P7: # %bb.0: # %entry ; P7: # %bb.0: # %entry
; P7-NEXT: addi r4, r4, 12 ; P7-NEXT: addi r4, r4, 12
; P7-NEXT: lfiwzx f0, 0, r4 ; P7-NEXT: lfiwzx f0, 0, r4
; P7-NEXT: xxspltw vs0, vs0, 1 ; P7-NEXT: xxspltw vs0, vs0, 1
; P7-NEXT: stxvw4x vs0, 0, r3 ; P7-NEXT: stxvw4x vs0, 0, r3
Show All 38 Lines
; P9-NEXT: lxvwsx vs0, 0, r4 ; P9-NEXT: lxvwsx vs0, 0, r4
; P9-NEXT: stxv vs0, 0(r3) ; P9-NEXT: stxv vs0, 0(r3)
; P9-NEXT: blr ; P9-NEXT: blr
; ;
; P8-LABEL: test3: ; P8-LABEL: test3:
; P8: # %bb.0: # %entry ; P8: # %bb.0: # %entry
; P8-NEXT: addi r4, r4, 12 ; P8-NEXT: addi r4, r4, 12
; P8-NEXT: lfiwzx f0, 0, r4 ; P8-NEXT: lfiwzx f0, 0, r4
; P8-NEXT: xxspltw v2, vs0, 1 ; P8-NEXT: xxspltw vs0, vs0, 1
; P8-NEXT: stvx v2, 0, r3 ; P8-NEXT: xxswapd vs0, vs0
; P8-NEXT: stxvd2x vs0, 0, r3
; P8-NEXT: blr ; P8-NEXT: blr
; ;
; P7-LABEL: test3: ; P7-LABEL: test3:
; P7: # %bb.0: # %entry ; P7: # %bb.0: # %entry
; P7-NEXT: addi r4, r4, 12 ; P7-NEXT: addi r4, r4, 12
; P7-NEXT: lfiwzx f0, 0, r4 ; P7-NEXT: lfiwzx f0, 0, r4
; P7-NEXT: xxspltw vs0, vs0, 1 ; P7-NEXT: xxspltw vs0, vs0, 1
; P7-NEXT: stxvw4x vs0, 0, r3 ; P7-NEXT: stxvw4x vs0, 0, r3
▲ Show 20 Lines • Show All 271 Lines • ▼ Show 20 Lines
; P9-NEXT: stxv v2, 0(r3) ; P9-NEXT: stxv v2, 0(r3)
; P9-NEXT: blr ; P9-NEXT: blr
; ;
; P8-LABEL: test7: ; P8-LABEL: test7:
; P8: # %bb.0: # %entry ; P8: # %bb.0: # %entry
; P8-NEXT: lhzx r4, 0, r4 ; P8-NEXT: lhzx r4, 0, r4
; P8-NEXT: mtvsrwz v2, r4 ; P8-NEXT: mtvsrwz v2, r4
; P8-NEXT: vsplth v2, v2, 3 ; P8-NEXT: vsplth v2, v2, 3
; P8-NEXT: stvx v2, 0, r3 ; P8-NEXT: xxswapd vs0, v2
; P8-NEXT: stxvd2x vs0, 0, r3
; P8-NEXT: blr ; P8-NEXT: blr
; ;
; P7-LABEL: test7: ; P7-LABEL: test7:
; P7: # %bb.0: # %entry ; P7: # %bb.0: # %entry
; P7-NEXT: li r5, 1 ; P7-NEXT: li r5, 1
; P7-NEXT: lvx v2, 0, r4 ; P7-NEXT: lvx v2, 0, r4
; P7-NEXT: lvsl v4, 0, r4 ; P7-NEXT: lvsl v4, 0, r4
; P7-NEXT: lvx v3, r5, r4 ; P7-NEXT: lvx v3, r5, r4
▲ Show 20 Lines • Show All 44 Lines • ▼ Show 20 Lines
; P9-NEXT: stxv v2, 0(r3) ; P9-NEXT: stxv v2, 0(r3)
; P9-NEXT: blr ; P9-NEXT: blr
; ;
; P8-LABEL: test8: ; P8-LABEL: test8:
; P8: # %bb.0: # %entry ; P8: # %bb.0: # %entry
; P8-NEXT: lbzx r4, 0, r4 ; P8-NEXT: lbzx r4, 0, r4
; P8-NEXT: mtvsrwz v2, r4 ; P8-NEXT: mtvsrwz v2, r4
; P8-NEXT: vspltb v2, v2, 7 ; P8-NEXT: vspltb v2, v2, 7
; P8-NEXT: stvx v2, 0, r3 ; P8-NEXT: xxswapd vs0, v2
; P8-NEXT: stxvd2x vs0, 0, r3
; P8-NEXT: blr ; P8-NEXT: blr
; ;
; P7-LABEL: test8: ; P7-LABEL: test8:
; P7: # %bb.0: # %entry ; P7: # %bb.0: # %entry
; P7-NEXT: lvsl v2, 0, r4 ; P7-NEXT: lvsl v2, 0, r4
; P7-NEXT: lvx v3, 0, r4 ; P7-NEXT: lvx v3, 0, r4
; P7-NEXT: vperm v2, v3, v3, v2 ; P7-NEXT: vperm v2, v3, v3, v2
; P7-NEXT: vspltb v2, v2, 0 ; P7-NEXT: vspltb v2, v2, 0
▲ Show 20 Lines • Show All 123 Lines • ▼ Show 20 Lines
define <16 x i8> @unadjusted_lxvwsx_v16i8(<16 x i8> *%s, <16 x i8> %t) { define <16 x i8> @unadjusted_lxvwsx_v16i8(<16 x i8> *%s, <16 x i8> %t) {
; P9-LABEL: unadjusted_lxvwsx_v16i8: ; P9-LABEL: unadjusted_lxvwsx_v16i8:
; P9: # %bb.0: # %entry ; P9: # %bb.0: # %entry
; P9-NEXT: lxvwsx v2, 0, r3 ; P9-NEXT: lxvwsx v2, 0, r3
; P9-NEXT: blr ; P9-NEXT: blr
; ;
; P8-LABEL: unadjusted_lxvwsx_v16i8: ; P8-LABEL: unadjusted_lxvwsx_v16i8:
; P8: # %bb.0: # %entry ; P8: # %bb.0: # %entry
; P8-NEXT: lvx v2, 0, r3 ; P8-NEXT: lxvd2x vs0, 0, r3
; P8-NEXT: xxswapd v2, vs0
; P8-NEXT: xxspltw v2, v2, 3 ; P8-NEXT: xxspltw v2, v2, 3
; P8-NEXT: blr ; P8-NEXT: blr
; ;
; P7-LABEL: unadjusted_lxvwsx_v16i8: ; P7-LABEL: unadjusted_lxvwsx_v16i8:
; P7: # %bb.0: # %entry ; P7: # %bb.0: # %entry
; P7-NEXT: lxvw4x vs0, 0, r3 ; P7-NEXT: lxvw4x vs0, 0, r3
; P7-NEXT: xxspltw v2, vs0, 0 ; P7-NEXT: xxspltw v2, vs0, 0
; P7-NEXT: blr ; P7-NEXT: blr
Show All 24 Lines
; P9-LABEL: adjusted_lxvwsx_v16i8: ; P9-LABEL: adjusted_lxvwsx_v16i8:
; P9: # %bb.0: # %entry ; P9: # %bb.0: # %entry
; P9-NEXT: addi r3, r3, 4 ; P9-NEXT: addi r3, r3, 4
; P9-NEXT: lxvwsx v2, 0, r3 ; P9-NEXT: lxvwsx v2, 0, r3
; P9-NEXT: blr ; P9-NEXT: blr
; ;
; P8-LABEL: adjusted_lxvwsx_v16i8: ; P8-LABEL: adjusted_lxvwsx_v16i8:
; P8: # %bb.0: # %entry ; P8: # %bb.0: # %entry
; P8-NEXT: lvx v2, 0, r3 ; P8-NEXT: lxvd2x vs0, 0, r3
; P8-NEXT: xxswapd v2, vs0
; P8-NEXT: xxspltw v2, v2, 2 ; P8-NEXT: xxspltw v2, v2, 2
; P8-NEXT: blr ; P8-NEXT: blr
; ;
; P7-LABEL: adjusted_lxvwsx_v16i8: ; P7-LABEL: adjusted_lxvwsx_v16i8:
; P7: # %bb.0: # %entry ; P7: # %bb.0: # %entry
; P7-NEXT: lxvw4x vs0, 0, r3 ; P7-NEXT: lxvw4x vs0, 0, r3
; P7-NEXT: xxspltw v2, vs0, 1 ; P7-NEXT: xxspltw v2, vs0, 1
; P7-NEXT: blr ; P7-NEXT: blr
Show All 25 Lines
; P9-LABEL: adjusted_lxvwsx_v16i8_2: ; P9-LABEL: adjusted_lxvwsx_v16i8_2:
; P9: # %bb.0: # %entry ; P9: # %bb.0: # %entry
; P9-NEXT: addi r3, r3, 8 ; P9-NEXT: addi r3, r3, 8
; P9-NEXT: lxvwsx v2, 0, r3 ; P9-NEXT: lxvwsx v2, 0, r3
; P9-NEXT: blr ; P9-NEXT: blr
; ;
; P8-LABEL: adjusted_lxvwsx_v16i8_2: ; P8-LABEL: adjusted_lxvwsx_v16i8_2:
; P8: # %bb.0: # %entry ; P8: # %bb.0: # %entry
; P8-NEXT: lvx v2, 0, r3 ; P8-NEXT: lxvd2x vs0, 0, r3
; P8-NEXT: xxswapd v2, vs0
; P8-NEXT: xxspltw v2, v2, 1 ; P8-NEXT: xxspltw v2, v2, 1
; P8-NEXT: blr ; P8-NEXT: blr
; ;
; P7-LABEL: adjusted_lxvwsx_v16i8_2: ; P7-LABEL: adjusted_lxvwsx_v16i8_2:
; P7: # %bb.0: # %entry ; P7: # %bb.0: # %entry
; P7-NEXT: lxvw4x vs0, 0, r3 ; P7-NEXT: lxvw4x vs0, 0, r3
; P7-NEXT: xxspltw v2, vs0, 2 ; P7-NEXT: xxspltw v2, vs0, 2
; P7-NEXT: blr ; P7-NEXT: blr
Show All 25 Lines
; P9-LABEL: adjusted_lxvwsx_v16i8_3: ; P9-LABEL: adjusted_lxvwsx_v16i8_3:
; P9: # %bb.0: # %entry ; P9: # %bb.0: # %entry
; P9-NEXT: addi r3, r3, 12 ; P9-NEXT: addi r3, r3, 12
; P9-NEXT: lxvwsx v2, 0, r3 ; P9-NEXT: lxvwsx v2, 0, r3
; P9-NEXT: blr ; P9-NEXT: blr
; ;
; P8-LABEL: adjusted_lxvwsx_v16i8_3: ; P8-LABEL: adjusted_lxvwsx_v16i8_3:
; P8: # %bb.0: # %entry ; P8: # %bb.0: # %entry
; P8-NEXT: lvx v2, 0, r3 ; P8-NEXT: lxvd2x vs0, 0, r3
; P8-NEXT: xxswapd v2, vs0
; P8-NEXT: xxspltw v2, v2, 0 ; P8-NEXT: xxspltw v2, v2, 0
; P8-NEXT: blr ; P8-NEXT: blr
; ;
; P7-LABEL: adjusted_lxvwsx_v16i8_3: ; P7-LABEL: adjusted_lxvwsx_v16i8_3:
; P7: # %bb.0: # %entry ; P7: # %bb.0: # %entry
; P7-NEXT: lxvw4x vs0, 0, r3 ; P7-NEXT: lxvw4x vs0, 0, r3
; P7-NEXT: xxspltw v2, vs0, 3 ; P7-NEXT: xxspltw v2, vs0, 3
; P7-NEXT: blr ; P7-NEXT: blr
▲ Show 20 Lines • Show All 551 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/load-shuffle-and-shuffle-store.ll

Show First 20 Lines • Show All 65 Lines • ▼ Show 20 Lines; CHECK-P9-BE-NEXT: blr
%v3 = shufflevector <2 x i64> %v1, <2 x i64> %v2, <2 x i32> <i32 3, i32 2> %v3 = shufflevector <2 x i64> %v1, <2 x i64> %v2, <2 x i32> <i32 3, i32 2>
ret <2 x i64> %v3 ret <2 x i64> %v3
} }
define <4 x i32> @load_swap10(<4 x i32>* %vp1, <4 x i32>* %vp2) { define <4 x i32> @load_swap10(<4 x i32>* %vp1, <4 x i32>* %vp2) {
; CHECK-P8-LABEL: load_swap10: ; CHECK-P8-LABEL: load_swap10:
; CHECK-P8: # %bb.0: ; CHECK-P8: # %bb.0:
; CHECK-P8-NEXT: addis r4, r2, .LCPI2_0@toc@ha ; CHECK-P8-NEXT: addis r4, r2, .LCPI2_0@toc@ha
; CHECK-P8-NEXT: lvx v3, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: addi r4, r4, .LCPI2_0@toc@l ; CHECK-P8-NEXT: addi r4, r4, .LCPI2_0@toc@l
; CHECK-P8-NEXT: lvx v2, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs1, 0, r4
; CHECK-P8-NEXT: vperm v2, v3, v3, v2 ; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: xxswapd v3, vs1
; CHECK-P8-NEXT: vperm v2, v2, v2, v3
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: load_swap10: ; CHECK-P9-LABEL: load_swap10:
; CHECK-P9: # %bb.0: ; CHECK-P9: # %bb.0:
; CHECK-P9-NEXT: lxvw4x v2, 0, r3 ; CHECK-P9-NEXT: lxvw4x v2, 0, r3
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-P8-BE-LABEL: load_swap10: ; CHECK-P8-BE-LABEL: load_swap10:
Show All 18 Lines; CHECK-P9-BE-NEXT: blr
%v3 = shufflevector <4 x i32> %v1, <4 x i32> %v2, <4 x i32> <i32 3, i32 2, i32 1, i32 0> %v3 = shufflevector <4 x i32> %v1, <4 x i32> %v2, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
ret <4 x i32> %v3 ret <4 x i32> %v3
} }
define <4 x i32> @load_swap11(<4 x i32>* %vp1, <4 x i32>* %vp2) { define <4 x i32> @load_swap11(<4 x i32>* %vp1, <4 x i32>* %vp2) {
; CHECK-P8-LABEL: load_swap11: ; CHECK-P8-LABEL: load_swap11:
; CHECK-P8: # %bb.0: ; CHECK-P8: # %bb.0:
; CHECK-P8-NEXT: addis r3, r2, .LCPI3_0@toc@ha ; CHECK-P8-NEXT: addis r3, r2, .LCPI3_0@toc@ha
; CHECK-P8-NEXT: lvx v3, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r4
; CHECK-P8-NEXT: addi r3, r3, .LCPI3_0@toc@l ; CHECK-P8-NEXT: addi r3, r3, .LCPI3_0@toc@l
; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs1, 0, r3
; CHECK-P8-NEXT: vperm v2, v3, v3, v2 ; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: xxswapd v3, vs1
; CHECK-P8-NEXT: vperm v2, v2, v2, v3
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: load_swap11: ; CHECK-P9-LABEL: load_swap11:
; CHECK-P9: # %bb.0: ; CHECK-P9: # %bb.0:
; CHECK-P9-NEXT: lxvw4x v2, 0, r4 ; CHECK-P9-NEXT: lxvw4x v2, 0, r4
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-P8-BE-LABEL: load_swap11: ; CHECK-P8-BE-LABEL: load_swap11:
Show All 18 Lines; CHECK-P9-BE-NEXT: blr
%v3 = shufflevector <4 x i32> %v1, <4 x i32> %v2, <4 x i32> <i32 7, i32 6, i32 5, i32 4> %v3 = shufflevector <4 x i32> %v1, <4 x i32> %v2, <4 x i32> <i32 7, i32 6, i32 5, i32 4>
ret <4 x i32> %v3 ret <4 x i32> %v3
} }
define <8 x i16> @load_swap20(<8 x i16>* %vp1, <8 x i16>* %vp2){ define <8 x i16> @load_swap20(<8 x i16>* %vp1, <8 x i16>* %vp2){
; CHECK-P8-LABEL: load_swap20: ; CHECK-P8-LABEL: load_swap20:
; CHECK-P8: # %bb.0: ; CHECK-P8: # %bb.0:
; CHECK-P8-NEXT: addis r4, r2, .LCPI4_0@toc@ha ; CHECK-P8-NEXT: addis r4, r2, .LCPI4_0@toc@ha
; CHECK-P8-NEXT: lvx v3, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: addi r4, r4, .LCPI4_0@toc@l ; CHECK-P8-NEXT: addi r4, r4, .LCPI4_0@toc@l
; CHECK-P8-NEXT: lvx v2, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs1, 0, r4
; CHECK-P8-NEXT: vperm v2, v3, v3, v2 ; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: xxswapd v3, vs1
; CHECK-P8-NEXT: vperm v2, v2, v2, v3
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: load_swap20: ; CHECK-P9-LABEL: load_swap20:
; CHECK-P9: # %bb.0: ; CHECK-P9: # %bb.0:
; CHECK-P9-NEXT: lxvh8x v2, 0, r3 ; CHECK-P9-NEXT: lxvh8x v2, 0, r3
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-P8-BE-LABEL: load_swap20: ; CHECK-P8-BE-LABEL: load_swap20:
Show All 18 Lines; CHECK-P9-BE-NEXT: blr
%v3 = shufflevector <8 x i16> %v1, <8 x i16> %v2, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0> %v3 = shufflevector <8 x i16> %v1, <8 x i16> %v2, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
ret <8 x i16> %v3 ret <8 x i16> %v3
} }
define <8 x i16> @load_swap21(<8 x i16>* %vp1, <8 x i16>* %vp2){ define <8 x i16> @load_swap21(<8 x i16>* %vp1, <8 x i16>* %vp2){
; CHECK-P8-LABEL: load_swap21: ; CHECK-P8-LABEL: load_swap21:
; CHECK-P8: # %bb.0: ; CHECK-P8: # %bb.0:
; CHECK-P8-NEXT: addis r3, r2, .LCPI5_0@toc@ha ; CHECK-P8-NEXT: addis r3, r2, .LCPI5_0@toc@ha
; CHECK-P8-NEXT: lvx v3, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r4
; CHECK-P8-NEXT: addi r3, r3, .LCPI5_0@toc@l ; CHECK-P8-NEXT: addi r3, r3, .LCPI5_0@toc@l
; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs1, 0, r3
; CHECK-P8-NEXT: vperm v2, v3, v3, v2 ; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: xxswapd v3, vs1
; CHECK-P8-NEXT: vperm v2, v2, v2, v3
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: load_swap21: ; CHECK-P9-LABEL: load_swap21:
; CHECK-P9: # %bb.0: ; CHECK-P9: # %bb.0:
; CHECK-P9-NEXT: lxvh8x v2, 0, r4 ; CHECK-P9-NEXT: lxvh8x v2, 0, r4
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-P8-BE-LABEL: load_swap21: ; CHECK-P8-BE-LABEL: load_swap21:
Show All 18 Lines; CHECK-P9-BE-NEXT: blr
%v3 = shufflevector <8 x i16> %v1, <8 x i16> %v2, <8 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8> %v3 = shufflevector <8 x i16> %v1, <8 x i16> %v2, <8 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8>
ret <8 x i16> %v3 ret <8 x i16> %v3
} }
define <16 x i8> @load_swap30(<16 x i8>* %vp1, <16 x i8>* %vp2){ define <16 x i8> @load_swap30(<16 x i8>* %vp1, <16 x i8>* %vp2){
; CHECK-P8-LABEL: load_swap30: ; CHECK-P8-LABEL: load_swap30:
; CHECK-P8: # %bb.0: ; CHECK-P8: # %bb.0:
; CHECK-P8-NEXT: addis r4, r2, .LCPI6_0@toc@ha ; CHECK-P8-NEXT: addis r4, r2, .LCPI6_0@toc@ha
; CHECK-P8-NEXT: lvx v3, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: addi r4, r4, .LCPI6_0@toc@l ; CHECK-P8-NEXT: addi r4, r4, .LCPI6_0@toc@l
; CHECK-P8-NEXT: lvx v2, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs1, 0, r4
; CHECK-P8-NEXT: vperm v2, v3, v3, v2 ; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: xxswapd v3, vs1
; CHECK-P8-NEXT: vperm v2, v2, v2, v3
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: load_swap30: ; CHECK-P9-LABEL: load_swap30:
; CHECK-P9: # %bb.0: ; CHECK-P9: # %bb.0:
; CHECK-P9-NEXT: lxvb16x v2, 0, r3 ; CHECK-P9-NEXT: lxvb16x v2, 0, r3
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-P8-BE-LABEL: load_swap30: ; CHECK-P8-BE-LABEL: load_swap30:
Show All 15 Lines; CHECK-P9-BE-NEXT: blr
%v3 = shufflevector <16 x i8> %v1, <16 x i8> %v2, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0> %v3 = shufflevector <16 x i8> %v1, <16 x i8> %v2, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
ret <16 x i8> %v3 ret <16 x i8> %v3
} }
define <16 x i8> @load_swap31(<16 x i8>* %vp1, <16 x i8>* %vp2){ define <16 x i8> @load_swap31(<16 x i8>* %vp1, <16 x i8>* %vp2){
; CHECK-P8-LABEL: load_swap31: ; CHECK-P8-LABEL: load_swap31:
; CHECK-P8: # %bb.0: ; CHECK-P8: # %bb.0:
; CHECK-P8-NEXT: addis r3, r2, .LCPI7_0@toc@ha ; CHECK-P8-NEXT: addis r3, r2, .LCPI7_0@toc@ha
; CHECK-P8-NEXT: lvx v3, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r4
; CHECK-P8-NEXT: addi r3, r3, .LCPI7_0@toc@l ; CHECK-P8-NEXT: addi r3, r3, .LCPI7_0@toc@l
; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs1, 0, r3
; CHECK-P8-NEXT: vperm v2, v3, v3, v2 ; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: xxswapd v3, vs1
; CHECK-P8-NEXT: vperm v2, v2, v2, v3
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: load_swap31: ; CHECK-P9-LABEL: load_swap31:
; CHECK-P9: # %bb.0: ; CHECK-P9: # %bb.0:
; CHECK-P9-NEXT: lxvb16x v2, 0, r4 ; CHECK-P9-NEXT: lxvb16x v2, 0, r4
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-P8-BE-LABEL: load_swap31: ; CHECK-P8-BE-LABEL: load_swap31:
▲ Show 20 Lines • Show All 43 Lines • ▼ Show 20 Lines; CHECK-P9-BE-NEXT: blr
%v3 = shufflevector <2 x double> %v1, <2 x double> %v2, <2 x i32> <i32 3, i32 2> %v3 = shufflevector <2 x double> %v1, <2 x double> %v2, <2 x i32> <i32 3, i32 2>
ret <2 x double> %v3 ret <2 x double> %v3
} }
define <4 x float> @load_swap50(<4 x float>* %vp1, <4 x float>* %vp2) { define <4 x float> @load_swap50(<4 x float>* %vp1, <4 x float>* %vp2) {
; CHECK-P8-LABEL: load_swap50: ; CHECK-P8-LABEL: load_swap50:
; CHECK-P8: # %bb.0: ; CHECK-P8: # %bb.0:
; CHECK-P8-NEXT: addis r4, r2, .LCPI9_0@toc@ha ; CHECK-P8-NEXT: addis r4, r2, .LCPI9_0@toc@ha
; CHECK-P8-NEXT: lvx v3, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: addi r4, r4, .LCPI9_0@toc@l ; CHECK-P8-NEXT: addi r4, r4, .LCPI9_0@toc@l
; CHECK-P8-NEXT: lvx v2, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs1, 0, r4
; CHECK-P8-NEXT: vperm v2, v3, v3, v2 ; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: xxswapd v3, vs1
; CHECK-P8-NEXT: vperm v2, v2, v2, v3
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: load_swap50: ; CHECK-P9-LABEL: load_swap50:
; CHECK-P9: # %bb.0: ; CHECK-P9: # %bb.0:
; CHECK-P9-NEXT: lxvw4x v2, 0, r3 ; CHECK-P9-NEXT: lxvw4x v2, 0, r3
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-P8-BE-LABEL: load_swap50: ; CHECK-P8-BE-LABEL: load_swap50:
Show All 18 Lines; CHECK-P9-BE-NEXT: blr
%v3 = shufflevector <4 x float> %v1, <4 x float> %v2, <4 x i32> <i32 3, i32 2, i32 1, i32 0> %v3 = shufflevector <4 x float> %v1, <4 x float> %v2, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
ret <4 x float> %v3 ret <4 x float> %v3
} }
define <4 x float> @load_swap51(<4 x float>* %vp1, <4 x float>* %vp2) { define <4 x float> @load_swap51(<4 x float>* %vp1, <4 x float>* %vp2) {
; CHECK-P8-LABEL: load_swap51: ; CHECK-P8-LABEL: load_swap51:
; CHECK-P8: # %bb.0: ; CHECK-P8: # %bb.0:
; CHECK-P8-NEXT: addis r3, r2, .LCPI10_0@toc@ha ; CHECK-P8-NEXT: addis r3, r2, .LCPI10_0@toc@ha
; CHECK-P8-NEXT: lvx v3, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r4
; CHECK-P8-NEXT: addi r3, r3, .LCPI10_0@toc@l ; CHECK-P8-NEXT: addi r3, r3, .LCPI10_0@toc@l
; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs1, 0, r3
; CHECK-P8-NEXT: vperm v2, v3, v3, v2 ; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: xxswapd v3, vs1
; CHECK-P8-NEXT: vperm v2, v2, v2, v3
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: load_swap51: ; CHECK-P9-LABEL: load_swap51:
; CHECK-P9: # %bb.0: ; CHECK-P9: # %bb.0:
; CHECK-P9-NEXT: lxvw4x v2, 0, r4 ; CHECK-P9-NEXT: lxvw4x v2, 0, r4
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-P8-BE-LABEL: load_swap51: ; CHECK-P8-BE-LABEL: load_swap51:
▲ Show 20 Lines • Show All 73 Lines • ▼ Show 20 Lines; CHECK-P9-BE-NEXT: blr
ret void ret void
} }
define void @swap_store10(<4 x i32> %v1, <4 x i32> %v2, <4 x i32>* %vp) { define void @swap_store10(<4 x i32> %v1, <4 x i32> %v2, <4 x i32>* %vp) {
; CHECK-P8-LABEL: swap_store10: ; CHECK-P8-LABEL: swap_store10:
; CHECK-P8: # %bb.0: ; CHECK-P8: # %bb.0:
; CHECK-P8-NEXT: addis r3, r2, .LCPI13_0@toc@ha ; CHECK-P8-NEXT: addis r3, r2, .LCPI13_0@toc@ha
; CHECK-P8-NEXT: addi r3, r3, .LCPI13_0@toc@l ; CHECK-P8-NEXT: addi r3, r3, .LCPI13_0@toc@l
; CHECK-P8-NEXT: lvx v3, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: xxswapd v3, vs0
; CHECK-P8-NEXT: vperm v2, v2, v2, v3 ; CHECK-P8-NEXT: vperm v2, v2, v2, v3
; CHECK-P8-NEXT: stvx v2, 0, r7 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: stxvd2x vs0, 0, r7
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: swap_store10: ; CHECK-P9-LABEL: swap_store10:
; CHECK-P9: # %bb.0: ; CHECK-P9: # %bb.0:
; CHECK-P9-NEXT: stxvw4x v2, 0, r7 ; CHECK-P9-NEXT: stxvw4x v2, 0, r7
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-P8-BE-LABEL: swap_store10: ; CHECK-P8-BE-LABEL: swap_store10:
Show All 18 Lines; CHECK-P9-BE-NEXT: blr
ret void ret void
} }
define void @swap_store11(<4 x i32> %v1, <4 x i32> %v2, <4 x i32>* %vp) { define void @swap_store11(<4 x i32> %v1, <4 x i32> %v2, <4 x i32>* %vp) {
; CHECK-P8-LABEL: swap_store11: ; CHECK-P8-LABEL: swap_store11:
; CHECK-P8: # %bb.0: ; CHECK-P8: # %bb.0:
; CHECK-P8-NEXT: addis r3, r2, .LCPI14_0@toc@ha ; CHECK-P8-NEXT: addis r3, r2, .LCPI14_0@toc@ha
; CHECK-P8-NEXT: addi r3, r3, .LCPI14_0@toc@l ; CHECK-P8-NEXT: addi r3, r3, .LCPI14_0@toc@l
; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: vperm v2, v3, v3, v2 ; CHECK-P8-NEXT: vperm v2, v3, v3, v2
; CHECK-P8-NEXT: stvx v2, 0, r7 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: stxvd2x vs0, 0, r7
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: swap_store11: ; CHECK-P9-LABEL: swap_store11:
; CHECK-P9: # %bb.0: ; CHECK-P9: # %bb.0:
; CHECK-P9-NEXT: stxvw4x v3, 0, r7 ; CHECK-P9-NEXT: stxvw4x v3, 0, r7
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-P8-BE-LABEL: swap_store11: ; CHECK-P8-BE-LABEL: swap_store11:
Show All 18 Lines; CHECK-P9-BE-NEXT: blr
ret void ret void
} }
define void @swap_store20(<8 x i16> %v1, <8 x i16> %v2, <8 x i16>* %vp) { define void @swap_store20(<8 x i16> %v1, <8 x i16> %v2, <8 x i16>* %vp) {
; CHECK-P8-LABEL: swap_store20: ; CHECK-P8-LABEL: swap_store20:
; CHECK-P8: # %bb.0: ; CHECK-P8: # %bb.0:
; CHECK-P8-NEXT: addis r3, r2, .LCPI15_0@toc@ha ; CHECK-P8-NEXT: addis r3, r2, .LCPI15_0@toc@ha
; CHECK-P8-NEXT: addi r3, r3, .LCPI15_0@toc@l ; CHECK-P8-NEXT: addi r3, r3, .LCPI15_0@toc@l
; CHECK-P8-NEXT: lvx v3, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: xxswapd v3, vs0
; CHECK-P8-NEXT: vperm v2, v2, v2, v3 ; CHECK-P8-NEXT: vperm v2, v2, v2, v3
; CHECK-P8-NEXT: stvx v2, 0, r7 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: stxvd2x vs0, 0, r7
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: swap_store20: ; CHECK-P9-LABEL: swap_store20:
; CHECK-P9: # %bb.0: ; CHECK-P9: # %bb.0:
; CHECK-P9-NEXT: stxvh8x v2, 0, r7 ; CHECK-P9-NEXT: stxvh8x v2, 0, r7
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-P8-BE-LABEL: swap_store20: ; CHECK-P8-BE-LABEL: swap_store20:
Show All 18 Lines; CHECK-P9-BE-NEXT: blr
ret void ret void
} }
define void @swap_store21(<8 x i16> %v1, <8 x i16> %v2, <8 x i16>* %vp) { define void @swap_store21(<8 x i16> %v1, <8 x i16> %v2, <8 x i16>* %vp) {
; CHECK-P8-LABEL: swap_store21: ; CHECK-P8-LABEL: swap_store21:
; CHECK-P8: # %bb.0: ; CHECK-P8: # %bb.0:
; CHECK-P8-NEXT: addis r3, r2, .LCPI16_0@toc@ha ; CHECK-P8-NEXT: addis r3, r2, .LCPI16_0@toc@ha
; CHECK-P8-NEXT: addi r3, r3, .LCPI16_0@toc@l ; CHECK-P8-NEXT: addi r3, r3, .LCPI16_0@toc@l
; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: vperm v2, v3, v3, v2 ; CHECK-P8-NEXT: vperm v2, v3, v3, v2
; CHECK-P8-NEXT: stvx v2, 0, r7 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: stxvd2x vs0, 0, r7
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: swap_store21: ; CHECK-P9-LABEL: swap_store21:
; CHECK-P9: # %bb.0: ; CHECK-P9: # %bb.0:
; CHECK-P9-NEXT: stxvh8x v3, 0, r7 ; CHECK-P9-NEXT: stxvh8x v3, 0, r7
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-P8-BE-LABEL: swap_store21: ; CHECK-P8-BE-LABEL: swap_store21:
Show All 18 Lines; CHECK-P9-BE-NEXT: blr
ret void ret void
} }
define void @swap_store30(<16 x i8> %v1, <16 x i8> %v2, <16 x i8>* %vp) { define void @swap_store30(<16 x i8> %v1, <16 x i8> %v2, <16 x i8>* %vp) {
; CHECK-P8-LABEL: swap_store30: ; CHECK-P8-LABEL: swap_store30:
; CHECK-P8: # %bb.0: ; CHECK-P8: # %bb.0:
; CHECK-P8-NEXT: addis r3, r2, .LCPI17_0@toc@ha ; CHECK-P8-NEXT: addis r3, r2, .LCPI17_0@toc@ha
; CHECK-P8-NEXT: addi r3, r3, .LCPI17_0@toc@l ; CHECK-P8-NEXT: addi r3, r3, .LCPI17_0@toc@l
; CHECK-P8-NEXT: lvx v3, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: xxswapd v3, vs0
; CHECK-P8-NEXT: vperm v2, v2, v2, v3 ; CHECK-P8-NEXT: vperm v2, v2, v2, v3
; CHECK-P8-NEXT: stvx v2, 0, r7 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: stxvd2x vs0, 0, r7
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: swap_store30: ; CHECK-P9-LABEL: swap_store30:
; CHECK-P9: # %bb.0: ; CHECK-P9: # %bb.0:
; CHECK-P9-NEXT: stxvb16x v2, 0, r7 ; CHECK-P9-NEXT: stxvb16x v2, 0, r7
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-P8-BE-LABEL: swap_store30: ; CHECK-P8-BE-LABEL: swap_store30:
Show All 15 Lines; CHECK-P9-BE-NEXT: blr
ret void ret void
} }
define void @swap_store31(<16 x i8> %v1, <16 x i8> %v2, <16 x i8>* %vp) { define void @swap_store31(<16 x i8> %v1, <16 x i8> %v2, <16 x i8>* %vp) {
; CHECK-P8-LABEL: swap_store31: ; CHECK-P8-LABEL: swap_store31:
; CHECK-P8: # %bb.0: ; CHECK-P8: # %bb.0:
; CHECK-P8-NEXT: addis r3, r2, .LCPI18_0@toc@ha ; CHECK-P8-NEXT: addis r3, r2, .LCPI18_0@toc@ha
; CHECK-P8-NEXT: addi r3, r3, .LCPI18_0@toc@l ; CHECK-P8-NEXT: addi r3, r3, .LCPI18_0@toc@l
; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: vperm v2, v3, v3, v2 ; CHECK-P8-NEXT: vperm v2, v3, v3, v2
; CHECK-P8-NEXT: stvx v2, 0, r7 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: stxvd2x vs0, 0, r7
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: swap_store31: ; CHECK-P9-LABEL: swap_store31:
; CHECK-P9: # %bb.0: ; CHECK-P9: # %bb.0:
; CHECK-P9-NEXT: stxvb16x v3, 0, r7 ; CHECK-P9-NEXT: stxvb16x v3, 0, r7
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-P8-BE-LABEL: swap_store31: ; CHECK-P8-BE-LABEL: swap_store31:
▲ Show 20 Lines • Show All 69 Lines • ▼ Show 20 Lines; CHECK-P9-BE-NEXT: blr
ret void ret void
} }
define void @swap_store50(<4 x float> %v1, <4 x float> %v2, <4 x float>* %vp) { define void @swap_store50(<4 x float> %v1, <4 x float> %v2, <4 x float>* %vp) {
; CHECK-P8-LABEL: swap_store50: ; CHECK-P8-LABEL: swap_store50:
; CHECK-P8: # %bb.0: ; CHECK-P8: # %bb.0:
; CHECK-P8-NEXT: addis r3, r2, .LCPI21_0@toc@ha ; CHECK-P8-NEXT: addis r3, r2, .LCPI21_0@toc@ha
; CHECK-P8-NEXT: addi r3, r3, .LCPI21_0@toc@l ; CHECK-P8-NEXT: addi r3, r3, .LCPI21_0@toc@l
; CHECK-P8-NEXT: lvx v3, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: xxswapd v3, vs0
; CHECK-P8-NEXT: vperm v2, v2, v2, v3 ; CHECK-P8-NEXT: vperm v2, v2, v2, v3
; CHECK-P8-NEXT: stvx v2, 0, r7 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: stxvd2x vs0, 0, r7
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: swap_store50: ; CHECK-P9-LABEL: swap_store50:
; CHECK-P9: # %bb.0: ; CHECK-P9: # %bb.0:
; CHECK-P9-NEXT: stxvw4x v2, 0, r7 ; CHECK-P9-NEXT: stxvw4x v2, 0, r7
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-P8-BE-LABEL: swap_store50: ; CHECK-P8-BE-LABEL: swap_store50:
Show All 18 Lines; CHECK-P9-BE-NEXT: blr
ret void ret void
} }
define void @swap_store51(<4 x float> %v1, <4 x float> %v2, <4 x float>* %vp) { define void @swap_store51(<4 x float> %v1, <4 x float> %v2, <4 x float>* %vp) {
; CHECK-P8-LABEL: swap_store51: ; CHECK-P8-LABEL: swap_store51:
; CHECK-P8: # %bb.0: ; CHECK-P8: # %bb.0:
; CHECK-P8-NEXT: addis r3, r2, .LCPI22_0@toc@ha ; CHECK-P8-NEXT: addis r3, r2, .LCPI22_0@toc@ha
; CHECK-P8-NEXT: addi r3, r3, .LCPI22_0@toc@l ; CHECK-P8-NEXT: addi r3, r3, .LCPI22_0@toc@l
; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: vperm v2, v3, v3, v2 ; CHECK-P8-NEXT: vperm v2, v3, v3, v2
; CHECK-P8-NEXT: stvx v2, 0, r7 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: stxvd2x vs0, 0, r7
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: swap_store51: ; CHECK-P9-LABEL: swap_store51:
; CHECK-P9: # %bb.0: ; CHECK-P9: # %bb.0:
; CHECK-P9-NEXT: stxvw4x v3, 0, r7 ; CHECK-P9-NEXT: stxvw4x v3, 0, r7
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-P8-BE-LABEL: swap_store51: ; CHECK-P8-BE-LABEL: swap_store51:
Show All 20 Lines

llvm/test/CodeGen/PowerPC/mma-acc-memops.ll

Show First 20 Lines • Show All 294 Lines • ▼ Show 20 Lines
; LE-PWR9-NEXT: stxvx vs1, r3, r4 ; LE-PWR9-NEXT: stxvx vs1, r3, r4
; LE-PWR9-NEXT: li r4, 19 ; LE-PWR9-NEXT: li r4, 19
; LE-PWR9-NEXT: stxvx vs0, r3, r4 ; LE-PWR9-NEXT: stxvx vs0, r3, r4
; LE-PWR9-NEXT: blr ; LE-PWR9-NEXT: blr
; ;
; LE-PWR8-LABEL: testUnalignedLdSt: ; LE-PWR8-LABEL: testUnalignedLdSt:
; LE-PWR8: # %bb.0: # %entry ; LE-PWR8: # %bb.0: # %entry
; LE-PWR8-NEXT: addis r3, r2, f@toc@ha ; LE-PWR8-NEXT: addis r3, r2, f@toc@ha
; LE-PWR8-NEXT: li r4, 59 ; LE-PWR8-NEXT: li r4, 43
; LE-PWR8-NEXT: li r5, 43 ; LE-PWR8-NEXT: li r5, 59
; LE-PWR8-NEXT: addi r3, r3, f@toc@l ; LE-PWR8-NEXT: addi r3, r3, f@toc@l
; LE-PWR8-NEXT: lxvd2x vs0, r3, r4 ; LE-PWR8-NEXT: lxvd2x vs0, r3, r4
; LE-PWR8-NEXT: li r4, 11 ; LE-PWR8-NEXT: li r4, 11
; LE-PWR8-NEXT: lxvd2x vs1, r3, r5 ; LE-PWR8-NEXT: lxvd2x vs1, r3, r5
; LE-PWR8-NEXT: li r5, 27 ; LE-PWR8-NEXT: li r5, 27
; LE-PWR8-NEXT: lxvd2x vs2, r3, r4 ; LE-PWR8-NEXT: lxvd2x vs2, r3, r4
; LE-PWR8-NEXT: lxvd2x vs3, r3, r5 ; LE-PWR8-NEXT: lxvd2x vs3, r3, r5
; LE-PWR8-NEXT: li r4, 51 ; LE-PWR8-NEXT: li r4, 67
; LE-PWR8-NEXT: li r5, 67 ; LE-PWR8-NEXT: li r5, 51
; LE-PWR8-NEXT: stxvd2x vs1, r3, r4 ; LE-PWR8-NEXT: stxvd2x vs1, r3, r4
; LE-PWR8-NEXT: li r4, 35 ; LE-PWR8-NEXT: li r4, 35
; LE-PWR8-NEXT: stxvd2x vs0, r3, r5 ; LE-PWR8-NEXT: stxvd2x vs0, r3, r5
; LE-PWR8-NEXT: li r5, 19 ; LE-PWR8-NEXT: li r5, 19
; LE-PWR8-NEXT: stxvd2x vs3, r3, r4 ; LE-PWR8-NEXT: stxvd2x vs3, r3, r4
; LE-PWR8-NEXT: stxvd2x vs2, r3, r5 ; LE-PWR8-NEXT: stxvd2x vs2, r3, r5
; LE-PWR8-NEXT: blr ; LE-PWR8-NEXT: blr
; ;
▲ Show 20 Lines • Show All 249 Lines • ▼ Show 20 Lines
; LE-PWR9-NEXT: stxvx vs1, r3, r4 ; LE-PWR9-NEXT: stxvx vs1, r3, r4
; LE-PWR9-NEXT: li r4, 19 ; LE-PWR9-NEXT: li r4, 19
; LE-PWR9-NEXT: stxvx vs0, r3, r4 ; LE-PWR9-NEXT: stxvx vs0, r3, r4
; LE-PWR9-NEXT: blr ; LE-PWR9-NEXT: blr
; ;
; LE-PWR8-LABEL: testUnalignedLdStPair: ; LE-PWR8-LABEL: testUnalignedLdStPair:
; LE-PWR8: # %bb.0: # %entry ; LE-PWR8: # %bb.0: # %entry
; LE-PWR8-NEXT: addis r3, r2, g@toc@ha ; LE-PWR8-NEXT: addis r3, r2, g@toc@ha
; LE-PWR8-NEXT: li r4, 27 ; LE-PWR8-NEXT: li r4, 11
; LE-PWR8-NEXT: li r5, 11 ; LE-PWR8-NEXT: li r5, 27
; LE-PWR8-NEXT: li r6, 19
; LE-PWR8-NEXT: li r8, 35
; LE-PWR8-NEXT: addi r3, r3, g@toc@l ; LE-PWR8-NEXT: addi r3, r3, g@toc@l
; LE-PWR8-NEXT: lxvd2x vs0, r3, r4 ; LE-PWR8-NEXT: lxvd2x vs0, r3, r4
; LE-PWR8-NEXT: ldx r5, r3, r5 ; LE-PWR8-NEXT: lxvd2x vs1, r3, r5
; LE-PWR8-NEXT: ldx r7, r3, r6 ; LE-PWR8-NEXT: li r4, 35
; LE-PWR8-NEXT: stdx r7, r3, r4 ; LE-PWR8-NEXT: li r5, 19
; LE-PWR8-NEXT: stdx r5, r3, r6 ; LE-PWR8-NEXT: stxvd2x vs1, r3, r4
; LE-PWR8-NEXT: stxvd2x vs0, r3, r8 ; LE-PWR8-NEXT: stxvd2x vs0, r3, r5
; LE-PWR8-NEXT: blr ; LE-PWR8-NEXT: blr
; ;
; BE-PWR9-LABEL: testUnalignedLdStPair: ; BE-PWR9-LABEL: testUnalignedLdStPair:
; BE-PWR9: # %bb.0: # %entry ; BE-PWR9: # %bb.0: # %entry
; BE-PWR9-NEXT: addis r3, r2, g@toc@ha ; BE-PWR9-NEXT: addis r3, r2, g@toc@ha
; BE-PWR9-NEXT: li r4, 11 ; BE-PWR9-NEXT: li r4, 11
; BE-PWR9-NEXT: addi r3, r3, g@toc@l ; BE-PWR9-NEXT: addi r3, r3, g@toc@l
; BE-PWR9-NEXT: lxvx vs0, r3, r4 ; BE-PWR9-NEXT: lxvx vs0, r3, r4
Show All 31 Lines

llvm/test/CodeGen/PowerPC/non-debug-mi-search-frspxsrsp.ll

Show All 24 Lines
; CHECK-NEXT: xxlxor 2, 2, 2 ; CHECK-NEXT: xxlxor 2, 2, 2
; CHECK-NEXT: .loc 1 3 26 is_stmt 1 ; CHECK-NEXT: .loc 1 3 26 is_stmt 1
; CHECK-NEXT: xxmrghd 0, 0, 2 ; CHECK-NEXT: xxmrghd 0, 0, 2
; CHECK-NEXT: xxmrghd 1, 2, 1 ; CHECK-NEXT: xxmrghd 1, 2, 1
; CHECK-NEXT: xvcvdpsp 34, 0 ; CHECK-NEXT: xvcvdpsp 34, 0
; CHECK-NEXT: xvcvdpsp 35, 1 ; CHECK-NEXT: xvcvdpsp 35, 1
; CHECK-NEXT: vmrgew 2, 2, 3 ; CHECK-NEXT: vmrgew 2, 2, 3
; CHECK-NEXT: .loc 1 3 9 is_stmt 0 ; CHECK-NEXT: .loc 1 3 9 is_stmt 0
; CHECK-NEXT: stvx 2, 0, 4 ; CHECK-NEXT: xxswapd 0, 34
; CHECK-NEXT: stxvd2x 0, 0, 4
; CHECK-NEXT: .loc 1 4 1 is_stmt 1 ; CHECK-NEXT: .loc 1 4 1 is_stmt 1
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
call void @llvm.dbg.value(metadata float* %Fptr, metadata !19, metadata !DIExpression()), !dbg !22 call void @llvm.dbg.value(metadata float* %Fptr, metadata !19, metadata !DIExpression()), !dbg !22
call void @llvm.dbg.value(metadata <4 x float>* %Vptr, metadata !20, metadata !DIExpression()), !dbg !22 call void @llvm.dbg.value(metadata <4 x float>* %Vptr, metadata !20, metadata !DIExpression()), !dbg !22
%0 = load float, float* %Fptr, align 4, !dbg !23, !tbaa !24 %0 = load float, float* %Fptr, align 4, !dbg !23, !tbaa !24
%conv = fpext float %0 to double, !dbg !28 %conv = fpext float %0 to double, !dbg !28
%sub = fsub double 1.000000e+00, %conv, !dbg !29 %sub = fsub double 1.000000e+00, %conv, !dbg !29
▲ Show 20 Lines • Show All 53 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/pcrel_ldst.ll

Show First 20 Lines • Show All 1,727 Lines • ▼ Show 20 Lines
; CHECK-P9-NEXT: addi r3, r3, GlobSt11@toc@l ; CHECK-P9-NEXT: addi r3, r3, GlobSt11@toc@l
; CHECK-P9-NEXT: stxv vs0, 0(r3) ; CHECK-P9-NEXT: stxv vs0, 0(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-P8-LE-LABEL: testGlob11PtrPlus0: ; CHECK-P8-LE-LABEL: testGlob11PtrPlus0:
; CHECK-P8-LE: # %bb.0: # %entry ; CHECK-P8-LE: # %bb.0: # %entry
; CHECK-P8-LE-NEXT: addis r3, r2, GlobLd11@toc@ha ; CHECK-P8-LE-NEXT: addis r3, r2, GlobLd11@toc@ha
; CHECK-P8-LE-NEXT: addi r3, r3, GlobLd11@toc@l ; CHECK-P8-LE-NEXT: addi r3, r3, GlobLd11@toc@l
; CHECK-P8-LE-NEXT: lvx v2, 0, r3 ; CHECK-P8-LE-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-LE-NEXT: addis r3, r2, GlobSt11@toc@ha ; CHECK-P8-LE-NEXT: addis r3, r2, GlobSt11@toc@ha
; CHECK-P8-LE-NEXT: addi r3, r3, GlobSt11@toc@l ; CHECK-P8-LE-NEXT: addi r3, r3, GlobSt11@toc@l
; CHECK-P8-LE-NEXT: stvx v2, 0, r3 ; CHECK-P8-LE-NEXT: stxvd2x vs0, 0, r3
; CHECK-P8-LE-NEXT: blr ; CHECK-P8-LE-NEXT: blr
; ;
; CHECK-P8-BE-LABEL: testGlob11PtrPlus0: ; CHECK-P8-BE-LABEL: testGlob11PtrPlus0:
; CHECK-P8-BE: # %bb.0: # %entry ; CHECK-P8-BE: # %bb.0: # %entry
; CHECK-P8-BE-NEXT: addis r3, r2, GlobLd11@toc@ha ; CHECK-P8-BE-NEXT: addis r3, r2, GlobLd11@toc@ha
; CHECK-P8-BE-NEXT: addi r3, r3, GlobLd11@toc@l ; CHECK-P8-BE-NEXT: addi r3, r3, GlobLd11@toc@l
; CHECK-P8-BE-NEXT: lxvw4x vs0, 0, r3 ; CHECK-P8-BE-NEXT: lxvw4x vs0, 0, r3
; CHECK-P8-BE-NEXT: addis r3, r2, GlobSt11@toc@ha ; CHECK-P8-BE-NEXT: addis r3, r2, GlobSt11@toc@ha
Show All 35 Lines
; CHECK-P9-NEXT: stxvx vs0, r3, r4 ; CHECK-P9-NEXT: stxvx vs0, r3, r4
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-P8-LE-LABEL: testGlob11PtrPlus3: ; CHECK-P8-LE-LABEL: testGlob11PtrPlus3:
; CHECK-P8-LE: # %bb.0: # %entry ; CHECK-P8-LE: # %bb.0: # %entry
; CHECK-P8-LE-NEXT: addis r3, r2, GlobLd11@toc@ha ; CHECK-P8-LE-NEXT: addis r3, r2, GlobLd11@toc@ha
; CHECK-P8-LE-NEXT: li r4, 3 ; CHECK-P8-LE-NEXT: li r4, 3
; CHECK-P8-LE-NEXT: addi r3, r3, GlobLd11@toc@l ; CHECK-P8-LE-NEXT: addi r3, r3, GlobLd11@toc@l
; CHECK-P8-LE-NEXT: lvx v2, r3, r4 ; CHECK-P8-LE-NEXT: lxvd2x vs0, r3, r4
; CHECK-P8-LE-NEXT: addis r3, r2, GlobSt11@toc@ha ; CHECK-P8-LE-NEXT: addis r3, r2, GlobSt11@toc@ha
; CHECK-P8-LE-NEXT: addi r3, r3, GlobSt11@toc@l ; CHECK-P8-LE-NEXT: addi r3, r3, GlobSt11@toc@l
; CHECK-P8-LE-NEXT: stvx v2, r3, r4 ; CHECK-P8-LE-NEXT: stxvd2x vs0, r3, r4
; CHECK-P8-LE-NEXT: blr ; CHECK-P8-LE-NEXT: blr
; ;
; CHECK-P8-BE-LABEL: testGlob11PtrPlus3: ; CHECK-P8-BE-LABEL: testGlob11PtrPlus3:
; CHECK-P8-BE: # %bb.0: # %entry ; CHECK-P8-BE: # %bb.0: # %entry
; CHECK-P8-BE-NEXT: addis r3, r2, GlobLd11@toc@ha ; CHECK-P8-BE-NEXT: addis r3, r2, GlobLd11@toc@ha
; CHECK-P8-BE-NEXT: li r4, 3 ; CHECK-P8-BE-NEXT: li r4, 3
; CHECK-P8-BE-NEXT: addi r3, r3, GlobLd11@toc@l ; CHECK-P8-BE-NEXT: addi r3, r3, GlobLd11@toc@l
; CHECK-P8-BE-NEXT: lxvw4x vs0, r3, r4 ; CHECK-P8-BE-NEXT: lxvw4x vs0, r3, r4
Show All 36 Lines
; CHECK-P9-NEXT: stxvx vs0, r3, r4 ; CHECK-P9-NEXT: stxvx vs0, r3, r4
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-P8-LE-LABEL: testGlob11PtrPlus4: ; CHECK-P8-LE-LABEL: testGlob11PtrPlus4:
; CHECK-P8-LE: # %bb.0: # %entry ; CHECK-P8-LE: # %bb.0: # %entry
; CHECK-P8-LE-NEXT: addis r3, r2, GlobLd11@toc@ha ; CHECK-P8-LE-NEXT: addis r3, r2, GlobLd11@toc@ha
; CHECK-P8-LE-NEXT: li r4, 4 ; CHECK-P8-LE-NEXT: li r4, 4
; CHECK-P8-LE-NEXT: addi r3, r3, GlobLd11@toc@l ; CHECK-P8-LE-NEXT: addi r3, r3, GlobLd11@toc@l
; CHECK-P8-LE-NEXT: lvx v2, r3, r4 ; CHECK-P8-LE-NEXT: lxvd2x vs0, r3, r4
; CHECK-P8-LE-NEXT: addis r3, r2, GlobSt11@toc@ha ; CHECK-P8-LE-NEXT: addis r3, r2, GlobSt11@toc@ha
; CHECK-P8-LE-NEXT: addi r3, r3, GlobSt11@toc@l ; CHECK-P8-LE-NEXT: addi r3, r3, GlobSt11@toc@l
; CHECK-P8-LE-NEXT: stvx v2, r3, r4 ; CHECK-P8-LE-NEXT: stxvd2x vs0, r3, r4
; CHECK-P8-LE-NEXT: blr ; CHECK-P8-LE-NEXT: blr
; ;
; CHECK-P8-BE-LABEL: testGlob11PtrPlus4: ; CHECK-P8-BE-LABEL: testGlob11PtrPlus4:
; CHECK-P8-BE: # %bb.0: # %entry ; CHECK-P8-BE: # %bb.0: # %entry
; CHECK-P8-BE-NEXT: addis r3, r2, GlobLd11@toc@ha ; CHECK-P8-BE-NEXT: addis r3, r2, GlobLd11@toc@ha
; CHECK-P8-BE-NEXT: li r4, 4 ; CHECK-P8-BE-NEXT: li r4, 4
; CHECK-P8-BE-NEXT: addi r3, r3, GlobLd11@toc@l ; CHECK-P8-BE-NEXT: addi r3, r3, GlobLd11@toc@l
; CHECK-P8-BE-NEXT: lxvw4x vs0, r3, r4 ; CHECK-P8-BE-NEXT: lxvw4x vs0, r3, r4
Show All 35 Lines
; CHECK-P9-NEXT: stxv vs0, 16(r3) ; CHECK-P9-NEXT: stxv vs0, 16(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-P8-LE-LABEL: testGlob11PtrPlus16: ; CHECK-P8-LE-LABEL: testGlob11PtrPlus16:
; CHECK-P8-LE: # %bb.0: # %entry ; CHECK-P8-LE: # %bb.0: # %entry
; CHECK-P8-LE-NEXT: addis r3, r2, GlobLd11@toc@ha ; CHECK-P8-LE-NEXT: addis r3, r2, GlobLd11@toc@ha
; CHECK-P8-LE-NEXT: li r4, 16 ; CHECK-P8-LE-NEXT: li r4, 16
; CHECK-P8-LE-NEXT: addi r3, r3, GlobLd11@toc@l ; CHECK-P8-LE-NEXT: addi r3, r3, GlobLd11@toc@l
; CHECK-P8-LE-NEXT: lvx v2, r3, r4 ; CHECK-P8-LE-NEXT: lxvd2x vs0, r3, r4
; CHECK-P8-LE-NEXT: addis r3, r2, GlobSt11@toc@ha ; CHECK-P8-LE-NEXT: addis r3, r2, GlobSt11@toc@ha
; CHECK-P8-LE-NEXT: addi r3, r3, GlobSt11@toc@l ; CHECK-P8-LE-NEXT: addi r3, r3, GlobSt11@toc@l
; CHECK-P8-LE-NEXT: stvx v2, r3, r4 ; CHECK-P8-LE-NEXT: stxvd2x vs0, r3, r4
; CHECK-P8-LE-NEXT: blr ; CHECK-P8-LE-NEXT: blr
; ;
; CHECK-P8-BE-LABEL: testGlob11PtrPlus16: ; CHECK-P8-BE-LABEL: testGlob11PtrPlus16:
; CHECK-P8-BE: # %bb.0: # %entry ; CHECK-P8-BE: # %bb.0: # %entry
; CHECK-P8-BE-NEXT: addis r3, r2, GlobLd11@toc@ha ; CHECK-P8-BE-NEXT: addis r3, r2, GlobLd11@toc@ha
; CHECK-P8-BE-NEXT: li r4, 16 ; CHECK-P8-BE-NEXT: li r4, 16
; CHECK-P8-BE-NEXT: addi r3, r3, GlobLd11@toc@l ; CHECK-P8-BE-NEXT: addi r3, r3, GlobLd11@toc@l
; CHECK-P8-BE-NEXT: lxvw4x vs0, r3, r4 ; CHECK-P8-BE-NEXT: lxvw4x vs0, r3, r4
Show All 40 Lines
; CHECK-P9-NEXT: stxvx vs0, r4, r3 ; CHECK-P9-NEXT: stxvx vs0, r4, r3
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-P8-LE-LABEL: testGlob11PtrPlusVar: ; CHECK-P8-LE-LABEL: testGlob11PtrPlusVar:
; CHECK-P8-LE: # %bb.0: # %entry ; CHECK-P8-LE: # %bb.0: # %entry
; CHECK-P8-LE-NEXT: addis r4, r2, GlobLd11@toc@ha ; CHECK-P8-LE-NEXT: addis r4, r2, GlobLd11@toc@ha
; CHECK-P8-LE-NEXT: sldi r3, r3, 4 ; CHECK-P8-LE-NEXT: sldi r3, r3, 4
; CHECK-P8-LE-NEXT: addi r4, r4, GlobLd11@toc@l ; CHECK-P8-LE-NEXT: addi r4, r4, GlobLd11@toc@l
; CHECK-P8-LE-NEXT: lvx v2, r4, r3 ; CHECK-P8-LE-NEXT: lxvd2x vs0, r4, r3
; CHECK-P8-LE-NEXT: addis r4, r2, GlobSt11@toc@ha ; CHECK-P8-LE-NEXT: addis r4, r2, GlobSt11@toc@ha
; CHECK-P8-LE-NEXT: addi r4, r4, GlobSt11@toc@l ; CHECK-P8-LE-NEXT: addi r4, r4, GlobSt11@toc@l
; CHECK-P8-LE-NEXT: stvx v2, r4, r3 ; CHECK-P8-LE-NEXT: stxvd2x vs0, r4, r3
; CHECK-P8-LE-NEXT: blr ; CHECK-P8-LE-NEXT: blr
; ;
; CHECK-P8-BE-LABEL: testGlob11PtrPlusVar: ; CHECK-P8-BE-LABEL: testGlob11PtrPlusVar:
; CHECK-P8-BE: # %bb.0: # %entry ; CHECK-P8-BE: # %bb.0: # %entry
; CHECK-P8-BE-NEXT: addis r4, r2, GlobLd11@toc@ha ; CHECK-P8-BE-NEXT: addis r4, r2, GlobLd11@toc@ha
; CHECK-P8-BE-NEXT: sldi r3, r3, 4 ; CHECK-P8-BE-NEXT: sldi r3, r3, 4
; CHECK-P8-BE-NEXT: addi r4, r4, GlobLd11@toc@l ; CHECK-P8-BE-NEXT: addi r4, r4, GlobLd11@toc@l
; CHECK-P8-BE-NEXT: lxvw4x vs0, r4, r3 ; CHECK-P8-BE-NEXT: lxvw4x vs0, r4, r3
Show All 36 Lines
; CHECK-P9-NEXT: addi r3, r3, GlobSt12@toc@l ; CHECK-P9-NEXT: addi r3, r3, GlobSt12@toc@l
; CHECK-P9-NEXT: stxv vs0, 0(r3) ; CHECK-P9-NEXT: stxv vs0, 0(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-P8-LE-LABEL: testGlob12PtrPlus0: ; CHECK-P8-LE-LABEL: testGlob12PtrPlus0:
; CHECK-P8-LE: # %bb.0: # %entry ; CHECK-P8-LE: # %bb.0: # %entry
; CHECK-P8-LE-NEXT: addis r3, r2, GlobLd12@toc@ha ; CHECK-P8-LE-NEXT: addis r3, r2, GlobLd12@toc@ha
; CHECK-P8-LE-NEXT: addi r3, r3, GlobLd12@toc@l ; CHECK-P8-LE-NEXT: addi r3, r3, GlobLd12@toc@l
; CHECK-P8-LE-NEXT: lvx v2, 0, r3 ; CHECK-P8-LE-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-LE-NEXT: addis r3, r2, GlobSt12@toc@ha ; CHECK-P8-LE-NEXT: addis r3, r2, GlobSt12@toc@ha
; CHECK-P8-LE-NEXT: addi r3, r3, GlobSt12@toc@l ; CHECK-P8-LE-NEXT: addi r3, r3, GlobSt12@toc@l
; CHECK-P8-LE-NEXT: stvx v2, 0, r3 ; CHECK-P8-LE-NEXT: stxvd2x vs0, 0, r3
; CHECK-P8-LE-NEXT: blr ; CHECK-P8-LE-NEXT: blr
; ;
; CHECK-P8-BE-LABEL: testGlob12PtrPlus0: ; CHECK-P8-BE-LABEL: testGlob12PtrPlus0:
; CHECK-P8-BE: # %bb.0: # %entry ; CHECK-P8-BE: # %bb.0: # %entry
; CHECK-P8-BE-NEXT: addis r3, r2, GlobLd12@toc@ha ; CHECK-P8-BE-NEXT: addis r3, r2, GlobLd12@toc@ha
; CHECK-P8-BE-NEXT: addi r3, r3, GlobLd12@toc@l ; CHECK-P8-BE-NEXT: addi r3, r3, GlobLd12@toc@l
; CHECK-P8-BE-NEXT: lxvw4x vs0, 0, r3 ; CHECK-P8-BE-NEXT: lxvw4x vs0, 0, r3
; CHECK-P8-BE-NEXT: addis r3, r2, GlobSt12@toc@ha ; CHECK-P8-BE-NEXT: addis r3, r2, GlobSt12@toc@ha
Show All 35 Lines
; CHECK-P9-NEXT: stxvx vs0, r3, r4 ; CHECK-P9-NEXT: stxvx vs0, r3, r4
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-P8-LE-LABEL: testGlob12PtrPlus3: ; CHECK-P8-LE-LABEL: testGlob12PtrPlus3:
; CHECK-P8-LE: # %bb.0: # %entry ; CHECK-P8-LE: # %bb.0: # %entry
; CHECK-P8-LE-NEXT: addis r3, r2, GlobLd12@toc@ha ; CHECK-P8-LE-NEXT: addis r3, r2, GlobLd12@toc@ha
; CHECK-P8-LE-NEXT: li r4, 3 ; CHECK-P8-LE-NEXT: li r4, 3
; CHECK-P8-LE-NEXT: addi r3, r3, GlobLd12@toc@l ; CHECK-P8-LE-NEXT: addi r3, r3, GlobLd12@toc@l
; CHECK-P8-LE-NEXT: lvx v2, r3, r4 ; CHECK-P8-LE-NEXT: lxvd2x vs0, r3, r4
; CHECK-P8-LE-NEXT: addis r3, r2, GlobSt12@toc@ha ; CHECK-P8-LE-NEXT: addis r3, r2, GlobSt12@toc@ha
; CHECK-P8-LE-NEXT: addi r3, r3, GlobSt12@toc@l ; CHECK-P8-LE-NEXT: addi r3, r3, GlobSt12@toc@l
; CHECK-P8-LE-NEXT: stvx v2, r3, r4 ; CHECK-P8-LE-NEXT: stxvd2x vs0, r3, r4
; CHECK-P8-LE-NEXT: blr ; CHECK-P8-LE-NEXT: blr
; ;
; CHECK-P8-BE-LABEL: testGlob12PtrPlus3: ; CHECK-P8-BE-LABEL: testGlob12PtrPlus3:
; CHECK-P8-BE: # %bb.0: # %entry ; CHECK-P8-BE: # %bb.0: # %entry
; CHECK-P8-BE-NEXT: addis r3, r2, GlobLd12@toc@ha ; CHECK-P8-BE-NEXT: addis r3, r2, GlobLd12@toc@ha
; CHECK-P8-BE-NEXT: li r4, 3 ; CHECK-P8-BE-NEXT: li r4, 3
; CHECK-P8-BE-NEXT: addi r3, r3, GlobLd12@toc@l ; CHECK-P8-BE-NEXT: addi r3, r3, GlobLd12@toc@l
; CHECK-P8-BE-NEXT: lxvw4x vs0, r3, r4 ; CHECK-P8-BE-NEXT: lxvw4x vs0, r3, r4
Show All 36 Lines
; CHECK-P9-NEXT: stxvx vs0, r3, r4 ; CHECK-P9-NEXT: stxvx vs0, r3, r4
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-P8-LE-LABEL: testGlob12PtrPlus4: ; CHECK-P8-LE-LABEL: testGlob12PtrPlus4:
; CHECK-P8-LE: # %bb.0: # %entry ; CHECK-P8-LE: # %bb.0: # %entry
; CHECK-P8-LE-NEXT: addis r3, r2, GlobLd12@toc@ha ; CHECK-P8-LE-NEXT: addis r3, r2, GlobLd12@toc@ha
; CHECK-P8-LE-NEXT: li r4, 4 ; CHECK-P8-LE-NEXT: li r4, 4
; CHECK-P8-LE-NEXT: addi r3, r3, GlobLd12@toc@l ; CHECK-P8-LE-NEXT: addi r3, r3, GlobLd12@toc@l
; CHECK-P8-LE-NEXT: lvx v2, r3, r4 ; CHECK-P8-LE-NEXT: lxvd2x vs0, r3, r4
; CHECK-P8-LE-NEXT: addis r3, r2, GlobSt12@toc@ha ; CHECK-P8-LE-NEXT: addis r3, r2, GlobSt12@toc@ha
; CHECK-P8-LE-NEXT: addi r3, r3, GlobSt12@toc@l ; CHECK-P8-LE-NEXT: addi r3, r3, GlobSt12@toc@l
; CHECK-P8-LE-NEXT: stvx v2, r3, r4 ; CHECK-P8-LE-NEXT: stxvd2x vs0, r3, r4
; CHECK-P8-LE-NEXT: blr ; CHECK-P8-LE-NEXT: blr
; ;
; CHECK-P8-BE-LABEL: testGlob12PtrPlus4: ; CHECK-P8-BE-LABEL: testGlob12PtrPlus4:
; CHECK-P8-BE: # %bb.0: # %entry ; CHECK-P8-BE: # %bb.0: # %entry
; CHECK-P8-BE-NEXT: addis r3, r2, GlobLd12@toc@ha ; CHECK-P8-BE-NEXT: addis r3, r2, GlobLd12@toc@ha
; CHECK-P8-BE-NEXT: li r4, 4 ; CHECK-P8-BE-NEXT: li r4, 4
; CHECK-P8-BE-NEXT: addi r3, r3, GlobLd12@toc@l ; CHECK-P8-BE-NEXT: addi r3, r3, GlobLd12@toc@l
; CHECK-P8-BE-NEXT: lxvw4x vs0, r3, r4 ; CHECK-P8-BE-NEXT: lxvw4x vs0, r3, r4
Show All 35 Lines
; CHECK-P9-NEXT: stxv vs0, 16(r3) ; CHECK-P9-NEXT: stxv vs0, 16(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-P8-LE-LABEL: testGlob12PtrPlus16: ; CHECK-P8-LE-LABEL: testGlob12PtrPlus16:
; CHECK-P8-LE: # %bb.0: # %entry ; CHECK-P8-LE: # %bb.0: # %entry
; CHECK-P8-LE-NEXT: addis r3, r2, GlobLd12@toc@ha ; CHECK-P8-LE-NEXT: addis r3, r2, GlobLd12@toc@ha
; CHECK-P8-LE-NEXT: li r4, 16 ; CHECK-P8-LE-NEXT: li r4, 16
; CHECK-P8-LE-NEXT: addi r3, r3, GlobLd12@toc@l ; CHECK-P8-LE-NEXT: addi r3, r3, GlobLd12@toc@l
; CHECK-P8-LE-NEXT: lvx v2, r3, r4 ; CHECK-P8-LE-NEXT: lxvd2x vs0, r3, r4
; CHECK-P8-LE-NEXT: addis r3, r2, GlobSt12@toc@ha ; CHECK-P8-LE-NEXT: addis r3, r2, GlobSt12@toc@ha
; CHECK-P8-LE-NEXT: addi r3, r3, GlobSt12@toc@l ; CHECK-P8-LE-NEXT: addi r3, r3, GlobSt12@toc@l
; CHECK-P8-LE-NEXT: stvx v2, r3, r4 ; CHECK-P8-LE-NEXT: stxvd2x vs0, r3, r4
; CHECK-P8-LE-NEXT: blr ; CHECK-P8-LE-NEXT: blr
; ;
; CHECK-P8-BE-LABEL: testGlob12PtrPlus16: ; CHECK-P8-BE-LABEL: testGlob12PtrPlus16:
; CHECK-P8-BE: # %bb.0: # %entry ; CHECK-P8-BE: # %bb.0: # %entry
; CHECK-P8-BE-NEXT: addis r3, r2, GlobLd12@toc@ha ; CHECK-P8-BE-NEXT: addis r3, r2, GlobLd12@toc@ha
; CHECK-P8-BE-NEXT: li r4, 16 ; CHECK-P8-BE-NEXT: li r4, 16
; CHECK-P8-BE-NEXT: addi r3, r3, GlobLd12@toc@l ; CHECK-P8-BE-NEXT: addi r3, r3, GlobLd12@toc@l
; CHECK-P8-BE-NEXT: lxvw4x vs0, r3, r4 ; CHECK-P8-BE-NEXT: lxvw4x vs0, r3, r4
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; CHECK-P9-NEXT: stxvx vs0, r4, r3 ; CHECK-P9-NEXT: stxvx vs0, r4, r3
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-P8-LE-LABEL: testGlob12PtrPlusVar: ; CHECK-P8-LE-LABEL: testGlob12PtrPlusVar:
; CHECK-P8-LE: # %bb.0: # %entry ; CHECK-P8-LE: # %bb.0: # %entry
; CHECK-P8-LE-NEXT: addis r4, r2, GlobLd12@toc@ha ; CHECK-P8-LE-NEXT: addis r4, r2, GlobLd12@toc@ha
; CHECK-P8-LE-NEXT: sldi r3, r3, 4 ; CHECK-P8-LE-NEXT: sldi r3, r3, 4
; CHECK-P8-LE-NEXT: addi r4, r4, GlobLd12@toc@l ; CHECK-P8-LE-NEXT: addi r4, r4, GlobLd12@toc@l
; CHECK-P8-LE-NEXT: lvx v2, r4, r3 ; CHECK-P8-LE-NEXT: lxvd2x vs0, r4, r3
; CHECK-P8-LE-NEXT: addis r4, r2, GlobSt12@toc@ha ; CHECK-P8-LE-NEXT: addis r4, r2, GlobSt12@toc@ha
; CHECK-P8-LE-NEXT: addi r4, r4, GlobSt12@toc@l ; CHECK-P8-LE-NEXT: addi r4, r4, GlobSt12@toc@l
; CHECK-P8-LE-NEXT: stvx v2, r4, r3 ; CHECK-P8-LE-NEXT: stxvd2x vs0, r4, r3
; CHECK-P8-LE-NEXT: blr ; CHECK-P8-LE-NEXT: blr
; ;
; CHECK-P8-BE-LABEL: testGlob12PtrPlusVar: ; CHECK-P8-BE-LABEL: testGlob12PtrPlusVar:
; CHECK-P8-BE: # %bb.0: # %entry ; CHECK-P8-BE: # %bb.0: # %entry
; CHECK-P8-BE-NEXT: addis r4, r2, GlobLd12@toc@ha ; CHECK-P8-BE-NEXT: addis r4, r2, GlobLd12@toc@ha
; CHECK-P8-BE-NEXT: sldi r3, r3, 4 ; CHECK-P8-BE-NEXT: sldi r3, r3, 4
; CHECK-P8-BE-NEXT: addi r4, r4, GlobLd12@toc@l ; CHECK-P8-BE-NEXT: addi r4, r4, GlobLd12@toc@l
; CHECK-P8-BE-NEXT: lxvw4x vs0, r4, r3 ; CHECK-P8-BE-NEXT: lxvw4x vs0, r4, r3
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llvm/test/CodeGen/PowerPC/ppc64-i128-abi.ll

Show First 20 Lines • Show All 211 Lines • ▼ Show 20 Lines
; callee. See comments for individual functions above for details on registers ; callee. See comments for individual functions above for details on registers
; used for parameters. ; used for parameters.
define <1 x i128> @call_v1i128_increment_by_one() nounwind { define <1 x i128> @call_v1i128_increment_by_one() nounwind {
%tmp = load <1 x i128>, <1 x i128>* @x, align 16 %tmp = load <1 x i128>, <1 x i128>* @x, align 16
%ret = call <1 x i128> @v1i128_increment_by_one(<1 x i128> %tmp) %ret = call <1 x i128> @v1i128_increment_by_one(<1 x i128> %tmp)
ret <1 x i128> %ret ret <1 x i128> %ret
; CHECK-LE-LABEL: @call_v1i128_increment_by_one ; CHECK-LE-LABEL: @call_v1i128_increment_by_one
; CHECK-LE: lvx 2, {{[0-9]+}}, {{[0-9]+}} ; CHECK-LE: lxvd2x [[VAL:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
; CHECK-LE: xxswapd 34, [[VAL]]
; CHECK-LE: bl v1i128_increment_by_one ; CHECK-LE: bl v1i128_increment_by_one
; CHECK-LE: blr ; CHECK-LE: blr
; CHECK-P9-LABEL: @call_v1i128_increment_by_one ; CHECK-P9-LABEL: @call_v1i128_increment_by_one
; CHECK-P9: lxv ; CHECK-P9: lxv
; CHECK-P9: bl {{.?}}v1i128_increment_by_one ; CHECK-P9: bl {{.?}}v1i128_increment_by_one
; CHECK-P9: blr ; CHECK-P9: blr
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define <1 x i128> @call_v1i128_increment_by_val() nounwind { define <1 x i128> @call_v1i128_increment_by_val() nounwind {
%tmp = load <1 x i128>, <1 x i128>* @x, align 16 %tmp = load <1 x i128>, <1 x i128>* @x, align 16
%tmp2 = load <1 x i128>, <1 x i128>* @y, align 16 %tmp2 = load <1 x i128>, <1 x i128>* @y, align 16
%ret = call <1 x i128> @v1i128_increment_by_val(<1 x i128> %tmp, <1 x i128> %tmp2) %ret = call <1 x i128> @v1i128_increment_by_val(<1 x i128> %tmp, <1 x i128> %tmp2)
ret <1 x i128> %ret ret <1 x i128> %ret
; CHECK-LE-LABEL: @call_v1i128_increment_by_val ; CHECK-LE-LABEL: @call_v1i128_increment_by_val
; CHECK-LE: lvx 2, {{[0-9]+}}, {{[0-9]+}} ; CHECK-LE: lxvd2x [[VAL1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
; CHECK-LE: lvx 3, {{[0-9]+}}, {{[0-9]+}} ; CHECK-LE-DAG: lxvd2x [[VAL2:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
; CHECK-LE-DAG: xxswapd 34, [[VAL1]]
; CHECK-LE: xxswapd 35, [[VAL2]]
; CHECK-LE: bl v1i128_increment_by_val ; CHECK-LE: bl v1i128_increment_by_val
; CHECK-LE: blr ; CHECK-LE: blr
; CHECK-P9-LABEL: @call_v1i128_increment_by_val ; CHECK-P9-LABEL: @call_v1i128_increment_by_val
; CHECK-P9-DAG: lxv v2 ; CHECK-P9-DAG: lxv v2
; CHECK-P9-DAG: lxv v3 ; CHECK-P9-DAG: lxv v3
; CHECK-P9: bl {{.?}}v1i128_increment_by_val ; CHECK-P9: bl {{.?}}v1i128_increment_by_val
; CHECK-P9: blr ; CHECK-P9: blr
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llvm/test/CodeGen/PowerPC/pr25080.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-- -mcpu=pwr8 < %s | FileCheck %s --check-prefix=LE ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-- -mcpu=pwr8 < %s | FileCheck %s --check-prefix=LE
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-- -mcpu=pwr8 < %s | FileCheck %s --check-prefix=BE ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-- -mcpu=pwr8 < %s | FileCheck %s --check-prefix=BE
define <8 x i16> @pr25080(<8 x i32> %a) { define <8 x i16> @pr25080(<8 x i32> %a) {
; LE-LABEL: pr25080: ; LE-LABEL: pr25080:
; LE: # %bb.0: # %entry ; LE: # %bb.0: # %entry
; LE-NEXT: addis 3, 2, .LCPI0_0@toc@ha ; LE-NEXT: addis 3, 2, .LCPI0_0@toc@ha
; LE-NEXT: xxlxor 37, 37, 37 ; LE-NEXT: xxlxor 37, 37, 37
; LE-NEXT: addi 3, 3, .LCPI0_0@toc@l ; LE-NEXT: addi 3, 3, .LCPI0_0@toc@l
; LE-NEXT: lvx 4, 0, 3 ; LE-NEXT: lxvd2x 0, 0, 3
; LE-NEXT: xxswapd 36, 0
; LE-NEXT: xxland 34, 34, 36 ; LE-NEXT: xxland 34, 34, 36
; LE-NEXT: xxland 35, 35, 36 ; LE-NEXT: xxland 35, 35, 36
; LE-NEXT: vcmpequw 2, 2, 5 ; LE-NEXT: vcmpequw 2, 2, 5
; LE-NEXT: vcmpequw 3, 3, 5 ; LE-NEXT: vcmpequw 3, 3, 5
; LE-NEXT: xxswapd 0, 34 ; LE-NEXT: xxswapd 0, 34
; LE-NEXT: mfvsrwz 3, 34 ; LE-NEXT: mfvsrwz 3, 34
; LE-NEXT: xxsldwi 1, 34, 34, 1 ; LE-NEXT: xxsldwi 1, 34, 34, 1
; LE-NEXT: mfvsrwz 4, 35 ; LE-NEXT: mfvsrwz 4, 35
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; LE-NEXT: mtvsrd 35, 3 ; LE-NEXT: mtvsrd 35, 3
; LE-NEXT: mffprwz 3, 0 ; LE-NEXT: mffprwz 3, 0
; LE-NEXT: vmrghh 2, 0, 2 ; LE-NEXT: vmrghh 2, 0, 2
; LE-NEXT: mtvsrd 32, 3 ; LE-NEXT: mtvsrd 32, 3
; LE-NEXT: addis 3, 2, .LCPI0_1@toc@ha ; LE-NEXT: addis 3, 2, .LCPI0_1@toc@ha
; LE-NEXT: vmrghh 4, 1, 4 ; LE-NEXT: vmrghh 4, 1, 4
; LE-NEXT: addi 3, 3, .LCPI0_1@toc@l ; LE-NEXT: addi 3, 3, .LCPI0_1@toc@l
; LE-NEXT: vmrghh 3, 3, 6 ; LE-NEXT: vmrghh 3, 3, 6
; LE-NEXT: lxvd2x 2, 0, 3
; LE-NEXT: vmrghh 5, 0, 5 ; LE-NEXT: vmrghh 5, 0, 5
; LE-NEXT: xxmrglw 0, 36, 34 ; LE-NEXT: xxmrglw 0, 36, 34
; LE-NEXT: vspltish 4, 15 ; LE-NEXT: vspltish 4, 15
; LE-NEXT: xxmrglw 1, 37, 35 ; LE-NEXT: xxmrglw 1, 37, 35
; LE-NEXT: lvx 3, 0, 3 ; LE-NEXT: xxswapd 35, 2
; LE-NEXT: xxmrgld 34, 1, 0 ; LE-NEXT: xxmrgld 34, 1, 0
; LE-NEXT: xxlor 34, 34, 35 ; LE-NEXT: xxlor 34, 34, 35
; LE-NEXT: vslh 2, 2, 4 ; LE-NEXT: vslh 2, 2, 4
; LE-NEXT: vsrah 2, 2, 4 ; LE-NEXT: vsrah 2, 2, 4
; LE-NEXT: blr ; LE-NEXT: blr
; ;
; BE-LABEL: pr25080: ; BE-LABEL: pr25080:
; BE: # %bb.0: # %entry ; BE: # %bb.0: # %entry
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llvm/test/CodeGen/PowerPC/recipest.ll

Show First 20 Lines • Show All 481 Lines • ▼ Show 20 Lines
; CHECK-P7-NEXT: blr ; CHECK-P7-NEXT: blr
; ;
; CHECK-P8-LABEL: hoo_fmf: ; CHECK-P8-LABEL: hoo_fmf:
; CHECK-P8: # %bb.0: ; CHECK-P8: # %bb.0:
; CHECK-P8-NEXT: xvrsqrtesp 0, 35 ; CHECK-P8-NEXT: xvrsqrtesp 0, 35
; CHECK-P8-NEXT: addis 3, 2, .LCPI12_0@toc@ha ; CHECK-P8-NEXT: addis 3, 2, .LCPI12_0@toc@ha
; CHECK-P8-NEXT: addis 4, 2, .LCPI12_1@toc@ha ; CHECK-P8-NEXT: addis 4, 2, .LCPI12_1@toc@ha
; CHECK-P8-NEXT: addi 3, 3, .LCPI12_0@toc@l ; CHECK-P8-NEXT: addi 3, 3, .LCPI12_0@toc@l
; CHECK-P8-NEXT: xvmulsp 1, 35, 0 ; CHECK-P8-NEXT: lxvd2x 1, 0, 3
; CHECK-P8-NEXT: lvx 3, 0, 3
; CHECK-P8-NEXT: addi 3, 4, .LCPI12_1@toc@l ; CHECK-P8-NEXT: addi 3, 4, .LCPI12_1@toc@l
; CHECK-P8-NEXT: lvx 4, 0, 3 ; CHECK-P8-NEXT: lxvd2x 3, 0, 3
; CHECK-P8-NEXT: xvmaddasp 35, 1, 0 ; CHECK-P8-NEXT: xxswapd 1, 1
; CHECK-P8-NEXT: xvmulsp 0, 0, 36 ; CHECK-P8-NEXT: xvmulsp 2, 35, 0
; CHECK-P8-NEXT: xxswapd 35, 3
; CHECK-P8-NEXT: xvmaddasp 1, 2, 0
; CHECK-P8-NEXT: xvmulsp 0, 0, 35 ; CHECK-P8-NEXT: xvmulsp 0, 0, 35
; CHECK-P8-NEXT: xvmulsp 0, 0, 1
; CHECK-P8-NEXT: xvmulsp 34, 34, 0 ; CHECK-P8-NEXT: xvmulsp 34, 34, 0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: hoo_fmf: ; CHECK-P9-LABEL: hoo_fmf:
; CHECK-P9: # %bb.0: ; CHECK-P9: # %bb.0:
; CHECK-P9-NEXT: xvrsqrtesp 0, 35 ; CHECK-P9-NEXT: xvrsqrtesp 0, 35
; CHECK-P9-NEXT: addis 3, 2, .LCPI12_0@toc@ha ; CHECK-P9-NEXT: addis 3, 2, .LCPI12_0@toc@ha
; CHECK-P9-NEXT: addi 3, 3, .LCPI12_0@toc@l ; CHECK-P9-NEXT: addi 3, 3, .LCPI12_0@toc@l
▲ Show 20 Lines • Show All 534 Lines • ▼ Show 20 Lines
; CHECK-P8: # %bb.0: ; CHECK-P8: # %bb.0:
; CHECK-P8-NEXT: xvtsqrtsp 0, 34 ; CHECK-P8-NEXT: xvtsqrtsp 0, 34
; CHECK-P8-NEXT: bc 12, 2, .LBB25_2 ; CHECK-P8-NEXT: bc 12, 2, .LBB25_2
; CHECK-P8-NEXT: # %bb.1: ; CHECK-P8-NEXT: # %bb.1:
; CHECK-P8-NEXT: xvrsqrtesp 0, 34 ; CHECK-P8-NEXT: xvrsqrtesp 0, 34
; CHECK-P8-NEXT: addis 3, 2, .LCPI25_0@toc@ha ; CHECK-P8-NEXT: addis 3, 2, .LCPI25_0@toc@ha
; CHECK-P8-NEXT: addis 4, 2, .LCPI25_1@toc@ha ; CHECK-P8-NEXT: addis 4, 2, .LCPI25_1@toc@ha
; CHECK-P8-NEXT: addi 3, 3, .LCPI25_0@toc@l ; CHECK-P8-NEXT: addi 3, 3, .LCPI25_0@toc@l
; CHECK-P8-NEXT: xvmulsp 1, 34, 0 ; CHECK-P8-NEXT: lxvd2x 1, 0, 3
; CHECK-P8-NEXT: lvx 2, 0, 3
; CHECK-P8-NEXT: addi 3, 4, .LCPI25_1@toc@l ; CHECK-P8-NEXT: addi 3, 4, .LCPI25_1@toc@l
; CHECK-P8-NEXT: lvx 3, 0, 3 ; CHECK-P8-NEXT: lxvd2x 3, 0, 3
; CHECK-P8-NEXT: xvmaddasp 34, 1, 0 ; CHECK-P8-NEXT: xxswapd 1, 1
; CHECK-P8-NEXT: xvmulsp 0, 1, 35 ; CHECK-P8-NEXT: xvmulsp 2, 34, 0
; CHECK-P8-NEXT: xvmulsp 34, 0, 34 ; CHECK-P8-NEXT: xxswapd 34, 3
; CHECK-P8-NEXT: xvmaddasp 1, 2, 0
; CHECK-P8-NEXT: xvmulsp 0, 2, 34
; CHECK-P8-NEXT: xvmulsp 34, 0, 1
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; CHECK-P8-NEXT: .LBB25_2: ; CHECK-P8-NEXT: .LBB25_2:
; CHECK-P8-NEXT: xvsqrtsp 34, 34 ; CHECK-P8-NEXT: xvsqrtsp 34, 34
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: hoo3_fmf: ; CHECK-P9-LABEL: hoo3_fmf:
; CHECK-P9: # %bb.0: ; CHECK-P9: # %bb.0:
; CHECK-P9-NEXT: xvtsqrtsp 0, 34 ; CHECK-P9-NEXT: xvtsqrtsp 0, 34
▲ Show 20 Lines • Show All 241 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/repeated-fp-divisors.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-- < %s | FileCheck %s ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-- < %s | FileCheck %s
; Check if this causes infinite loop when estimation disabled ; Check if this causes infinite loop when estimation disabled
define <4 x float> @repeated_fp_divisor_noest(float %a, <4 x float> %b) { define <4 x float> @repeated_fp_divisor_noest(float %a, <4 x float> %b) {
; CHECK-LABEL: repeated_fp_divisor_noest: ; CHECK-LABEL: repeated_fp_divisor_noest:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: xscvdpspn 0, 1 ; CHECK-NEXT: xscvdpspn 0, 1
; CHECK-NEXT: addis 3, 2, .LCPI0_1@toc@ha ; CHECK-NEXT: addis 3, 2, .LCPI0_1@toc@ha
; CHECK-NEXT: addi 3, 3, .LCPI0_1@toc@l ; CHECK-NEXT: addi 3, 3, .LCPI0_1@toc@l
; CHECK-NEXT: lvx 3, 0, 3 ; CHECK-NEXT: lxvd2x 1, 0, 3
; CHECK-NEXT: addis 3, 2, .LCPI0_0@toc@ha ; CHECK-NEXT: addis 3, 2, .LCPI0_0@toc@ha
; CHECK-NEXT: addi 3, 3, .LCPI0_0@toc@l ; CHECK-NEXT: addi 3, 3, .LCPI0_0@toc@l
; CHECK-NEXT: xxswapd 35, 1
; CHECK-NEXT: lxvd2x 1, 0, 3
; CHECK-NEXT: xxspltw 0, 0, 0 ; CHECK-NEXT: xxspltw 0, 0, 0
; CHECK-NEXT: xvdivsp 0, 35, 0 ; CHECK-NEXT: xvdivsp 0, 35, 0
; CHECK-NEXT: lvx 3, 0, 3 ; CHECK-NEXT: xxswapd 35, 1
; CHECK-NEXT: xvmulsp 1, 34, 35 ; CHECK-NEXT: xvmulsp 1, 34, 35
; CHECK-NEXT: xvmulsp 34, 1, 0 ; CHECK-NEXT: xvmulsp 34, 1, 0
; CHECK-NEXT: blr ; CHECK-NEXT: blr
%ins = insertelement <4 x float> undef, float %a, i32 0 %ins = insertelement <4 x float> undef, float %a, i32 0
%splat = shufflevector <4 x float> %ins, <4 x float> undef, <4 x i32> zeroinitializer %splat = shufflevector <4 x float> %ins, <4 x float> undef, <4 x i32> zeroinitializer
%t1 = fmul reassoc <4 x float> %b, <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 0x3FF028F5C0000000> %t1 = fmul reassoc <4 x float> %b, <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 0x3FF028F5C0000000>
%mul = fdiv reassoc arcp nsz <4 x float> %t1, %splat %mul = fdiv reassoc arcp nsz <4 x float> %t1, %splat
ret <4 x float> %mul ret <4 x float> %mul
} }
define <4 x float> @repeated_fp_divisor(float %a, <4 x float> %b) { define <4 x float> @repeated_fp_divisor(float %a, <4 x float> %b) {
; CHECK-LABEL: repeated_fp_divisor: ; CHECK-LABEL: repeated_fp_divisor:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: xscvdpspn 0, 1 ; CHECK-NEXT: xscvdpspn 0, 1
; CHECK-NEXT: addis 3, 2, .LCPI1_0@toc@ha ; CHECK-NEXT: addis 3, 2, .LCPI1_0@toc@ha
; CHECK-NEXT: addi 3, 3, .LCPI1_0@toc@l ; CHECK-NEXT: addi 3, 3, .LCPI1_0@toc@l
; CHECK-NEXT: lvx 3, 0, 3 ; CHECK-NEXT: lxvd2x 1, 0, 3
; CHECK-NEXT: addis 3, 2, .LCPI1_1@toc@ha ; CHECK-NEXT: addis 3, 2, .LCPI1_1@toc@ha
; CHECK-NEXT: addi 3, 3, .LCPI1_1@toc@l ; CHECK-NEXT: addi 3, 3, .LCPI1_1@toc@l
; CHECK-NEXT: lvx 4, 0, 3 ; CHECK-NEXT: xxswapd 1, 1
; CHECK-NEXT: xxspltw 0, 0, 0 ; CHECK-NEXT: xxspltw 0, 0, 0
; CHECK-NEXT: xvresp 1, 0 ; CHECK-NEXT: xvresp 2, 0
; CHECK-NEXT: xvmaddasp 35, 0, 1 ; CHECK-NEXT: xvmaddasp 1, 0, 2
; CHECK-NEXT: xvmulsp 0, 34, 36 ; CHECK-NEXT: lxvd2x 0, 0, 3
; CHECK-NEXT: xvnmsubasp 1, 1, 35 ; CHECK-NEXT: xxswapd 35, 0
; CHECK-NEXT: xvmulsp 34, 0, 1 ; CHECK-NEXT: xvnmsubasp 2, 2, 1
; CHECK-NEXT: xvmulsp 0, 34, 35
; CHECK-NEXT: xvmulsp 34, 0, 2
; CHECK-NEXT: blr ; CHECK-NEXT: blr
%ins = insertelement <4 x float> undef, float %a, i32 0 %ins = insertelement <4 x float> undef, float %a, i32 0
%splat = shufflevector <4 x float> %ins, <4 x float> undef, <4 x i32> zeroinitializer %splat = shufflevector <4 x float> %ins, <4 x float> undef, <4 x i32> zeroinitializer
%t1 = fmul contract reassoc <4 x float> %b, <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 0x3FF028F5C0000000> %t1 = fmul contract reassoc <4 x float> %b, <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 0x3FF028F5C0000000>
%mul = fdiv contract reassoc arcp nsz ninf <4 x float> %t1, %splat %mul = fdiv contract reassoc arcp nsz ninf <4 x float> %t1, %splat
ret <4 x float> %mul ret <4 x float> %mul
} }

llvm/test/CodeGen/PowerPC/sat-add.ll

Show First 20 Lines • Show All 373 Lines • ▼ Show 20 Lines; CHECK-NEXT: blr
ret i64 %r ret i64 %r
} }
define <16 x i8> @unsigned_sat_constant_v16i8_using_min(<16 x i8> %x) { define <16 x i8> @unsigned_sat_constant_v16i8_using_min(<16 x i8> %x) {
; CHECK-LABEL: unsigned_sat_constant_v16i8_using_min: ; CHECK-LABEL: unsigned_sat_constant_v16i8_using_min:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addis 3, 2, .LCPI24_0@toc@ha ; CHECK-NEXT: addis 3, 2, .LCPI24_0@toc@ha
; CHECK-NEXT: addi 3, 3, .LCPI24_0@toc@l ; CHECK-NEXT: addi 3, 3, .LCPI24_0@toc@l
; CHECK-NEXT: lvx 3, 0, 3 ; CHECK-NEXT: lxvd2x 0, 0, 3
; CHECK-NEXT: addis 3, 2, .LCPI24_1@toc@ha ; CHECK-NEXT: addis 3, 2, .LCPI24_1@toc@ha
; CHECK-NEXT: addi 3, 3, .LCPI24_1@toc@l ; CHECK-NEXT: addi 3, 3, .LCPI24_1@toc@l
; CHECK-NEXT: xxswapd 35, 0
; CHECK-NEXT: lxvd2x 0, 0, 3
; CHECK-NEXT: vminub 2, 2, 3 ; CHECK-NEXT: vminub 2, 2, 3
; CHECK-NEXT: lvx 3, 0, 3 ; CHECK-NEXT: xxswapd 35, 0
; CHECK-NEXT: vaddubm 2, 2, 3 ; CHECK-NEXT: vaddubm 2, 2, 3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
%c = icmp ult <16 x i8> %x, <i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43> %c = icmp ult <16 x i8> %x, <i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43>
%s = select <16 x i1> %c, <16 x i8> %x, <16 x i8> <i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43> %s = select <16 x i1> %c, <16 x i8> %x, <16 x i8> <i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43>
%r = add <16 x i8> %s, <i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42> %r = add <16 x i8> %s, <i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42>
ret <16 x i8> %r ret <16 x i8> %r
} }
define <16 x i8> @unsigned_sat_constant_v16i8_using_cmp_sum(<16 x i8> %x) { define <16 x i8> @unsigned_sat_constant_v16i8_using_cmp_sum(<16 x i8> %x) {
; CHECK-LABEL: unsigned_sat_constant_v16i8_using_cmp_sum: ; CHECK-LABEL: unsigned_sat_constant_v16i8_using_cmp_sum:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addis 3, 2, .LCPI25_0@toc@ha ; CHECK-NEXT: addis 3, 2, .LCPI25_0@toc@ha
; CHECK-NEXT: addi 3, 3, .LCPI25_0@toc@l ; CHECK-NEXT: addi 3, 3, .LCPI25_0@toc@l
; CHECK-NEXT: lvx 3, 0, 3 ; CHECK-NEXT: lxvd2x 0, 0, 3
; CHECK-NEXT: xxswapd 35, 0
; CHECK-NEXT: vaddubs 2, 2, 3 ; CHECK-NEXT: vaddubs 2, 2, 3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
%a = add <16 x i8> %x, <i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42> %a = add <16 x i8> %x, <i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42>
%c = icmp ugt <16 x i8> %x, %a %c = icmp ugt <16 x i8> %x, %a
%r = select <16 x i1> %c, <16 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>, <16 x i8> %a %r = select <16 x i1> %c, <16 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>, <16 x i8> %a
ret <16 x i8> %r ret <16 x i8> %r
} }
define <16 x i8> @unsigned_sat_constant_v16i8_using_cmp_notval(<16 x i8> %x) { define <16 x i8> @unsigned_sat_constant_v16i8_using_cmp_notval(<16 x i8> %x) {
; CHECK-LABEL: unsigned_sat_constant_v16i8_using_cmp_notval: ; CHECK-LABEL: unsigned_sat_constant_v16i8_using_cmp_notval:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addis 3, 2, .LCPI26_0@toc@ha ; CHECK-NEXT: addis 3, 2, .LCPI26_0@toc@ha
; CHECK-NEXT: addi 3, 3, .LCPI26_0@toc@l ; CHECK-NEXT: addi 3, 3, .LCPI26_0@toc@l
; CHECK-NEXT: lvx 3, 0, 3 ; CHECK-NEXT: lxvd2x 0, 0, 3
; CHECK-NEXT: xxswapd 35, 0
; CHECK-NEXT: vaddubs 2, 2, 3 ; CHECK-NEXT: vaddubs 2, 2, 3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
%a = add <16 x i8> %x, <i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42> %a = add <16 x i8> %x, <i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42>
%c = icmp ugt <16 x i8> %x, <i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43> %c = icmp ugt <16 x i8> %x, <i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43>
%r = select <16 x i1> %c, <16 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>, <16 x i8> %a %r = select <16 x i1> %c, <16 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>, <16 x i8> %a
ret <16 x i8> %r ret <16 x i8> %r
} }
define <8 x i16> @unsigned_sat_constant_v8i16_using_min(<8 x i16> %x) { define <8 x i16> @unsigned_sat_constant_v8i16_using_min(<8 x i16> %x) {
; CHECK-LABEL: unsigned_sat_constant_v8i16_using_min: ; CHECK-LABEL: unsigned_sat_constant_v8i16_using_min:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addis 3, 2, .LCPI27_0@toc@ha ; CHECK-NEXT: addis 3, 2, .LCPI27_0@toc@ha
; CHECK-NEXT: addi 3, 3, .LCPI27_0@toc@l ; CHECK-NEXT: addi 3, 3, .LCPI27_0@toc@l
; CHECK-NEXT: lvx 3, 0, 3 ; CHECK-NEXT: lxvd2x 0, 0, 3
; CHECK-NEXT: addis 3, 2, .LCPI27_1@toc@ha ; CHECK-NEXT: addis 3, 2, .LCPI27_1@toc@ha
; CHECK-NEXT: addi 3, 3, .LCPI27_1@toc@l ; CHECK-NEXT: addi 3, 3, .LCPI27_1@toc@l
; CHECK-NEXT: xxswapd 35, 0
; CHECK-NEXT: lxvd2x 0, 0, 3
; CHECK-NEXT: vminuh 2, 2, 3 ; CHECK-NEXT: vminuh 2, 2, 3
; CHECK-NEXT: lvx 3, 0, 3 ; CHECK-NEXT: xxswapd 35, 0
; CHECK-NEXT: vadduhm 2, 2, 3 ; CHECK-NEXT: vadduhm 2, 2, 3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
%c = icmp ult <8 x i16> %x, <i16 -43, i16 -43, i16 -43, i16 -43, i16 -43, i16 -43, i16 -43, i16 -43> %c = icmp ult <8 x i16> %x, <i16 -43, i16 -43, i16 -43, i16 -43, i16 -43, i16 -43, i16 -43, i16 -43>
%s = select <8 x i1> %c, <8 x i16> %x, <8 x i16> <i16 -43, i16 -43, i16 -43, i16 -43, i16 -43, i16 -43, i16 -43, i16 -43> %s = select <8 x i1> %c, <8 x i16> %x, <8 x i16> <i16 -43, i16 -43, i16 -43, i16 -43, i16 -43, i16 -43, i16 -43, i16 -43>
%r = add <8 x i16> %s, <i16 42, i16 42, i16 42, i16 42, i16 42, i16 42, i16 42, i16 42> %r = add <8 x i16> %s, <i16 42, i16 42, i16 42, i16 42, i16 42, i16 42, i16 42, i16 42>
ret <8 x i16> %r ret <8 x i16> %r
} }
define <8 x i16> @unsigned_sat_constant_v8i16_using_cmp_sum(<8 x i16> %x) { define <8 x i16> @unsigned_sat_constant_v8i16_using_cmp_sum(<8 x i16> %x) {
; CHECK-LABEL: unsigned_sat_constant_v8i16_using_cmp_sum: ; CHECK-LABEL: unsigned_sat_constant_v8i16_using_cmp_sum:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addis 3, 2, .LCPI28_0@toc@ha ; CHECK-NEXT: addis 3, 2, .LCPI28_0@toc@ha
; CHECK-NEXT: addi 3, 3, .LCPI28_0@toc@l ; CHECK-NEXT: addi 3, 3, .LCPI28_0@toc@l
; CHECK-NEXT: lvx 3, 0, 3 ; CHECK-NEXT: lxvd2x 0, 0, 3
; CHECK-NEXT: xxswapd 35, 0
; CHECK-NEXT: vadduhs 2, 2, 3 ; CHECK-NEXT: vadduhs 2, 2, 3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
%a = add <8 x i16> %x, <i16 42, i16 42, i16 42, i16 42, i16 42, i16 42, i16 42, i16 42> %a = add <8 x i16> %x, <i16 42, i16 42, i16 42, i16 42, i16 42, i16 42, i16 42, i16 42>
%c = icmp ugt <8 x i16> %x, %a %c = icmp ugt <8 x i16> %x, %a
%r = select <8 x i1> %c, <8 x i16> <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>, <8 x i16> %a %r = select <8 x i1> %c, <8 x i16> <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>, <8 x i16> %a
ret <8 x i16> %r ret <8 x i16> %r
} }
define <8 x i16> @unsigned_sat_constant_v8i16_using_cmp_notval(<8 x i16> %x) { define <8 x i16> @unsigned_sat_constant_v8i16_using_cmp_notval(<8 x i16> %x) {
; CHECK-LABEL: unsigned_sat_constant_v8i16_using_cmp_notval: ; CHECK-LABEL: unsigned_sat_constant_v8i16_using_cmp_notval:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addis 3, 2, .LCPI29_0@toc@ha ; CHECK-NEXT: addis 3, 2, .LCPI29_0@toc@ha
; CHECK-NEXT: addi 3, 3, .LCPI29_0@toc@l ; CHECK-NEXT: addi 3, 3, .LCPI29_0@toc@l
; CHECK-NEXT: lvx 3, 0, 3 ; CHECK-NEXT: lxvd2x 0, 0, 3
; CHECK-NEXT: xxswapd 35, 0
; CHECK-NEXT: vadduhs 2, 2, 3 ; CHECK-NEXT: vadduhs 2, 2, 3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
%a = add <8 x i16> %x, <i16 42, i16 42, i16 42, i16 42, i16 42, i16 42, i16 42, i16 42> %a = add <8 x i16> %x, <i16 42, i16 42, i16 42, i16 42, i16 42, i16 42, i16 42, i16 42>
%c = icmp ugt <8 x i16> %x, <i16 -43, i16 -43, i16 -43, i16 -43, i16 -43, i16 -43, i16 -43, i16 -43> %c = icmp ugt <8 x i16> %x, <i16 -43, i16 -43, i16 -43, i16 -43, i16 -43, i16 -43, i16 -43, i16 -43>
%r = select <8 x i1> %c, <8 x i16> <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>, <8 x i16> %a %r = select <8 x i1> %c, <8 x i16> <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>, <8 x i16> %a
ret <8 x i16> %r ret <8 x i16> %r
} }
define <4 x i32> @unsigned_sat_constant_v4i32_using_min(<4 x i32> %x) { define <4 x i32> @unsigned_sat_constant_v4i32_using_min(<4 x i32> %x) {
; CHECK-LABEL: unsigned_sat_constant_v4i32_using_min: ; CHECK-LABEL: unsigned_sat_constant_v4i32_using_min:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addis 3, 2, .LCPI30_0@toc@ha ; CHECK-NEXT: addis 3, 2, .LCPI30_0@toc@ha
; CHECK-NEXT: addi 3, 3, .LCPI30_0@toc@l ; CHECK-NEXT: addi 3, 3, .LCPI30_0@toc@l
; CHECK-NEXT: lvx 3, 0, 3 ; CHECK-NEXT: lxvd2x 0, 0, 3
; CHECK-NEXT: addis 3, 2, .LCPI30_1@toc@ha ; CHECK-NEXT: addis 3, 2, .LCPI30_1@toc@ha
; CHECK-NEXT: addi 3, 3, .LCPI30_1@toc@l ; CHECK-NEXT: addi 3, 3, .LCPI30_1@toc@l
; CHECK-NEXT: xxswapd 35, 0
; CHECK-NEXT: lxvd2x 0, 0, 3
; CHECK-NEXT: vminuw 2, 2, 3 ; CHECK-NEXT: vminuw 2, 2, 3
; CHECK-NEXT: lvx 3, 0, 3 ; CHECK-NEXT: xxswapd 35, 0
; CHECK-NEXT: vadduwm 2, 2, 3 ; CHECK-NEXT: vadduwm 2, 2, 3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
%c = icmp ult <4 x i32> %x, <i32 -43, i32 -43, i32 -43, i32 -43> %c = icmp ult <4 x i32> %x, <i32 -43, i32 -43, i32 -43, i32 -43>
%s = select <4 x i1> %c, <4 x i32> %x, <4 x i32> <i32 -43, i32 -43, i32 -43, i32 -43> %s = select <4 x i1> %c, <4 x i32> %x, <4 x i32> <i32 -43, i32 -43, i32 -43, i32 -43>
%r = add <4 x i32> %s, <i32 42, i32 42, i32 42, i32 42> %r = add <4 x i32> %s, <i32 42, i32 42, i32 42, i32 42>
ret <4 x i32> %r ret <4 x i32> %r
} }
define <4 x i32> @unsigned_sat_constant_v4i32_using_cmp_sum(<4 x i32> %x) { define <4 x i32> @unsigned_sat_constant_v4i32_using_cmp_sum(<4 x i32> %x) {
; CHECK-LABEL: unsigned_sat_constant_v4i32_using_cmp_sum: ; CHECK-LABEL: unsigned_sat_constant_v4i32_using_cmp_sum:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addis 3, 2, .LCPI31_0@toc@ha ; CHECK-NEXT: addis 3, 2, .LCPI31_0@toc@ha
; CHECK-NEXT: addi 3, 3, .LCPI31_0@toc@l ; CHECK-NEXT: addi 3, 3, .LCPI31_0@toc@l
; CHECK-NEXT: lvx 3, 0, 3 ; CHECK-NEXT: lxvd2x 0, 0, 3
; CHECK-NEXT: xxswapd 35, 0
; CHECK-NEXT: vadduws 2, 2, 3 ; CHECK-NEXT: vadduws 2, 2, 3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
%a = add <4 x i32> %x, <i32 42, i32 42, i32 42, i32 42> %a = add <4 x i32> %x, <i32 42, i32 42, i32 42, i32 42>
%c = icmp ugt <4 x i32> %x, %a %c = icmp ugt <4 x i32> %x, %a
%r = select <4 x i1> %c, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, <4 x i32> %a %r = select <4 x i1> %c, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, <4 x i32> %a
ret <4 x i32> %r ret <4 x i32> %r
} }
define <4 x i32> @unsigned_sat_constant_v4i32_using_cmp_notval(<4 x i32> %x) { define <4 x i32> @unsigned_sat_constant_v4i32_using_cmp_notval(<4 x i32> %x) {
; CHECK-LABEL: unsigned_sat_constant_v4i32_using_cmp_notval: ; CHECK-LABEL: unsigned_sat_constant_v4i32_using_cmp_notval:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addis 3, 2, .LCPI32_0@toc@ha ; CHECK-NEXT: addis 3, 2, .LCPI32_0@toc@ha
; CHECK-NEXT: addi 3, 3, .LCPI32_0@toc@l ; CHECK-NEXT: addi 3, 3, .LCPI32_0@toc@l
; CHECK-NEXT: lvx 3, 0, 3 ; CHECK-NEXT: lxvd2x 0, 0, 3
; CHECK-NEXT: xxswapd 35, 0
; CHECK-NEXT: vadduws 2, 2, 3 ; CHECK-NEXT: vadduws 2, 2, 3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
%a = add <4 x i32> %x, <i32 42, i32 42, i32 42, i32 42> %a = add <4 x i32> %x, <i32 42, i32 42, i32 42, i32 42>
%c = icmp ugt <4 x i32> %x, <i32 -43, i32 -43, i32 -43, i32 -43> %c = icmp ugt <4 x i32> %x, <i32 -43, i32 -43, i32 -43, i32 -43>
%r = select <4 x i1> %c, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, <4 x i32> %a %r = select <4 x i1> %c, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, <4 x i32> %a
ret <4 x i32> %r ret <4 x i32> %r
} }
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llvm/test/CodeGen/PowerPC/scalar_vector_test_4.ll

Show All 34 Lines
; P9BE-NEXT: lwz r3, 0(r3) ; P9BE-NEXT: lwz r3, 0(r3)
; P9BE-NEXT: mtfprwz f0, r3 ; P9BE-NEXT: mtfprwz f0, r3
; P9BE-NEXT: xxinsertw v2, vs0, 0 ; P9BE-NEXT: xxinsertw v2, vs0, 0
; P9BE-NEXT: blr ; P9BE-NEXT: blr
; ;
; P8LE-LABEL: s2v_test1: ; P8LE-LABEL: s2v_test1:
; P8LE: # %bb.0: # %entry ; P8LE: # %bb.0: # %entry
; P8LE-NEXT: addis r4, r2, .LCPI0_0@toc@ha ; P8LE-NEXT: addis r4, r2, .LCPI0_0@toc@ha
; P8LE-NEXT: lxsiwzx v4, 0, r3 ; P8LE-NEXT: lxsiwzx v3, 0, r3
; P8LE-NEXT: addi r4, r4, .LCPI0_0@toc@l ; P8LE-NEXT: addi r4, r4, .LCPI0_0@toc@l
; P8LE-NEXT: lvx v3, 0, r4 ; P8LE-NEXT: lxvd2x vs0, 0, r4
; P8LE-NEXT: vperm v2, v2, v4, v3 ; P8LE-NEXT: xxswapd v4, vs0
; P8LE-NEXT: vperm v2, v2, v3, v4
; P8LE-NEXT: blr ; P8LE-NEXT: blr
; ;
; P8BE-LABEL: s2v_test1: ; P8BE-LABEL: s2v_test1:
; P8BE: # %bb.0: # %entry ; P8BE: # %bb.0: # %entry
; P8BE-NEXT: addis r4, r2, .LCPI0_0@toc@ha ; P8BE-NEXT: addis r4, r2, .LCPI0_0@toc@ha
; P8BE-NEXT: lxsiwzx v4, 0, r3 ; P8BE-NEXT: lxsiwzx v4, 0, r3
; P8BE-NEXT: addi r4, r4, .LCPI0_0@toc@l ; P8BE-NEXT: addi r4, r4, .LCPI0_0@toc@l
; P8BE-NEXT: lxvw4x v3, 0, r4 ; P8BE-NEXT: lxvw4x v3, 0, r4
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; P9BE-NEXT: xxinsertw v2, vs0, 0 ; P9BE-NEXT: xxinsertw v2, vs0, 0
; P9BE-NEXT: blr ; P9BE-NEXT: blr
; ;
; P8LE-LABEL: s2v_test2: ; P8LE-LABEL: s2v_test2:
; P8LE: # %bb.0: # %entry ; P8LE: # %bb.0: # %entry
; P8LE-NEXT: addis r4, r2, .LCPI1_0@toc@ha ; P8LE-NEXT: addis r4, r2, .LCPI1_0@toc@ha
; P8LE-NEXT: addi r3, r3, 4 ; P8LE-NEXT: addi r3, r3, 4
; P8LE-NEXT: addi r4, r4, .LCPI1_0@toc@l ; P8LE-NEXT: addi r4, r4, .LCPI1_0@toc@l
; P8LE-NEXT: lxsiwzx v4, 0, r3 ; P8LE-NEXT: lxsiwzx v3, 0, r3
; P8LE-NEXT: lvx v3, 0, r4 ; P8LE-NEXT: lxvd2x vs0, 0, r4
; P8LE-NEXT: vperm v2, v2, v4, v3 ; P8LE-NEXT: xxswapd v4, vs0
; P8LE-NEXT: vperm v2, v2, v3, v4
; P8LE-NEXT: blr ; P8LE-NEXT: blr
; ;
; P8BE-LABEL: s2v_test2: ; P8BE-LABEL: s2v_test2:
; P8BE: # %bb.0: # %entry ; P8BE: # %bb.0: # %entry
; P8BE-NEXT: addis r4, r2, .LCPI1_0@toc@ha ; P8BE-NEXT: addis r4, r2, .LCPI1_0@toc@ha
; P8BE-NEXT: addi r3, r3, 4 ; P8BE-NEXT: addi r3, r3, 4
; P8BE-NEXT: addi r4, r4, .LCPI1_0@toc@l ; P8BE-NEXT: addi r4, r4, .LCPI1_0@toc@l
; P8BE-NEXT: lxsiwzx v4, 0, r3 ; P8BE-NEXT: lxsiwzx v4, 0, r3
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; P9BE-NEXT: lwzx r3, r3, r4 ; P9BE-NEXT: lwzx r3, r3, r4
; P9BE-NEXT: mtfprwz f0, r3 ; P9BE-NEXT: mtfprwz f0, r3
; P9BE-NEXT: xxinsertw v2, vs0, 0 ; P9BE-NEXT: xxinsertw v2, vs0, 0
; P9BE-NEXT: blr ; P9BE-NEXT: blr
; ;
; P8LE-LABEL: s2v_test3: ; P8LE-LABEL: s2v_test3:
; P8LE: # %bb.0: # %entry ; P8LE: # %bb.0: # %entry
; P8LE-NEXT: addis r4, r2, .LCPI2_0@toc@ha ; P8LE-NEXT: addis r4, r2, .LCPI2_0@toc@ha
; P8LE-NEXT: sldi r5, r7, 2
; P8LE-NEXT: addi r4, r4, .LCPI2_0@toc@l ; P8LE-NEXT: addi r4, r4, .LCPI2_0@toc@l
; P8LE-NEXT: lxsiwzx v3, r3, r5 ; P8LE-NEXT: lxvd2x vs0, 0, r4
; P8LE-NEXT: lvx v4, 0, r4 ; P8LE-NEXT: sldi r4, r7, 2
; P8LE-NEXT: lxsiwzx v3, r3, r4
; P8LE-NEXT: xxswapd v4, vs0
; P8LE-NEXT: vperm v2, v2, v3, v4 ; P8LE-NEXT: vperm v2, v2, v3, v4
; P8LE-NEXT: blr ; P8LE-NEXT: blr
; ;
; P8BE-LABEL: s2v_test3: ; P8BE-LABEL: s2v_test3:
; P8BE: # %bb.0: # %entry ; P8BE: # %bb.0: # %entry
; P8BE-NEXT: addis r4, r2, .LCPI2_0@toc@ha ; P8BE-NEXT: addis r4, r2, .LCPI2_0@toc@ha
; P8BE-NEXT: sldi r5, r7, 2 ; P8BE-NEXT: sldi r5, r7, 2
; P8BE-NEXT: addi r4, r4, .LCPI2_0@toc@l ; P8BE-NEXT: addi r4, r4, .LCPI2_0@toc@l
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; P9BE-NEXT: xxinsertw v2, vs0, 0 ; P9BE-NEXT: xxinsertw v2, vs0, 0
; P9BE-NEXT: blr ; P9BE-NEXT: blr
; ;
; P8LE-LABEL: s2v_test4: ; P8LE-LABEL: s2v_test4:
; P8LE: # %bb.0: # %entry ; P8LE: # %bb.0: # %entry
; P8LE-NEXT: addis r4, r2, .LCPI3_0@toc@ha ; P8LE-NEXT: addis r4, r2, .LCPI3_0@toc@ha
; P8LE-NEXT: addi r3, r3, 4 ; P8LE-NEXT: addi r3, r3, 4
; P8LE-NEXT: addi r4, r4, .LCPI3_0@toc@l ; P8LE-NEXT: addi r4, r4, .LCPI3_0@toc@l
; P8LE-NEXT: lxsiwzx v4, 0, r3 ; P8LE-NEXT: lxsiwzx v3, 0, r3
; P8LE-NEXT: lvx v3, 0, r4 ; P8LE-NEXT: lxvd2x vs0, 0, r4
; P8LE-NEXT: vperm v2, v2, v4, v3 ; P8LE-NEXT: xxswapd v4, vs0
; P8LE-NEXT: vperm v2, v2, v3, v4
; P8LE-NEXT: blr ; P8LE-NEXT: blr
; ;
; P8BE-LABEL: s2v_test4: ; P8BE-LABEL: s2v_test4:
; P8BE: # %bb.0: # %entry ; P8BE: # %bb.0: # %entry
; P8BE-NEXT: addis r4, r2, .LCPI3_0@toc@ha ; P8BE-NEXT: addis r4, r2, .LCPI3_0@toc@ha
; P8BE-NEXT: addi r3, r3, 4 ; P8BE-NEXT: addi r3, r3, 4
; P8BE-NEXT: addi r4, r4, .LCPI3_0@toc@l ; P8BE-NEXT: addi r4, r4, .LCPI3_0@toc@l
; P8BE-NEXT: lxsiwzx v4, 0, r3 ; P8BE-NEXT: lxsiwzx v4, 0, r3
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; P9BE-NEXT: lwz r3, 0(r5) ; P9BE-NEXT: lwz r3, 0(r5)
; P9BE-NEXT: mtfprwz f0, r3 ; P9BE-NEXT: mtfprwz f0, r3
; P9BE-NEXT: xxinsertw v2, vs0, 0 ; P9BE-NEXT: xxinsertw v2, vs0, 0
; P9BE-NEXT: blr ; P9BE-NEXT: blr
; ;
; P8LE-LABEL: s2v_test5: ; P8LE-LABEL: s2v_test5:
; P8LE: # %bb.0: # %entry ; P8LE: # %bb.0: # %entry
; P8LE-NEXT: addis r3, r2, .LCPI4_0@toc@ha ; P8LE-NEXT: addis r3, r2, .LCPI4_0@toc@ha
; P8LE-NEXT: lxsiwzx v4, 0, r5 ; P8LE-NEXT: lxsiwzx v3, 0, r5
; P8LE-NEXT: addi r3, r3, .LCPI4_0@toc@l ; P8LE-NEXT: addi r3, r3, .LCPI4_0@toc@l
; P8LE-NEXT: lvx v3, 0, r3 ; P8LE-NEXT: lxvd2x vs0, 0, r3
; P8LE-NEXT: vperm v2, v2, v4, v3 ; P8LE-NEXT: xxswapd v4, vs0
; P8LE-NEXT: vperm v2, v2, v3, v4
; P8LE-NEXT: blr ; P8LE-NEXT: blr
; ;
; P8BE-LABEL: s2v_test5: ; P8BE-LABEL: s2v_test5:
; P8BE: # %bb.0: # %entry ; P8BE: # %bb.0: # %entry
; P8BE-NEXT: addis r3, r2, .LCPI4_0@toc@ha ; P8BE-NEXT: addis r3, r2, .LCPI4_0@toc@ha
; P8BE-NEXT: lxsiwzx v4, 0, r5 ; P8BE-NEXT: lxsiwzx v4, 0, r5
; P8BE-NEXT: addi r3, r3, .LCPI4_0@toc@l ; P8BE-NEXT: addi r3, r3, .LCPI4_0@toc@l
; P8BE-NEXT: lxvw4x v3, 0, r3 ; P8BE-NEXT: lxvw4x v3, 0, r3
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; P9BE-NEXT: lwz r3, 0(r3) ; P9BE-NEXT: lwz r3, 0(r3)
; P9BE-NEXT: mtfprwz f0, r3 ; P9BE-NEXT: mtfprwz f0, r3
; P9BE-NEXT: xxinsertw v2, vs0, 0 ; P9BE-NEXT: xxinsertw v2, vs0, 0
; P9BE-NEXT: blr ; P9BE-NEXT: blr
; ;
; P8LE-LABEL: s2v_test_f1: ; P8LE-LABEL: s2v_test_f1:
; P8LE: # %bb.0: # %entry ; P8LE: # %bb.0: # %entry
; P8LE-NEXT: addis r4, r2, .LCPI5_0@toc@ha ; P8LE-NEXT: addis r4, r2, .LCPI5_0@toc@ha
; P8LE-NEXT: lxsiwzx v4, 0, r3 ; P8LE-NEXT: lxsiwzx v3, 0, r3
; P8LE-NEXT: addi r4, r4, .LCPI5_0@toc@l ; P8LE-NEXT: addi r4, r4, .LCPI5_0@toc@l
; P8LE-NEXT: lvx v3, 0, r4 ; P8LE-NEXT: lxvd2x vs0, 0, r4
; P8LE-NEXT: vperm v2, v2, v4, v3 ; P8LE-NEXT: xxswapd v4, vs0
; P8LE-NEXT: vperm v2, v2, v3, v4
; P8LE-NEXT: blr ; P8LE-NEXT: blr
; ;
; P8BE-LABEL: s2v_test_f1: ; P8BE-LABEL: s2v_test_f1:
; P8BE: # %bb.0: # %entry ; P8BE: # %bb.0: # %entry
; P8BE-NEXT: addis r4, r2, .LCPI5_0@toc@ha ; P8BE-NEXT: addis r4, r2, .LCPI5_0@toc@ha
; P8BE-NEXT: lxsiwzx v4, 0, r3 ; P8BE-NEXT: lxsiwzx v4, 0, r3
; P8BE-NEXT: addi r4, r4, .LCPI5_0@toc@l ; P8BE-NEXT: addi r4, r4, .LCPI5_0@toc@l
; P8BE-NEXT: lxvw4x v3, 0, r4 ; P8BE-NEXT: lxvw4x v3, 0, r4
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llvm/test/CodeGen/PowerPC/signbit-shift.ll

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define <4 x i32> @add_zext_ifpos_vec_splat(<4 x i32> %x) { define <4 x i32> @add_zext_ifpos_vec_splat(<4 x i32> %x) {
; CHECK-LABEL: add_zext_ifpos_vec_splat: ; CHECK-LABEL: add_zext_ifpos_vec_splat:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: xxleqv 35, 35, 35 ; CHECK-NEXT: xxleqv 35, 35, 35
; CHECK-NEXT: addis 3, 2, .LCPI2_0@toc@ha ; CHECK-NEXT: addis 3, 2, .LCPI2_0@toc@ha
; CHECK-NEXT: addi 3, 3, .LCPI2_0@toc@l ; CHECK-NEXT: addi 3, 3, .LCPI2_0@toc@l
; CHECK-NEXT: vcmpgtsw 2, 2, 3 ; CHECK-NEXT: vcmpgtsw 2, 2, 3
; CHECK-NEXT: lvx 3, 0, 3 ; CHECK-NEXT: lxvd2x 0, 0, 3
; CHECK-NEXT: xxswapd 35, 0
; CHECK-NEXT: vsubuwm 2, 3, 2 ; CHECK-NEXT: vsubuwm 2, 3, 2
; CHECK-NEXT: blr ; CHECK-NEXT: blr
%c = icmp sgt <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1> %c = icmp sgt <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>
%e = zext <4 x i1> %c to <4 x i32> %e = zext <4 x i1> %c to <4 x i32>
%r = add <4 x i32> %e, <i32 41, i32 41, i32 41, i32 41> %r = add <4 x i32> %e, <i32 41, i32 41, i32 41, i32 41>
ret <4 x i32> %r ret <4 x i32> %r
} }
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define <4 x i32> @add_sext_ifpos_vec_splat(<4 x i32> %x) { define <4 x i32> @add_sext_ifpos_vec_splat(<4 x i32> %x) {
; CHECK-LABEL: add_sext_ifpos_vec_splat: ; CHECK-LABEL: add_sext_ifpos_vec_splat:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: xxleqv 35, 35, 35 ; CHECK-NEXT: xxleqv 35, 35, 35
; CHECK-NEXT: addis 3, 2, .LCPI6_0@toc@ha ; CHECK-NEXT: addis 3, 2, .LCPI6_0@toc@ha
; CHECK-NEXT: addi 3, 3, .LCPI6_0@toc@l ; CHECK-NEXT: addi 3, 3, .LCPI6_0@toc@l
; CHECK-NEXT: vcmpgtsw 2, 2, 3 ; CHECK-NEXT: vcmpgtsw 2, 2, 3
; CHECK-NEXT: lvx 3, 0, 3 ; CHECK-NEXT: lxvd2x 0, 0, 3
; CHECK-NEXT: xxswapd 35, 0
; CHECK-NEXT: vadduwm 2, 2, 3 ; CHECK-NEXT: vadduwm 2, 2, 3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
%c = icmp sgt <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1> %c = icmp sgt <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>
%e = sext <4 x i1> %c to <4 x i32> %e = sext <4 x i1> %c to <4 x i32>
%r = add <4 x i32> %e, <i32 42, i32 42, i32 42, i32 42> %r = add <4 x i32> %e, <i32 42, i32 42, i32 42, i32 42>
ret <4 x i32> %r ret <4 x i32> %r
} }
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define <4 x i32> @add_lshr_not_vec_splat(<4 x i32> %x) { define <4 x i32> @add_lshr_not_vec_splat(<4 x i32> %x) {
; CHECK-LABEL: add_lshr_not_vec_splat: ; CHECK-LABEL: add_lshr_not_vec_splat:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vspltisw 3, -16 ; CHECK-NEXT: vspltisw 3, -16
; CHECK-NEXT: vspltisw 4, 15 ; CHECK-NEXT: vspltisw 4, 15
; CHECK-NEXT: addis 3, 2, .LCPI15_0@toc@ha ; CHECK-NEXT: addis 3, 2, .LCPI15_0@toc@ha
; CHECK-NEXT: addi 3, 3, .LCPI15_0@toc@l ; CHECK-NEXT: addi 3, 3, .LCPI15_0@toc@l
; CHECK-NEXT: lxvd2x 0, 0, 3
; CHECK-NEXT: vsubuwm 3, 4, 3 ; CHECK-NEXT: vsubuwm 3, 4, 3
; CHECK-NEXT: vsraw 2, 2, 3 ; CHECK-NEXT: vsraw 2, 2, 3
; CHECK-NEXT: lvx 3, 0, 3 ; CHECK-NEXT: xxswapd 35, 0
; CHECK-NEXT: vadduwm 2, 2, 3 ; CHECK-NEXT: vadduwm 2, 2, 3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
%c = xor <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1> %c = xor <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>
%e = lshr <4 x i32> %c, <i32 31, i32 31, i32 31, i32 31> %e = lshr <4 x i32> %c, <i32 31, i32 31, i32 31, i32 31>
%r = add <4 x i32> %e, <i32 42, i32 42, i32 42, i32 42> %r = add <4 x i32> %e, <i32 42, i32 42, i32 42, i32 42>
ret <4 x i32> %r ret <4 x i32> %r
} }
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define <4 x i32> @sub_lshr_not_vec_splat(<4 x i32> %x) { define <4 x i32> @sub_lshr_not_vec_splat(<4 x i32> %x) {
; CHECK-LABEL: sub_lshr_not_vec_splat: ; CHECK-LABEL: sub_lshr_not_vec_splat:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vspltisw 3, -16 ; CHECK-NEXT: vspltisw 3, -16
; CHECK-NEXT: vspltisw 4, 15 ; CHECK-NEXT: vspltisw 4, 15
; CHECK-NEXT: addis 3, 2, .LCPI17_0@toc@ha ; CHECK-NEXT: addis 3, 2, .LCPI17_0@toc@ha
; CHECK-NEXT: addi 3, 3, .LCPI17_0@toc@l ; CHECK-NEXT: addi 3, 3, .LCPI17_0@toc@l
; CHECK-NEXT: lxvd2x 0, 0, 3
; CHECK-NEXT: vsubuwm 3, 4, 3 ; CHECK-NEXT: vsubuwm 3, 4, 3
; CHECK-NEXT: vsrw 2, 2, 3 ; CHECK-NEXT: vsrw 2, 2, 3
; CHECK-NEXT: lvx 3, 0, 3 ; CHECK-NEXT: xxswapd 35, 0
; CHECK-NEXT: vadduwm 2, 2, 3 ; CHECK-NEXT: vadduwm 2, 2, 3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
%c = xor <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1> %c = xor <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>
%e = lshr <4 x i32> %c, <i32 31, i32 31, i32 31, i32 31> %e = lshr <4 x i32> %c, <i32 31, i32 31, i32 31, i32 31>
%r = sub <4 x i32> <i32 42, i32 42, i32 42, i32 42>, %e %r = sub <4 x i32> <i32 42, i32 42, i32 42, i32 42>, %e
ret <4 x i32> %r ret <4 x i32> %r
} }
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define <4 x i32> @sub_const_op_lshr_vec(<4 x i32> %x) { define <4 x i32> @sub_const_op_lshr_vec(<4 x i32> %x) {
; CHECK-LABEL: sub_const_op_lshr_vec: ; CHECK-LABEL: sub_const_op_lshr_vec:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vspltisw 3, -16 ; CHECK-NEXT: vspltisw 3, -16
; CHECK-NEXT: vspltisw 4, 15 ; CHECK-NEXT: vspltisw 4, 15
; CHECK-NEXT: addis 3, 2, .LCPI21_0@toc@ha ; CHECK-NEXT: addis 3, 2, .LCPI21_0@toc@ha
; CHECK-NEXT: addi 3, 3, .LCPI21_0@toc@l ; CHECK-NEXT: addi 3, 3, .LCPI21_0@toc@l
; CHECK-NEXT: lxvd2x 0, 0, 3
; CHECK-NEXT: vsubuwm 3, 4, 3 ; CHECK-NEXT: vsubuwm 3, 4, 3
; CHECK-NEXT: vsraw 2, 2, 3 ; CHECK-NEXT: vsraw 2, 2, 3
; CHECK-NEXT: lvx 3, 0, 3 ; CHECK-NEXT: xxswapd 35, 0
; CHECK-NEXT: vadduwm 2, 2, 3 ; CHECK-NEXT: vadduwm 2, 2, 3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
%sh = lshr <4 x i32> %x, <i32 31, i32 31, i32 31, i32 31> %sh = lshr <4 x i32> %x, <i32 31, i32 31, i32 31, i32 31>
%r = sub <4 x i32> <i32 42, i32 42, i32 42, i32 42>, %sh %r = sub <4 x i32> <i32 42, i32 42, i32 42, i32 42>, %sh
ret <4 x i32> %r ret <4 x i32> %r
} }

llvm/test/CodeGen/PowerPC/store_fptoi.ll

Show All 20 Lines
; CHECK-PWR8: # %bb.0: # %entry ; CHECK-PWR8: # %bb.0: # %entry
; CHECK-PWR8-NEXT: mflr 0 ; CHECK-PWR8-NEXT: mflr 0
; CHECK-PWR8-NEXT: .cfi_def_cfa_offset 48 ; CHECK-PWR8-NEXT: .cfi_def_cfa_offset 48
; CHECK-PWR8-NEXT: .cfi_offset lr, 16 ; CHECK-PWR8-NEXT: .cfi_offset lr, 16
; CHECK-PWR8-NEXT: .cfi_offset r30, -16 ; CHECK-PWR8-NEXT: .cfi_offset r30, -16
; CHECK-PWR8-NEXT: std 30, -16(1) # 8-byte Folded Spill ; CHECK-PWR8-NEXT: std 30, -16(1) # 8-byte Folded Spill
; CHECK-PWR8-NEXT: std 0, 16(1) ; CHECK-PWR8-NEXT: std 0, 16(1)
; CHECK-PWR8-NEXT: stdu 1, -48(1) ; CHECK-PWR8-NEXT: stdu 1, -48(1)
; CHECK-PWR8-NEXT: lvx 2, 0, 3 ; CHECK-PWR8-NEXT: lxvd2x 0, 0, 3
; CHECK-PWR8-NEXT: mr 30, 4 ; CHECK-PWR8-NEXT: mr 30, 4
; CHECK-PWR8-NEXT: xxswapd 2, 0
; CHECK-PWR8-NEXT: bl __fixkfdi ; CHECK-PWR8-NEXT: bl __fixkfdi
; CHECK-PWR8-NEXT: nop ; CHECK-PWR8-NEXT: nop
; CHECK-PWR8-NEXT: std 3, 0(30) ; CHECK-PWR8-NEXT: std 3, 0(30)
; CHECK-PWR8-NEXT: addi 1, 1, 48 ; CHECK-PWR8-NEXT: addi 1, 1, 48
; CHECK-PWR8-NEXT: ld 0, 16(1) ; CHECK-PWR8-NEXT: ld 0, 16(1)
; CHECK-PWR8-NEXT: ld 30, -16(1) # 8-byte Folded Reload ; CHECK-PWR8-NEXT: ld 30, -16(1) # 8-byte Folded Reload
; CHECK-PWR8-NEXT: mtlr 0 ; CHECK-PWR8-NEXT: mtlr 0
; CHECK-PWR8-NEXT: blr ; CHECK-PWR8-NEXT: blr
Show All 19 Lines
; CHECK-PWR8: # %bb.0: # %entry ; CHECK-PWR8: # %bb.0: # %entry
; CHECK-PWR8-NEXT: mflr 0 ; CHECK-PWR8-NEXT: mflr 0
; CHECK-PWR8-NEXT: .cfi_def_cfa_offset 48 ; CHECK-PWR8-NEXT: .cfi_def_cfa_offset 48
; CHECK-PWR8-NEXT: .cfi_offset lr, 16 ; CHECK-PWR8-NEXT: .cfi_offset lr, 16
; CHECK-PWR8-NEXT: .cfi_offset r30, -16 ; CHECK-PWR8-NEXT: .cfi_offset r30, -16
; CHECK-PWR8-NEXT: std 30, -16(1) # 8-byte Folded Spill ; CHECK-PWR8-NEXT: std 30, -16(1) # 8-byte Folded Spill
; CHECK-PWR8-NEXT: std 0, 16(1) ; CHECK-PWR8-NEXT: std 0, 16(1)
; CHECK-PWR8-NEXT: stdu 1, -48(1) ; CHECK-PWR8-NEXT: stdu 1, -48(1)
; CHECK-PWR8-NEXT: lvx 2, 0, 3 ; CHECK-PWR8-NEXT: lxvd2x 0, 0, 3
; CHECK-PWR8-NEXT: mr 30, 4 ; CHECK-PWR8-NEXT: mr 30, 4
; CHECK-PWR8-NEXT: xxswapd 2, 0
; CHECK-PWR8-NEXT: bl __fixkfsi ; CHECK-PWR8-NEXT: bl __fixkfsi
; CHECK-PWR8-NEXT: nop ; CHECK-PWR8-NEXT: nop
; CHECK-PWR8-NEXT: stw 3, 0(30) ; CHECK-PWR8-NEXT: stw 3, 0(30)
; CHECK-PWR8-NEXT: addi 1, 1, 48 ; CHECK-PWR8-NEXT: addi 1, 1, 48
; CHECK-PWR8-NEXT: ld 0, 16(1) ; CHECK-PWR8-NEXT: ld 0, 16(1)
; CHECK-PWR8-NEXT: ld 30, -16(1) # 8-byte Folded Reload ; CHECK-PWR8-NEXT: ld 30, -16(1) # 8-byte Folded Reload
; CHECK-PWR8-NEXT: mtlr 0 ; CHECK-PWR8-NEXT: mtlr 0
; CHECK-PWR8-NEXT: blr ; CHECK-PWR8-NEXT: blr
Show All 19 Lines
; CHECK-PWR8: # %bb.0: # %entry ; CHECK-PWR8: # %bb.0: # %entry
; CHECK-PWR8-NEXT: mflr 0 ; CHECK-PWR8-NEXT: mflr 0
; CHECK-PWR8-NEXT: .cfi_def_cfa_offset 48 ; CHECK-PWR8-NEXT: .cfi_def_cfa_offset 48
; CHECK-PWR8-NEXT: .cfi_offset lr, 16 ; CHECK-PWR8-NEXT: .cfi_offset lr, 16
; CHECK-PWR8-NEXT: .cfi_offset r30, -16 ; CHECK-PWR8-NEXT: .cfi_offset r30, -16
; CHECK-PWR8-NEXT: std 30, -16(1) # 8-byte Folded Spill ; CHECK-PWR8-NEXT: std 30, -16(1) # 8-byte Folded Spill
; CHECK-PWR8-NEXT: std 0, 16(1) ; CHECK-PWR8-NEXT: std 0, 16(1)
; CHECK-PWR8-NEXT: stdu 1, -48(1) ; CHECK-PWR8-NEXT: stdu 1, -48(1)
; CHECK-PWR8-NEXT: lvx 2, 0, 3 ; CHECK-PWR8-NEXT: lxvd2x 0, 0, 3
; CHECK-PWR8-NEXT: mr 30, 4 ; CHECK-PWR8-NEXT: mr 30, 4
; CHECK-PWR8-NEXT: xxswapd 2, 0
; CHECK-PWR8-NEXT: bl __fixunskfdi ; CHECK-PWR8-NEXT: bl __fixunskfdi
; CHECK-PWR8-NEXT: nop ; CHECK-PWR8-NEXT: nop
; CHECK-PWR8-NEXT: std 3, 0(30) ; CHECK-PWR8-NEXT: std 3, 0(30)
; CHECK-PWR8-NEXT: addi 1, 1, 48 ; CHECK-PWR8-NEXT: addi 1, 1, 48
; CHECK-PWR8-NEXT: ld 0, 16(1) ; CHECK-PWR8-NEXT: ld 0, 16(1)
; CHECK-PWR8-NEXT: ld 30, -16(1) # 8-byte Folded Reload ; CHECK-PWR8-NEXT: ld 30, -16(1) # 8-byte Folded Reload
; CHECK-PWR8-NEXT: mtlr 0 ; CHECK-PWR8-NEXT: mtlr 0
; CHECK-PWR8-NEXT: blr ; CHECK-PWR8-NEXT: blr
Show All 19 Lines
; CHECK-PWR8: # %bb.0: # %entry ; CHECK-PWR8: # %bb.0: # %entry
; CHECK-PWR8-NEXT: mflr 0 ; CHECK-PWR8-NEXT: mflr 0
; CHECK-PWR8-NEXT: .cfi_def_cfa_offset 48 ; CHECK-PWR8-NEXT: .cfi_def_cfa_offset 48
; CHECK-PWR8-NEXT: .cfi_offset lr, 16 ; CHECK-PWR8-NEXT: .cfi_offset lr, 16
; CHECK-PWR8-NEXT: .cfi_offset r30, -16 ; CHECK-PWR8-NEXT: .cfi_offset r30, -16
; CHECK-PWR8-NEXT: std 30, -16(1) # 8-byte Folded Spill ; CHECK-PWR8-NEXT: std 30, -16(1) # 8-byte Folded Spill
; CHECK-PWR8-NEXT: std 0, 16(1) ; CHECK-PWR8-NEXT: std 0, 16(1)
; CHECK-PWR8-NEXT: stdu 1, -48(1) ; CHECK-PWR8-NEXT: stdu 1, -48(1)
; CHECK-PWR8-NEXT: lvx 2, 0, 3 ; CHECK-PWR8-NEXT: lxvd2x 0, 0, 3
; CHECK-PWR8-NEXT: mr 30, 4 ; CHECK-PWR8-NEXT: mr 30, 4
; CHECK-PWR8-NEXT: xxswapd 2, 0
; CHECK-PWR8-NEXT: bl __fixunskfsi ; CHECK-PWR8-NEXT: bl __fixunskfsi
; CHECK-PWR8-NEXT: nop ; CHECK-PWR8-NEXT: nop
; CHECK-PWR8-NEXT: stw 3, 0(30) ; CHECK-PWR8-NEXT: stw 3, 0(30)
; CHECK-PWR8-NEXT: addi 1, 1, 48 ; CHECK-PWR8-NEXT: addi 1, 1, 48
; CHECK-PWR8-NEXT: ld 0, 16(1) ; CHECK-PWR8-NEXT: ld 0, 16(1)
; CHECK-PWR8-NEXT: ld 30, -16(1) # 8-byte Folded Reload ; CHECK-PWR8-NEXT: ld 30, -16(1) # 8-byte Folded Reload
; CHECK-PWR8-NEXT: mtlr 0 ; CHECK-PWR8-NEXT: mtlr 0
; CHECK-PWR8-NEXT: blr ; CHECK-PWR8-NEXT: blr
▲ Show 20 Lines • Show All 868 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/test-vector-insert.ll

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define dso_local <4 x i32> @test(<4 x i32> %a, double %b) { define dso_local <4 x i32> @test(<4 x i32> %a, double %b) {
; CHECK-LE-P7-LABEL: test: ; CHECK-LE-P7-LABEL: test:
; CHECK-LE-P7: # %bb.0: # %entry ; CHECK-LE-P7: # %bb.0: # %entry
; CHECK-LE-P7-NEXT: xscvdpsxws f0, f1 ; CHECK-LE-P7-NEXT: xscvdpsxws f0, f1
; CHECK-LE-P7-NEXT: addi r3, r1, -4 ; CHECK-LE-P7-NEXT: addi r3, r1, -4
; CHECK-LE-P7-NEXT: addis r4, r2, .LCPI0_0@toc@ha ; CHECK-LE-P7-NEXT: addis r4, r2, .LCPI0_0@toc@ha
; CHECK-LE-P7-NEXT: addi r4, r4, .LCPI0_0@toc@l ; CHECK-LE-P7-NEXT: addi r4, r4, .LCPI0_0@toc@l
; CHECK-LE-P7-NEXT: lvx v3, 0, r4
; CHECK-LE-P7-NEXT: stfiwx f0, 0, r3 ; CHECK-LE-P7-NEXT: stfiwx f0, 0, r3
; CHECK-LE-P7-NEXT: lxvd2x vs0, 0, r4
; CHECK-LE-P7-NEXT: lwz r3, -4(r1) ; CHECK-LE-P7-NEXT: lwz r3, -4(r1)
; CHECK-LE-P7-NEXT: stw r3, -32(r1) ; CHECK-LE-P7-NEXT: stw r3, -32(r1)
; CHECK-LE-P7-NEXT: addi r3, r1, -32 ; CHECK-LE-P7-NEXT: addi r3, r1, -32
; CHECK-LE-P7-NEXT: lvx v4, 0, r3 ; CHECK-LE-P7-NEXT: xxswapd v3, vs0
; CHECK-LE-P7-NEXT: lxvd2x vs1, 0, r3
; CHECK-LE-P7-NEXT: xxswapd v4, vs1
; CHECK-LE-P7-NEXT: vperm v2, v4, v2, v3 ; CHECK-LE-P7-NEXT: vperm v2, v4, v2, v3
; CHECK-LE-P7-NEXT: blr ; CHECK-LE-P7-NEXT: blr
; ;
; CHECK-LE-P8-LABEL: test: ; CHECK-LE-P8-LABEL: test:
; CHECK-LE-P8: # %bb.0: # %entry ; CHECK-LE-P8: # %bb.0: # %entry
; CHECK-LE-P8-NEXT: xscvdpsxws v3, f1
; CHECK-LE-P8-NEXT: addis r3, r2, .LCPI0_0@toc@ha ; CHECK-LE-P8-NEXT: addis r3, r2, .LCPI0_0@toc@ha
; CHECK-LE-P8-NEXT: xscvdpsxws v3, f1
; CHECK-LE-P8-NEXT: addi r3, r3, .LCPI0_0@toc@l ; CHECK-LE-P8-NEXT: addi r3, r3, .LCPI0_0@toc@l
; CHECK-LE-P8-NEXT: lvx v4, 0, r3 ; CHECK-LE-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-LE-P8-NEXT: xxswapd v4, vs0
; CHECK-LE-P8-NEXT: vperm v2, v3, v2, v4 ; CHECK-LE-P8-NEXT: vperm v2, v3, v2, v4
; CHECK-LE-P8-NEXT: blr ; CHECK-LE-P8-NEXT: blr
; ;
; CHECK-LE-P9-LABEL: test: ; CHECK-LE-P9-LABEL: test:
; CHECK-LE-P9: # %bb.0: # %entry ; CHECK-LE-P9: # %bb.0: # %entry
; CHECK-LE-P9-NEXT: xscvdpsxws f0, f1 ; CHECK-LE-P9-NEXT: xscvdpsxws f0, f1
; CHECK-LE-P9-NEXT: xxinsertw v2, vs0, 0 ; CHECK-LE-P9-NEXT: xxinsertw v2, vs0, 0
; CHECK-LE-P9-NEXT: blr ; CHECK-LE-P9-NEXT: blr
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define dso_local <4 x i32> @test2(<4 x i32> %a, float %b) { define dso_local <4 x i32> @test2(<4 x i32> %a, float %b) {
; CHECK-LE-P7-LABEL: test2: ; CHECK-LE-P7-LABEL: test2:
; CHECK-LE-P7: # %bb.0: # %entry ; CHECK-LE-P7: # %bb.0: # %entry
; CHECK-LE-P7-NEXT: xscvdpsxws f0, f1 ; CHECK-LE-P7-NEXT: xscvdpsxws f0, f1
; CHECK-LE-P7-NEXT: addi r3, r1, -4 ; CHECK-LE-P7-NEXT: addi r3, r1, -4
; CHECK-LE-P7-NEXT: addis r4, r2, .LCPI1_0@toc@ha ; CHECK-LE-P7-NEXT: addis r4, r2, .LCPI1_0@toc@ha
; CHECK-LE-P7-NEXT: addi r4, r4, .LCPI1_0@toc@l ; CHECK-LE-P7-NEXT: addi r4, r4, .LCPI1_0@toc@l
; CHECK-LE-P7-NEXT: lvx v3, 0, r4
; CHECK-LE-P7-NEXT: stfiwx f0, 0, r3 ; CHECK-LE-P7-NEXT: stfiwx f0, 0, r3
; CHECK-LE-P7-NEXT: lxvd2x vs0, 0, r4
; CHECK-LE-P7-NEXT: lwz r3, -4(r1) ; CHECK-LE-P7-NEXT: lwz r3, -4(r1)
; CHECK-LE-P7-NEXT: stw r3, -32(r1) ; CHECK-LE-P7-NEXT: stw r3, -32(r1)
; CHECK-LE-P7-NEXT: addi r3, r1, -32 ; CHECK-LE-P7-NEXT: addi r3, r1, -32
; CHECK-LE-P7-NEXT: lvx v4, 0, r3 ; CHECK-LE-P7-NEXT: xxswapd v3, vs0
; CHECK-LE-P7-NEXT: lxvd2x vs1, 0, r3
; CHECK-LE-P7-NEXT: xxswapd v4, vs1
; CHECK-LE-P7-NEXT: vperm v2, v4, v2, v3 ; CHECK-LE-P7-NEXT: vperm v2, v4, v2, v3
; CHECK-LE-P7-NEXT: blr ; CHECK-LE-P7-NEXT: blr
; ;
; CHECK-LE-P8-LABEL: test2: ; CHECK-LE-P8-LABEL: test2:
; CHECK-LE-P8: # %bb.0: # %entry ; CHECK-LE-P8: # %bb.0: # %entry
; CHECK-LE-P8-NEXT: xscvdpsxws v3, f1
; CHECK-LE-P8-NEXT: addis r3, r2, .LCPI1_0@toc@ha ; CHECK-LE-P8-NEXT: addis r3, r2, .LCPI1_0@toc@ha
; CHECK-LE-P8-NEXT: xscvdpsxws v3, f1
; CHECK-LE-P8-NEXT: addi r3, r3, .LCPI1_0@toc@l ; CHECK-LE-P8-NEXT: addi r3, r3, .LCPI1_0@toc@l
; CHECK-LE-P8-NEXT: lvx v4, 0, r3 ; CHECK-LE-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-LE-P8-NEXT: xxswapd v4, vs0
; CHECK-LE-P8-NEXT: vperm v2, v3, v2, v4 ; CHECK-LE-P8-NEXT: vperm v2, v3, v2, v4
; CHECK-LE-P8-NEXT: blr ; CHECK-LE-P8-NEXT: blr
; ;
; CHECK-LE-P9-LABEL: test2: ; CHECK-LE-P9-LABEL: test2:
; CHECK-LE-P9: # %bb.0: # %entry ; CHECK-LE-P9: # %bb.0: # %entry
; CHECK-LE-P9-NEXT: xscvdpsxws f0, f1 ; CHECK-LE-P9-NEXT: xscvdpsxws f0, f1
; CHECK-LE-P9-NEXT: xxinsertw v2, vs0, 0 ; CHECK-LE-P9-NEXT: xxinsertw v2, vs0, 0
; CHECK-LE-P9-NEXT: blr ; CHECK-LE-P9-NEXT: blr
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define dso_local <4 x i32> @test3(<4 x i32> %a, double %b) { define dso_local <4 x i32> @test3(<4 x i32> %a, double %b) {
; CHECK-LE-P7-LABEL: test3: ; CHECK-LE-P7-LABEL: test3:
; CHECK-LE-P7: # %bb.0: # %entry ; CHECK-LE-P7: # %bb.0: # %entry
; CHECK-LE-P7-NEXT: xscvdpuxws f0, f1 ; CHECK-LE-P7-NEXT: xscvdpuxws f0, f1
; CHECK-LE-P7-NEXT: addi r3, r1, -4 ; CHECK-LE-P7-NEXT: addi r3, r1, -4
; CHECK-LE-P7-NEXT: addis r4, r2, .LCPI2_0@toc@ha ; CHECK-LE-P7-NEXT: addis r4, r2, .LCPI2_0@toc@ha
; CHECK-LE-P7-NEXT: addi r4, r4, .LCPI2_0@toc@l ; CHECK-LE-P7-NEXT: addi r4, r4, .LCPI2_0@toc@l
; CHECK-LE-P7-NEXT: lvx v3, 0, r4
; CHECK-LE-P7-NEXT: stfiwx f0, 0, r3 ; CHECK-LE-P7-NEXT: stfiwx f0, 0, r3
; CHECK-LE-P7-NEXT: lxvd2x vs0, 0, r4
; CHECK-LE-P7-NEXT: lwz r3, -4(r1) ; CHECK-LE-P7-NEXT: lwz r3, -4(r1)
; CHECK-LE-P7-NEXT: stw r3, -32(r1) ; CHECK-LE-P7-NEXT: stw r3, -32(r1)
; CHECK-LE-P7-NEXT: addi r3, r1, -32 ; CHECK-LE-P7-NEXT: addi r3, r1, -32
; CHECK-LE-P7-NEXT: lvx v4, 0, r3 ; CHECK-LE-P7-NEXT: xxswapd v3, vs0
; CHECK-LE-P7-NEXT: lxvd2x vs1, 0, r3
; CHECK-LE-P7-NEXT: xxswapd v4, vs1
; CHECK-LE-P7-NEXT: vperm v2, v4, v2, v3 ; CHECK-LE-P7-NEXT: vperm v2, v4, v2, v3
; CHECK-LE-P7-NEXT: blr ; CHECK-LE-P7-NEXT: blr
; ;
; CHECK-LE-P8-LABEL: test3: ; CHECK-LE-P8-LABEL: test3:
; CHECK-LE-P8: # %bb.0: # %entry ; CHECK-LE-P8: # %bb.0: # %entry
; CHECK-LE-P8-NEXT: xscvdpuxws v3, f1
; CHECK-LE-P8-NEXT: addis r3, r2, .LCPI2_0@toc@ha ; CHECK-LE-P8-NEXT: addis r3, r2, .LCPI2_0@toc@ha
; CHECK-LE-P8-NEXT: xscvdpuxws v3, f1
; CHECK-LE-P8-NEXT: addi r3, r3, .LCPI2_0@toc@l ; CHECK-LE-P8-NEXT: addi r3, r3, .LCPI2_0@toc@l
; CHECK-LE-P8-NEXT: lvx v4, 0, r3 ; CHECK-LE-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-LE-P8-NEXT: xxswapd v4, vs0
; CHECK-LE-P8-NEXT: vperm v2, v3, v2, v4 ; CHECK-LE-P8-NEXT: vperm v2, v3, v2, v4
; CHECK-LE-P8-NEXT: blr ; CHECK-LE-P8-NEXT: blr
; ;
; CHECK-LE-P9-LABEL: test3: ; CHECK-LE-P9-LABEL: test3:
; CHECK-LE-P9: # %bb.0: # %entry ; CHECK-LE-P9: # %bb.0: # %entry
; CHECK-LE-P9-NEXT: xscvdpuxws f0, f1 ; CHECK-LE-P9-NEXT: xscvdpuxws f0, f1
; CHECK-LE-P9-NEXT: xxinsertw v2, vs0, 0 ; CHECK-LE-P9-NEXT: xxinsertw v2, vs0, 0
; CHECK-LE-P9-NEXT: blr ; CHECK-LE-P9-NEXT: blr
Show All 35 Lines
define dso_local <4 x i32> @test4(<4 x i32> %a, float %b) { define dso_local <4 x i32> @test4(<4 x i32> %a, float %b) {
; CHECK-LE-P7-LABEL: test4: ; CHECK-LE-P7-LABEL: test4:
; CHECK-LE-P7: # %bb.0: # %entry ; CHECK-LE-P7: # %bb.0: # %entry
; CHECK-LE-P7-NEXT: xscvdpuxws f0, f1 ; CHECK-LE-P7-NEXT: xscvdpuxws f0, f1
; CHECK-LE-P7-NEXT: addi r3, r1, -4 ; CHECK-LE-P7-NEXT: addi r3, r1, -4
; CHECK-LE-P7-NEXT: addis r4, r2, .LCPI3_0@toc@ha ; CHECK-LE-P7-NEXT: addis r4, r2, .LCPI3_0@toc@ha
; CHECK-LE-P7-NEXT: addi r4, r4, .LCPI3_0@toc@l ; CHECK-LE-P7-NEXT: addi r4, r4, .LCPI3_0@toc@l
; CHECK-LE-P7-NEXT: lvx v3, 0, r4
; CHECK-LE-P7-NEXT: stfiwx f0, 0, r3 ; CHECK-LE-P7-NEXT: stfiwx f0, 0, r3
; CHECK-LE-P7-NEXT: lxvd2x vs0, 0, r4
; CHECK-LE-P7-NEXT: lwz r3, -4(r1) ; CHECK-LE-P7-NEXT: lwz r3, -4(r1)
; CHECK-LE-P7-NEXT: stw r3, -32(r1) ; CHECK-LE-P7-NEXT: stw r3, -32(r1)
; CHECK-LE-P7-NEXT: addi r3, r1, -32 ; CHECK-LE-P7-NEXT: addi r3, r1, -32
; CHECK-LE-P7-NEXT: lvx v4, 0, r3 ; CHECK-LE-P7-NEXT: xxswapd v3, vs0
; CHECK-LE-P7-NEXT: lxvd2x vs1, 0, r3
; CHECK-LE-P7-NEXT: xxswapd v4, vs1
; CHECK-LE-P7-NEXT: vperm v2, v4, v2, v3 ; CHECK-LE-P7-NEXT: vperm v2, v4, v2, v3
; CHECK-LE-P7-NEXT: blr ; CHECK-LE-P7-NEXT: blr
; ;
; CHECK-LE-P8-LABEL: test4: ; CHECK-LE-P8-LABEL: test4:
; CHECK-LE-P8: # %bb.0: # %entry ; CHECK-LE-P8: # %bb.0: # %entry
; CHECK-LE-P8-NEXT: xscvdpuxws v3, f1
; CHECK-LE-P8-NEXT: addis r3, r2, .LCPI3_0@toc@ha ; CHECK-LE-P8-NEXT: addis r3, r2, .LCPI3_0@toc@ha
; CHECK-LE-P8-NEXT: xscvdpuxws v3, f1
; CHECK-LE-P8-NEXT: addi r3, r3, .LCPI3_0@toc@l ; CHECK-LE-P8-NEXT: addi r3, r3, .LCPI3_0@toc@l
; CHECK-LE-P8-NEXT: lvx v4, 0, r3 ; CHECK-LE-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-LE-P8-NEXT: xxswapd v4, vs0
; CHECK-LE-P8-NEXT: vperm v2, v3, v2, v4 ; CHECK-LE-P8-NEXT: vperm v2, v3, v2, v4
; CHECK-LE-P8-NEXT: blr ; CHECK-LE-P8-NEXT: blr
; ;
; CHECK-LE-P9-LABEL: test4: ; CHECK-LE-P9-LABEL: test4:
; CHECK-LE-P9: # %bb.0: # %entry ; CHECK-LE-P9: # %bb.0: # %entry
; CHECK-LE-P9-NEXT: xscvdpuxws f0, f1 ; CHECK-LE-P9-NEXT: xscvdpuxws f0, f1
; CHECK-LE-P9-NEXT: xxinsertw v2, vs0, 0 ; CHECK-LE-P9-NEXT: xxinsertw v2, vs0, 0
; CHECK-LE-P9-NEXT: blr ; CHECK-LE-P9-NEXT: blr
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llvm/test/CodeGen/PowerPC/toc-float.ll

Show First 20 Lines • Show All 144 Lines • ▼ Show 20 Lines
; CHECK-P9-NEXT: lxv 34, 32(3) ; CHECK-P9-NEXT: lxv 34, 32(3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-P8-LABEL: vectorArray: ; CHECK-P8-LABEL: vectorArray:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: addis 3, 2, .LC0@toc@ha ; CHECK-P8-NEXT: addis 3, 2, .LC0@toc@ha
; CHECK-P8-NEXT: ld 3, .LC0@toc@l(3) ; CHECK-P8-NEXT: ld 3, .LC0@toc@l(3)
; CHECK-P8-NEXT: addi 3, 3, 32 ; CHECK-P8-NEXT: addi 3, 3, 32
; CHECK-P8-NEXT: lvx 2, 0, 3 ; CHECK-P8-NEXT: lxvd2x 0, 0, 3
; CHECK-P8-NEXT: xxswapd 34, 0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
entry: entry:
%0 = load <4 x i32>, <4 x i32>* getelementptr inbounds ([10 x <4 x i32>], [10 x <4 x i32>]* @vec_arr, i64 0, i64 2), align 16 %0 = load <4 x i32>, <4 x i32>* getelementptr inbounds ([10 x <4 x i32>], [10 x <4 x i32>]* @vec_arr, i64 0, i64 2), align 16
ret <4 x i32> %0 ret <4 x i32> %0
} }

llvm/test/CodeGen/PowerPC/urem-seteq-illegal-types.ll

Show First 20 Lines • Show All 157 Lines • ▼ Show 20 Lines
; PPC-NEXT: # %bb.7: ; PPC-NEXT: # %bb.7:
; PPC-NEXT: ori 3, 6, 0 ; PPC-NEXT: ori 3, 6, 0
; PPC-NEXT: blr ; PPC-NEXT: blr
; ;
; PPC64LE-LABEL: test_urem_vec: ; PPC64LE-LABEL: test_urem_vec:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: addis 6, 2, .LCPI4_0@toc@ha ; PPC64LE-NEXT: addis 6, 2, .LCPI4_0@toc@ha
; PPC64LE-NEXT: mtfprwz 0, 3 ; PPC64LE-NEXT: mtfprwz 0, 3
; PPC64LE-NEXT: mtfprwz 1, 4
; PPC64LE-NEXT: addi 3, 6, .LCPI4_0@toc@l
; PPC64LE-NEXT: addis 4, 2, .LCPI4_2@toc@ha
; PPC64LE-NEXT: lvx 2, 0, 3
; PPC64LE-NEXT: mtvsrwz 36, 5
; PPC64LE-NEXT: addis 3, 2, .LCPI4_1@toc@ha ; PPC64LE-NEXT: addis 3, 2, .LCPI4_1@toc@ha
; PPC64LE-NEXT: xxmrghw 35, 1, 0 ; PPC64LE-NEXT: addi 6, 6, .LCPI4_0@toc@l
; PPC64LE-NEXT: mtfprwz 2, 4
; PPC64LE-NEXT: addi 3, 3, .LCPI4_1@toc@l ; PPC64LE-NEXT: addi 3, 3, .LCPI4_1@toc@l
; PPC64LE-NEXT: vperm 2, 4, 3, 2 ; PPC64LE-NEXT: addis 4, 2, .LCPI4_2@toc@ha
; PPC64LE-NEXT: vspltisw 3, -11 ; PPC64LE-NEXT: lxvd2x 1, 0, 6
; PPC64LE-NEXT: lvx 4, 0, 3 ; PPC64LE-NEXT: mtvsrwz 36, 5
; PPC64LE-NEXT: xxmrghw 34, 2, 0
; PPC64LE-NEXT: lxvd2x 0, 0, 3
; PPC64LE-NEXT: addi 3, 4, .LCPI4_2@toc@l ; PPC64LE-NEXT: addi 3, 4, .LCPI4_2@toc@l
; PPC64LE-NEXT: addis 4, 2, .LCPI4_4@toc@ha ; PPC64LE-NEXT: addis 4, 2, .LCPI4_4@toc@ha
; PPC64LE-NEXT: lvx 5, 0, 3
; PPC64LE-NEXT: addis 3, 2, .LCPI4_3@toc@ha
; PPC64LE-NEXT: addi 4, 4, .LCPI4_4@toc@l ; PPC64LE-NEXT: addi 4, 4, .LCPI4_4@toc@l
; PPC64LE-NEXT: xxswapd 35, 1
; PPC64LE-NEXT: lxvd2x 1, 0, 3
; PPC64LE-NEXT: addis 3, 2, .LCPI4_3@toc@ha
; PPC64LE-NEXT: addi 3, 3, .LCPI4_3@toc@l ; PPC64LE-NEXT: addi 3, 3, .LCPI4_3@toc@l
; PPC64LE-NEXT: vsrw 3, 3, 3 ; PPC64LE-NEXT: vperm 2, 4, 2, 3
; PPC64LE-NEXT: vsubuwm 2, 2, 4 ; PPC64LE-NEXT: vspltisw 3, -11
; PPC64LE-NEXT: lvx 4, 0, 3 ; PPC64LE-NEXT: xxswapd 36, 0
; PPC64LE-NEXT: xxswapd 37, 1
; PPC64LE-NEXT: lxvd2x 0, 0, 3
; PPC64LE-NEXT: lxvd2x 1, 0, 4
; PPC64LE-NEXT: addis 3, 2, .LCPI4_5@toc@ha ; PPC64LE-NEXT: addis 3, 2, .LCPI4_5@toc@ha
; PPC64LE-NEXT: addi 3, 3, .LCPI4_5@toc@l ; PPC64LE-NEXT: addi 3, 3, .LCPI4_5@toc@l
; PPC64LE-NEXT: vsrw 3, 3, 3
; PPC64LE-NEXT: vsubuwm 2, 2, 4
; PPC64LE-NEXT: xxswapd 36, 0
; PPC64LE-NEXT: lxvd2x 0, 0, 3
; PPC64LE-NEXT: vmuluwm 2, 2, 5 ; PPC64LE-NEXT: vmuluwm 2, 2, 5
; PPC64LE-NEXT: lvx 5, 0, 4 ; PPC64LE-NEXT: xxswapd 37, 1
; PPC64LE-NEXT: xxland 32, 34, 35 ; PPC64LE-NEXT: xxland 32, 34, 35
; PPC64LE-NEXT: vslw 2, 2, 4 ; PPC64LE-NEXT: vslw 2, 2, 4
; PPC64LE-NEXT: vsrw 4, 0, 5 ; PPC64LE-NEXT: vsrw 4, 0, 5
; PPC64LE-NEXT: xxlor 0, 36, 34 ; PPC64LE-NEXT: xxlor 1, 36, 34
; PPC64LE-NEXT: lvx 2, 0, 3 ; PPC64LE-NEXT: xxswapd 34, 0
; PPC64LE-NEXT: xxland 35, 0, 35 ; PPC64LE-NEXT: xxland 35, 1, 35
; PPC64LE-NEXT: vcmpgtuw 2, 3, 2 ; PPC64LE-NEXT: vcmpgtuw 2, 3, 2
; PPC64LE-NEXT: xxswapd 0, 34 ; PPC64LE-NEXT: xxswapd 0, 34
; PPC64LE-NEXT: xxsldwi 1, 34, 34, 1 ; PPC64LE-NEXT: xxsldwi 1, 34, 34, 1
; PPC64LE-NEXT: mfvsrwz 5, 34 ; PPC64LE-NEXT: mfvsrwz 5, 34
; PPC64LE-NEXT: mffprwz 3, 0 ; PPC64LE-NEXT: mffprwz 3, 0
; PPC64LE-NEXT: mffprwz 4, 1 ; PPC64LE-NEXT: mffprwz 4, 1
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%urem = urem <3 x i11> %X, <i11 6, i11 7, i11 -5> %urem = urem <3 x i11> %X, <i11 6, i11 7, i11 -5>
▲ Show 20 Lines • Show All 78 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/vavg.ll

Show First 20 Lines • Show All 144 Lines • ▼ Show 20 Lines
; CHECK-P9-NEXT: vspltish 3, 1 ; CHECK-P9-NEXT: vspltish 3, 1
; CHECK-P9-NEXT: vsrah 2, 2, 3 ; CHECK-P9-NEXT: vsrah 2, 2, 3
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-P8-LABEL: test_v8i16_sign_negative: ; CHECK-P8-LABEL: test_v8i16_sign_negative:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: addis 3, 2, .LCPI6_0@toc@ha ; CHECK-P8-NEXT: addis 3, 2, .LCPI6_0@toc@ha
; CHECK-P8-NEXT: vadduhm 2, 2, 3 ; CHECK-P8-NEXT: vadduhm 2, 2, 3
; CHECK-P8-NEXT: vspltish 4, 1 ; CHECK-P8-NEXT: vspltish 3, 1
; CHECK-P8-NEXT: addi 3, 3, .LCPI6_0@toc@l ; CHECK-P8-NEXT: addi 3, 3, .LCPI6_0@toc@l
; CHECK-P8-NEXT: lvx 3, 0, 3 ; CHECK-P8-NEXT: lxvd2x 0, 0, 3
; CHECK-P8-NEXT: vadduhm 2, 2, 3 ; CHECK-P8-NEXT: xxswapd 36, 0
; CHECK-P8-NEXT: vsrah 2, 2, 4 ; CHECK-P8-NEXT: vadduhm 2, 2, 4
; CHECK-P8-NEXT: vsrah 2, 2, 3
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P7-LABEL: test_v8i16_sign_negative: ; CHECK-P7-LABEL: test_v8i16_sign_negative:
; CHECK-P7: # %bb.0: # %entry ; CHECK-P7: # %bb.0: # %entry
; CHECK-P7-NEXT: addis 3, 2, .LCPI6_0@toc@ha ; CHECK-P7-NEXT: addis 3, 2, .LCPI6_0@toc@ha
; CHECK-P7-NEXT: vadduhm 2, 2, 3 ; CHECK-P7-NEXT: vadduhm 2, 2, 3
; CHECK-P7-NEXT: vspltish 4, 1 ; CHECK-P7-NEXT: vspltish 3, 1
; CHECK-P7-NEXT: addi 3, 3, .LCPI6_0@toc@l ; CHECK-P7-NEXT: addi 3, 3, .LCPI6_0@toc@l
; CHECK-P7-NEXT: lvx 3, 0, 3 ; CHECK-P7-NEXT: lxvd2x 0, 0, 3
; CHECK-P7-NEXT: vadduhm 2, 2, 3 ; CHECK-P7-NEXT: xxswapd 36, 0
; CHECK-P7-NEXT: vsrah 2, 2, 4 ; CHECK-P7-NEXT: vadduhm 2, 2, 4
; CHECK-P7-NEXT: vsrah 2, 2, 3
; CHECK-P7-NEXT: blr ; CHECK-P7-NEXT: blr
entry: entry:
%add = add <8 x i16> %m, <i16 1, i16 1, i16 1, i16 -1, i16 1, i16 1, i16 1, i16 1> %add = add <8 x i16> %m, <i16 1, i16 1, i16 1, i16 -1, i16 1, i16 1, i16 1, i16 1>
%add1 = add <8 x i16> %add, %n %add1 = add <8 x i16> %add, %n
%shr = ashr <8 x i16> %add1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1> %shr = ashr <8 x i16> %add1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
ret <8 x i16> %shr ret <8 x i16> %shr
} }
▲ Show 20 Lines • Show All 64 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/vec-icmpeq-v2i64-p7.ll

Show All 18 Lines
; CHECK-NEXT: lwz 3, -12(1) ; CHECK-NEXT: lwz 3, -12(1)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK_LE-LABEL: shufeq: ; CHECK_LE-LABEL: shufeq:
; CHECK_LE: # %bb.0: # %entry ; CHECK_LE: # %bb.0: # %entry
; CHECK_LE-NEXT: xxswapd 35, 34 ; CHECK_LE-NEXT: xxswapd 35, 34
; CHECK_LE-NEXT: addis 3, 2, .LCPI0_0@toc@ha ; CHECK_LE-NEXT: addis 3, 2, .LCPI0_0@toc@ha
; CHECK_LE-NEXT: addi 3, 3, .LCPI0_0@toc@l ; CHECK_LE-NEXT: addi 3, 3, .LCPI0_0@toc@l
; CHECK_LE-NEXT: vcmpequw 2, 2, 3 ; CHECK_LE-NEXT: lxvd2x 0, 0, 3
; CHECK_LE-NEXT: lvx 3, 0, 3
; CHECK_LE-NEXT: addi 3, 1, -16 ; CHECK_LE-NEXT: addi 3, 1, -16
; CHECK_LE-NEXT: vcmpequw 2, 2, 3
; CHECK_LE-NEXT: xxswapd 35, 0
; CHECK_LE-NEXT: vperm 3, 2, 2, 3 ; CHECK_LE-NEXT: vperm 3, 2, 2, 3
; CHECK_LE-NEXT: xxland 34, 35, 34 ; CHECK_LE-NEXT: xxland 0, 35, 34
; CHECK_LE-NEXT: stvx 2, 0, 3 ; CHECK_LE-NEXT: xxswapd 0, 0
; CHECK_LE-NEXT: stxvd2x 0, 0, 3
; CHECK_LE-NEXT: ld 3, -16(1) ; CHECK_LE-NEXT: ld 3, -16(1)
; CHECK_LE-NEXT: blr ; CHECK_LE-NEXT: blr
; ;
; CHECK_P8LE-LABEL: shufeq: ; CHECK_P8LE-LABEL: shufeq:
; CHECK_P8LE: # %bb.0: # %entry ; CHECK_P8LE: # %bb.0: # %entry
; CHECK_P8LE-NEXT: xxswapd 35, 34 ; CHECK_P8LE-NEXT: xxswapd 35, 34
; CHECK_P8LE-NEXT: vcmpequd 2, 2, 3 ; CHECK_P8LE-NEXT: vcmpequd 2, 2, 3
; CHECK_P8LE-NEXT: xxswapd 0, 34 ; CHECK_P8LE-NEXT: xxswapd 0, 34
Show All 20 Lines
; CHECK-NEXT: lwz 3, -12(1) ; CHECK-NEXT: lwz 3, -12(1)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK_LE-LABEL: shufne: ; CHECK_LE-LABEL: shufne:
; CHECK_LE: # %bb.0: # %entry ; CHECK_LE: # %bb.0: # %entry
; CHECK_LE-NEXT: xxswapd 35, 34 ; CHECK_LE-NEXT: xxswapd 35, 34
; CHECK_LE-NEXT: addis 3, 2, .LCPI1_0@toc@ha ; CHECK_LE-NEXT: addis 3, 2, .LCPI1_0@toc@ha
; CHECK_LE-NEXT: addi 3, 3, .LCPI1_0@toc@l ; CHECK_LE-NEXT: addi 3, 3, .LCPI1_0@toc@l
; CHECK_LE-NEXT: vcmpequw 2, 2, 3 ; CHECK_LE-NEXT: lxvd2x 0, 0, 3
; CHECK_LE-NEXT: lvx 3, 0, 3
; CHECK_LE-NEXT: addi 3, 1, -16 ; CHECK_LE-NEXT: addi 3, 1, -16
; CHECK_LE-NEXT: vcmpequw 2, 2, 3
; CHECK_LE-NEXT: xxswapd 35, 0
; CHECK_LE-NEXT: vperm 3, 2, 2, 3 ; CHECK_LE-NEXT: vperm 3, 2, 2, 3
; CHECK_LE-NEXT: xxland 34, 35, 34 ; CHECK_LE-NEXT: xxland 0, 35, 34
; CHECK_LE-NEXT: stvx 2, 0, 3 ; CHECK_LE-NEXT: xxswapd 0, 0
; CHECK_LE-NEXT: stxvd2x 0, 0, 3
; CHECK_LE-NEXT: ld 3, -16(1) ; CHECK_LE-NEXT: ld 3, -16(1)
; CHECK_LE-NEXT: blr ; CHECK_LE-NEXT: blr
; ;
; CHECK_P8LE-LABEL: shufne: ; CHECK_P8LE-LABEL: shufne:
; CHECK_P8LE: # %bb.0: # %entry ; CHECK_P8LE: # %bb.0: # %entry
; CHECK_P8LE-NEXT: xxswapd 35, 34 ; CHECK_P8LE-NEXT: xxswapd 35, 34
; CHECK_P8LE-NEXT: vcmpequd 2, 2, 3 ; CHECK_P8LE-NEXT: vcmpequd 2, 2, 3
; CHECK_P8LE-NEXT: xxswapd 0, 34 ; CHECK_P8LE-NEXT: xxswapd 0, 34
Show All 13 Lines
; CHECK-NEXT: vcmpequw 2, 2, 3 ; CHECK-NEXT: vcmpequw 2, 2, 3
; CHECK-NEXT: lxvw4x 35, 0, 3 ; CHECK-NEXT: lxvw4x 35, 0, 3
; CHECK-NEXT: vperm 3, 2, 2, 3 ; CHECK-NEXT: vperm 3, 2, 2, 3
; CHECK-NEXT: xxland 34, 35, 34 ; CHECK-NEXT: xxland 34, 35, 34
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK_LE-LABEL: cmpeq: ; CHECK_LE-LABEL: cmpeq:
; CHECK_LE: # %bb.0: # %entry ; CHECK_LE: # %bb.0: # %entry
; CHECK_LE-NEXT: vcmpequw 2, 2, 3
; CHECK_LE-NEXT: addis 3, 2, .LCPI2_0@toc@ha ; CHECK_LE-NEXT: addis 3, 2, .LCPI2_0@toc@ha
; CHECK_LE-NEXT: vcmpequw 2, 2, 3
; CHECK_LE-NEXT: addi 3, 3, .LCPI2_0@toc@l ; CHECK_LE-NEXT: addi 3, 3, .LCPI2_0@toc@l
; CHECK_LE-NEXT: lvx 3, 0, 3 ; CHECK_LE-NEXT: lxvd2x 0, 0, 3
; CHECK_LE-NEXT: xxswapd 35, 0
; CHECK_LE-NEXT: vperm 3, 2, 2, 3 ; CHECK_LE-NEXT: vperm 3, 2, 2, 3
; CHECK_LE-NEXT: xxland 34, 35, 34 ; CHECK_LE-NEXT: xxland 34, 35, 34
; CHECK_LE-NEXT: blr ; CHECK_LE-NEXT: blr
; ;
; CHECK_P8LE-LABEL: cmpeq: ; CHECK_P8LE-LABEL: cmpeq:
; CHECK_P8LE: # %bb.0: # %entry ; CHECK_P8LE: # %bb.0: # %entry
; CHECK_P8LE-NEXT: vcmpequd 2, 2, 3 ; CHECK_P8LE-NEXT: vcmpequd 2, 2, 3
; CHECK_P8LE-NEXT: blr ; CHECK_P8LE-NEXT: blr
Show All 11 Lines
; CHECK-NEXT: lxvw4x 35, 0, 3 ; CHECK-NEXT: lxvw4x 35, 0, 3
; CHECK-NEXT: xxlnor 34, 34, 34 ; CHECK-NEXT: xxlnor 34, 34, 34
; CHECK-NEXT: vperm 3, 2, 2, 3 ; CHECK-NEXT: vperm 3, 2, 2, 3
; CHECK-NEXT: xxlor 34, 35, 34 ; CHECK-NEXT: xxlor 34, 35, 34
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK_LE-LABEL: cmpne: ; CHECK_LE-LABEL: cmpne:
; CHECK_LE: # %bb.0: # %entry ; CHECK_LE: # %bb.0: # %entry
; CHECK_LE-NEXT: vcmpequw 2, 2, 3
; CHECK_LE-NEXT: addis 3, 2, .LCPI3_0@toc@ha ; CHECK_LE-NEXT: addis 3, 2, .LCPI3_0@toc@ha
; CHECK_LE-NEXT: vcmpequw 2, 2, 3
; CHECK_LE-NEXT: addi 3, 3, .LCPI3_0@toc@l ; CHECK_LE-NEXT: addi 3, 3, .LCPI3_0@toc@l
; CHECK_LE-NEXT: lvx 3, 0, 3 ; CHECK_LE-NEXT: lxvd2x 0, 0, 3
; CHECK_LE-NEXT: xxswapd 35, 0
; CHECK_LE-NEXT: xxlnor 34, 34, 34 ; CHECK_LE-NEXT: xxlnor 34, 34, 34
; CHECK_LE-NEXT: vperm 3, 2, 2, 3 ; CHECK_LE-NEXT: vperm 3, 2, 2, 3
; CHECK_LE-NEXT: xxlor 34, 35, 34 ; CHECK_LE-NEXT: xxlor 34, 35, 34
; CHECK_LE-NEXT: blr ; CHECK_LE-NEXT: blr
; ;
; CHECK_P8LE-LABEL: cmpne: ; CHECK_P8LE-LABEL: cmpne:
; CHECK_P8LE: # %bb.0: # %entry ; CHECK_P8LE: # %bb.0: # %entry
; CHECK_P8LE-NEXT: vcmpequd 2, 2, 3 ; CHECK_P8LE-NEXT: vcmpequd 2, 2, 3
; CHECK_P8LE-NEXT: xxlnor 34, 34, 34 ; CHECK_P8LE-NEXT: xxlnor 34, 34, 34
; CHECK_P8LE-NEXT: blr ; CHECK_P8LE-NEXT: blr
entry: entry:
%cmp = icmp ne <2 x i64> %a, %b %cmp = icmp ne <2 x i64> %a, %b
%sext = sext <2 x i1> %cmp to <2 x i64> %sext = sext <2 x i1> %cmp to <2 x i64>
ret <2 x i64> %sext ret <2 x i64> %sext
} }

llvm/test/CodeGen/PowerPC/vec-itofp.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \ ; RUN: -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
; RUN: FileCheck %s --check-prefix=CHECK-P8 ; RUN: FileCheck %s --check-prefix=CHECK-P8
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \ ; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
; RUN: FileCheck %s --check-prefix=CHECK-P9 ; RUN: FileCheck %s --check-prefix=CHECK-P9
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \ ; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
; RUN: FileCheck %s --check-prefix=CHECK-BE ; RUN: FileCheck %s --check-prefix=CHECK-BE
define void @test8(<8 x double>* nocapture %Sink, <8 x i16>* nocapture readonly %SrcPtr) { define void @test8(<8 x double>* nocapture %Sink, <8 x i16>* nocapture readonly %SrcPtr) {
; CHECK-P8-LABEL: test8: ; CHECK-P8-LABEL: test8:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: addis r5, r2, .LCPI0_0@toc@ha ; CHECK-P8-NEXT: addis r5, r2, .LCPI0_0@toc@ha
; CHECK-P8-NEXT: addis r6, r2, .LCPI0_2@toc@ha ; CHECK-P8-NEXT: addis r6, r2, .LCPI0_2@toc@ha
; CHECK-P8-NEXT: lvx v3, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r4
; CHECK-P8-NEXT: addis r4, r2, .LCPI0_1@toc@ha ; CHECK-P8-NEXT: addis r4, r2, .LCPI0_3@toc@ha
; CHECK-P8-NEXT: xxlxor v4, v4, v4 ; CHECK-P8-NEXT: xxlxor v4, v4, v4
; CHECK-P8-NEXT: addi r5, r5, .LCPI0_0@toc@l ; CHECK-P8-NEXT: addi r5, r5, .LCPI0_0@toc@l
; CHECK-P8-NEXT: addi r6, r6, .LCPI0_2@toc@l ; CHECK-P8-NEXT: addi r4, r4, .LCPI0_3@toc@l
; CHECK-P8-NEXT: addi r4, r4, .LCPI0_1@toc@l ; CHECK-P8-NEXT: lxvd2x vs1, 0, r5
; CHECK-P8-NEXT: lvx v2, 0, r5 ; CHECK-P8-NEXT: addi r5, r6, .LCPI0_2@toc@l
; CHECK-P8-NEXT: addis r5, r2, .LCPI0_3@toc@ha ; CHECK-P8-NEXT: lxvd2x vs3, 0, r4
; CHECK-P8-NEXT: lvx v5, 0, r6
; CHECK-P8-NEXT: lvx v1, 0, r4
; CHECK-P8-NEXT: li r4, 48 ; CHECK-P8-NEXT: li r4, 48
; CHECK-P8-NEXT: addi r5, r5, .LCPI0_3@toc@l ; CHECK-P8-NEXT: lxvd2x vs2, 0, r5
; CHECK-P8-NEXT: lvx v0, 0, r5 ; CHECK-P8-NEXT: addis r5, r2, .LCPI0_1@toc@ha
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: addi r5, r5, .LCPI0_1@toc@l
; CHECK-P8-NEXT: lxvd2x vs4, 0, r5
; CHECK-P8-NEXT: xxswapd v0, vs3
; CHECK-P8-NEXT: xxswapd v3, vs1
; CHECK-P8-NEXT: li r5, 32 ; CHECK-P8-NEXT: li r5, 32
; CHECK-P8-NEXT: vperm v2, v4, v3, v2 ; CHECK-P8-NEXT: xxswapd v5, vs2
; CHECK-P8-NEXT: vperm v5, v4, v3, v5 ; CHECK-P8-NEXT: xxswapd v1, vs4
; CHECK-P8-NEXT: vperm v0, v4, v3, v0 ; CHECK-P8-NEXT: vperm v0, v4, v2, v0
; CHECK-P8-NEXT: vperm v3, v4, v3, v1 ; CHECK-P8-NEXT: vperm v3, v4, v2, v3
; CHECK-P8-NEXT: xvcvuxddp vs0, v2 ; CHECK-P8-NEXT: vperm v5, v4, v2, v5
; CHECK-P8-NEXT: xvcvuxddp vs1, v5 ; CHECK-P8-NEXT: vperm v2, v4, v2, v1
; CHECK-P8-NEXT: xvcvuxddp vs2, v0 ; CHECK-P8-NEXT: xvcvuxddp vs2, v0
; CHECK-P8-NEXT: xvcvuxddp vs3, v3 ; CHECK-P8-NEXT: xvcvuxddp vs0, v3
; CHECK-P8-NEXT: xvcvuxddp vs1, v5
; CHECK-P8-NEXT: xvcvuxddp vs3, v2
; CHECK-P8-NEXT: xxswapd vs2, vs2
; CHECK-P8-NEXT: xxswapd vs0, vs0 ; CHECK-P8-NEXT: xxswapd vs0, vs0
; CHECK-P8-NEXT: xxswapd vs1, vs1 ; CHECK-P8-NEXT: xxswapd vs1, vs1
; CHECK-P8-NEXT: xxswapd vs2, vs2
; CHECK-P8-NEXT: xxswapd vs3, vs3 ; CHECK-P8-NEXT: xxswapd vs3, vs3
; CHECK-P8-NEXT: stxvd2x vs2, r3, r4 ; CHECK-P8-NEXT: stxvd2x vs2, r3, r4
; CHECK-P8-NEXT: li r4, 16 ; CHECK-P8-NEXT: li r4, 16
; CHECK-P8-NEXT: stxvd2x vs1, r3, r5 ; CHECK-P8-NEXT: stxvd2x vs1, r3, r5
; CHECK-P8-NEXT: stxvd2x vs3, r3, r4 ; CHECK-P8-NEXT: stxvd2x vs3, r3, r4
; CHECK-P8-NEXT: stxvd2x vs0, 0, r3 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r3
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
▲ Show 20 Lines • Show All 63 Lines • ▼ Show 20 Linesentry:
ret void ret void
} }
define void @test4(<4 x double>* nocapture %Sink, <4 x i16>* nocapture readonly %SrcPtr) { define void @test4(<4 x double>* nocapture %Sink, <4 x i16>* nocapture readonly %SrcPtr) {
; CHECK-P8-LABEL: test4: ; CHECK-P8-LABEL: test4:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: addis r5, r2, .LCPI1_0@toc@ha ; CHECK-P8-NEXT: addis r5, r2, .LCPI1_0@toc@ha
; CHECK-P8-NEXT: addis r6, r2, .LCPI1_1@toc@ha ; CHECK-P8-NEXT: addis r6, r2, .LCPI1_1@toc@ha
; CHECK-P8-NEXT: lvx v3, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r4
; CHECK-P8-NEXT: xxlxor v4, v4, v4 ; CHECK-P8-NEXT: xxlxor v4, v4, v4
; CHECK-P8-NEXT: li r4, 16
; CHECK-P8-NEXT: addi r5, r5, .LCPI1_0@toc@l ; CHECK-P8-NEXT: addi r5, r5, .LCPI1_0@toc@l
; CHECK-P8-NEXT: lvx v2, 0, r5 ; CHECK-P8-NEXT: addi r4, r6, .LCPI1_1@toc@l
; CHECK-P8-NEXT: addi r5, r6, .LCPI1_1@toc@l ; CHECK-P8-NEXT: lxvd2x vs1, 0, r5
; CHECK-P8-NEXT: lvx v5, 0, r5 ; CHECK-P8-NEXT: lxvd2x vs2, 0, r4
; CHECK-P8-NEXT: vperm v2, v4, v3, v2 ; CHECK-P8-NEXT: li r4, 16
; CHECK-P8-NEXT: vperm v3, v4, v3, v5 ; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: xvcvuxddp vs0, v2 ; CHECK-P8-NEXT: xxswapd v3, vs1
; CHECK-P8-NEXT: xvcvuxddp vs1, v3 ; CHECK-P8-NEXT: xxswapd v5, vs2
; CHECK-P8-NEXT: vperm v3, v4, v2, v3
; CHECK-P8-NEXT: vperm v2, v4, v2, v5
; CHECK-P8-NEXT: xvcvuxddp vs0, v3
; CHECK-P8-NEXT: xvcvuxddp vs1, v2
; CHECK-P8-NEXT: xxswapd vs0, vs0 ; CHECK-P8-NEXT: xxswapd vs0, vs0
; CHECK-P8-NEXT: xxswapd vs1, vs1 ; CHECK-P8-NEXT: xxswapd vs1, vs1
; CHECK-P8-NEXT: stxvd2x vs1, r3, r4 ; CHECK-P8-NEXT: stxvd2x vs1, r3, r4
; CHECK-P8-NEXT: stxvd2x vs0, 0, r3 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r3
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test4: ; CHECK-P9-LABEL: test4:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
Show All 36 Linesentry:
store <4 x double> %1, <4 x double>* %Sink, align 16 store <4 x double> %1, <4 x double>* %Sink, align 16
ret void ret void
} }
define void @test2(<2 x double>* nocapture %Sink, <2 x i16>* nocapture readonly %SrcPtr) { define void @test2(<2 x double>* nocapture %Sink, <2 x i16>* nocapture readonly %SrcPtr) {
; CHECK-P8-LABEL: test2: ; CHECK-P8-LABEL: test2:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: addis r5, r2, .LCPI2_0@toc@ha ; CHECK-P8-NEXT: addis r5, r2, .LCPI2_0@toc@ha
; CHECK-P8-NEXT: lvx v3, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r4
; CHECK-P8-NEXT: xxlxor v4, v4, v4 ; CHECK-P8-NEXT: xxlxor v4, v4, v4
; CHECK-P8-NEXT: addi r5, r5, .LCPI2_0@toc@l ; CHECK-P8-NEXT: addi r5, r5, .LCPI2_0@toc@l
; CHECK-P8-NEXT: lvx v2, 0, r5 ; CHECK-P8-NEXT: lxvd2x vs1, 0, r5
; CHECK-P8-NEXT: vperm v2, v4, v3, v2 ; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: xxswapd v3, vs1
; CHECK-P8-NEXT: vperm v2, v4, v2, v3
; CHECK-P8-NEXT: xvcvuxddp vs0, v2 ; CHECK-P8-NEXT: xvcvuxddp vs0, v2
; CHECK-P8-NEXT: xxswapd vs0, vs0 ; CHECK-P8-NEXT: xxswapd vs0, vs0
; CHECK-P8-NEXT: stxvd2x vs0, 0, r3 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r3
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test2: ; CHECK-P9-LABEL: test2:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lxv v2, 0(r4) ; CHECK-P9-NEXT: lxv v2, 0(r4)
Show All 24 Linesentry:
ret void ret void
} }
define void @stest8(<8 x double>* nocapture %Sink, <8 x i16>* nocapture readonly %SrcPtr) { define void @stest8(<8 x double>* nocapture %Sink, <8 x i16>* nocapture readonly %SrcPtr) {
; CHECK-P8-LABEL: stest8: ; CHECK-P8-LABEL: stest8:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: addis r5, r2, .LCPI3_0@toc@ha ; CHECK-P8-NEXT: addis r5, r2, .LCPI3_0@toc@ha
; CHECK-P8-NEXT: addis r6, r2, .LCPI3_2@toc@ha ; CHECK-P8-NEXT: addis r6, r2, .LCPI3_2@toc@ha
; CHECK-P8-NEXT: lvx v3, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r4
; CHECK-P8-NEXT: addis r4, r2, .LCPI3_1@toc@ha ; CHECK-P8-NEXT: addis r4, r2, .LCPI3_3@toc@ha
; CHECK-P8-NEXT: addi r5, r5, .LCPI3_0@toc@l ; CHECK-P8-NEXT: addi r5, r5, .LCPI3_0@toc@l
; CHECK-P8-NEXT: addi r6, r6, .LCPI3_2@toc@l ; CHECK-P8-NEXT: addi r4, r4, .LCPI3_3@toc@l
; CHECK-P8-NEXT: lxvd2x vs1, 0, r5
; CHECK-P8-NEXT: addi r5, r6, .LCPI3_2@toc@l
; CHECK-P8-NEXT: lxvd2x vs3, 0, r4
; CHECK-P8-NEXT: addis r4, r2, .LCPI3_1@toc@ha
; CHECK-P8-NEXT: lxvd2x vs2, 0, r5
; CHECK-P8-NEXT: addis r5, r2, .LCPI3_4@toc@ha
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: addi r4, r4, .LCPI3_1@toc@l ; CHECK-P8-NEXT: addi r4, r4, .LCPI3_1@toc@l
; CHECK-P8-NEXT: lvx v2, 0, r5 ; CHECK-P8-NEXT: addi r5, r5, .LCPI3_4@toc@l
; CHECK-P8-NEXT: addis r5, r2, .LCPI3_3@toc@ha
; CHECK-P8-NEXT: lvx v4, 0, r6
; CHECK-P8-NEXT: addis r6, r2, .LCPI3_4@toc@ha
; CHECK-P8-NEXT: lxvd2x vs0, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r4
; CHECK-P8-NEXT: li r4, 48 ; CHECK-P8-NEXT: li r4, 48
; CHECK-P8-NEXT: addi r5, r5, .LCPI3_3@toc@l ; CHECK-P8-NEXT: lxvd2x vs4, 0, r5
; CHECK-P8-NEXT: lvx v5, 0, r5 ; CHECK-P8-NEXT: xxswapd v3, vs1
; CHECK-P8-NEXT: addi r5, r6, .LCPI3_4@toc@l ; CHECK-P8-NEXT: xxswapd v5, vs3
; CHECK-P8-NEXT: lvx v0, 0, r5
; CHECK-P8-NEXT: vperm v2, v3, v3, v2
; CHECK-P8-NEXT: li r5, 32 ; CHECK-P8-NEXT: li r5, 32
; CHECK-P8-NEXT: vperm v4, v3, v3, v4 ; CHECK-P8-NEXT: xxswapd v4, vs2
; CHECK-P8-NEXT: vperm v5, v3, v3, v5 ; CHECK-P8-NEXT: xxswapd v0, vs4
; CHECK-P8-NEXT: vperm v3, v3, v3, v0 ; CHECK-P8-NEXT: vperm v3, v2, v2, v3
; CHECK-P8-NEXT: vperm v4, v2, v2, v4
; CHECK-P8-NEXT: vperm v5, v2, v2, v5
; CHECK-P8-NEXT: vperm v2, v2, v2, v0
; CHECK-P8-NEXT: xxswapd v0, vs0 ; CHECK-P8-NEXT: xxswapd v0, vs0
; CHECK-P8-NEXT: vsld v2, v2, v0 ; CHECK-P8-NEXT: vsld v3, v3, v0
; CHECK-P8-NEXT: vsld v4, v4, v0 ; CHECK-P8-NEXT: vsld v4, v4, v0
; CHECK-P8-NEXT: vsld v5, v5, v0 ; CHECK-P8-NEXT: vsld v5, v5, v0
; CHECK-P8-NEXT: vsld v3, v3, v0 ; CHECK-P8-NEXT: vsld v2, v2, v0
; CHECK-P8-NEXT: vsrad v2, v2, v0
; CHECK-P8-NEXT: vsrad v3, v3, v0 ; CHECK-P8-NEXT: vsrad v3, v3, v0
; CHECK-P8-NEXT: vsrad v2, v2, v0
; CHECK-P8-NEXT: vsrad v4, v4, v0 ; CHECK-P8-NEXT: vsrad v4, v4, v0
; CHECK-P8-NEXT: vsrad v5, v5, v0 ; CHECK-P8-NEXT: vsrad v5, v5, v0
; CHECK-P8-NEXT: xvcvsxddp vs2, v3 ; CHECK-P8-NEXT: xvcvsxddp vs2, v2
; CHECK-P8-NEXT: xvcvsxddp vs0, v2 ; CHECK-P8-NEXT: xvcvsxddp vs0, v3
; CHECK-P8-NEXT: xvcvsxddp vs1, v5 ; CHECK-P8-NEXT: xvcvsxddp vs1, v5
; CHECK-P8-NEXT: xvcvsxddp vs3, v4 ; CHECK-P8-NEXT: xvcvsxddp vs3, v4
; CHECK-P8-NEXT: xxswapd vs2, vs2 ; CHECK-P8-NEXT: xxswapd vs2, vs2
; CHECK-P8-NEXT: xxswapd vs0, vs0 ; CHECK-P8-NEXT: xxswapd vs0, vs0
; CHECK-P8-NEXT: xxswapd vs1, vs1 ; CHECK-P8-NEXT: xxswapd vs1, vs1
; CHECK-P8-NEXT: xxswapd vs3, vs3 ; CHECK-P8-NEXT: xxswapd vs3, vs3
; CHECK-P8-NEXT: stxvd2x vs2, r3, r4 ; CHECK-P8-NEXT: stxvd2x vs2, r3, r4
; CHECK-P8-NEXT: li r4, 16 ; CHECK-P8-NEXT: li r4, 16
▲ Show 20 Lines • Show All 74 Lines • ▼ Show 20 Linesentry:
ret void ret void
} }
define void @stest4(<4 x double>* nocapture %Sink, <4 x i16>* nocapture readonly %SrcPtr) { define void @stest4(<4 x double>* nocapture %Sink, <4 x i16>* nocapture readonly %SrcPtr) {
; CHECK-P8-LABEL: stest4: ; CHECK-P8-LABEL: stest4:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: addis r5, r2, .LCPI4_0@toc@ha ; CHECK-P8-NEXT: addis r5, r2, .LCPI4_0@toc@ha
; CHECK-P8-NEXT: addis r6, r2, .LCPI4_2@toc@ha ; CHECK-P8-NEXT: addis r6, r2, .LCPI4_2@toc@ha
; CHECK-P8-NEXT: lvx v3, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r4
; CHECK-P8-NEXT: addis r4, r2, .LCPI4_1@toc@ha
; CHECK-P8-NEXT: addi r5, r5, .LCPI4_0@toc@l ; CHECK-P8-NEXT: addi r5, r5, .LCPI4_0@toc@l
; CHECK-P8-NEXT: addi r4, r6, .LCPI4_2@toc@l
; CHECK-P8-NEXT: lxvd2x vs1, 0, r5
; CHECK-P8-NEXT: lxvd2x vs2, 0, r4
; CHECK-P8-NEXT: addis r4, r2, .LCPI4_1@toc@ha
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: addi r4, r4, .LCPI4_1@toc@l ; CHECK-P8-NEXT: addi r4, r4, .LCPI4_1@toc@l
; CHECK-P8-NEXT: lvx v2, 0, r5
; CHECK-P8-NEXT: addi r5, r6, .LCPI4_2@toc@l
; CHECK-P8-NEXT: lxvd2x vs0, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r4
; CHECK-P8-NEXT: li r4, 16 ; CHECK-P8-NEXT: li r4, 16
; CHECK-P8-NEXT: lvx v4, 0, r5 ; CHECK-P8-NEXT: xxswapd v3, vs1
; CHECK-P8-NEXT: vperm v2, v3, v3, v2 ; CHECK-P8-NEXT: xxswapd v4, vs2
; CHECK-P8-NEXT: vperm v3, v3, v3, v4 ; CHECK-P8-NEXT: vperm v3, v2, v2, v3
; CHECK-P8-NEXT: vperm v2, v2, v2, v4
; CHECK-P8-NEXT: xxswapd v4, vs0 ; CHECK-P8-NEXT: xxswapd v4, vs0
; CHECK-P8-NEXT: vsld v2, v2, v4
; CHECK-P8-NEXT: vsld v3, v3, v4 ; CHECK-P8-NEXT: vsld v3, v3, v4
; CHECK-P8-NEXT: vsrad v2, v2, v4 ; CHECK-P8-NEXT: vsld v2, v2, v4
; CHECK-P8-NEXT: vsrad v3, v3, v4 ; CHECK-P8-NEXT: vsrad v3, v3, v4
; CHECK-P8-NEXT: xvcvsxddp vs0, v2 ; CHECK-P8-NEXT: vsrad v2, v2, v4
; CHECK-P8-NEXT: xvcvsxddp vs1, v3 ; CHECK-P8-NEXT: xvcvsxddp vs0, v3
; CHECK-P8-NEXT: xvcvsxddp vs1, v2
; CHECK-P8-NEXT: xxswapd vs0, vs0 ; CHECK-P8-NEXT: xxswapd vs0, vs0
; CHECK-P8-NEXT: xxswapd vs1, vs1 ; CHECK-P8-NEXT: xxswapd vs1, vs1
; CHECK-P8-NEXT: stxvd2x vs1, r3, r4 ; CHECK-P8-NEXT: stxvd2x vs1, r3, r4
; CHECK-P8-NEXT: stxvd2x vs0, 0, r3 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r3
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: stest4: ; CHECK-P9-LABEL: stest4:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
Show All 38 Linesentry:
store <4 x double> %1, <4 x double>* %Sink, align 16 store <4 x double> %1, <4 x double>* %Sink, align 16
ret void ret void
} }
define void @stest2(<2 x double>* nocapture %Sink, <2 x i16>* nocapture readonly %SrcPtr) { define void @stest2(<2 x double>* nocapture %Sink, <2 x i16>* nocapture readonly %SrcPtr) {
; CHECK-P8-LABEL: stest2: ; CHECK-P8-LABEL: stest2:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: addis r5, r2, .LCPI5_0@toc@ha ; CHECK-P8-NEXT: addis r5, r2, .LCPI5_0@toc@ha
; CHECK-P8-NEXT: lvx v3, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r4
; CHECK-P8-NEXT: addis r4, r2, .LCPI5_1@toc@ha ; CHECK-P8-NEXT: addis r4, r2, .LCPI5_1@toc@ha
; CHECK-P8-NEXT: addi r5, r5, .LCPI5_0@toc@l ; CHECK-P8-NEXT: addi r5, r5, .LCPI5_0@toc@l
; CHECK-P8-NEXT: addi r4, r4, .LCPI5_1@toc@l ; CHECK-P8-NEXT: addi r4, r4, .LCPI5_1@toc@l
; CHECK-P8-NEXT: lvx v2, 0, r5 ; CHECK-P8-NEXT: lxvd2x vs1, 0, r5
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: lxvd2x vs0, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r4
; CHECK-P8-NEXT: vperm v2, v3, v3, v2 ; CHECK-P8-NEXT: xxswapd v3, vs1
; CHECK-P8-NEXT: vperm v2, v2, v2, v3
; CHECK-P8-NEXT: xxswapd v3, vs0 ; CHECK-P8-NEXT: xxswapd v3, vs0
; CHECK-P8-NEXT: vsld v2, v2, v3 ; CHECK-P8-NEXT: vsld v2, v2, v3
; CHECK-P8-NEXT: vsrad v2, v2, v3 ; CHECK-P8-NEXT: vsrad v2, v2, v3
; CHECK-P8-NEXT: xvcvsxddp vs0, v2 ; CHECK-P8-NEXT: xvcvsxddp vs0, v2
; CHECK-P8-NEXT: xxswapd vs0, vs0 ; CHECK-P8-NEXT: xxswapd vs0, vs0
; CHECK-P8-NEXT: stxvd2x vs0, 0, r3 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r3
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
Show All 29 Lines

llvm/test/CodeGen/PowerPC/vec-trunc.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: -mattr=+vsx -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \ ; RUN: -mattr=+vsx -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
; RUN: FileCheck %s ; RUN: FileCheck %s
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
; RUN: -mattr=+vsx -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \ ; RUN: -mattr=+vsx -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
; RUN: FileCheck %s --check-prefix=CHECK-BE ; RUN: FileCheck %s --check-prefix=CHECK-BE
define void @test8i8(<8 x i8>* nocapture %Sink, <8 x i16>* nocapture readonly %SrcPtr) { define void @test8i8(<8 x i8>* nocapture %Sink, <8 x i16>* nocapture readonly %SrcPtr) {
; CHECK-LABEL: test8i8: ; CHECK-LABEL: test8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lvx v2, 0, r4 ; CHECK-NEXT: lxvd2x vs0, 0, r4
; CHECK-NEXT: xxswapd v2, vs0
; CHECK-NEXT: vpkuhum v2, v2, v2 ; CHECK-NEXT: vpkuhum v2, v2, v2
; CHECK-NEXT: xxswapd vs0, v2 ; CHECK-NEXT: xxswapd vs0, v2
; CHECK-NEXT: stfdx f0, 0, r3 ; CHECK-NEXT: stfdx f0, 0, r3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-BE-LABEL: test8i8: ; CHECK-BE-LABEL: test8i8:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxvw4x v2, 0, r4 ; CHECK-BE-NEXT: lxvw4x v2, 0, r4
; CHECK-BE-NEXT: addi r5, r1, -16 ; CHECK-BE-NEXT: addi r5, r1, -16
; CHECK-BE-NEXT: vpkuhum v2, v2, v2 ; CHECK-BE-NEXT: vpkuhum v2, v2, v2
; CHECK-BE-NEXT: stxvd2x v2, 0, r5 ; CHECK-BE-NEXT: stxvd2x v2, 0, r5
; CHECK-BE-NEXT: ld r4, -16(r1) ; CHECK-BE-NEXT: ld r4, -16(r1)
; CHECK-BE-NEXT: std r4, 0(r3) ; CHECK-BE-NEXT: std r4, 0(r3)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = load <8 x i16>, <8 x i16>* %SrcPtr, align 16 %0 = load <8 x i16>, <8 x i16>* %SrcPtr, align 16
%1 = trunc <8 x i16> %0 to <8 x i8> %1 = trunc <8 x i16> %0 to <8 x i8>
store <8 x i8> %1, <8 x i8>* %Sink, align 16 store <8 x i8> %1, <8 x i8>* %Sink, align 16
ret void ret void
} }
define void @test4i8(<4 x i8>* nocapture %Sink, <4 x i16>* nocapture readonly %SrcPtr) { define void @test4i8(<4 x i8>* nocapture %Sink, <4 x i16>* nocapture readonly %SrcPtr) {
; CHECK-LABEL: test4i8: ; CHECK-LABEL: test4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lvx v2, 0, r4 ; CHECK-NEXT: lxvd2x vs0, 0, r4
; CHECK-NEXT: xxswapd v2, vs0
; CHECK-NEXT: vpkuhum v2, v2, v2 ; CHECK-NEXT: vpkuhum v2, v2, v2
; CHECK-NEXT: xxsldwi vs0, v2, v2, 2 ; CHECK-NEXT: xxsldwi vs0, v2, v2, 2
; CHECK-NEXT: stfiwx f0, 0, r3 ; CHECK-NEXT: stfiwx f0, 0, r3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-BE-LABEL: test4i8: ; CHECK-BE-LABEL: test4i8:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxvw4x v2, 0, r4 ; CHECK-BE-NEXT: lxvw4x v2, 0, r4
Show All 9 Linesentry:
store <4 x i8> %1, <4 x i8>* %Sink, align 16 store <4 x i8> %1, <4 x i8>* %Sink, align 16
ret void ret void
} }
define void @test4i8w(<4 x i8>* nocapture %Sink, <4 x i32>* nocapture readonly %SrcPtr) { define void @test4i8w(<4 x i8>* nocapture %Sink, <4 x i32>* nocapture readonly %SrcPtr) {
; CHECK-LABEL: test4i8w: ; CHECK-LABEL: test4i8w:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LCPI2_0@toc@ha ; CHECK-NEXT: addis r5, r2, .LCPI2_0@toc@ha
; CHECK-NEXT: lvx v3, 0, r4 ; CHECK-NEXT: lxvd2x vs0, 0, r4
; CHECK-NEXT: addi r5, r5, .LCPI2_0@toc@l ; CHECK-NEXT: addi r5, r5, .LCPI2_0@toc@l
; CHECK-NEXT: lvx v2, 0, r5 ; CHECK-NEXT: lxvd2x vs1, 0, r5
; CHECK-NEXT: vperm v2, v3, v3, v2 ; CHECK-NEXT: xxswapd v2, vs0
; CHECK-NEXT: xxswapd v3, vs1
; CHECK-NEXT: vperm v2, v2, v2, v3
; CHECK-NEXT: xxsldwi vs0, v2, v2, 2 ; CHECK-NEXT: xxsldwi vs0, v2, v2, 2
; CHECK-NEXT: stfiwx f0, 0, r3 ; CHECK-NEXT: stfiwx f0, 0, r3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-BE-LABEL: test4i8w: ; CHECK-BE-LABEL: test4i8w:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LCPI2_0@toc@ha ; CHECK-BE-NEXT: addis r5, r2, .LCPI2_0@toc@ha
; CHECK-BE-NEXT: lxvw4x v2, 0, r4 ; CHECK-BE-NEXT: lxvw4x v2, 0, r4
Show All 10 Linesentry:
%1 = trunc <4 x i32> %0 to <4 x i8> %1 = trunc <4 x i32> %0 to <4 x i8>
store <4 x i8> %1, <4 x i8>* %Sink, align 16 store <4 x i8> %1, <4 x i8>* %Sink, align 16
ret void ret void
} }
define void @test2i8(<2 x i8>* nocapture %Sink, <2 x i16>* nocapture readonly %SrcPtr) { define void @test2i8(<2 x i8>* nocapture %Sink, <2 x i16>* nocapture readonly %SrcPtr) {
; CHECK-LABEL: test2i8: ; CHECK-LABEL: test2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lvx v2, 0, r4 ; CHECK-NEXT: lxvd2x vs0, 0, r4
; CHECK-NEXT: xxswapd v2, vs0
; CHECK-NEXT: vpkuhum v2, v2, v2 ; CHECK-NEXT: vpkuhum v2, v2, v2
; CHECK-NEXT: xxswapd vs0, v2 ; CHECK-NEXT: xxswapd vs0, v2
; CHECK-NEXT: mffprd r4, f0 ; CHECK-NEXT: mffprd r4, f0
; CHECK-NEXT: clrldi r4, r4, 48 ; CHECK-NEXT: clrldi r4, r4, 48
; CHECK-NEXT: sth r4, 0(r3) ; CHECK-NEXT: sth r4, 0(r3)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-BE-LABEL: test2i8: ; CHECK-BE-LABEL: test2i8:
Show All 10 Linesentry:
%1 = trunc <2 x i16> %0 to <2 x i8> %1 = trunc <2 x i16> %0 to <2 x i8>
store <2 x i8> %1, <2 x i8>* %Sink, align 16 store <2 x i8> %1, <2 x i8>* %Sink, align 16
ret void ret void
} }
define void @test4i16(<4 x i16>* nocapture %Sink, <4 x i32>* nocapture readonly %SrcPtr) { define void @test4i16(<4 x i16>* nocapture %Sink, <4 x i32>* nocapture readonly %SrcPtr) {
; CHECK-LABEL: test4i16: ; CHECK-LABEL: test4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lvx v2, 0, r4 ; CHECK-NEXT: lxvd2x vs0, 0, r4
; CHECK-NEXT: xxswapd v2, vs0
; CHECK-NEXT: vpkuwum v2, v2, v2 ; CHECK-NEXT: vpkuwum v2, v2, v2
; CHECK-NEXT: xxswapd vs0, v2 ; CHECK-NEXT: xxswapd vs0, v2
; CHECK-NEXT: stfdx f0, 0, r3 ; CHECK-NEXT: stfdx f0, 0, r3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-BE-LABEL: test4i16: ; CHECK-BE-LABEL: test4i16:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxvw4x v2, 0, r4 ; CHECK-BE-NEXT: lxvw4x v2, 0, r4
; CHECK-BE-NEXT: addi r5, r1, -16 ; CHECK-BE-NEXT: addi r5, r1, -16
; CHECK-BE-NEXT: vpkuwum v2, v2, v2 ; CHECK-BE-NEXT: vpkuwum v2, v2, v2
; CHECK-BE-NEXT: stxvd2x v2, 0, r5 ; CHECK-BE-NEXT: stxvd2x v2, 0, r5
; CHECK-BE-NEXT: ld r4, -16(r1) ; CHECK-BE-NEXT: ld r4, -16(r1)
; CHECK-BE-NEXT: std r4, 0(r3) ; CHECK-BE-NEXT: std r4, 0(r3)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = load <4 x i32>, <4 x i32>* %SrcPtr, align 16 %0 = load <4 x i32>, <4 x i32>* %SrcPtr, align 16
%1 = trunc <4 x i32> %0 to <4 x i16> %1 = trunc <4 x i32> %0 to <4 x i16>
store <4 x i16> %1, <4 x i16>* %Sink, align 16 store <4 x i16> %1, <4 x i16>* %Sink, align 16
ret void ret void
} }
define void @test2i16(<2 x i16>* nocapture %Sink, <2 x i32>* nocapture readonly %SrcPtr) { define void @test2i16(<2 x i16>* nocapture %Sink, <2 x i32>* nocapture readonly %SrcPtr) {
; CHECK-LABEL: test2i16: ; CHECK-LABEL: test2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lvx v2, 0, r4 ; CHECK-NEXT: lxvd2x vs0, 0, r4
; CHECK-NEXT: xxswapd v2, vs0
; CHECK-NEXT: vpkuwum v2, v2, v2 ; CHECK-NEXT: vpkuwum v2, v2, v2
; CHECK-NEXT: xxsldwi vs0, v2, v2, 2 ; CHECK-NEXT: xxsldwi vs0, v2, v2, 2
; CHECK-NEXT: stfiwx f0, 0, r3 ; CHECK-NEXT: stfiwx f0, 0, r3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-BE-LABEL: test2i16: ; CHECK-BE-LABEL: test2i16:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxvw4x v2, 0, r4 ; CHECK-BE-NEXT: lxvw4x v2, 0, r4
; CHECK-BE-NEXT: addi r5, r1, -16 ; CHECK-BE-NEXT: addi r5, r1, -16
; CHECK-BE-NEXT: vpkuwum v2, v2, v2 ; CHECK-BE-NEXT: vpkuwum v2, v2, v2
; CHECK-BE-NEXT: stxvw4x v2, 0, r5 ; CHECK-BE-NEXT: stxvw4x v2, 0, r5
; CHECK-BE-NEXT: lwz r4, -16(r1) ; CHECK-BE-NEXT: lwz r4, -16(r1)
; CHECK-BE-NEXT: stw r4, 0(r3) ; CHECK-BE-NEXT: stw r4, 0(r3)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = load <2 x i32>, <2 x i32>* %SrcPtr, align 16 %0 = load <2 x i32>, <2 x i32>* %SrcPtr, align 16
%1 = trunc <2 x i32> %0 to <2 x i16> %1 = trunc <2 x i32> %0 to <2 x i16>
store <2 x i16> %1, <2 x i16>* %Sink, align 16 store <2 x i16> %1, <2 x i16>* %Sink, align 16
ret void ret void
} }
define void @test2i16d(<2 x i16>* nocapture %Sink, <2 x i64>* nocapture readonly %SrcPtr) { define void @test2i16d(<2 x i16>* nocapture %Sink, <2 x i64>* nocapture readonly %SrcPtr) {
; CHECK-LABEL: test2i16d: ; CHECK-LABEL: test2i16d:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lxvd2x vs0, 0, r4
; CHECK-NEXT: addis r5, r2, .LCPI6_0@toc@ha ; CHECK-NEXT: addis r5, r2, .LCPI6_0@toc@ha
; CHECK-NEXT: addi r4, r5, .LCPI6_0@toc@l ; CHECK-NEXT: lxvd2x vs0, 0, r4
; CHECK-NEXT: lvx v3, 0, r4 ; CHECK-NEXT: addi r5, r5, .LCPI6_0@toc@l
; CHECK-NEXT: lxvd2x vs1, 0, r5
; CHECK-NEXT: xxswapd v2, vs0 ; CHECK-NEXT: xxswapd v2, vs0
; CHECK-NEXT: xxswapd v3, vs1
; CHECK-NEXT: vperm v2, v2, v2, v3 ; CHECK-NEXT: vperm v2, v2, v2, v3
; CHECK-NEXT: xxsldwi vs0, v2, v2, 2 ; CHECK-NEXT: xxsldwi vs0, v2, v2, 2
; CHECK-NEXT: stfiwx f0, 0, r3 ; CHECK-NEXT: stfiwx f0, 0, r3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-BE-LABEL: test2i16d: ; CHECK-BE-LABEL: test2i16d:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LCPI6_0@toc@ha ; CHECK-BE-NEXT: addis r5, r2, .LCPI6_0@toc@ha
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llvm/test/CodeGen/PowerPC/vec-trunc2.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: -mattr=+vsx -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \ ; RUN: -mattr=+vsx -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
; RUN: FileCheck %s ; RUN: FileCheck %s
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
; RUN: -mattr=+vsx -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \ ; RUN: -mattr=+vsx -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
; RUN: FileCheck %s --check-prefix=CHECK-BE ; RUN: FileCheck %s --check-prefix=CHECK-BE
define dso_local <8 x i8> @test8x32(i32 %i1, i32 %i2, i32 %i3, i32 %i4, i32 %i5, i32 %i6, i32 %i7, i32 %i8) { define dso_local <8 x i8> @test8x32(i32 %i1, i32 %i2, i32 %i3, i32 %i4, i32 %i5, i32 %i6, i32 %i7, i32 %i8) {
; CHECK-LABEL: test8x32: ; CHECK-LABEL: test8x32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addis r11, r2, .LCPI0_0@toc@ha
; CHECK-NEXT: rldimi r3, r4, 32, 0 ; CHECK-NEXT: rldimi r3, r4, 32, 0
; CHECK-NEXT: rldimi r5, r6, 32, 0 ; CHECK-NEXT: rldimi r5, r6, 32, 0
; CHECK-NEXT: addis r11, r2, .LCPI0_0@toc@ha
; CHECK-NEXT: rldimi r7, r8, 32, 0
; CHECK-NEXT: rldimi r9, r10, 32, 0
; CHECK-NEXT: mtfprd f0, r3 ; CHECK-NEXT: mtfprd f0, r3
; CHECK-NEXT: addi r3, r11, .LCPI0_0@toc@l ; CHECK-NEXT: addi r3, r11, .LCPI0_0@toc@l
; CHECK-NEXT: rldimi r7, r8, 32, 0
; CHECK-NEXT: rldimi r9, r10, 32, 0
; CHECK-NEXT: lxvd2x vs3, 0, r3
; CHECK-NEXT: mtfprd f1, r5 ; CHECK-NEXT: mtfprd f1, r5
; CHECK-NEXT: lvx v4, 0, r3
; CHECK-NEXT: mtfprd f2, r7 ; CHECK-NEXT: mtfprd f2, r7
; CHECK-NEXT: mtfprd f3, r9 ; CHECK-NEXT: mtfprd f4, r9
; CHECK-NEXT: xxmrghd v2, vs1, vs0 ; CHECK-NEXT: xxmrghd v2, vs1, vs0
; CHECK-NEXT: xxmrghd v3, vs3, vs2 ; CHECK-NEXT: xxswapd v4, vs3
; CHECK-NEXT: xxmrghd v3, vs4, vs2
; CHECK-NEXT: vperm v2, v3, v2, v4 ; CHECK-NEXT: vperm v2, v3, v2, v4
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-BE-LABEL: test8x32: ; CHECK-BE-LABEL: test8x32:
; CHECK-BE: # %bb.0: ; CHECK-BE: # %bb.0:
; CHECK-BE-NEXT: stw r10, -80(r1) ; CHECK-BE-NEXT: stw r10, -80(r1)
; CHECK-BE-NEXT: stw r9, -96(r1) ; CHECK-BE-NEXT: stw r9, -96(r1)
; CHECK-BE-NEXT: stw r8, -112(r1) ; CHECK-BE-NEXT: stw r8, -112(r1)
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ret <8 x i8> %v2 ret <8 x i8> %v2
} }
define dso_local <4 x i16> @test4x64(i64 %i1, i64 %i2, i64 %i3, i64 %i4) { define dso_local <4 x i16> @test4x64(i64 %i1, i64 %i2, i64 %i3, i64 %i4) {
; CHECK-LABEL: test4x64: ; CHECK-LABEL: test4x64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addis r7, r2, .LCPI1_0@toc@ha ; CHECK-NEXT: addis r7, r2, .LCPI1_0@toc@ha
; CHECK-NEXT: mtfprd f0, r5 ; CHECK-NEXT: mtfprd f0, r5
; CHECK-NEXT: addi r5, r7, .LCPI1_0@toc@l
; CHECK-NEXT: mtfprd f1, r6 ; CHECK-NEXT: mtfprd f1, r6
; CHECK-NEXT: lxvd2x vs3, 0, r5
; CHECK-NEXT: mtfprd f2, r3 ; CHECK-NEXT: mtfprd f2, r3
; CHECK-NEXT: addi r3, r7, .LCPI1_0@toc@l ; CHECK-NEXT: mtfprd f4, r4
; CHECK-NEXT: mtfprd f3, r4
; CHECK-NEXT: xxmrghd v2, vs1, vs0 ; CHECK-NEXT: xxmrghd v2, vs1, vs0
; CHECK-NEXT: lvx v4, 0, r3 ; CHECK-NEXT: xxmrghd v3, vs4, vs2
; CHECK-NEXT: xxmrghd v3, vs3, vs2 ; CHECK-NEXT: xxswapd v4, vs3
; CHECK-NEXT: vperm v2, v2, v3, v4 ; CHECK-NEXT: vperm v2, v2, v3, v4
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-BE-LABEL: test4x64: ; CHECK-BE-LABEL: test4x64:
; CHECK-BE: # %bb.0: ; CHECK-BE: # %bb.0:
; CHECK-BE-NEXT: std r6, -8(r1) ; CHECK-BE-NEXT: std r6, -8(r1)
; CHECK-BE-NEXT: std r5, -16(r1) ; CHECK-BE-NEXT: std r5, -16(r1)
; CHECK-BE-NEXT: std r4, -24(r1) ; CHECK-BE-NEXT: std r4, -24(r1)
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llvm/test/CodeGen/PowerPC/vec_cmpd_p7.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; Test the doubleword comparison expansions on Power7 ; Test the doubleword comparison expansions on Power7
; ;
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: -mcpu=pwr7 < %s | FileCheck %s ; RUN: -mcpu=pwr7 < %s | FileCheck %s
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
; RUN: -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-BE ; RUN: -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-BE
define <2 x i64> @v2si64_cmp(<2 x i64> %x, <2 x i64> %y) nounwind readnone { define <2 x i64> @v2si64_cmp(<2 x i64> %x, <2 x i64> %y) nounwind readnone {
; CHECK-LABEL: v2si64_cmp: ; CHECK-LABEL: v2si64_cmp:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vcmpequw 2, 2, 3
; CHECK-NEXT: addis 3, 2, .LCPI0_0@toc@ha ; CHECK-NEXT: addis 3, 2, .LCPI0_0@toc@ha
; CHECK-NEXT: vcmpequw 2, 2, 3
; CHECK-NEXT: addi 3, 3, .LCPI0_0@toc@l ; CHECK-NEXT: addi 3, 3, .LCPI0_0@toc@l
; CHECK-NEXT: lvx 3, 0, 3 ; CHECK-NEXT: lxvd2x 0, 0, 3
; CHECK-NEXT: xxswapd 35, 0
; CHECK-NEXT: vperm 3, 2, 2, 3 ; CHECK-NEXT: vperm 3, 2, 2, 3
; CHECK-NEXT: xxland 34, 35, 34 ; CHECK-NEXT: xxland 34, 35, 34
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-BE-LABEL: v2si64_cmp: ; CHECK-BE-LABEL: v2si64_cmp:
; CHECK-BE: # %bb.0: ; CHECK-BE: # %bb.0:
; CHECK-BE-NEXT: vcmpequw 2, 2, 3 ; CHECK-BE-NEXT: vcmpequw 2, 2, 3
; CHECK-BE-NEXT: addis 3, 2, .LCPI0_0@toc@ha ; CHECK-BE-NEXT: addis 3, 2, .LCPI0_0@toc@ha
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llvm/test/CodeGen/PowerPC/vec_constants.ll

Show All 15 Lines
; BE-NEXT: stxvw4x 0, 0, 4 ; BE-NEXT: stxvw4x 0, 0, 4
; BE-NEXT: lxvw4x 0, 0, 5 ; BE-NEXT: lxvw4x 0, 0, 5
; BE-NEXT: xvabssp 0, 0 ; BE-NEXT: xvabssp 0, 0
; BE-NEXT: stxvw4x 0, 0, 5 ; BE-NEXT: stxvw4x 0, 0, 5
; BE-NEXT: blr ; BE-NEXT: blr
; ;
; LE-LABEL: test1: ; LE-LABEL: test1:
; LE: # %bb.0: ; LE: # %bb.0:
; LE-NEXT: lvx 2, 0, 3 ; LE-NEXT: lxvd2x 0, 0, 3
; LE-NEXT: xxswapd 34, 0
; LE-NEXT: vspltisb 3, -1 ; LE-NEXT: vspltisb 3, -1
; LE-NEXT: vslw 3, 3, 3 ; LE-NEXT: vslw 3, 3, 3
; LE-NEXT: xxland 34, 34, 35 ; LE-NEXT: xxland 0, 34, 35
; LE-NEXT: stvx 2, 0, 3 ; LE-NEXT: xxswapd 0, 0
; LE-NEXT: lvx 2, 0, 4 ; LE-NEXT: stxvd2x 0, 0, 3
; LE-NEXT: xxlandc 34, 34, 35 ; LE-NEXT: lxvd2x 0, 0, 4
; LE-NEXT: stvx 2, 0, 4 ; LE-NEXT: xxswapd 34, 0
; LE-NEXT: lvx 2, 0, 5 ; LE-NEXT: xxlandc 0, 34, 35
; LE-NEXT: xvabssp 34, 34 ; LE-NEXT: xxswapd 0, 0
; LE-NEXT: stvx 2, 0, 5 ; LE-NEXT: stxvd2x 0, 0, 4
; LE-NEXT: lxvd2x 0, 0, 5
; LE-NEXT: xxswapd 34, 0
; LE-NEXT: xvabssp 0, 34
; LE-NEXT: xxswapd 0, 0
; LE-NEXT: stxvd2x 0, 0, 5
; LE-NEXT: blr ; LE-NEXT: blr
%tmp = load <4 x i32>, <4 x i32>* %P1 ; <<4 x i32>> [#uses=1] %tmp = load <4 x i32>, <4 x i32>* %P1 ; <<4 x i32>> [#uses=1]
%tmp4 = and <4 x i32> %tmp, < i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648 > ; <<4 x i32>> [#uses=1] %tmp4 = and <4 x i32> %tmp, < i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648 > ; <<4 x i32>> [#uses=1]
store <4 x i32> %tmp4, <4 x i32>* %P1 store <4 x i32> %tmp4, <4 x i32>* %P1
%tmp7 = load <4 x i32>, <4 x i32>* %P2 ; <<4 x i32>> [#uses=1] %tmp7 = load <4 x i32>, <4 x i32>* %P2 ; <<4 x i32>> [#uses=1]
%tmp9 = and <4 x i32> %tmp7, < i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647 > ; <<4 x i32>> [#uses=1] %tmp9 = and <4 x i32> %tmp7, < i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647 > ; <<4 x i32>> [#uses=1]
store <4 x i32> %tmp9, <4 x i32>* %P2 store <4 x i32> %tmp9, <4 x i32>* %P2
%tmp.upgrd.1 = load <4 x float>, <4 x float>* %P3 ; <<4 x float>> [#uses=1] %tmp.upgrd.1 = load <4 x float>, <4 x float>* %P3 ; <<4 x float>> [#uses=1]
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llvm/test/CodeGen/PowerPC/vec_conv_fp32_to_i16_elts.ll

Show First 20 Lines • Show All 160 Lines • ▼ Show 20 Linesentry:
%0 = fptoui <4 x float> %a to <4 x i16> %0 = fptoui <4 x float> %a to <4 x i16>
%1 = bitcast <4 x i16> %0 to i64 %1 = bitcast <4 x i16> %0 to i64
ret i64 %1 ret i64 %1
} }
define <8 x i16> @test8elt(<8 x float>* nocapture readonly) local_unnamed_addr #2 { define <8 x i16> @test8elt(<8 x float>* nocapture readonly) local_unnamed_addr #2 {
; CHECK-P8-LABEL: test8elt: ; CHECK-P8-LABEL: test8elt:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: li r4, 16 ; CHECK-P8-NEXT: li r4, 16
; CHECK-P8-NEXT: lvx v3, r3, r4 ; CHECK-P8-NEXT: lxvd2x vs1, r3, r4
; CHECK-P8-NEXT: xxsldwi vs0, v2, v2, 3 ; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: xxswapd vs1, v2
; CHECK-P8-NEXT: xscvspdpn f2, v2
; CHECK-P8-NEXT: xxsldwi vs4, v2, v2, 1
; CHECK-P8-NEXT: xxsldwi vs5, v3, v3, 3
; CHECK-P8-NEXT: xscvspdpn f3, v3
; CHECK-P8-NEXT: xscvspdpn f0, vs0 ; CHECK-P8-NEXT: xscvspdpn f0, vs0
; CHECK-P8-NEXT: xxswapd v3, vs1
; CHECK-P8-NEXT: xscvspdpn f1, vs1 ; CHECK-P8-NEXT: xscvspdpn f1, vs1
; CHECK-P8-NEXT: xxsldwi vs2, v2, v2, 3
; CHECK-P8-NEXT: xxsldwi vs4, v2, v2, 1
; CHECK-P8-NEXT: xscvspdpn f3, v2
; CHECK-P8-NEXT: xxsldwi vs6, v3, v3, 3
; CHECK-P8-NEXT: xxsldwi vs7, v3, v3, 1
; CHECK-P8-NEXT: xscvspdpn f5, v3
; CHECK-P8-NEXT: xscvspdpn f2, vs2
; CHECK-P8-NEXT: xscvspdpn f4, vs4 ; CHECK-P8-NEXT: xscvspdpn f4, vs4
; CHECK-P8-NEXT: xscvspdpn f5, vs5
; CHECK-P8-NEXT: xscvdpsxws f2, f2
; CHECK-P8-NEXT: xscvdpsxws f3, f3
; CHECK-P8-NEXT: xscvdpsxws f0, f0 ; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: xscvspdpn f6, vs6
; CHECK-P8-NEXT: xscvdpsxws f3, f3
; CHECK-P8-NEXT: xscvspdpn f7, vs7
; CHECK-P8-NEXT: xscvdpsxws f2, f2
; CHECK-P8-NEXT: xscvdpsxws f4, f4
; CHECK-P8-NEXT: xscvdpsxws f1, f1 ; CHECK-P8-NEXT: xscvdpsxws f1, f1
; CHECK-P8-NEXT: xscvdpsxws f5, f5
; CHECK-P8-NEXT: mffprwz r3, f0 ; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: xxswapd vs0, v3 ; CHECK-P8-NEXT: mffprwz r4, f3
; CHECK-P8-NEXT: mffprwz r4, f1
; CHECK-P8-NEXT: xxsldwi vs1, v3, v3, 1
; CHECK-P8-NEXT: mtvsrd v2, r3 ; CHECK-P8-NEXT: mtvsrd v2, r3
; CHECK-P8-NEXT: xscvspdpn f0, vs0
; CHECK-P8-NEXT: mffprwz r3, f2 ; CHECK-P8-NEXT: mffprwz r3, f2
; CHECK-P8-NEXT: xscvdpsxws f2, f4 ; CHECK-P8-NEXT: xscvdpsxws f0, f6
; CHECK-P8-NEXT: xscvspdpn f1, vs1 ; CHECK-P8-NEXT: xscvdpsxws f2, f7
; CHECK-P8-NEXT: xscvdpsxws f4, f5 ; CHECK-P8-NEXT: mtvsrd v3, r4
; CHECK-P8-NEXT: mtvsrd v4, r4 ; CHECK-P8-NEXT: mffprwz r4, f4
; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: vmrghh v2, v4, v2
; CHECK-P8-NEXT: mffprwz r4, f2
; CHECK-P8-NEXT: xscvdpsxws f1, f1
; CHECK-P8-NEXT: mtvsrd v3, r3
; CHECK-P8-NEXT: mffprwz r3, f3
; CHECK-P8-NEXT: mtvsrd v4, r4
; CHECK-P8-NEXT: mffprwz r4, f0
; CHECK-P8-NEXT: vmrghh v3, v3, v4
; CHECK-P8-NEXT: mtvsrd v4, r3 ; CHECK-P8-NEXT: mtvsrd v4, r3
; CHECK-P8-NEXT: mffprwz r3, f4 ; CHECK-P8-NEXT: mtvsrd v5, r4
; CHECK-P8-NEXT: mtvsrd v0, r4
; CHECK-P8-NEXT: mtvsrd v5, r3
; CHECK-P8-NEXT: mffprwz r3, f1 ; CHECK-P8-NEXT: mffprwz r3, f1
; CHECK-P8-NEXT: vmrghh v5, v0, v5 ; CHECK-P8-NEXT: mffprwz r4, f5
; CHECK-P8-NEXT: vmrghh v2, v2, v4
; CHECK-P8-NEXT: vmrghh v3, v3, v5
; CHECK-P8-NEXT: mtvsrd v4, r3
; CHECK-P8-NEXT: mtvsrd v5, r4
; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: mffprwz r4, f2
; CHECK-P8-NEXT: mtvsrd v0, r3
; CHECK-P8-NEXT: mtvsrd v1, r4
; CHECK-P8-NEXT: xxmrglw vs0, v3, v2 ; CHECK-P8-NEXT: xxmrglw vs0, v3, v2
; CHECK-P8-NEXT: mtvsrd v1, r3 ; CHECK-P8-NEXT: vmrghh v4, v4, v0
; CHECK-P8-NEXT: vmrghh v4, v4, v1 ; CHECK-P8-NEXT: vmrghh v5, v5, v1
; CHECK-P8-NEXT: xxmrglw vs1, v4, v5 ; CHECK-P8-NEXT: xxmrglw vs1, v5, v4
; CHECK-P8-NEXT: xxmrgld v2, vs1, vs0 ; CHECK-P8-NEXT: xxmrgld v2, vs1, vs0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test8elt: ; CHECK-P9-LABEL: test8elt:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lxv vs1, 0(r3) ; CHECK-P9-NEXT: lxv vs1, 0(r3)
; CHECK-P9-NEXT: lxv vs0, 16(r3) ; CHECK-P9-NEXT: lxv vs0, 16(r3)
; CHECK-P9-NEXT: xxsldwi vs2, vs1, vs1, 3 ; CHECK-P9-NEXT: xxsldwi vs2, vs1, vs1, 3
▲ Show 20 Lines • Show All 100 Lines • ▼ Show 20 Linesentry:
%a = load <8 x float>, <8 x float>* %0, align 32 %a = load <8 x float>, <8 x float>* %0, align 32
%1 = fptoui <8 x float> %a to <8 x i16> %1 = fptoui <8 x float> %a to <8 x i16>
ret <8 x i16> %1 ret <8 x i16> %1
} }
define void @test16elt(<16 x i16>* noalias nocapture sret(<16 x i16>) %agg.result, <16 x float>* nocapture readonly) local_unnamed_addr #3 { define void @test16elt(<16 x i16>* noalias nocapture sret(<16 x i16>) %agg.result, <16 x float>* nocapture readonly) local_unnamed_addr #3 {
; CHECK-P8-LABEL: test16elt: ; CHECK-P8-LABEL: test16elt:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: lvx v5, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r4
; CHECK-P8-NEXT: li r5, 16 ; CHECK-P8-NEXT: li r5, 16
; CHECK-P8-NEXT: li r6, 32 ; CHECK-P8-NEXT: li r6, 32
; CHECK-P8-NEXT: lvx v3, r4, r5 ; CHECK-P8-NEXT: lxvd2x vs1, r4, r5
; CHECK-P8-NEXT: lvx v2, r4, r6 ; CHECK-P8-NEXT: lxvd2x vs2, r4, r6
; CHECK-P8-NEXT: li r6, 48 ; CHECK-P8-NEXT: li r6, 48
; CHECK-P8-NEXT: xxsldwi vs0, v5, v5, 3 ; CHECK-P8-NEXT: lxvd2x vs3, r4, r6
; CHECK-P8-NEXT: xscvspdpn f1, v5 ; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: lvx v4, r4, r6
; CHECK-P8-NEXT: xxswapd vs3, v5
; CHECK-P8-NEXT: xxsldwi vs5, v5, v5, 1
; CHECK-P8-NEXT: xxsldwi vs7, v3, v3, 3
; CHECK-P8-NEXT: xxswapd vs8, v3
; CHECK-P8-NEXT: xscvspdpn f0, vs0 ; CHECK-P8-NEXT: xscvspdpn f0, vs0
; CHECK-P8-NEXT: xscvspdpn f3, vs3 ; CHECK-P8-NEXT: xscvspdpn f4, vs1
; CHECK-P8-NEXT: xscvspdpn f5, vs5 ; CHECK-P8-NEXT: xxswapd v3, vs1
; CHECK-P8-NEXT: xscvdpsxws f1, f1 ; CHECK-P8-NEXT: xscvspdpn f1, vs2
; CHECK-P8-NEXT: xscvspdpn f7, vs7 ; CHECK-P8-NEXT: xxswapd v4, vs2
; CHECK-P8-NEXT: xscvspdpn f8, vs8 ; CHECK-P8-NEXT: xxsldwi vs6, v2, v2, 3
; CHECK-P8-NEXT: xxsldwi vs8, v2, v2, 1
; CHECK-P8-NEXT: xscvspdpn f7, v2
; CHECK-P8-NEXT: xxsldwi vs9, v3, v3, 3
; CHECK-P8-NEXT: xscvspdpn f5, vs3
; CHECK-P8-NEXT: xxswapd v0, vs3
; CHECK-P8-NEXT: xscvspdpn f6, vs6
; CHECK-P8-NEXT: xscvdpsxws f0, f0 ; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: xscvdpsxws f3, f3 ; CHECK-P8-NEXT: xscvspdpn f8, vs8
; CHECK-P8-NEXT: xscvdpsxws f4, f4
; CHECK-P8-NEXT: xscvspdpn f9, vs9
; CHECK-P8-NEXT: xscvspdpn f2, v3 ; CHECK-P8-NEXT: xscvspdpn f2, v3
; CHECK-P8-NEXT: mffprwz r4, f1 ; CHECK-P8-NEXT: xscvdpsxws f6, f6
; CHECK-P8-NEXT: xscvdpsxws f1, f5 ; CHECK-P8-NEXT: mffprwz r4, f0
; CHECK-P8-NEXT: xscvdpsxws f0, f7
; CHECK-P8-NEXT: xxsldwi vs7, v0, v0, 3
; CHECK-P8-NEXT: mtvsrd v2, r4
; CHECK-P8-NEXT: mffprwz r4, f4
; CHECK-P8-NEXT: xscvdpsxws f4, f8
; CHECK-P8-NEXT: mtvsrd v5, r4 ; CHECK-P8-NEXT: mtvsrd v5, r4
; CHECK-P8-NEXT: mffprwz r4, f6
; CHECK-P8-NEXT: xscvdpsxws f6, f9
; CHECK-P8-NEXT: xscvspdpn f10, v4
; CHECK-P8-NEXT: mtvsrd v1, r4
; CHECK-P8-NEXT: mffprwz r4, f0 ; CHECK-P8-NEXT: mffprwz r4, f0
; CHECK-P8-NEXT: xxsldwi vs0, v3, v3, 1 ; CHECK-P8-NEXT: xxsldwi vs0, v3, v3, 1
; CHECK-P8-NEXT: xscvspdpn f4, v2 ; CHECK-P8-NEXT: xscvdpsxws f1, f1
; CHECK-P8-NEXT: xscvdpsxws f5, f7 ; CHECK-P8-NEXT: xscvspdpn f3, v0
; CHECK-P8-NEXT: xxsldwi vs7, v4, v4, 3
; CHECK-P8-NEXT: mtvsrd v3, r4 ; CHECK-P8-NEXT: mtvsrd v3, r4
; CHECK-P8-NEXT: mffprwz r4, f3 ; CHECK-P8-NEXT: mffprwz r4, f4
; CHECK-P8-NEXT: xxsldwi vs3, v2, v2, 3 ; CHECK-P8-NEXT: xxsldwi vs4, v4, v4, 3
; CHECK-P8-NEXT: xscvspdpn f6, v4 ; CHECK-P8-NEXT: xscvdpsxws f5, f5
; CHECK-P8-NEXT: mtvsrd v0, r4 ; CHECK-P8-NEXT: vmrghh v2, v2, v1
; CHECK-P8-NEXT: mffprwz r4, f1
; CHECK-P8-NEXT: xscvdpsxws f1, f8
; CHECK-P8-NEXT: xxswapd vs8, v4
; CHECK-P8-NEXT: xscvspdpn f0, vs0 ; CHECK-P8-NEXT: xscvspdpn f0, vs0
; CHECK-P8-NEXT: mtvsrd v1, r4
; CHECK-P8-NEXT: mffprwz r4, f6
; CHECK-P8-NEXT: xxsldwi vs6, v4, v4, 1
; CHECK-P8-NEXT: xscvdpsxws f2, f2 ; CHECK-P8-NEXT: xscvdpsxws f2, f2
; CHECK-P8-NEXT: vmrghh v3, v3, v1
; CHECK-P8-NEXT: mtvsrd v1, r4 ; CHECK-P8-NEXT: mtvsrd v1, r4
; CHECK-P8-NEXT: mffprwz r4, f5
; CHECK-P8-NEXT: xxswapd vs5, v2
; CHECK-P8-NEXT: xscvspdpn f3, vs3
; CHECK-P8-NEXT: xscvdpsxws f4, f4
; CHECK-P8-NEXT: vmrghh v3, v0, v3
; CHECK-P8-NEXT: mtvsrd v0, r4
; CHECK-P8-NEXT: mffprwz r4, f1 ; CHECK-P8-NEXT: mffprwz r4, f1
; CHECK-P8-NEXT: xscvdpsxws f6, f6 ; CHECK-P8-NEXT: xscvdpsxws f1, f10
; CHECK-P8-NEXT: xscvspdpn f1, vs5 ; CHECK-P8-NEXT: vmrghh v4, v5, v1
; CHECK-P8-NEXT: xxsldwi vs5, v2, v2, 1 ; CHECK-P8-NEXT: xscvspdpn f4, vs4
; CHECK-P8-NEXT: mtvsrd v6, r4 ; CHECK-P8-NEXT: mtvsrd v5, r4
; CHECK-P8-NEXT: mffprwz r4, f5
; CHECK-P8-NEXT: xscvdpsxws f3, f3
; CHECK-P8-NEXT: mtvsrd v1, r4
; CHECK-P8-NEXT: mffprwz r4, f2 ; CHECK-P8-NEXT: mffprwz r4, f2
; CHECK-P8-NEXT: xxsldwi vs2, v0, v0, 1
; CHECK-P8-NEXT: xscvdpsxws f0, f0 ; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: vmrghh v2, v5, v1 ; CHECK-P8-NEXT: xscvspdpn f6, vs6
; CHECK-P8-NEXT: vmrghh v5, v6, v0
; CHECK-P8-NEXT: mtvsrd v0, r4
; CHECK-P8-NEXT: mffprwz r4, f4
; CHECK-P8-NEXT: xscvdpsxws f2, f3
; CHECK-P8-NEXT: xscvspdpn f5, vs5
; CHECK-P8-NEXT: mtvsrd v1, r4
; CHECK-P8-NEXT: mffprwz r4, f6
; CHECK-P8-NEXT: xscvdpsxws f1, f1
; CHECK-P8-NEXT: mtvsrd v6, r4 ; CHECK-P8-NEXT: mtvsrd v6, r4
; CHECK-P8-NEXT: mffprwz r4, f0 ; CHECK-P8-NEXT: mffprwz r4, f1
; CHECK-P8-NEXT: xscvspdpn f7, vs7 ; CHECK-P8-NEXT: xscvspdpn f7, vs7
; CHECK-P8-NEXT: xscvdpsxws f1, f4
; CHECK-P8-NEXT: mtvsrd v7, r4 ; CHECK-P8-NEXT: mtvsrd v7, r4
; CHECK-P8-NEXT: mffprwz r4, f2 ; CHECK-P8-NEXT: mffprwz r4, f3
; CHECK-P8-NEXT: xxsldwi vs2, v4, v4, 1 ; CHECK-P8-NEXT: xscvdpsxws f3, f6
; CHECK-P8-NEXT: xscvspdpn f8, vs8 ; CHECK-P8-NEXT: mtvsrd v0, r4
; CHECK-P8-NEXT: xscvdpsxws f0, f5
; CHECK-P8-NEXT: mtvsrd v4, r4
; CHECK-P8-NEXT: mffprwz r4, f1
; CHECK-P8-NEXT: xscvspdpn f1, vs2
; CHECK-P8-NEXT: xscvdpsxws f3, f7
; CHECK-P8-NEXT: mtvsrd v8, r4
; CHECK-P8-NEXT: mffprwz r4, f0 ; CHECK-P8-NEXT: mffprwz r4, f0
; CHECK-P8-NEXT: xscvdpsxws f0, f8 ; CHECK-P8-NEXT: xscvspdpn f0, vs2
; CHECK-P8-NEXT: mtvsrd v8, r4
; CHECK-P8-NEXT: mffprwz r4, f1
; CHECK-P8-NEXT: xscvdpsxws f1, f7
; CHECK-P8-NEXT: mtvsrd v9, r4 ; CHECK-P8-NEXT: mtvsrd v9, r4
; CHECK-P8-NEXT: xscvdpsxws f1, f1
; CHECK-P8-NEXT: mffprwz r4, f3 ; CHECK-P8-NEXT: mffprwz r4, f3
; CHECK-P8-NEXT: vmrghh v0, v0, v7 ; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: mtvsrd v7, r4 ; CHECK-P8-NEXT: vmrghh v6, v6, v8
; CHECK-P8-NEXT: mffprwz r4, f0
; CHECK-P8-NEXT: xxmrglw vs0, v2, v3
; CHECK-P8-NEXT: vmrghh v4, v8, v4
; CHECK-P8-NEXT: mtvsrd v8, r4 ; CHECK-P8-NEXT: mtvsrd v8, r4
; CHECK-P8-NEXT: mffprwz r4, f1 ; CHECK-P8-NEXT: mffprwz r4, f1
; CHECK-P8-NEXT: vmrghh v1, v1, v9 ; CHECK-P8-NEXT: vmrghh v5, v5, v9
; CHECK-P8-NEXT: xxmrglw vs1, v0, v5
; CHECK-P8-NEXT: mtvsrd v9, r4 ; CHECK-P8-NEXT: mtvsrd v9, r4
; CHECK-P8-NEXT: vmrghh v7, v8, v7 ; CHECK-P8-NEXT: mffprwz r4, f0
; CHECK-P8-NEXT: vmrghh v6, v6, v9 ; CHECK-P8-NEXT: xxmrglw vs0, v3, v2
; CHECK-P8-NEXT: vmrghh v7, v7, v8
; CHECK-P8-NEXT: xxmrglw vs1, v6, v4
; CHECK-P8-NEXT: mtvsrd v8, r4
; CHECK-P8-NEXT: vmrghh v1, v1, v9
; CHECK-P8-NEXT: vmrghh v0, v0, v8
; CHECK-P8-NEXT: xxmrgld v2, vs1, vs0 ; CHECK-P8-NEXT: xxmrgld v2, vs1, vs0
; CHECK-P8-NEXT: xxmrglw vs2, v1, v4 ; CHECK-P8-NEXT: xxmrglw vs2, v7, v5
; CHECK-P8-NEXT: stvx v2, 0, r3 ; CHECK-P8-NEXT: xxswapd vs1, v2
; CHECK-P8-NEXT: xxmrglw vs3, v6, v7 ; CHECK-P8-NEXT: xxmrglw vs3, v0, v1
; CHECK-P8-NEXT: xxmrgld v3, vs3, vs2 ; CHECK-P8-NEXT: xxmrgld v3, vs3, vs2
; CHECK-P8-NEXT: stvx v3, r3, r5 ; CHECK-P8-NEXT: xxswapd vs0, v3
; CHECK-P8-NEXT: stxvd2x vs0, r3, r5
; CHECK-P8-NEXT: stxvd2x vs1, 0, r3
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test16elt: ; CHECK-P9-LABEL: test16elt:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lxv vs1, 0(r4) ; CHECK-P9-NEXT: lxv vs1, 0(r4)
; CHECK-P9-NEXT: lxv vs0, 16(r4) ; CHECK-P9-NEXT: lxv vs0, 16(r4)
; CHECK-P9-NEXT: xxsldwi vs2, vs1, vs1, 3 ; CHECK-P9-NEXT: xxsldwi vs2, vs1, vs1, 3
; CHECK-P9-NEXT: xxswapd vs3, vs1 ; CHECK-P9-NEXT: xxswapd vs3, vs1
▲ Show 20 Lines • Show All 352 Lines • ▼ Show 20 Linesentry:
%0 = fptosi <4 x float> %a to <4 x i16> %0 = fptosi <4 x float> %a to <4 x i16>
%1 = bitcast <4 x i16> %0 to i64 %1 = bitcast <4 x i16> %0 to i64
ret i64 %1 ret i64 %1
} }
define <8 x i16> @test8elt_signed(<8 x float>* nocapture readonly) local_unnamed_addr #2 { define <8 x i16> @test8elt_signed(<8 x float>* nocapture readonly) local_unnamed_addr #2 {
; CHECK-P8-LABEL: test8elt_signed: ; CHECK-P8-LABEL: test8elt_signed:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: li r4, 16 ; CHECK-P8-NEXT: li r4, 16
; CHECK-P8-NEXT: lvx v3, r3, r4 ; CHECK-P8-NEXT: lxvd2x vs1, r3, r4
; CHECK-P8-NEXT: xxsldwi vs0, v2, v2, 3 ; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: xxswapd vs1, v2
; CHECK-P8-NEXT: xscvspdpn f2, v2
; CHECK-P8-NEXT: xxsldwi vs4, v2, v2, 1
; CHECK-P8-NEXT: xxsldwi vs5, v3, v3, 3
; CHECK-P8-NEXT: xscvspdpn f3, v3
; CHECK-P8-NEXT: xscvspdpn f0, vs0 ; CHECK-P8-NEXT: xscvspdpn f0, vs0
; CHECK-P8-NEXT: xxswapd v3, vs1
; CHECK-P8-NEXT: xscvspdpn f1, vs1 ; CHECK-P8-NEXT: xscvspdpn f1, vs1
; CHECK-P8-NEXT: xxsldwi vs2, v2, v2, 3
; CHECK-P8-NEXT: xxsldwi vs4, v2, v2, 1
; CHECK-P8-NEXT: xscvspdpn f3, v2
; CHECK-P8-NEXT: xxsldwi vs6, v3, v3, 3
; CHECK-P8-NEXT: xxsldwi vs7, v3, v3, 1
; CHECK-P8-NEXT: xscvspdpn f5, v3
; CHECK-P8-NEXT: xscvspdpn f2, vs2
; CHECK-P8-NEXT: xscvspdpn f4, vs4 ; CHECK-P8-NEXT: xscvspdpn f4, vs4
; CHECK-P8-NEXT: xscvspdpn f5, vs5
; CHECK-P8-NEXT: xscvdpsxws f2, f2
; CHECK-P8-NEXT: xscvdpsxws f3, f3
; CHECK-P8-NEXT: xscvdpsxws f0, f0 ; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: xscvspdpn f6, vs6
; CHECK-P8-NEXT: xscvdpsxws f3, f3
; CHECK-P8-NEXT: xscvspdpn f7, vs7
; CHECK-P8-NEXT: xscvdpsxws f2, f2
; CHECK-P8-NEXT: xscvdpsxws f4, f4
; CHECK-P8-NEXT: xscvdpsxws f1, f1 ; CHECK-P8-NEXT: xscvdpsxws f1, f1
; CHECK-P8-NEXT: xscvdpsxws f5, f5
; CHECK-P8-NEXT: mffprwz r3, f0 ; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: xxswapd vs0, v3 ; CHECK-P8-NEXT: mffprwz r4, f3
; CHECK-P8-NEXT: mffprwz r4, f1
; CHECK-P8-NEXT: xxsldwi vs1, v3, v3, 1
; CHECK-P8-NEXT: mtvsrd v2, r3 ; CHECK-P8-NEXT: mtvsrd v2, r3
; CHECK-P8-NEXT: xscvspdpn f0, vs0
; CHECK-P8-NEXT: mffprwz r3, f2 ; CHECK-P8-NEXT: mffprwz r3, f2
; CHECK-P8-NEXT: xscvdpsxws f2, f4 ; CHECK-P8-NEXT: xscvdpsxws f0, f6
; CHECK-P8-NEXT: xscvspdpn f1, vs1 ; CHECK-P8-NEXT: xscvdpsxws f2, f7
; CHECK-P8-NEXT: xscvdpsxws f4, f5 ; CHECK-P8-NEXT: mtvsrd v3, r4
; CHECK-P8-NEXT: mtvsrd v4, r4 ; CHECK-P8-NEXT: mffprwz r4, f4
; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: vmrghh v2, v4, v2
; CHECK-P8-NEXT: mffprwz r4, f2
; CHECK-P8-NEXT: xscvdpsxws f1, f1
; CHECK-P8-NEXT: mtvsrd v3, r3
; CHECK-P8-NEXT: mffprwz r3, f3
; CHECK-P8-NEXT: mtvsrd v4, r4
; CHECK-P8-NEXT: mffprwz r4, f0
; CHECK-P8-NEXT: vmrghh v3, v3, v4
; CHECK-P8-NEXT: mtvsrd v4, r3 ; CHECK-P8-NEXT: mtvsrd v4, r3
; CHECK-P8-NEXT: mffprwz r3, f4 ; CHECK-P8-NEXT: mtvsrd v5, r4
; CHECK-P8-NEXT: mtvsrd v0, r4
; CHECK-P8-NEXT: mtvsrd v5, r3
; CHECK-P8-NEXT: mffprwz r3, f1 ; CHECK-P8-NEXT: mffprwz r3, f1
; CHECK-P8-NEXT: vmrghh v5, v0, v5 ; CHECK-P8-NEXT: mffprwz r4, f5
; CHECK-P8-NEXT: vmrghh v2, v2, v4
; CHECK-P8-NEXT: vmrghh v3, v3, v5
; CHECK-P8-NEXT: mtvsrd v4, r3
; CHECK-P8-NEXT: mtvsrd v5, r4
; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: mffprwz r4, f2
; CHECK-P8-NEXT: mtvsrd v0, r3
; CHECK-P8-NEXT: mtvsrd v1, r4
; CHECK-P8-NEXT: xxmrglw vs0, v3, v2 ; CHECK-P8-NEXT: xxmrglw vs0, v3, v2
; CHECK-P8-NEXT: mtvsrd v1, r3 ; CHECK-P8-NEXT: vmrghh v4, v4, v0
; CHECK-P8-NEXT: vmrghh v4, v4, v1 ; CHECK-P8-NEXT: vmrghh v5, v5, v1
; CHECK-P8-NEXT: xxmrglw vs1, v4, v5 ; CHECK-P8-NEXT: xxmrglw vs1, v5, v4
; CHECK-P8-NEXT: xxmrgld v2, vs1, vs0 ; CHECK-P8-NEXT: xxmrgld v2, vs1, vs0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test8elt_signed: ; CHECK-P9-LABEL: test8elt_signed:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lxv vs1, 0(r3) ; CHECK-P9-NEXT: lxv vs1, 0(r3)
; CHECK-P9-NEXT: lxv vs0, 16(r3) ; CHECK-P9-NEXT: lxv vs0, 16(r3)
; CHECK-P9-NEXT: xxsldwi vs2, vs1, vs1, 3 ; CHECK-P9-NEXT: xxsldwi vs2, vs1, vs1, 3
▲ Show 20 Lines • Show All 100 Lines • ▼ Show 20 Linesentry:
%a = load <8 x float>, <8 x float>* %0, align 32 %a = load <8 x float>, <8 x float>* %0, align 32
%1 = fptosi <8 x float> %a to <8 x i16> %1 = fptosi <8 x float> %a to <8 x i16>
ret <8 x i16> %1 ret <8 x i16> %1
} }
define void @test16elt_signed(<16 x i16>* noalias nocapture sret(<16 x i16>) %agg.result, <16 x float>* nocapture readonly) local_unnamed_addr #3 { define void @test16elt_signed(<16 x i16>* noalias nocapture sret(<16 x i16>) %agg.result, <16 x float>* nocapture readonly) local_unnamed_addr #3 {
; CHECK-P8-LABEL: test16elt_signed: ; CHECK-P8-LABEL: test16elt_signed:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: lvx v5, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r4
; CHECK-P8-NEXT: li r5, 16 ; CHECK-P8-NEXT: li r5, 16
; CHECK-P8-NEXT: li r6, 32 ; CHECK-P8-NEXT: li r6, 32
; CHECK-P8-NEXT: lvx v3, r4, r5 ; CHECK-P8-NEXT: lxvd2x vs1, r4, r5
; CHECK-P8-NEXT: lvx v2, r4, r6 ; CHECK-P8-NEXT: lxvd2x vs2, r4, r6
; CHECK-P8-NEXT: li r6, 48 ; CHECK-P8-NEXT: li r6, 48
; CHECK-P8-NEXT: xxsldwi vs0, v5, v5, 3 ; CHECK-P8-NEXT: lxvd2x vs3, r4, r6
; CHECK-P8-NEXT: xscvspdpn f1, v5 ; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: lvx v4, r4, r6
; CHECK-P8-NEXT: xxswapd vs3, v5
; CHECK-P8-NEXT: xxsldwi vs5, v5, v5, 1
; CHECK-P8-NEXT: xxsldwi vs7, v3, v3, 3
; CHECK-P8-NEXT: xxswapd vs8, v3
; CHECK-P8-NEXT: xscvspdpn f0, vs0 ; CHECK-P8-NEXT: xscvspdpn f0, vs0
; CHECK-P8-NEXT: xscvspdpn f3, vs3 ; CHECK-P8-NEXT: xscvspdpn f4, vs1
; CHECK-P8-NEXT: xscvspdpn f5, vs5 ; CHECK-P8-NEXT: xxswapd v3, vs1
; CHECK-P8-NEXT: xscvdpsxws f1, f1 ; CHECK-P8-NEXT: xscvspdpn f1, vs2
; CHECK-P8-NEXT: xscvspdpn f7, vs7 ; CHECK-P8-NEXT: xxswapd v4, vs2
; CHECK-P8-NEXT: xscvspdpn f8, vs8 ; CHECK-P8-NEXT: xxsldwi vs6, v2, v2, 3
; CHECK-P8-NEXT: xxsldwi vs8, v2, v2, 1
; CHECK-P8-NEXT: xscvspdpn f7, v2
; CHECK-P8-NEXT: xxsldwi vs9, v3, v3, 3
; CHECK-P8-NEXT: xscvspdpn f5, vs3
; CHECK-P8-NEXT: xxswapd v0, vs3
; CHECK-P8-NEXT: xscvspdpn f6, vs6
; CHECK-P8-NEXT: xscvdpsxws f0, f0 ; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: xscvdpsxws f3, f3 ; CHECK-P8-NEXT: xscvspdpn f8, vs8
; CHECK-P8-NEXT: xscvdpsxws f4, f4
; CHECK-P8-NEXT: xscvspdpn f9, vs9
; CHECK-P8-NEXT: xscvspdpn f2, v3 ; CHECK-P8-NEXT: xscvspdpn f2, v3
; CHECK-P8-NEXT: mffprwz r4, f1 ; CHECK-P8-NEXT: xscvdpsxws f6, f6
; CHECK-P8-NEXT: xscvdpsxws f1, f5 ; CHECK-P8-NEXT: mffprwz r4, f0
; CHECK-P8-NEXT: xscvdpsxws f0, f7
; CHECK-P8-NEXT: xxsldwi vs7, v0, v0, 3
; CHECK-P8-NEXT: mtvsrd v2, r4
; CHECK-P8-NEXT: mffprwz r4, f4
; CHECK-P8-NEXT: xscvdpsxws f4, f8
; CHECK-P8-NEXT: mtvsrd v5, r4 ; CHECK-P8-NEXT: mtvsrd v5, r4
; CHECK-P8-NEXT: mffprwz r4, f6
; CHECK-P8-NEXT: xscvdpsxws f6, f9
; CHECK-P8-NEXT: xscvspdpn f10, v4
; CHECK-P8-NEXT: mtvsrd v1, r4
; CHECK-P8-NEXT: mffprwz r4, f0 ; CHECK-P8-NEXT: mffprwz r4, f0
; CHECK-P8-NEXT: xxsldwi vs0, v3, v3, 1 ; CHECK-P8-NEXT: xxsldwi vs0, v3, v3, 1
; CHECK-P8-NEXT: xscvspdpn f4, v2 ; CHECK-P8-NEXT: xscvdpsxws f1, f1
; CHECK-P8-NEXT: xscvdpsxws f5, f7 ; CHECK-P8-NEXT: xscvspdpn f3, v0
; CHECK-P8-NEXT: xxsldwi vs7, v4, v4, 3
; CHECK-P8-NEXT: mtvsrd v3, r4 ; CHECK-P8-NEXT: mtvsrd v3, r4
; CHECK-P8-NEXT: mffprwz r4, f3 ; CHECK-P8-NEXT: mffprwz r4, f4
; CHECK-P8-NEXT: xxsldwi vs3, v2, v2, 3 ; CHECK-P8-NEXT: xxsldwi vs4, v4, v4, 3
; CHECK-P8-NEXT: xscvspdpn f6, v4 ; CHECK-P8-NEXT: xscvdpsxws f5, f5
; CHECK-P8-NEXT: mtvsrd v0, r4 ; CHECK-P8-NEXT: vmrghh v2, v2, v1
; CHECK-P8-NEXT: mffprwz r4, f1
; CHECK-P8-NEXT: xscvdpsxws f1, f8
; CHECK-P8-NEXT: xxswapd vs8, v4
; CHECK-P8-NEXT: xscvspdpn f0, vs0 ; CHECK-P8-NEXT: xscvspdpn f0, vs0
; CHECK-P8-NEXT: mtvsrd v1, r4
; CHECK-P8-NEXT: mffprwz r4, f6
; CHECK-P8-NEXT: xxsldwi vs6, v4, v4, 1
; CHECK-P8-NEXT: xscvdpsxws f2, f2 ; CHECK-P8-NEXT: xscvdpsxws f2, f2
; CHECK-P8-NEXT: vmrghh v3, v3, v1
; CHECK-P8-NEXT: mtvsrd v1, r4 ; CHECK-P8-NEXT: mtvsrd v1, r4
; CHECK-P8-NEXT: mffprwz r4, f5
; CHECK-P8-NEXT: xxswapd vs5, v2
; CHECK-P8-NEXT: xscvspdpn f3, vs3
; CHECK-P8-NEXT: xscvdpsxws f4, f4
; CHECK-P8-NEXT: vmrghh v3, v0, v3
; CHECK-P8-NEXT: mtvsrd v0, r4
; CHECK-P8-NEXT: mffprwz r4, f1 ; CHECK-P8-NEXT: mffprwz r4, f1
; CHECK-P8-NEXT: xscvdpsxws f6, f6 ; CHECK-P8-NEXT: xscvdpsxws f1, f10
; CHECK-P8-NEXT: xscvspdpn f1, vs5 ; CHECK-P8-NEXT: vmrghh v4, v5, v1
; CHECK-P8-NEXT: xxsldwi vs5, v2, v2, 1 ; CHECK-P8-NEXT: xscvspdpn f4, vs4
; CHECK-P8-NEXT: mtvsrd v6, r4 ; CHECK-P8-NEXT: mtvsrd v5, r4
; CHECK-P8-NEXT: mffprwz r4, f5
; CHECK-P8-NEXT: xscvdpsxws f3, f3
; CHECK-P8-NEXT: mtvsrd v1, r4
; CHECK-P8-NEXT: mffprwz r4, f2 ; CHECK-P8-NEXT: mffprwz r4, f2
; CHECK-P8-NEXT: xxsldwi vs2, v0, v0, 1
; CHECK-P8-NEXT: xscvdpsxws f0, f0 ; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: vmrghh v2, v5, v1 ; CHECK-P8-NEXT: xscvspdpn f6, vs6
; CHECK-P8-NEXT: vmrghh v5, v6, v0
; CHECK-P8-NEXT: mtvsrd v0, r4
; CHECK-P8-NEXT: mffprwz r4, f4
; CHECK-P8-NEXT: xscvdpsxws f2, f3
; CHECK-P8-NEXT: xscvspdpn f5, vs5
; CHECK-P8-NEXT: mtvsrd v1, r4
; CHECK-P8-NEXT: mffprwz r4, f6
; CHECK-P8-NEXT: xscvdpsxws f1, f1
; CHECK-P8-NEXT: mtvsrd v6, r4 ; CHECK-P8-NEXT: mtvsrd v6, r4
; CHECK-P8-NEXT: mffprwz r4, f0 ; CHECK-P8-NEXT: mffprwz r4, f1
; CHECK-P8-NEXT: xscvspdpn f7, vs7 ; CHECK-P8-NEXT: xscvspdpn f7, vs7
; CHECK-P8-NEXT: xscvdpsxws f1, f4
; CHECK-P8-NEXT: mtvsrd v7, r4 ; CHECK-P8-NEXT: mtvsrd v7, r4
; CHECK-P8-NEXT: mffprwz r4, f2 ; CHECK-P8-NEXT: mffprwz r4, f3
; CHECK-P8-NEXT: xxsldwi vs2, v4, v4, 1 ; CHECK-P8-NEXT: xscvdpsxws f3, f6
; CHECK-P8-NEXT: xscvspdpn f8, vs8 ; CHECK-P8-NEXT: mtvsrd v0, r4
; CHECK-P8-NEXT: xscvdpsxws f0, f5
; CHECK-P8-NEXT: mtvsrd v4, r4
; CHECK-P8-NEXT: mffprwz r4, f1
; CHECK-P8-NEXT: xscvspdpn f1, vs2
; CHECK-P8-NEXT: xscvdpsxws f3, f7
; CHECK-P8-NEXT: mtvsrd v8, r4
; CHECK-P8-NEXT: mffprwz r4, f0 ; CHECK-P8-NEXT: mffprwz r4, f0
; CHECK-P8-NEXT: xscvdpsxws f0, f8 ; CHECK-P8-NEXT: xscvspdpn f0, vs2
; CHECK-P8-NEXT: mtvsrd v8, r4
; CHECK-P8-NEXT: mffprwz r4, f1
; CHECK-P8-NEXT: xscvdpsxws f1, f7
; CHECK-P8-NEXT: mtvsrd v9, r4 ; CHECK-P8-NEXT: mtvsrd v9, r4
; CHECK-P8-NEXT: xscvdpsxws f1, f1
; CHECK-P8-NEXT: mffprwz r4, f3 ; CHECK-P8-NEXT: mffprwz r4, f3
; CHECK-P8-NEXT: vmrghh v0, v0, v7 ; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: mtvsrd v7, r4 ; CHECK-P8-NEXT: vmrghh v6, v6, v8
; CHECK-P8-NEXT: mffprwz r4, f0
; CHECK-P8-NEXT: xxmrglw vs0, v2, v3
; CHECK-P8-NEXT: vmrghh v4, v8, v4
; CHECK-P8-NEXT: mtvsrd v8, r4 ; CHECK-P8-NEXT: mtvsrd v8, r4
; CHECK-P8-NEXT: mffprwz r4, f1 ; CHECK-P8-NEXT: mffprwz r4, f1
; CHECK-P8-NEXT: vmrghh v1, v1, v9 ; CHECK-P8-NEXT: vmrghh v5, v5, v9
; CHECK-P8-NEXT: xxmrglw vs1, v0, v5
; CHECK-P8-NEXT: mtvsrd v9, r4 ; CHECK-P8-NEXT: mtvsrd v9, r4
; CHECK-P8-NEXT: vmrghh v7, v8, v7 ; CHECK-P8-NEXT: mffprwz r4, f0
; CHECK-P8-NEXT: vmrghh v6, v6, v9 ; CHECK-P8-NEXT: xxmrglw vs0, v3, v2
; CHECK-P8-NEXT: vmrghh v7, v7, v8
; CHECK-P8-NEXT: xxmrglw vs1, v6, v4
; CHECK-P8-NEXT: mtvsrd v8, r4
; CHECK-P8-NEXT: vmrghh v1, v1, v9
; CHECK-P8-NEXT: vmrghh v0, v0, v8
; CHECK-P8-NEXT: xxmrgld v2, vs1, vs0 ; CHECK-P8-NEXT: xxmrgld v2, vs1, vs0
; CHECK-P8-NEXT: xxmrglw vs2, v1, v4 ; CHECK-P8-NEXT: xxmrglw vs2, v7, v5
; CHECK-P8-NEXT: stvx v2, 0, r3 ; CHECK-P8-NEXT: xxswapd vs1, v2
; CHECK-P8-NEXT: xxmrglw vs3, v6, v7 ; CHECK-P8-NEXT: xxmrglw vs3, v0, v1
; CHECK-P8-NEXT: xxmrgld v3, vs3, vs2 ; CHECK-P8-NEXT: xxmrgld v3, vs3, vs2
; CHECK-P8-NEXT: stvx v3, r3, r5 ; CHECK-P8-NEXT: xxswapd vs0, v3
; CHECK-P8-NEXT: stxvd2x vs0, r3, r5
; CHECK-P8-NEXT: stxvd2x vs1, 0, r3
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test16elt_signed: ; CHECK-P9-LABEL: test16elt_signed:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lxv vs1, 0(r4) ; CHECK-P9-NEXT: lxv vs1, 0(r4)
; CHECK-P9-NEXT: lxv vs0, 16(r4) ; CHECK-P9-NEXT: lxv vs0, 16(r4)
; CHECK-P9-NEXT: xxsldwi vs2, vs1, vs1, 3 ; CHECK-P9-NEXT: xxsldwi vs2, vs1, vs1, 3
; CHECK-P9-NEXT: xxswapd vs3, vs1 ; CHECK-P9-NEXT: xxswapd vs3, vs1
▲ Show 20 Lines • Show All 202 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/vec_conv_fp32_to_i64_elts.ll

Show First 20 Lines • Show All 84 Lines • ▼ Show 20 Linesentry:
store <4 x i64> %0, <4 x i64>* %agg.result, align 32 store <4 x i64> %0, <4 x i64>* %agg.result, align 32
ret void ret void
} }
define void @test8elt(<8 x i64>* noalias nocapture sret(<8 x i64>) %agg.result, <8 x float>* nocapture readonly) local_unnamed_addr #2 { define void @test8elt(<8 x i64>* noalias nocapture sret(<8 x i64>) %agg.result, <8 x float>* nocapture readonly) local_unnamed_addr #2 {
; CHECK-P8-LABEL: test8elt: ; CHECK-P8-LABEL: test8elt:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: li r5, 16 ; CHECK-P8-NEXT: li r5, 16
; CHECK-P8-NEXT: lvx v3, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs1, 0, r4
; CHECK-P8-NEXT: li r6, 32 ; CHECK-P8-NEXT: li r6, 32
; CHECK-P8-NEXT: lvx v2, r4, r5 ; CHECK-P8-NEXT: lxvd2x vs0, r4, r5
; CHECK-P8-NEXT: li r4, 48 ; CHECK-P8-NEXT: li r4, 48
; CHECK-P8-NEXT: xxswapd v3, vs1
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: xxmrglw vs2, v3, v3 ; CHECK-P8-NEXT: xxmrglw vs2, v3, v3
; CHECK-P8-NEXT: xxmrghw vs3, v3, v3 ; CHECK-P8-NEXT: xxmrghw vs3, v3, v3
; CHECK-P8-NEXT: xxmrglw vs0, v2, v2 ; CHECK-P8-NEXT: xxmrglw vs0, v2, v2
; CHECK-P8-NEXT: xxmrghw vs1, v2, v2 ; CHECK-P8-NEXT: xxmrghw vs1, v2, v2
; CHECK-P8-NEXT: xvcvspdp vs2, vs2 ; CHECK-P8-NEXT: xvcvspdp vs2, vs2
; CHECK-P8-NEXT: xvcvspdp vs0, vs0 ; CHECK-P8-NEXT: xvcvspdp vs0, vs0
; CHECK-P8-NEXT: xvcvspdp vs1, vs1 ; CHECK-P8-NEXT: xvcvspdp vs1, vs1
; CHECK-P8-NEXT: xvcvspdp vs3, vs3 ; CHECK-P8-NEXT: xvcvspdp vs3, vs3
▲ Show 20 Lines • Show All 63 Lines • ▼ Show 20 Lines
define void @test16elt(<16 x i64>* noalias nocapture sret(<16 x i64>) %agg.result, <16 x float>* nocapture readonly) local_unnamed_addr #2 { define void @test16elt(<16 x i64>* noalias nocapture sret(<16 x i64>) %agg.result, <16 x float>* nocapture readonly) local_unnamed_addr #2 {
; CHECK-P8-LABEL: test16elt: ; CHECK-P8-LABEL: test16elt:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: li r7, 48 ; CHECK-P8-NEXT: li r7, 48
; CHECK-P8-NEXT: li r5, 16 ; CHECK-P8-NEXT: li r5, 16
; CHECK-P8-NEXT: li r6, 32 ; CHECK-P8-NEXT: li r6, 32
; CHECK-P8-NEXT: li r8, 64 ; CHECK-P8-NEXT: li r8, 64
; CHECK-P8-NEXT: lvx v4, r4, r7 ; CHECK-P8-NEXT: lxvd2x vs2, r4, r7
; CHECK-P8-NEXT: lvx v2, r4, r5 ; CHECK-P8-NEXT: lxvd2x vs0, r4, r5
; CHECK-P8-NEXT: lvx v3, r4, r6 ; CHECK-P8-NEXT: lxvd2x vs1, r4, r6
; CHECK-P8-NEXT: xxswapd v4, vs2
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: lxvd2x vs0, 0, r4
; CHECK-P8-NEXT: li r4, 112
; CHECK-P8-NEXT: xxswapd v3, vs1
; CHECK-P8-NEXT: xxmrghw vs3, v4, v4 ; CHECK-P8-NEXT: xxmrghw vs3, v4, v4
; CHECK-P8-NEXT: xxmrglw vs1, v2, v2
; CHECK-P8-NEXT: xxmrghw vs2, v2, v2
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: xxmrglw vs5, v4, v4 ; CHECK-P8-NEXT: xxmrglw vs5, v4, v4
; CHECK-P8-NEXT: xxmrglw vs0, v2, v2 ; CHECK-P8-NEXT: xxmrglw vs0, v3, v3
; CHECK-P8-NEXT: xxmrghw vs1, v2, v2
; CHECK-P8-NEXT: lvx v2, 0, r4
; CHECK-P8-NEXT: li r4, 112
; CHECK-P8-NEXT: xxmrglw vs2, v3, v3
; CHECK-P8-NEXT: xxmrghw vs4, v3, v3
; CHECK-P8-NEXT: xvcvspdp vs3, vs3 ; CHECK-P8-NEXT: xvcvspdp vs3, vs3
; CHECK-P8-NEXT: xxmrghw vs4, v3, v3
; CHECK-P8-NEXT: xxmrglw vs6, v2, v2 ; CHECK-P8-NEXT: xxmrglw vs6, v2, v2
; CHECK-P8-NEXT: xxmrghw vs7, v2, v2 ; CHECK-P8-NEXT: xxmrghw vs7, v2, v2
; CHECK-P8-NEXT: xvcvspdp vs5, vs5 ; CHECK-P8-NEXT: xvcvspdp vs5, vs5
; CHECK-P8-NEXT: xvcvspdp vs0, vs0
; CHECK-P8-NEXT: xvcvspdp vs1, vs1 ; CHECK-P8-NEXT: xvcvspdp vs1, vs1
; CHECK-P8-NEXT: xvcvspdp vs2, vs2 ; CHECK-P8-NEXT: xvcvspdp vs2, vs2
; CHECK-P8-NEXT: xvcvspdp vs0, vs0
; CHECK-P8-NEXT: xvcvspdp vs4, vs4 ; CHECK-P8-NEXT: xvcvspdp vs4, vs4
; CHECK-P8-NEXT: xvcvspdp vs6, vs6 ; CHECK-P8-NEXT: xvcvspdp vs6, vs6
; CHECK-P8-NEXT: xvcvspdp vs7, vs7 ; CHECK-P8-NEXT: xvcvspdp vs7, vs7
; CHECK-P8-NEXT: xvcvdpuxds v3, vs3 ; CHECK-P8-NEXT: xvcvdpuxds v3, vs3
; CHECK-P8-NEXT: xvcvdpuxds v5, vs5 ; CHECK-P8-NEXT: xvcvdpuxds v5, vs5
; CHECK-P8-NEXT: xvcvdpuxds v2, vs0 ; CHECK-P8-NEXT: xvcvdpuxds v2, vs1
; CHECK-P8-NEXT: xvcvdpuxds v4, vs1 ; CHECK-P8-NEXT: xvcvdpuxds v4, vs2
; CHECK-P8-NEXT: xvcvdpuxds v0, vs4 ; CHECK-P8-NEXT: xvcvdpuxds v0, vs4
; CHECK-P8-NEXT: xvcvdpuxds v1, vs2 ; CHECK-P8-NEXT: xvcvdpuxds v1, vs0
; CHECK-P8-NEXT: xvcvdpuxds v6, vs6 ; CHECK-P8-NEXT: xvcvdpuxds v6, vs6
; CHECK-P8-NEXT: xxswapd vs0, v3 ; CHECK-P8-NEXT: xxswapd vs0, v3
; CHECK-P8-NEXT: xvcvdpuxds v7, vs7 ; CHECK-P8-NEXT: xvcvdpuxds v7, vs7
; CHECK-P8-NEXT: xxswapd vs1, v5 ; CHECK-P8-NEXT: xxswapd vs1, v5
; CHECK-P8-NEXT: xxswapd vs4, v2 ; CHECK-P8-NEXT: xxswapd vs4, v2
; CHECK-P8-NEXT: stxvd2x vs0, r3, r4 ; CHECK-P8-NEXT: stxvd2x vs0, r3, r4
; CHECK-P8-NEXT: li r4, 96 ; CHECK-P8-NEXT: li r4, 96
; CHECK-P8-NEXT: xxswapd vs3, v4 ; CHECK-P8-NEXT: xxswapd vs3, v4
▲ Show 20 Lines • Show All 173 Lines • ▼ Show 20 Linesentry:
store <4 x i64> %0, <4 x i64>* %agg.result, align 32 store <4 x i64> %0, <4 x i64>* %agg.result, align 32
ret void ret void
} }
define void @test8elt_signed(<8 x i64>* noalias nocapture sret(<8 x i64>) %agg.result, <8 x float>* nocapture readonly) local_unnamed_addr #2 { define void @test8elt_signed(<8 x i64>* noalias nocapture sret(<8 x i64>) %agg.result, <8 x float>* nocapture readonly) local_unnamed_addr #2 {
; CHECK-P8-LABEL: test8elt_signed: ; CHECK-P8-LABEL: test8elt_signed:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: li r5, 16 ; CHECK-P8-NEXT: li r5, 16
; CHECK-P8-NEXT: lvx v3, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs1, 0, r4
; CHECK-P8-NEXT: li r6, 32 ; CHECK-P8-NEXT: li r6, 32
; CHECK-P8-NEXT: lvx v2, r4, r5 ; CHECK-P8-NEXT: lxvd2x vs0, r4, r5
; CHECK-P8-NEXT: li r4, 48 ; CHECK-P8-NEXT: li r4, 48
; CHECK-P8-NEXT: xxswapd v3, vs1
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: xxmrglw vs2, v3, v3 ; CHECK-P8-NEXT: xxmrglw vs2, v3, v3
; CHECK-P8-NEXT: xxmrghw vs3, v3, v3 ; CHECK-P8-NEXT: xxmrghw vs3, v3, v3
; CHECK-P8-NEXT: xxmrglw vs0, v2, v2 ; CHECK-P8-NEXT: xxmrglw vs0, v2, v2
; CHECK-P8-NEXT: xxmrghw vs1, v2, v2 ; CHECK-P8-NEXT: xxmrghw vs1, v2, v2
; CHECK-P8-NEXT: xvcvspdp vs2, vs2 ; CHECK-P8-NEXT: xvcvspdp vs2, vs2
; CHECK-P8-NEXT: xvcvspdp vs0, vs0 ; CHECK-P8-NEXT: xvcvspdp vs0, vs0
; CHECK-P8-NEXT: xvcvspdp vs1, vs1 ; CHECK-P8-NEXT: xvcvspdp vs1, vs1
; CHECK-P8-NEXT: xvcvspdp vs3, vs3 ; CHECK-P8-NEXT: xvcvspdp vs3, vs3
▲ Show 20 Lines • Show All 63 Lines • ▼ Show 20 Lines
define void @test16elt_signed(<16 x i64>* noalias nocapture sret(<16 x i64>) %agg.result, <16 x float>* nocapture readonly) local_unnamed_addr #2 { define void @test16elt_signed(<16 x i64>* noalias nocapture sret(<16 x i64>) %agg.result, <16 x float>* nocapture readonly) local_unnamed_addr #2 {
; CHECK-P8-LABEL: test16elt_signed: ; CHECK-P8-LABEL: test16elt_signed:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: li r7, 48 ; CHECK-P8-NEXT: li r7, 48
; CHECK-P8-NEXT: li r5, 16 ; CHECK-P8-NEXT: li r5, 16
; CHECK-P8-NEXT: li r6, 32 ; CHECK-P8-NEXT: li r6, 32
; CHECK-P8-NEXT: li r8, 64 ; CHECK-P8-NEXT: li r8, 64
; CHECK-P8-NEXT: lvx v4, r4, r7 ; CHECK-P8-NEXT: lxvd2x vs2, r4, r7
; CHECK-P8-NEXT: lvx v2, r4, r5 ; CHECK-P8-NEXT: lxvd2x vs0, r4, r5
; CHECK-P8-NEXT: lvx v3, r4, r6 ; CHECK-P8-NEXT: lxvd2x vs1, r4, r6
; CHECK-P8-NEXT: xxswapd v4, vs2
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: lxvd2x vs0, 0, r4
; CHECK-P8-NEXT: li r4, 112
; CHECK-P8-NEXT: xxswapd v3, vs1
; CHECK-P8-NEXT: xxmrghw vs3, v4, v4 ; CHECK-P8-NEXT: xxmrghw vs3, v4, v4
; CHECK-P8-NEXT: xxmrglw vs1, v2, v2
; CHECK-P8-NEXT: xxmrghw vs2, v2, v2
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: xxmrglw vs5, v4, v4 ; CHECK-P8-NEXT: xxmrglw vs5, v4, v4
; CHECK-P8-NEXT: xxmrglw vs0, v2, v2 ; CHECK-P8-NEXT: xxmrglw vs0, v3, v3
; CHECK-P8-NEXT: xxmrghw vs1, v2, v2
; CHECK-P8-NEXT: lvx v2, 0, r4
; CHECK-P8-NEXT: li r4, 112
; CHECK-P8-NEXT: xxmrglw vs2, v3, v3
; CHECK-P8-NEXT: xxmrghw vs4, v3, v3
; CHECK-P8-NEXT: xvcvspdp vs3, vs3 ; CHECK-P8-NEXT: xvcvspdp vs3, vs3
; CHECK-P8-NEXT: xxmrghw vs4, v3, v3
; CHECK-P8-NEXT: xxmrglw vs6, v2, v2 ; CHECK-P8-NEXT: xxmrglw vs6, v2, v2
; CHECK-P8-NEXT: xxmrghw vs7, v2, v2 ; CHECK-P8-NEXT: xxmrghw vs7, v2, v2
; CHECK-P8-NEXT: xvcvspdp vs5, vs5 ; CHECK-P8-NEXT: xvcvspdp vs5, vs5
; CHECK-P8-NEXT: xvcvspdp vs0, vs0
; CHECK-P8-NEXT: xvcvspdp vs1, vs1 ; CHECK-P8-NEXT: xvcvspdp vs1, vs1
; CHECK-P8-NEXT: xvcvspdp vs2, vs2 ; CHECK-P8-NEXT: xvcvspdp vs2, vs2
; CHECK-P8-NEXT: xvcvspdp vs0, vs0
; CHECK-P8-NEXT: xvcvspdp vs4, vs4 ; CHECK-P8-NEXT: xvcvspdp vs4, vs4
; CHECK-P8-NEXT: xvcvspdp vs6, vs6 ; CHECK-P8-NEXT: xvcvspdp vs6, vs6
; CHECK-P8-NEXT: xvcvspdp vs7, vs7 ; CHECK-P8-NEXT: xvcvspdp vs7, vs7
; CHECK-P8-NEXT: xvcvdpuxds v3, vs3 ; CHECK-P8-NEXT: xvcvdpuxds v3, vs3
; CHECK-P8-NEXT: xvcvdpuxds v5, vs5 ; CHECK-P8-NEXT: xvcvdpuxds v5, vs5
; CHECK-P8-NEXT: xvcvdpuxds v2, vs0 ; CHECK-P8-NEXT: xvcvdpuxds v2, vs1
; CHECK-P8-NEXT: xvcvdpuxds v4, vs1 ; CHECK-P8-NEXT: xvcvdpuxds v4, vs2
; CHECK-P8-NEXT: xvcvdpuxds v0, vs4 ; CHECK-P8-NEXT: xvcvdpuxds v0, vs4
; CHECK-P8-NEXT: xvcvdpuxds v1, vs2 ; CHECK-P8-NEXT: xvcvdpuxds v1, vs0
; CHECK-P8-NEXT: xvcvdpuxds v6, vs6 ; CHECK-P8-NEXT: xvcvdpuxds v6, vs6
; CHECK-P8-NEXT: xxswapd vs0, v3 ; CHECK-P8-NEXT: xxswapd vs0, v3
; CHECK-P8-NEXT: xvcvdpuxds v7, vs7 ; CHECK-P8-NEXT: xvcvdpuxds v7, vs7
; CHECK-P8-NEXT: xxswapd vs1, v5 ; CHECK-P8-NEXT: xxswapd vs1, v5
; CHECK-P8-NEXT: xxswapd vs4, v2 ; CHECK-P8-NEXT: xxswapd vs4, v2
; CHECK-P8-NEXT: stxvd2x vs0, r3, r4 ; CHECK-P8-NEXT: stxvd2x vs0, r3, r4
; CHECK-P8-NEXT: li r4, 96 ; CHECK-P8-NEXT: li r4, 96
; CHECK-P8-NEXT: xxswapd vs3, v4 ; CHECK-P8-NEXT: xxswapd vs3, v4
▲ Show 20 Lines • Show All 99 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/vec_conv_fp32_to_i8_elts.ll

Show First 20 Lines • Show All 169 Lines • ▼ Show 20 Linesentry:
%0 = fptoui <4 x float> %a to <4 x i8> %0 = fptoui <4 x float> %a to <4 x i8>
%1 = bitcast <4 x i8> %0 to i32 %1 = bitcast <4 x i8> %0 to i32
ret i32 %1 ret i32 %1
} }
define i64 @test8elt(<8 x float>* nocapture readonly) local_unnamed_addr #2 { define i64 @test8elt(<8 x float>* nocapture readonly) local_unnamed_addr #2 {
; CHECK-P8-LABEL: test8elt: ; CHECK-P8-LABEL: test8elt:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: li r4, 16 ; CHECK-P8-NEXT: li r4, 16
; CHECK-P8-NEXT: lvx v3, r3, r4 ; CHECK-P8-NEXT: lxvd2x vs1, r3, r4
; CHECK-P8-NEXT: xxsldwi vs0, v2, v2, 3 ; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: xxswapd vs1, v2
; CHECK-P8-NEXT: xscvspdpn f2, v2
; CHECK-P8-NEXT: xxsldwi vs4, v2, v2, 1
; CHECK-P8-NEXT: xxsldwi vs5, v3, v3, 3
; CHECK-P8-NEXT: xscvspdpn f3, v3
; CHECK-P8-NEXT: xscvspdpn f0, vs0 ; CHECK-P8-NEXT: xscvspdpn f0, vs0
; CHECK-P8-NEXT: xxswapd v3, vs1
; CHECK-P8-NEXT: xscvspdpn f1, vs1 ; CHECK-P8-NEXT: xscvspdpn f1, vs1
; CHECK-P8-NEXT: xxsldwi vs2, v2, v2, 3
; CHECK-P8-NEXT: xxsldwi vs4, v2, v2, 1
; CHECK-P8-NEXT: xscvspdpn f3, v2
; CHECK-P8-NEXT: xxsldwi vs6, v3, v3, 3
; CHECK-P8-NEXT: xxsldwi vs7, v3, v3, 1
; CHECK-P8-NEXT: xscvspdpn f5, v3
; CHECK-P8-NEXT: xscvspdpn f2, vs2
; CHECK-P8-NEXT: xscvspdpn f4, vs4 ; CHECK-P8-NEXT: xscvspdpn f4, vs4
; CHECK-P8-NEXT: xscvspdpn f5, vs5
; CHECK-P8-NEXT: xscvdpsxws f2, f2
; CHECK-P8-NEXT: xscvdpsxws f3, f3
; CHECK-P8-NEXT: xscvdpsxws f0, f0 ; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: xscvspdpn f6, vs6
; CHECK-P8-NEXT: xscvdpsxws f3, f3
; CHECK-P8-NEXT: xscvspdpn f7, vs7
; CHECK-P8-NEXT: xscvdpsxws f2, f2
; CHECK-P8-NEXT: xscvdpsxws f4, f4
; CHECK-P8-NEXT: xscvdpsxws f1, f1 ; CHECK-P8-NEXT: xscvdpsxws f1, f1
; CHECK-P8-NEXT: xscvdpsxws f5, f5
; CHECK-P8-NEXT: mffprwz r3, f0 ; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: xxswapd vs0, v3 ; CHECK-P8-NEXT: mffprwz r4, f3
; CHECK-P8-NEXT: mffprwz r4, f1
; CHECK-P8-NEXT: xxsldwi vs1, v3, v3, 1
; CHECK-P8-NEXT: mtvsrd v2, r3 ; CHECK-P8-NEXT: mtvsrd v2, r3
; CHECK-P8-NEXT: xscvspdpn f0, vs0
; CHECK-P8-NEXT: mffprwz r3, f2 ; CHECK-P8-NEXT: mffprwz r3, f2
; CHECK-P8-NEXT: xscvdpsxws f2, f4 ; CHECK-P8-NEXT: xscvdpsxws f0, f6
; CHECK-P8-NEXT: xscvspdpn f1, vs1 ; CHECK-P8-NEXT: xscvdpsxws f2, f7
; CHECK-P8-NEXT: xscvdpsxws f4, f5 ; CHECK-P8-NEXT: mtvsrd v3, r4
; CHECK-P8-NEXT: mtvsrd v4, r4 ; CHECK-P8-NEXT: mffprwz r4, f4
; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: vmrghb v2, v4, v2
; CHECK-P8-NEXT: mffprwz r4, f2
; CHECK-P8-NEXT: xscvdpsxws f1, f1
; CHECK-P8-NEXT: mtvsrd v3, r3
; CHECK-P8-NEXT: mffprwz r3, f3
; CHECK-P8-NEXT: mtvsrd v4, r4
; CHECK-P8-NEXT: mffprwz r4, f0
; CHECK-P8-NEXT: vmrghb v3, v3, v4
; CHECK-P8-NEXT: mtvsrd v4, r3 ; CHECK-P8-NEXT: mtvsrd v4, r3
; CHECK-P8-NEXT: mffprwz r3, f4 ; CHECK-P8-NEXT: mtvsrd v5, r4
; CHECK-P8-NEXT: mtvsrd v0, r4
; CHECK-P8-NEXT: mtvsrd v5, r3
; CHECK-P8-NEXT: mffprwz r3, f1 ; CHECK-P8-NEXT: mffprwz r3, f1
; CHECK-P8-NEXT: vmrghb v5, v0, v5 ; CHECK-P8-NEXT: mffprwz r4, f5
; CHECK-P8-NEXT: mtvsrd v1, r3 ; CHECK-P8-NEXT: vmrghb v2, v2, v4
; CHECK-P8-NEXT: vmrghb v3, v3, v5
; CHECK-P8-NEXT: mtvsrd v4, r3
; CHECK-P8-NEXT: mtvsrd v5, r4
; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: mffprwz r4, f2
; CHECK-P8-NEXT: mtvsrd v0, r3
; CHECK-P8-NEXT: mtvsrd v1, r4
; CHECK-P8-NEXT: vmrghb v4, v4, v0
; CHECK-P8-NEXT: vmrghb v5, v5, v1
; CHECK-P8-NEXT: vmrglh v2, v3, v2 ; CHECK-P8-NEXT: vmrglh v2, v3, v2
; CHECK-P8-NEXT: vmrghb v4, v4, v1 ; CHECK-P8-NEXT: vmrglh v3, v5, v4
; CHECK-P8-NEXT: vmrglh v3, v4, v5
; CHECK-P8-NEXT: xxmrglw vs0, v3, v2 ; CHECK-P8-NEXT: xxmrglw vs0, v3, v2
; CHECK-P8-NEXT: xxswapd vs0, vs0 ; CHECK-P8-NEXT: xxswapd vs0, vs0
; CHECK-P8-NEXT: mffprd r3, f0 ; CHECK-P8-NEXT: mffprd r3, f0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test8elt: ; CHECK-P9-LABEL: test8elt:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lxv vs1, 0(r3) ; CHECK-P9-NEXT: lxv vs1, 0(r3)
▲ Show 20 Lines • Show All 105 Lines • ▼ Show 20 Linesentry:
%1 = fptoui <8 x float> %a to <8 x i8> %1 = fptoui <8 x float> %a to <8 x i8>
%2 = bitcast <8 x i8> %1 to i64 %2 = bitcast <8 x i8> %1 to i64
ret i64 %2 ret i64 %2
} }
define <16 x i8> @test16elt(<16 x float>* nocapture readonly) local_unnamed_addr #3 { define <16 x i8> @test16elt(<16 x float>* nocapture readonly) local_unnamed_addr #3 {
; CHECK-P8-LABEL: test16elt: ; CHECK-P8-LABEL: test16elt:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: lvx v4, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: li r4, 16 ; CHECK-P8-NEXT: li r4, 16
; CHECK-P8-NEXT: li r5, 32 ; CHECK-P8-NEXT: lxvd2x vs2, r3, r4
; CHECK-P8-NEXT: lvx v3, r3, r4 ; CHECK-P8-NEXT: li r4, 32
; CHECK-P8-NEXT: lvx v2, r3, r5 ; CHECK-P8-NEXT: lxvd2x vs3, r3, r4
; CHECK-P8-NEXT: xxsldwi vs0, v4, v4, 3 ; CHECK-P8-NEXT: li r4, 48
; CHECK-P8-NEXT: xxswapd vs2, v4 ; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: xxsldwi vs4, v4, v4, 1
; CHECK-P8-NEXT: xscvspdpn f1, v4
; CHECK-P8-NEXT: xscvspdpn f3, v3
; CHECK-P8-NEXT: xxsldwi vs6, v3, v3, 3
; CHECK-P8-NEXT: xscvspdpn f0, vs0 ; CHECK-P8-NEXT: xscvspdpn f0, vs0
; CHECK-P8-NEXT: xxswapd vs7, v3 ; CHECK-P8-NEXT: lxvd2x vs4, r3, r4
; CHECK-P8-NEXT: xxswapd v3, vs2
; CHECK-P8-NEXT: xscvspdpn f5, vs2
; CHECK-P8-NEXT: xxswapd v5, vs3
; CHECK-P8-NEXT: xscvspdpn f6, vs3
; CHECK-P8-NEXT: xxsldwi vs1, v2, v2, 3
; CHECK-P8-NEXT: xscvspdpn f8, v2
; CHECK-P8-NEXT: xxsldwi vs2, v3, v3, 3
; CHECK-P8-NEXT: xxsldwi vs9, v3, v3, 1
; CHECK-P8-NEXT: xscvspdpn f3, v5
; CHECK-P8-NEXT: xxswapd v7, vs4
; CHECK-P8-NEXT: xscvspdpn f1, vs1
; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: xscvspdpn f2, vs2 ; CHECK-P8-NEXT: xscvspdpn f2, vs2
; CHECK-P8-NEXT: xxsldwi vs8, v3, v3, 1 ; CHECK-P8-NEXT: xscvdpsxws f5, f5
; CHECK-P8-NEXT: xscvspdpn f4, vs4 ; CHECK-P8-NEXT: xscvdpsxws f8, f8
; CHECK-P8-NEXT: xxsldwi vs9, v2, v2, 3 ; CHECK-P8-NEXT: xscvspdpn f9, vs9
; CHECK-P8-NEXT: xscvspdpn f6, vs6
; CHECK-P8-NEXT: xscvdpsxws f1, f1 ; CHECK-P8-NEXT: xscvdpsxws f1, f1
; CHECK-P8-NEXT: xscvspdpn f7, vs7 ; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: xscvdpsxws f0, f0 ; CHECK-P8-NEXT: xxsldwi vs0, v2, v2, 1
; CHECK-P8-NEXT: xscvdpsxws f2, f2 ; CHECK-P8-NEXT: xscvdpsxws f2, f2
; CHECK-P8-NEXT: xscvdpsxws f4, f4 ; CHECK-P8-NEXT: mtvsrd v4, r3
; CHECK-P8-NEXT: xscvspdpn f8, vs8
; CHECK-P8-NEXT: xscvdpsxws f3, f3
; CHECK-P8-NEXT: xscvspdpn f9, vs9
; CHECK-P8-NEXT: mffprwz r4, f0
; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: mffprwz r5, f2
; CHECK-P8-NEXT: mtvsrd v3, r4
; CHECK-P8-NEXT: xscvspdpn f0, vs0 ; CHECK-P8-NEXT: xscvspdpn f0, vs0
; CHECK-P8-NEXT: mffprwz r3, f5
; CHECK-P8-NEXT: mffprwz r4, f1 ; CHECK-P8-NEXT: mffprwz r4, f1
; CHECK-P8-NEXT: mtvsrd v4, r5 ; CHECK-P8-NEXT: xscvspdpn f1, v3
; CHECK-P8-NEXT: mffprwz r5, f4 ; CHECK-P8-NEXT: mtvsrd v0, r4
; CHECK-P8-NEXT: xscvdpsxws f1, f6 ; CHECK-P8-NEXT: mtvsrd v3, r3
; CHECK-P8-NEXT: vmrghb v3, v4, v3
; CHECK-P8-NEXT: mtvsrd v4, r5
; CHECK-P8-NEXT: mffprwz r5, f3
; CHECK-P8-NEXT: xscvdpsxws f3, f7
; CHECK-P8-NEXT: xscvdpsxws f4, f8
; CHECK-P8-NEXT: xscvdpsxws f0, f0 ; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: mtvsrd v5, r4 ; CHECK-P8-NEXT: mffprwz r3, f8
; CHECK-P8-NEXT: li r4, 48 ; CHECK-P8-NEXT: vmrghb v2, v4, v0
; CHECK-P8-NEXT: lvx v0, r3, r4 ; CHECK-P8-NEXT: xscvdpsxws f1, f1
; CHECK-P8-NEXT: mffprwz r3, f1 ; CHECK-P8-NEXT: xscvdpsxws f5, f9
; CHECK-P8-NEXT: xxsldwi vs1, v2, v2, 1 ; CHECK-P8-NEXT: mtvsrd v4, r3
; CHECK-P8-NEXT: xscvspdpn f5, v2
; CHECK-P8-NEXT: mffprwz r4, f3
; CHECK-P8-NEXT: xxsldwi vs3, v0, v0, 3
; CHECK-P8-NEXT: mtvsrd v1, r3
; CHECK-P8-NEXT: mffprwz r3, f4
; CHECK-P8-NEXT: xxswapd vs4, v0
; CHECK-P8-NEXT: xscvspdpn f1, vs1
; CHECK-P8-NEXT: mtvsrd v7, r3
; CHECK-P8-NEXT: mffprwz r3, f0 ; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: xxsldwi vs0, v0, v0, 1 ; CHECK-P8-NEXT: xxsldwi vs0, v5, v5, 3
; CHECK-P8-NEXT: xscvspdpn f2, v0 ; CHECK-P8-NEXT: xscvspdpn f7, vs4
; CHECK-P8-NEXT: xscvspdpn f3, vs3 ; CHECK-P8-NEXT: xxsldwi vs4, v7, v7, 3
; CHECK-P8-NEXT: xscvdpsxws f6, f9 ; CHECK-P8-NEXT: mtvsrd v1, r3
; CHECK-P8-NEXT: xscvspdpn f4, vs4 ; CHECK-P8-NEXT: mffprwz r4, f1
; CHECK-P8-NEXT: xscvspdpn f0, vs0 ; CHECK-P8-NEXT: xscvspdpn f0, vs0
; CHECK-P8-NEXT: xscvdpsxws f5, f5 ; CHECK-P8-NEXT: mtvsrd v0, r4
; CHECK-P8-NEXT: xscvdpsxws f1, f1 ; CHECK-P8-NEXT: mffprwz r4, f2
; CHECK-P8-NEXT: xscvdpsxws f2, f2 ; CHECK-P8-NEXT: xxsldwi vs2, v5, v5, 1
; CHECK-P8-NEXT: mffprwz r3, f5
; CHECK-P8-NEXT: xscvdpsxws f5, f6
; CHECK-P8-NEXT: xxsldwi vs6, v7, v7, 1
; CHECK-P8-NEXT: xscvspdpn f2, vs2
; CHECK-P8-NEXT: xscvspdpn f1, v7
; CHECK-P8-NEXT: xscvdpsxws f3, f3 ; CHECK-P8-NEXT: xscvdpsxws f3, f3
; CHECK-P8-NEXT: mtvsrd v6, r4 ; CHECK-P8-NEXT: xscvspdpn f4, vs4
; CHECK-P8-NEXT: mffprwz r4, f6 ; CHECK-P8-NEXT: xscvspdpn f6, vs6
; CHECK-P8-NEXT: xscvdpsxws f4, f4
; CHECK-P8-NEXT: xscvdpsxws f0, f0 ; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: vmrghb v2, v6, v1 ; CHECK-P8-NEXT: xscvdpsxws f2, f2
; CHECK-P8-NEXT: mtvsrd v1, r4 ; CHECK-P8-NEXT: mtvsrd v6, r4
; CHECK-P8-NEXT: mffprwz r4, f5 ; CHECK-P8-NEXT: mtvsrd v8, r3
; CHECK-P8-NEXT: mtvsrd v6, r3 ; CHECK-P8-NEXT: xscvdpsxws f7, f7
; CHECK-P8-NEXT: mffprwz r3, f1 ; CHECK-P8-NEXT: xscvdpsxws f1, f1
; CHECK-P8-NEXT: vmrghb v4, v5, v4 ; CHECK-P8-NEXT: mffprwz r3, f5
; CHECK-P8-NEXT: mtvsrd v5, r5 ; CHECK-P8-NEXT: mffprwz r4, f3
; CHECK-P8-NEXT: vmrghb v0, v6, v1 ; CHECK-P8-NEXT: vmrghb v4, v4, v1
; CHECK-P8-NEXT: vmrghb v5, v0, v8
; CHECK-P8-NEXT: mtvsrd v0, r3
; CHECK-P8-NEXT: mtvsrd v1, r4 ; CHECK-P8-NEXT: mtvsrd v1, r4
; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: mffprwz r4, f2 ; CHECK-P8-NEXT: mffprwz r4, f2
; CHECK-P8-NEXT: xscvdpsxws f0, f4
; CHECK-P8-NEXT: xscvdpsxws f2, f6
; CHECK-P8-NEXT: vmrghb v3, v3, v6
; CHECK-P8-NEXT: mtvsrd v6, r3 ; CHECK-P8-NEXT: mtvsrd v6, r3
; CHECK-P8-NEXT: mffprwz r3, f3 ; CHECK-P8-NEXT: mtvsrd v7, r4
; CHECK-P8-NEXT: vmrghb v5, v5, v7 ; CHECK-P8-NEXT: mffprwz r3, f7
; CHECK-P8-NEXT: vmrghb v1, v1, v6 ; CHECK-P8-NEXT: mffprwz r4, f1
; CHECK-P8-NEXT: mtvsrd v6, r4 ; CHECK-P8-NEXT: vmrghb v0, v0, v6
; CHECK-P8-NEXT: mffprwz r4, f4 ; CHECK-P8-NEXT: vmrghb v1, v1, v7
; CHECK-P8-NEXT: mtvsrd v7, r3 ; CHECK-P8-NEXT: mtvsrd v6, r3
; CHECK-P8-NEXT: mtvsrd v7, r4
; CHECK-P8-NEXT: mffprwz r3, f0 ; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: mtvsrd v8, r4 ; CHECK-P8-NEXT: mffprwz r4, f2
; CHECK-P8-NEXT: mtvsrd v9, r3 ; CHECK-P8-NEXT: mtvsrd v8, r3
; CHECK-P8-NEXT: vmrghb v7, v8, v7 ; CHECK-P8-NEXT: mtvsrd v9, r4
; CHECK-P8-NEXT: vmrghb v6, v6, v9 ; CHECK-P8-NEXT: vmrghb v6, v6, v8
; CHECK-P8-NEXT: vmrglh v3, v4, v3 ; CHECK-P8-NEXT: vmrghb v7, v7, v9
; CHECK-P8-NEXT: vmrglh v2, v5, v2 ; CHECK-P8-NEXT: vmrglh v2, v4, v2
; CHECK-P8-NEXT: vmrglh v3, v5, v3
; CHECK-P8-NEXT: vmrglh v4, v1, v0 ; CHECK-P8-NEXT: vmrglh v4, v1, v0
; CHECK-P8-NEXT: vmrglh v5, v6, v7 ; CHECK-P8-NEXT: vmrglh v5, v7, v6
; CHECK-P8-NEXT: xxmrglw vs0, v2, v3 ; CHECK-P8-NEXT: xxmrglw vs0, v3, v2
; CHECK-P8-NEXT: xxmrglw vs1, v5, v4 ; CHECK-P8-NEXT: xxmrglw vs1, v5, v4
; CHECK-P8-NEXT: xxmrgld v2, vs1, vs0 ; CHECK-P8-NEXT: xxmrgld v2, vs1, vs0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test16elt: ; CHECK-P9-LABEL: test16elt:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lxv vs3, 0(r3) ; CHECK-P9-NEXT: lxv vs3, 0(r3)
; CHECK-P9-NEXT: lxv vs0, 48(r3) ; CHECK-P9-NEXT: lxv vs0, 48(r3)
▲ Show 20 Lines • Show All 360 Lines • ▼ Show 20 Linesentry:
%0 = fptosi <4 x float> %a to <4 x i8> %0 = fptosi <4 x float> %a to <4 x i8>
%1 = bitcast <4 x i8> %0 to i32 %1 = bitcast <4 x i8> %0 to i32
ret i32 %1 ret i32 %1
} }
define i64 @test8elt_signed(<8 x float>* nocapture readonly) local_unnamed_addr #2 { define i64 @test8elt_signed(<8 x float>* nocapture readonly) local_unnamed_addr #2 {
; CHECK-P8-LABEL: test8elt_signed: ; CHECK-P8-LABEL: test8elt_signed:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: li r4, 16 ; CHECK-P8-NEXT: li r4, 16
; CHECK-P8-NEXT: lvx v3, r3, r4 ; CHECK-P8-NEXT: lxvd2x vs1, r3, r4
; CHECK-P8-NEXT: xxsldwi vs0, v2, v2, 3 ; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: xxswapd vs1, v2
; CHECK-P8-NEXT: xscvspdpn f2, v2
; CHECK-P8-NEXT: xxsldwi vs4, v2, v2, 1
; CHECK-P8-NEXT: xxsldwi vs5, v3, v3, 3
; CHECK-P8-NEXT: xscvspdpn f3, v3
; CHECK-P8-NEXT: xscvspdpn f0, vs0 ; CHECK-P8-NEXT: xscvspdpn f0, vs0
; CHECK-P8-NEXT: xxswapd v3, vs1
; CHECK-P8-NEXT: xscvspdpn f1, vs1 ; CHECK-P8-NEXT: xscvspdpn f1, vs1
; CHECK-P8-NEXT: xxsldwi vs2, v2, v2, 3
; CHECK-P8-NEXT: xxsldwi vs4, v2, v2, 1
; CHECK-P8-NEXT: xscvspdpn f3, v2
; CHECK-P8-NEXT: xxsldwi vs6, v3, v3, 3
; CHECK-P8-NEXT: xxsldwi vs7, v3, v3, 1
; CHECK-P8-NEXT: xscvspdpn f5, v3
; CHECK-P8-NEXT: xscvspdpn f2, vs2
; CHECK-P8-NEXT: xscvspdpn f4, vs4 ; CHECK-P8-NEXT: xscvspdpn f4, vs4
; CHECK-P8-NEXT: xscvspdpn f5, vs5
; CHECK-P8-NEXT: xscvdpsxws f2, f2
; CHECK-P8-NEXT: xscvdpsxws f3, f3
; CHECK-P8-NEXT: xscvdpsxws f0, f0 ; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: xscvspdpn f6, vs6
; CHECK-P8-NEXT: xscvdpsxws f3, f3
; CHECK-P8-NEXT: xscvspdpn f7, vs7
; CHECK-P8-NEXT: xscvdpsxws f2, f2
; CHECK-P8-NEXT: xscvdpsxws f4, f4
; CHECK-P8-NEXT: xscvdpsxws f1, f1 ; CHECK-P8-NEXT: xscvdpsxws f1, f1
; CHECK-P8-NEXT: xscvdpsxws f5, f5
; CHECK-P8-NEXT: mffprwz r3, f0 ; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: xxswapd vs0, v3 ; CHECK-P8-NEXT: mffprwz r4, f3
; CHECK-P8-NEXT: mffprwz r4, f1
; CHECK-P8-NEXT: xxsldwi vs1, v3, v3, 1
; CHECK-P8-NEXT: mtvsrd v2, r3 ; CHECK-P8-NEXT: mtvsrd v2, r3
; CHECK-P8-NEXT: xscvspdpn f0, vs0
; CHECK-P8-NEXT: mffprwz r3, f2 ; CHECK-P8-NEXT: mffprwz r3, f2
; CHECK-P8-NEXT: xscvdpsxws f2, f4 ; CHECK-P8-NEXT: xscvdpsxws f0, f6
; CHECK-P8-NEXT: xscvspdpn f1, vs1 ; CHECK-P8-NEXT: xscvdpsxws f2, f7
; CHECK-P8-NEXT: xscvdpsxws f4, f5 ; CHECK-P8-NEXT: mtvsrd v3, r4
; CHECK-P8-NEXT: mtvsrd v4, r4 ; CHECK-P8-NEXT: mffprwz r4, f4
; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: vmrghb v2, v4, v2
; CHECK-P8-NEXT: mffprwz r4, f2
; CHECK-P8-NEXT: xscvdpsxws f1, f1
; CHECK-P8-NEXT: mtvsrd v3, r3
; CHECK-P8-NEXT: mffprwz r3, f3
; CHECK-P8-NEXT: mtvsrd v4, r4
; CHECK-P8-NEXT: mffprwz r4, f0
; CHECK-P8-NEXT: vmrghb v3, v3, v4
; CHECK-P8-NEXT: mtvsrd v4, r3 ; CHECK-P8-NEXT: mtvsrd v4, r3
; CHECK-P8-NEXT: mffprwz r3, f4 ; CHECK-P8-NEXT: mtvsrd v5, r4
; CHECK-P8-NEXT: mtvsrd v0, r4
; CHECK-P8-NEXT: mtvsrd v5, r3
; CHECK-P8-NEXT: mffprwz r3, f1 ; CHECK-P8-NEXT: mffprwz r3, f1
; CHECK-P8-NEXT: vmrghb v5, v0, v5 ; CHECK-P8-NEXT: mffprwz r4, f5
; CHECK-P8-NEXT: mtvsrd v1, r3 ; CHECK-P8-NEXT: vmrghb v2, v2, v4
; CHECK-P8-NEXT: vmrghb v3, v3, v5
; CHECK-P8-NEXT: mtvsrd v4, r3
; CHECK-P8-NEXT: mtvsrd v5, r4
; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: mffprwz r4, f2
; CHECK-P8-NEXT: mtvsrd v0, r3
; CHECK-P8-NEXT: mtvsrd v1, r4
; CHECK-P8-NEXT: vmrghb v4, v4, v0
; CHECK-P8-NEXT: vmrghb v5, v5, v1
; CHECK-P8-NEXT: vmrglh v2, v3, v2 ; CHECK-P8-NEXT: vmrglh v2, v3, v2
; CHECK-P8-NEXT: vmrghb v4, v4, v1 ; CHECK-P8-NEXT: vmrglh v3, v5, v4
; CHECK-P8-NEXT: vmrglh v3, v4, v5
; CHECK-P8-NEXT: xxmrglw vs0, v3, v2 ; CHECK-P8-NEXT: xxmrglw vs0, v3, v2
; CHECK-P8-NEXT: xxswapd vs0, vs0 ; CHECK-P8-NEXT: xxswapd vs0, vs0
; CHECK-P8-NEXT: mffprd r3, f0 ; CHECK-P8-NEXT: mffprd r3, f0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test8elt_signed: ; CHECK-P9-LABEL: test8elt_signed:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lxv vs1, 0(r3) ; CHECK-P9-NEXT: lxv vs1, 0(r3)
▲ Show 20 Lines • Show All 105 Lines • ▼ Show 20 Linesentry:
%1 = fptosi <8 x float> %a to <8 x i8> %1 = fptosi <8 x float> %a to <8 x i8>
%2 = bitcast <8 x i8> %1 to i64 %2 = bitcast <8 x i8> %1 to i64
ret i64 %2 ret i64 %2
} }
define <16 x i8> @test16elt_signed(<16 x float>* nocapture readonly) local_unnamed_addr #3 { define <16 x i8> @test16elt_signed(<16 x float>* nocapture readonly) local_unnamed_addr #3 {
; CHECK-P8-LABEL: test16elt_signed: ; CHECK-P8-LABEL: test16elt_signed:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: lvx v4, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: li r4, 16 ; CHECK-P8-NEXT: li r4, 16
; CHECK-P8-NEXT: li r5, 32 ; CHECK-P8-NEXT: lxvd2x vs2, r3, r4
; CHECK-P8-NEXT: lvx v3, r3, r4 ; CHECK-P8-NEXT: li r4, 32
; CHECK-P8-NEXT: lvx v2, r3, r5 ; CHECK-P8-NEXT: lxvd2x vs3, r3, r4
; CHECK-P8-NEXT: xxsldwi vs0, v4, v4, 3 ; CHECK-P8-NEXT: li r4, 48
; CHECK-P8-NEXT: xxswapd vs2, v4 ; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: xxsldwi vs4, v4, v4, 1
; CHECK-P8-NEXT: xscvspdpn f1, v4
; CHECK-P8-NEXT: xscvspdpn f3, v3
; CHECK-P8-NEXT: xxsldwi vs6, v3, v3, 3
; CHECK-P8-NEXT: xscvspdpn f0, vs0 ; CHECK-P8-NEXT: xscvspdpn f0, vs0
; CHECK-P8-NEXT: xxswapd vs7, v3 ; CHECK-P8-NEXT: lxvd2x vs4, r3, r4
; CHECK-P8-NEXT: xxswapd v3, vs2
; CHECK-P8-NEXT: xscvspdpn f5, vs2
; CHECK-P8-NEXT: xxswapd v5, vs3
; CHECK-P8-NEXT: xscvspdpn f6, vs3
; CHECK-P8-NEXT: xxsldwi vs1, v2, v2, 3
; CHECK-P8-NEXT: xscvspdpn f8, v2
; CHECK-P8-NEXT: xxsldwi vs2, v3, v3, 3
; CHECK-P8-NEXT: xxsldwi vs9, v3, v3, 1
; CHECK-P8-NEXT: xscvspdpn f3, v5
; CHECK-P8-NEXT: xxswapd v7, vs4
; CHECK-P8-NEXT: xscvspdpn f1, vs1
; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: xscvspdpn f2, vs2 ; CHECK-P8-NEXT: xscvspdpn f2, vs2
; CHECK-P8-NEXT: xxsldwi vs8, v3, v3, 1 ; CHECK-P8-NEXT: xscvdpsxws f5, f5
; CHECK-P8-NEXT: xscvspdpn f4, vs4 ; CHECK-P8-NEXT: xscvdpsxws f8, f8
; CHECK-P8-NEXT: xxsldwi vs9, v2, v2, 3 ; CHECK-P8-NEXT: xscvspdpn f9, vs9
; CHECK-P8-NEXT: xscvspdpn f6, vs6
; CHECK-P8-NEXT: xscvdpsxws f1, f1 ; CHECK-P8-NEXT: xscvdpsxws f1, f1
; CHECK-P8-NEXT: xscvspdpn f7, vs7 ; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: xscvdpsxws f0, f0 ; CHECK-P8-NEXT: xxsldwi vs0, v2, v2, 1
; CHECK-P8-NEXT: xscvdpsxws f2, f2 ; CHECK-P8-NEXT: xscvdpsxws f2, f2
; CHECK-P8-NEXT: xscvdpsxws f4, f4 ; CHECK-P8-NEXT: mtvsrd v4, r3
; CHECK-P8-NEXT: xscvspdpn f8, vs8
; CHECK-P8-NEXT: xscvdpsxws f3, f3
; CHECK-P8-NEXT: xscvspdpn f9, vs9
; CHECK-P8-NEXT: mffprwz r4, f0
; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: mffprwz r5, f2
; CHECK-P8-NEXT: mtvsrd v3, r4
; CHECK-P8-NEXT: xscvspdpn f0, vs0 ; CHECK-P8-NEXT: xscvspdpn f0, vs0
; CHECK-P8-NEXT: mffprwz r3, f5
; CHECK-P8-NEXT: mffprwz r4, f1 ; CHECK-P8-NEXT: mffprwz r4, f1
; CHECK-P8-NEXT: mtvsrd v4, r5 ; CHECK-P8-NEXT: xscvspdpn f1, v3
; CHECK-P8-NEXT: mffprwz r5, f4 ; CHECK-P8-NEXT: mtvsrd v0, r4
; CHECK-P8-NEXT: xscvdpsxws f1, f6 ; CHECK-P8-NEXT: mtvsrd v3, r3
; CHECK-P8-NEXT: vmrghb v3, v4, v3
; CHECK-P8-NEXT: mtvsrd v4, r5
; CHECK-P8-NEXT: mffprwz r5, f3
; CHECK-P8-NEXT: xscvdpsxws f3, f7
; CHECK-P8-NEXT: xscvdpsxws f4, f8
; CHECK-P8-NEXT: xscvdpsxws f0, f0 ; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: mtvsrd v5, r4 ; CHECK-P8-NEXT: mffprwz r3, f8
; CHECK-P8-NEXT: li r4, 48 ; CHECK-P8-NEXT: vmrghb v2, v4, v0
; CHECK-P8-NEXT: lvx v0, r3, r4 ; CHECK-P8-NEXT: xscvdpsxws f1, f1
; CHECK-P8-NEXT: mffprwz r3, f1 ; CHECK-P8-NEXT: xscvdpsxws f5, f9
; CHECK-P8-NEXT: xxsldwi vs1, v2, v2, 1 ; CHECK-P8-NEXT: mtvsrd v4, r3
; CHECK-P8-NEXT: xscvspdpn f5, v2
; CHECK-P8-NEXT: mffprwz r4, f3
; CHECK-P8-NEXT: xxsldwi vs3, v0, v0, 3
; CHECK-P8-NEXT: mtvsrd v1, r3
; CHECK-P8-NEXT: mffprwz r3, f4
; CHECK-P8-NEXT: xxswapd vs4, v0
; CHECK-P8-NEXT: xscvspdpn f1, vs1
; CHECK-P8-NEXT: mtvsrd v7, r3
; CHECK-P8-NEXT: mffprwz r3, f0 ; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: xxsldwi vs0, v0, v0, 1 ; CHECK-P8-NEXT: xxsldwi vs0, v5, v5, 3
; CHECK-P8-NEXT: xscvspdpn f2, v0 ; CHECK-P8-NEXT: xscvspdpn f7, vs4
; CHECK-P8-NEXT: xscvspdpn f3, vs3 ; CHECK-P8-NEXT: xxsldwi vs4, v7, v7, 3
; CHECK-P8-NEXT: xscvdpsxws f6, f9 ; CHECK-P8-NEXT: mtvsrd v1, r3
; CHECK-P8-NEXT: xscvspdpn f4, vs4 ; CHECK-P8-NEXT: mffprwz r4, f1
; CHECK-P8-NEXT: xscvspdpn f0, vs0 ; CHECK-P8-NEXT: xscvspdpn f0, vs0
; CHECK-P8-NEXT: xscvdpsxws f5, f5 ; CHECK-P8-NEXT: mtvsrd v0, r4
; CHECK-P8-NEXT: xscvdpsxws f1, f1 ; CHECK-P8-NEXT: mffprwz r4, f2
; CHECK-P8-NEXT: xscvdpsxws f2, f2 ; CHECK-P8-NEXT: xxsldwi vs2, v5, v5, 1
; CHECK-P8-NEXT: mffprwz r3, f5
; CHECK-P8-NEXT: xscvdpsxws f5, f6
; CHECK-P8-NEXT: xxsldwi vs6, v7, v7, 1
; CHECK-P8-NEXT: xscvspdpn f2, vs2
; CHECK-P8-NEXT: xscvspdpn f1, v7
; CHECK-P8-NEXT: xscvdpsxws f3, f3 ; CHECK-P8-NEXT: xscvdpsxws f3, f3
; CHECK-P8-NEXT: mtvsrd v6, r4 ; CHECK-P8-NEXT: xscvspdpn f4, vs4
; CHECK-P8-NEXT: mffprwz r4, f6 ; CHECK-P8-NEXT: xscvspdpn f6, vs6
; CHECK-P8-NEXT: xscvdpsxws f4, f4
; CHECK-P8-NEXT: xscvdpsxws f0, f0 ; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: vmrghb v2, v6, v1 ; CHECK-P8-NEXT: xscvdpsxws f2, f2
; CHECK-P8-NEXT: mtvsrd v1, r4 ; CHECK-P8-NEXT: mtvsrd v6, r4
; CHECK-P8-NEXT: mffprwz r4, f5 ; CHECK-P8-NEXT: mtvsrd v8, r3
; CHECK-P8-NEXT: mtvsrd v6, r3 ; CHECK-P8-NEXT: xscvdpsxws f7, f7
; CHECK-P8-NEXT: mffprwz r3, f1 ; CHECK-P8-NEXT: xscvdpsxws f1, f1
; CHECK-P8-NEXT: vmrghb v4, v5, v4 ; CHECK-P8-NEXT: mffprwz r3, f5
; CHECK-P8-NEXT: mtvsrd v5, r5 ; CHECK-P8-NEXT: mffprwz r4, f3
; CHECK-P8-NEXT: vmrghb v0, v6, v1 ; CHECK-P8-NEXT: vmrghb v4, v4, v1
; CHECK-P8-NEXT: vmrghb v5, v0, v8
; CHECK-P8-NEXT: mtvsrd v0, r3
; CHECK-P8-NEXT: mtvsrd v1, r4 ; CHECK-P8-NEXT: mtvsrd v1, r4
; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: mffprwz r4, f2 ; CHECK-P8-NEXT: mffprwz r4, f2
; CHECK-P8-NEXT: xscvdpsxws f0, f4
; CHECK-P8-NEXT: xscvdpsxws f2, f6
; CHECK-P8-NEXT: vmrghb v3, v3, v6
; CHECK-P8-NEXT: mtvsrd v6, r3 ; CHECK-P8-NEXT: mtvsrd v6, r3
; CHECK-P8-NEXT: mffprwz r3, f3 ; CHECK-P8-NEXT: mtvsrd v7, r4
; CHECK-P8-NEXT: vmrghb v5, v5, v7 ; CHECK-P8-NEXT: mffprwz r3, f7
; CHECK-P8-NEXT: vmrghb v1, v1, v6 ; CHECK-P8-NEXT: mffprwz r4, f1
; CHECK-P8-NEXT: mtvsrd v6, r4 ; CHECK-P8-NEXT: vmrghb v0, v0, v6
; CHECK-P8-NEXT: mffprwz r4, f4 ; CHECK-P8-NEXT: vmrghb v1, v1, v7
; CHECK-P8-NEXT: mtvsrd v7, r3 ; CHECK-P8-NEXT: mtvsrd v6, r3
; CHECK-P8-NEXT: mtvsrd v7, r4
; CHECK-P8-NEXT: mffprwz r3, f0 ; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: mtvsrd v8, r4 ; CHECK-P8-NEXT: mffprwz r4, f2
; CHECK-P8-NEXT: mtvsrd v9, r3 ; CHECK-P8-NEXT: mtvsrd v8, r3
; CHECK-P8-NEXT: vmrghb v7, v8, v7 ; CHECK-P8-NEXT: mtvsrd v9, r4
; CHECK-P8-NEXT: vmrghb v6, v6, v9 ; CHECK-P8-NEXT: vmrghb v6, v6, v8
; CHECK-P8-NEXT: vmrglh v3, v4, v3 ; CHECK-P8-NEXT: vmrghb v7, v7, v9
; CHECK-P8-NEXT: vmrglh v2, v5, v2 ; CHECK-P8-NEXT: vmrglh v2, v4, v2
; CHECK-P8-NEXT: vmrglh v3, v5, v3
; CHECK-P8-NEXT: vmrglh v4, v1, v0 ; CHECK-P8-NEXT: vmrglh v4, v1, v0
; CHECK-P8-NEXT: vmrglh v5, v6, v7 ; CHECK-P8-NEXT: vmrglh v5, v7, v6
; CHECK-P8-NEXT: xxmrglw vs0, v2, v3 ; CHECK-P8-NEXT: xxmrglw vs0, v3, v2
; CHECK-P8-NEXT: xxmrglw vs1, v5, v4 ; CHECK-P8-NEXT: xxmrglw vs1, v5, v4
; CHECK-P8-NEXT: xxmrgld v2, vs1, vs0 ; CHECK-P8-NEXT: xxmrgld v2, vs1, vs0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test16elt_signed: ; CHECK-P9-LABEL: test16elt_signed:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lxv vs3, 0(r3) ; CHECK-P9-NEXT: lxv vs3, 0(r3)
; CHECK-P9-NEXT: lxv vs0, 48(r3) ; CHECK-P9-NEXT: lxv vs0, 48(r3)
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llvm/test/CodeGen/PowerPC/vec_conv_fp64_to_i16_elts.ll

Show First 20 Lines • Show All 365 Lines • ▼ Show 20 Lines
; CHECK-P8-NEXT: xxmrglw vs0, v3, v2 ; CHECK-P8-NEXT: xxmrglw vs0, v3, v2
; CHECK-P8-NEXT: vmrghh v1, v9, v1 ; CHECK-P8-NEXT: vmrghh v1, v9, v1
; CHECK-P8-NEXT: xxmrglw vs1, v5, v4 ; CHECK-P8-NEXT: xxmrglw vs1, v5, v4
; CHECK-P8-NEXT: mtvsrd v9, r4 ; CHECK-P8-NEXT: mtvsrd v9, r4
; CHECK-P8-NEXT: vmrghh v6, v8, v6 ; CHECK-P8-NEXT: vmrghh v6, v8, v6
; CHECK-P8-NEXT: vmrghh v7, v9, v7 ; CHECK-P8-NEXT: vmrghh v7, v9, v7
; CHECK-P8-NEXT: xxmrgld v2, vs1, vs0 ; CHECK-P8-NEXT: xxmrgld v2, vs1, vs0
; CHECK-P8-NEXT: xxmrglw vs2, v1, v0 ; CHECK-P8-NEXT: xxmrglw vs2, v1, v0
; CHECK-P8-NEXT: stvx v2, 0, r3 ; CHECK-P8-NEXT: xxswapd vs1, v2
; CHECK-P8-NEXT: xxmrglw vs3, v7, v6 ; CHECK-P8-NEXT: xxmrglw vs3, v7, v6
; CHECK-P8-NEXT: xxmrgld v3, vs3, vs2 ; CHECK-P8-NEXT: xxmrgld v3, vs3, vs2
; CHECK-P8-NEXT: stvx v3, r3, r5 ; CHECK-P8-NEXT: xxswapd vs0, v3
; CHECK-P8-NEXT: stxvd2x vs0, r3, r5
; CHECK-P8-NEXT: stxvd2x vs1, 0, r3
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test16elt: ; CHECK-P9-LABEL: test16elt:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lxv vs2, 0(r4) ; CHECK-P9-NEXT: lxv vs2, 0(r4)
; CHECK-P9-NEXT: lxv vs1, 16(r4) ; CHECK-P9-NEXT: lxv vs1, 16(r4)
; CHECK-P9-NEXT: lxv vs0, 32(r4) ; CHECK-P9-NEXT: lxv vs0, 32(r4)
; CHECK-P9-NEXT: xscvdpsxws f3, f2 ; CHECK-P9-NEXT: xscvdpsxws f3, f2
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; CHECK-P8-NEXT: xxmrglw vs0, v3, v2 ; CHECK-P8-NEXT: xxmrglw vs0, v3, v2
; CHECK-P8-NEXT: vmrghh v1, v9, v1 ; CHECK-P8-NEXT: vmrghh v1, v9, v1
; CHECK-P8-NEXT: xxmrglw vs1, v5, v4 ; CHECK-P8-NEXT: xxmrglw vs1, v5, v4
; CHECK-P8-NEXT: mtvsrd v9, r4 ; CHECK-P8-NEXT: mtvsrd v9, r4
; CHECK-P8-NEXT: vmrghh v6, v8, v6 ; CHECK-P8-NEXT: vmrghh v6, v8, v6
; CHECK-P8-NEXT: vmrghh v7, v9, v7 ; CHECK-P8-NEXT: vmrghh v7, v9, v7
; CHECK-P8-NEXT: xxmrgld v2, vs1, vs0 ; CHECK-P8-NEXT: xxmrgld v2, vs1, vs0
; CHECK-P8-NEXT: xxmrglw vs2, v1, v0 ; CHECK-P8-NEXT: xxmrglw vs2, v1, v0
; CHECK-P8-NEXT: stvx v2, 0, r3 ; CHECK-P8-NEXT: xxswapd vs1, v2
; CHECK-P8-NEXT: xxmrglw vs3, v7, v6 ; CHECK-P8-NEXT: xxmrglw vs3, v7, v6
; CHECK-P8-NEXT: xxmrgld v3, vs3, vs2 ; CHECK-P8-NEXT: xxmrgld v3, vs3, vs2
; CHECK-P8-NEXT: stvx v3, r3, r5 ; CHECK-P8-NEXT: xxswapd vs0, v3
; CHECK-P8-NEXT: stxvd2x vs0, r3, r5
; CHECK-P8-NEXT: stxvd2x vs1, 0, r3
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test16elt_signed: ; CHECK-P9-LABEL: test16elt_signed:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lxv vs2, 0(r4) ; CHECK-P9-NEXT: lxv vs2, 0(r4)
; CHECK-P9-NEXT: lxv vs1, 16(r4) ; CHECK-P9-NEXT: lxv vs1, 16(r4)
; CHECK-P9-NEXT: lxv vs0, 32(r4) ; CHECK-P9-NEXT: lxv vs0, 32(r4)
; CHECK-P9-NEXT: xscvdpsxws f3, f2 ; CHECK-P9-NEXT: xscvdpsxws f3, f2
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llvm/test/CodeGen/PowerPC/vec_conv_fp64_to_i32_elts.ll

Show First 20 Lines • Show All 89 Lines • ▼ Show 20 Lines
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: li r5, 32 ; CHECK-P8-NEXT: li r5, 32
; CHECK-P8-NEXT: li r6, 48 ; CHECK-P8-NEXT: li r6, 48
; CHECK-P8-NEXT: lxvd2x vs3, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs3, 0, r4
; CHECK-P8-NEXT: lxvd2x vs0, r4, r5 ; CHECK-P8-NEXT: lxvd2x vs0, r4, r5
; CHECK-P8-NEXT: li r5, 16 ; CHECK-P8-NEXT: li r5, 16
; CHECK-P8-NEXT: lxvd2x vs1, r4, r6 ; CHECK-P8-NEXT: lxvd2x vs1, r4, r6
; CHECK-P8-NEXT: lxvd2x vs2, r4, r5 ; CHECK-P8-NEXT: lxvd2x vs2, r4, r5
; CHECK-P8-NEXT: xxswapd vs3, vs3 ; CHECK-P8-NEXT: xxmrghd vs4, vs0, vs1
; CHECK-P8-NEXT: xxswapd vs0, vs0 ; CHECK-P8-NEXT: xxmrgld vs0, vs0, vs1
; CHECK-P8-NEXT: xxswapd vs1, vs1 ; CHECK-P8-NEXT: xxmrghd vs1, vs3, vs2
; CHECK-P8-NEXT: xxswapd vs2, vs2 ; CHECK-P8-NEXT: xxmrgld vs2, vs3, vs2
; CHECK-P8-NEXT: xxmrgld vs4, vs1, vs0
; CHECK-P8-NEXT: xxmrghd vs0, vs1, vs0
; CHECK-P8-NEXT: xxmrgld vs1, vs2, vs3
; CHECK-P8-NEXT: xxmrghd vs2, vs2, vs3
; CHECK-P8-NEXT: xvcvdpuxws v2, vs4 ; CHECK-P8-NEXT: xvcvdpuxws v2, vs4
; CHECK-P8-NEXT: xvcvdpuxws v3, vs0 ; CHECK-P8-NEXT: xvcvdpuxws v3, vs0
; CHECK-P8-NEXT: xvcvdpuxws v4, vs1 ; CHECK-P8-NEXT: xvcvdpuxws v4, vs1
; CHECK-P8-NEXT: xvcvdpuxws v5, vs2 ; CHECK-P8-NEXT: xvcvdpuxws v5, vs2
; CHECK-P8-NEXT: vmrgew v2, v3, v2 ; CHECK-P8-NEXT: vmrgew v2, v3, v2
; CHECK-P8-NEXT: vmrgew v3, v5, v4 ; CHECK-P8-NEXT: vmrgew v3, v5, v4
; CHECK-P8-NEXT: stvx v2, r3, r5 ; CHECK-P8-NEXT: stxvd2x v2, r3, r5
; CHECK-P8-NEXT: stvx v3, 0, r3 ; CHECK-P8-NEXT: stxvd2x v3, 0, r3
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test8elt: ; CHECK-P9-LABEL: test8elt:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lxv vs2, 0(r4) ; CHECK-P9-NEXT: lxv vs2, 0(r4)
; CHECK-P9-NEXT: lxv vs3, 16(r4) ; CHECK-P9-NEXT: lxv vs3, 16(r4)
; CHECK-P9-NEXT: lxv vs0, 32(r4) ; CHECK-P9-NEXT: lxv vs0, 32(r4)
; CHECK-P9-NEXT: lxv vs1, 48(r4) ; CHECK-P9-NEXT: lxv vs1, 48(r4)
Show All 37 Linesentry:
ret void ret void
} }
define void @test16elt(<16 x i32>* noalias nocapture sret(<16 x i32>) %agg.result, <16 x double>* nocapture readonly) local_unnamed_addr #2 { define void @test16elt(<16 x i32>* noalias nocapture sret(<16 x i32>) %agg.result, <16 x double>* nocapture readonly) local_unnamed_addr #2 {
; CHECK-P8-LABEL: test16elt: ; CHECK-P8-LABEL: test16elt:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: li r5, 32 ; CHECK-P8-NEXT: li r5, 32
; CHECK-P8-NEXT: li r6, 48 ; CHECK-P8-NEXT: li r6, 48
; CHECK-P8-NEXT: li r8, 64 ; CHECK-P8-NEXT: li r7, 64
; CHECK-P8-NEXT: li r7, 16 ; CHECK-P8-NEXT: li r8, 80
; CHECK-P8-NEXT: li r9, 80 ; CHECK-P8-NEXT: lxvd2x vs8, 0, r4
; CHECK-P8-NEXT: lxvd2x vs7, 0, r4
; CHECK-P8-NEXT: lxvd2x vs0, r4, r5 ; CHECK-P8-NEXT: lxvd2x vs0, r4, r5
; CHECK-P8-NEXT: lxvd2x vs1, r4, r6 ; CHECK-P8-NEXT: lxvd2x vs1, r4, r6
; CHECK-P8-NEXT: lxvd2x vs3, r4, r8
; CHECK-P8-NEXT: li r8, 96
; CHECK-P8-NEXT: lxvd2x vs2, r4, r7 ; CHECK-P8-NEXT: lxvd2x vs2, r4, r7
; CHECK-P8-NEXT: lxvd2x vs5, r4, r8 ; CHECK-P8-NEXT: lxvd2x vs3, r4, r8
; CHECK-P8-NEXT: li r7, 96
; CHECK-P8-NEXT: li r8, 112 ; CHECK-P8-NEXT: li r8, 112
; CHECK-P8-NEXT: lxvd2x vs4, r4, r9 ; CHECK-P8-NEXT: lxvd2x vs5, r4, r7
; CHECK-P8-NEXT: xxswapd vs0, vs0 ; CHECK-P8-NEXT: li r7, 16
; CHECK-P8-NEXT: xxswapd vs1, vs1
; CHECK-P8-NEXT: lxvd2x vs6, r4, r8 ; CHECK-P8-NEXT: lxvd2x vs6, r4, r8
; CHECK-P8-NEXT: xxswapd vs2, vs2 ; CHECK-P8-NEXT: xxmrghd vs4, vs0, vs1
; CHECK-P8-NEXT: xxswapd vs3, vs3 ; CHECK-P8-NEXT: xxmrgld vs0, vs0, vs1
; CHECK-P8-NEXT: xxswapd vs4, vs4 ; CHECK-P8-NEXT: lxvd2x vs7, r4, r7
; CHECK-P8-NEXT: xxswapd vs5, vs5 ; CHECK-P8-NEXT: xxmrghd vs1, vs2, vs3
; CHECK-P8-NEXT: xxmrgld vs8, vs1, vs0 ; CHECK-P8-NEXT: xxmrgld vs2, vs2, vs3
; CHECK-P8-NEXT: xxswapd vs6, vs6 ; CHECK-P8-NEXT: xxmrghd vs3, vs5, vs6
; CHECK-P8-NEXT: xxmrghd vs0, vs1, vs0
; CHECK-P8-NEXT: xxswapd vs1, vs7
; CHECK-P8-NEXT: xxmrgld vs7, vs4, vs3
; CHECK-P8-NEXT: xxmrghd vs3, vs4, vs3
; CHECK-P8-NEXT: xxmrgld vs4, vs6, vs5
; CHECK-P8-NEXT: xvcvdpuxws v2, vs8
; CHECK-P8-NEXT: xvcvdpuxws v3, vs0 ; CHECK-P8-NEXT: xvcvdpuxws v3, vs0
; CHECK-P8-NEXT: xxmrghd vs0, vs6, vs5 ; CHECK-P8-NEXT: xxmrgld vs0, vs5, vs6
; CHECK-P8-NEXT: xxmrgld vs5, vs2, vs1 ; CHECK-P8-NEXT: xvcvdpuxws v4, vs1
; CHECK-P8-NEXT: xxmrghd vs1, vs2, vs1 ; CHECK-P8-NEXT: xxmrghd vs1, vs8, vs7
; CHECK-P8-NEXT: xvcvdpuxws v4, vs7 ; CHECK-P8-NEXT: xvcvdpuxws v5, vs2
; CHECK-P8-NEXT: xvcvdpuxws v5, vs3 ; CHECK-P8-NEXT: xxmrgld vs2, vs8, vs7
; CHECK-P8-NEXT: xvcvdpuxws v0, vs4 ; CHECK-P8-NEXT: xvcvdpuxws v2, vs4
; CHECK-P8-NEXT: xvcvdpuxws v0, vs3
; CHECK-P8-NEXT: xvcvdpuxws v1, vs0 ; CHECK-P8-NEXT: xvcvdpuxws v1, vs0
; CHECK-P8-NEXT: xvcvdpuxws v6, vs5 ; CHECK-P8-NEXT: xvcvdpuxws v6, vs1
; CHECK-P8-NEXT: xvcvdpuxws v7, vs1 ; CHECK-P8-NEXT: xvcvdpuxws v7, vs2
; CHECK-P8-NEXT: vmrgew v2, v3, v2 ; CHECK-P8-NEXT: vmrgew v2, v3, v2
; CHECK-P8-NEXT: vmrgew v3, v5, v4 ; CHECK-P8-NEXT: vmrgew v3, v5, v4
; CHECK-P8-NEXT: vmrgew v4, v1, v0 ; CHECK-P8-NEXT: vmrgew v4, v1, v0
; CHECK-P8-NEXT: vmrgew v5, v7, v6 ; CHECK-P8-NEXT: vmrgew v5, v7, v6
; CHECK-P8-NEXT: stvx v2, r3, r7 ; CHECK-P8-NEXT: stxvd2x v4, r3, r6
; CHECK-P8-NEXT: stvx v3, r3, r5 ; CHECK-P8-NEXT: stxvd2x v3, r3, r5
; CHECK-P8-NEXT: stvx v4, r3, r6 ; CHECK-P8-NEXT: stxvd2x v2, r3, r7
; CHECK-P8-NEXT: stvx v5, 0, r3 ; CHECK-P8-NEXT: stxvd2x v5, 0, r3
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test16elt: ; CHECK-P9-LABEL: test16elt:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lxv vs6, 0(r4) ; CHECK-P9-NEXT: lxv vs6, 0(r4)
; CHECK-P9-NEXT: lxv vs7, 16(r4) ; CHECK-P9-NEXT: lxv vs7, 16(r4)
; CHECK-P9-NEXT: lxv vs4, 32(r4) ; CHECK-P9-NEXT: lxv vs4, 32(r4)
; CHECK-P9-NEXT: lxv vs5, 48(r4) ; CHECK-P9-NEXT: lxv vs5, 48(r4)
▲ Show 20 Lines • Show All 150 Lines • ▼ Show 20 Lines
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: li r5, 32 ; CHECK-P8-NEXT: li r5, 32
; CHECK-P8-NEXT: li r6, 48 ; CHECK-P8-NEXT: li r6, 48
; CHECK-P8-NEXT: lxvd2x vs3, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs3, 0, r4
; CHECK-P8-NEXT: lxvd2x vs0, r4, r5 ; CHECK-P8-NEXT: lxvd2x vs0, r4, r5
; CHECK-P8-NEXT: li r5, 16 ; CHECK-P8-NEXT: li r5, 16
; CHECK-P8-NEXT: lxvd2x vs1, r4, r6 ; CHECK-P8-NEXT: lxvd2x vs1, r4, r6
; CHECK-P8-NEXT: lxvd2x vs2, r4, r5 ; CHECK-P8-NEXT: lxvd2x vs2, r4, r5
; CHECK-P8-NEXT: xxswapd vs3, vs3 ; CHECK-P8-NEXT: xxmrghd vs4, vs0, vs1
; CHECK-P8-NEXT: xxswapd vs0, vs0 ; CHECK-P8-NEXT: xxmrgld vs0, vs0, vs1
; CHECK-P8-NEXT: xxswapd vs1, vs1 ; CHECK-P8-NEXT: xxmrghd vs1, vs3, vs2
; CHECK-P8-NEXT: xxswapd vs2, vs2 ; CHECK-P8-NEXT: xxmrgld vs2, vs3, vs2
; CHECK-P8-NEXT: xxmrgld vs4, vs1, vs0
; CHECK-P8-NEXT: xxmrghd vs0, vs1, vs0
; CHECK-P8-NEXT: xxmrgld vs1, vs2, vs3
; CHECK-P8-NEXT: xxmrghd vs2, vs2, vs3
; CHECK-P8-NEXT: xvcvdpsxws v2, vs4 ; CHECK-P8-NEXT: xvcvdpsxws v2, vs4
; CHECK-P8-NEXT: xvcvdpsxws v3, vs0 ; CHECK-P8-NEXT: xvcvdpsxws v3, vs0
; CHECK-P8-NEXT: xvcvdpsxws v4, vs1 ; CHECK-P8-NEXT: xvcvdpsxws v4, vs1
; CHECK-P8-NEXT: xvcvdpsxws v5, vs2 ; CHECK-P8-NEXT: xvcvdpsxws v5, vs2
; CHECK-P8-NEXT: vmrgew v2, v3, v2 ; CHECK-P8-NEXT: vmrgew v2, v3, v2
; CHECK-P8-NEXT: vmrgew v3, v5, v4 ; CHECK-P8-NEXT: vmrgew v3, v5, v4
; CHECK-P8-NEXT: stvx v2, r3, r5 ; CHECK-P8-NEXT: stxvd2x v2, r3, r5
; CHECK-P8-NEXT: stvx v3, 0, r3 ; CHECK-P8-NEXT: stxvd2x v3, 0, r3
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test8elt_signed: ; CHECK-P9-LABEL: test8elt_signed:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lxv vs2, 0(r4) ; CHECK-P9-NEXT: lxv vs2, 0(r4)
; CHECK-P9-NEXT: lxv vs3, 16(r4) ; CHECK-P9-NEXT: lxv vs3, 16(r4)
; CHECK-P9-NEXT: lxv vs0, 32(r4) ; CHECK-P9-NEXT: lxv vs0, 32(r4)
; CHECK-P9-NEXT: lxv vs1, 48(r4) ; CHECK-P9-NEXT: lxv vs1, 48(r4)
Show All 37 Linesentry:
ret void ret void
} }
define void @test16elt_signed(<16 x i32>* noalias nocapture sret(<16 x i32>) %agg.result, <16 x double>* nocapture readonly) local_unnamed_addr #2 { define void @test16elt_signed(<16 x i32>* noalias nocapture sret(<16 x i32>) %agg.result, <16 x double>* nocapture readonly) local_unnamed_addr #2 {
; CHECK-P8-LABEL: test16elt_signed: ; CHECK-P8-LABEL: test16elt_signed:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: li r5, 32 ; CHECK-P8-NEXT: li r5, 32
; CHECK-P8-NEXT: li r6, 48 ; CHECK-P8-NEXT: li r6, 48
; CHECK-P8-NEXT: li r8, 64 ; CHECK-P8-NEXT: li r7, 64
; CHECK-P8-NEXT: li r7, 16 ; CHECK-P8-NEXT: li r8, 80
; CHECK-P8-NEXT: li r9, 80 ; CHECK-P8-NEXT: lxvd2x vs8, 0, r4
; CHECK-P8-NEXT: lxvd2x vs7, 0, r4
; CHECK-P8-NEXT: lxvd2x vs0, r4, r5 ; CHECK-P8-NEXT: lxvd2x vs0, r4, r5
; CHECK-P8-NEXT: lxvd2x vs1, r4, r6 ; CHECK-P8-NEXT: lxvd2x vs1, r4, r6
; CHECK-P8-NEXT: lxvd2x vs3, r4, r8
; CHECK-P8-NEXT: li r8, 96
; CHECK-P8-NEXT: lxvd2x vs2, r4, r7 ; CHECK-P8-NEXT: lxvd2x vs2, r4, r7
; CHECK-P8-NEXT: lxvd2x vs5, r4, r8 ; CHECK-P8-NEXT: lxvd2x vs3, r4, r8
; CHECK-P8-NEXT: li r7, 96
; CHECK-P8-NEXT: li r8, 112 ; CHECK-P8-NEXT: li r8, 112
; CHECK-P8-NEXT: lxvd2x vs4, r4, r9 ; CHECK-P8-NEXT: lxvd2x vs5, r4, r7
; CHECK-P8-NEXT: xxswapd vs0, vs0 ; CHECK-P8-NEXT: li r7, 16
; CHECK-P8-NEXT: xxswapd vs1, vs1
; CHECK-P8-NEXT: lxvd2x vs6, r4, r8 ; CHECK-P8-NEXT: lxvd2x vs6, r4, r8
; CHECK-P8-NEXT: xxswapd vs2, vs2 ; CHECK-P8-NEXT: xxmrghd vs4, vs0, vs1
; CHECK-P8-NEXT: xxswapd vs3, vs3 ; CHECK-P8-NEXT: xxmrgld vs0, vs0, vs1
; CHECK-P8-NEXT: xxswapd vs4, vs4 ; CHECK-P8-NEXT: lxvd2x vs7, r4, r7
; CHECK-P8-NEXT: xxswapd vs5, vs5 ; CHECK-P8-NEXT: xxmrghd vs1, vs2, vs3
; CHECK-P8-NEXT: xxmrgld vs8, vs1, vs0 ; CHECK-P8-NEXT: xxmrgld vs2, vs2, vs3
; CHECK-P8-NEXT: xxswapd vs6, vs6 ; CHECK-P8-NEXT: xxmrghd vs3, vs5, vs6
; CHECK-P8-NEXT: xxmrghd vs0, vs1, vs0
; CHECK-P8-NEXT: xxswapd vs1, vs7
; CHECK-P8-NEXT: xxmrgld vs7, vs4, vs3
; CHECK-P8-NEXT: xxmrghd vs3, vs4, vs3
; CHECK-P8-NEXT: xxmrgld vs4, vs6, vs5
; CHECK-P8-NEXT: xvcvdpsxws v2, vs8
; CHECK-P8-NEXT: xvcvdpsxws v3, vs0 ; CHECK-P8-NEXT: xvcvdpsxws v3, vs0
; CHECK-P8-NEXT: xxmrghd vs0, vs6, vs5 ; CHECK-P8-NEXT: xxmrgld vs0, vs5, vs6
; CHECK-P8-NEXT: xxmrgld vs5, vs2, vs1 ; CHECK-P8-NEXT: xvcvdpsxws v4, vs1
; CHECK-P8-NEXT: xxmrghd vs1, vs2, vs1 ; CHECK-P8-NEXT: xxmrghd vs1, vs8, vs7
; CHECK-P8-NEXT: xvcvdpsxws v4, vs7 ; CHECK-P8-NEXT: xvcvdpsxws v5, vs2
; CHECK-P8-NEXT: xvcvdpsxws v5, vs3 ; CHECK-P8-NEXT: xxmrgld vs2, vs8, vs7
; CHECK-P8-NEXT: xvcvdpsxws v0, vs4 ; CHECK-P8-NEXT: xvcvdpsxws v2, vs4
; CHECK-P8-NEXT: xvcvdpsxws v0, vs3
; CHECK-P8-NEXT: xvcvdpsxws v1, vs0 ; CHECK-P8-NEXT: xvcvdpsxws v1, vs0
; CHECK-P8-NEXT: xvcvdpsxws v6, vs5 ; CHECK-P8-NEXT: xvcvdpsxws v6, vs1
; CHECK-P8-NEXT: xvcvdpsxws v7, vs1 ; CHECK-P8-NEXT: xvcvdpsxws v7, vs2
; CHECK-P8-NEXT: vmrgew v2, v3, v2 ; CHECK-P8-NEXT: vmrgew v2, v3, v2
; CHECK-P8-NEXT: vmrgew v3, v5, v4 ; CHECK-P8-NEXT: vmrgew v3, v5, v4
; CHECK-P8-NEXT: vmrgew v4, v1, v0 ; CHECK-P8-NEXT: vmrgew v4, v1, v0
; CHECK-P8-NEXT: vmrgew v5, v7, v6 ; CHECK-P8-NEXT: vmrgew v5, v7, v6
; CHECK-P8-NEXT: stvx v2, r3, r7 ; CHECK-P8-NEXT: stxvd2x v4, r3, r6
; CHECK-P8-NEXT: stvx v3, r3, r5 ; CHECK-P8-NEXT: stxvd2x v3, r3, r5
; CHECK-P8-NEXT: stvx v4, r3, r6 ; CHECK-P8-NEXT: stxvd2x v2, r3, r7
; CHECK-P8-NEXT: stvx v5, 0, r3 ; CHECK-P8-NEXT: stxvd2x v5, 0, r3
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test16elt_signed: ; CHECK-P9-LABEL: test16elt_signed:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lxv vs6, 0(r4) ; CHECK-P9-NEXT: lxv vs6, 0(r4)
; CHECK-P9-NEXT: lxv vs7, 16(r4) ; CHECK-P9-NEXT: lxv vs7, 16(r4)
; CHECK-P9-NEXT: lxv vs4, 32(r4) ; CHECK-P9-NEXT: lxv vs4, 32(r4)
; CHECK-P9-NEXT: lxv vs5, 48(r4) ; CHECK-P9-NEXT: lxv vs5, 48(r4)
▲ Show 20 Lines • Show All 71 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/vec_conv_fp_to_i_4byte_elts.ll

Show First 20 Lines • Show All 58 Lines • ▼ Show 20 Linesentry:
%0 = fptoui <4 x float> %a to <4 x i32> %0 = fptoui <4 x float> %a to <4 x i32>
ret <4 x i32> %0 ret <4 x i32> %0
} }
define void @test8elt(<8 x i32>* noalias nocapture sret(<8 x i32>) %agg.result, <8 x float>* nocapture readonly) local_unnamed_addr #2 { define void @test8elt(<8 x i32>* noalias nocapture sret(<8 x i32>) %agg.result, <8 x float>* nocapture readonly) local_unnamed_addr #2 {
; CHECK-P8-LABEL: test8elt: ; CHECK-P8-LABEL: test8elt:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: li r5, 16 ; CHECK-P8-NEXT: li r5, 16
; CHECK-P8-NEXT: lvx v3, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs1, 0, r4
; CHECK-P8-NEXT: lvx v2, r4, r5 ; CHECK-P8-NEXT: lxvd2x vs0, r4, r5
; CHECK-P8-NEXT: xvcvspuxws v3, v3 ; CHECK-P8-NEXT: xvcvspuxws vs1, vs1
; CHECK-P8-NEXT: xvcvspuxws v2, v2 ; CHECK-P8-NEXT: xvcvspuxws vs0, vs0
; CHECK-P8-NEXT: stvx v3, 0, r3 ; CHECK-P8-NEXT: stxvd2x vs0, r3, r5
; CHECK-P8-NEXT: stvx v2, r3, r5 ; CHECK-P8-NEXT: stxvd2x vs1, 0, r3
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test8elt: ; CHECK-P9-LABEL: test8elt:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lxv vs0, 16(r4) ; CHECK-P9-NEXT: lxv vs0, 16(r4)
; CHECK-P9-NEXT: lxv vs1, 0(r4) ; CHECK-P9-NEXT: lxv vs1, 0(r4)
; CHECK-P9-NEXT: xvcvspuxws vs1, vs1 ; CHECK-P9-NEXT: xvcvspuxws vs1, vs1
; CHECK-P9-NEXT: xvcvspuxws vs0, vs0 ; CHECK-P9-NEXT: xvcvspuxws vs0, vs0
Show All 18 Lines
} }
define void @test16elt(<16 x i32>* noalias nocapture sret(<16 x i32>) %agg.result, <16 x float>* nocapture readonly) local_unnamed_addr #2 { define void @test16elt(<16 x i32>* noalias nocapture sret(<16 x i32>) %agg.result, <16 x float>* nocapture readonly) local_unnamed_addr #2 {
; CHECK-P8-LABEL: test16elt: ; CHECK-P8-LABEL: test16elt:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: li r5, 16 ; CHECK-P8-NEXT: li r5, 16
; CHECK-P8-NEXT: li r6, 32 ; CHECK-P8-NEXT: li r6, 32
; CHECK-P8-NEXT: li r7, 48 ; CHECK-P8-NEXT: li r7, 48
; CHECK-P8-NEXT: lvx v5, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs3, 0, r4
; CHECK-P8-NEXT: lvx v2, r4, r5 ; CHECK-P8-NEXT: lxvd2x vs0, r4, r5
; CHECK-P8-NEXT: lvx v3, r4, r6 ; CHECK-P8-NEXT: lxvd2x vs1, r4, r6
; CHECK-P8-NEXT: lvx v4, r4, r7 ; CHECK-P8-NEXT: lxvd2x vs2, r4, r7
; CHECK-P8-NEXT: xvcvspuxws v5, v5 ; CHECK-P8-NEXT: xvcvspuxws vs3, vs3
; CHECK-P8-NEXT: xvcvspuxws v2, v2 ; CHECK-P8-NEXT: xvcvspuxws vs0, vs0
; CHECK-P8-NEXT: xvcvspuxws v3, v3 ; CHECK-P8-NEXT: xvcvspuxws vs1, vs1
; CHECK-P8-NEXT: xvcvspuxws v4, v4 ; CHECK-P8-NEXT: xvcvspuxws vs2, vs2
; CHECK-P8-NEXT: stvx v5, 0, r3 ; CHECK-P8-NEXT: stxvd2x vs2, r3, r7
; CHECK-P8-NEXT: stvx v2, r3, r5 ; CHECK-P8-NEXT: stxvd2x vs1, r3, r6
; CHECK-P8-NEXT: stvx v3, r3, r6 ; CHECK-P8-NEXT: stxvd2x vs0, r3, r5
; CHECK-P8-NEXT: stvx v4, r3, r7 ; CHECK-P8-NEXT: stxvd2x vs3, 0, r3
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test16elt: ; CHECK-P9-LABEL: test16elt:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lxv vs0, 48(r4) ; CHECK-P9-NEXT: lxv vs0, 48(r4)
; CHECK-P9-NEXT: lxv vs1, 32(r4) ; CHECK-P9-NEXT: lxv vs1, 32(r4)
; CHECK-P9-NEXT: lxv vs2, 16(r4) ; CHECK-P9-NEXT: lxv vs2, 16(r4)
; CHECK-P9-NEXT: lxv vs3, 0(r4) ; CHECK-P9-NEXT: lxv vs3, 0(r4)
▲ Show 20 Lines • Show All 79 Lines • ▼ Show 20 Linesentry:
%0 = fptosi <4 x float> %a to <4 x i32> %0 = fptosi <4 x float> %a to <4 x i32>
ret <4 x i32> %0 ret <4 x i32> %0
} }
define void @test8elt_signed(<8 x i32>* noalias nocapture sret(<8 x i32>) %agg.result, <8 x float>* nocapture readonly) local_unnamed_addr #2 { define void @test8elt_signed(<8 x i32>* noalias nocapture sret(<8 x i32>) %agg.result, <8 x float>* nocapture readonly) local_unnamed_addr #2 {
; CHECK-P8-LABEL: test8elt_signed: ; CHECK-P8-LABEL: test8elt_signed:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: li r5, 16 ; CHECK-P8-NEXT: li r5, 16
; CHECK-P8-NEXT: lvx v3, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs1, 0, r4
; CHECK-P8-NEXT: lvx v2, r4, r5 ; CHECK-P8-NEXT: lxvd2x vs0, r4, r5
; CHECK-P8-NEXT: xvcvspsxws v3, v3 ; CHECK-P8-NEXT: xvcvspsxws vs1, vs1
; CHECK-P8-NEXT: xvcvspsxws v2, v2 ; CHECK-P8-NEXT: xvcvspsxws vs0, vs0
; CHECK-P8-NEXT: stvx v3, 0, r3 ; CHECK-P8-NEXT: stxvd2x vs0, r3, r5
; CHECK-P8-NEXT: stvx v2, r3, r5 ; CHECK-P8-NEXT: stxvd2x vs1, 0, r3
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test8elt_signed: ; CHECK-P9-LABEL: test8elt_signed:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lxv vs0, 16(r4) ; CHECK-P9-NEXT: lxv vs0, 16(r4)
; CHECK-P9-NEXT: lxv vs1, 0(r4) ; CHECK-P9-NEXT: lxv vs1, 0(r4)
; CHECK-P9-NEXT: xvcvspsxws vs1, vs1 ; CHECK-P9-NEXT: xvcvspsxws vs1, vs1
; CHECK-P9-NEXT: xvcvspsxws vs0, vs0 ; CHECK-P9-NEXT: xvcvspsxws vs0, vs0
Show All 18 Lines
} }
define void @test16elt_signed(<16 x i32>* noalias nocapture sret(<16 x i32>) %agg.result, <16 x float>* nocapture readonly) local_unnamed_addr #2 { define void @test16elt_signed(<16 x i32>* noalias nocapture sret(<16 x i32>) %agg.result, <16 x float>* nocapture readonly) local_unnamed_addr #2 {
; CHECK-P8-LABEL: test16elt_signed: ; CHECK-P8-LABEL: test16elt_signed:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: li r5, 16 ; CHECK-P8-NEXT: li r5, 16
; CHECK-P8-NEXT: li r6, 32 ; CHECK-P8-NEXT: li r6, 32
; CHECK-P8-NEXT: li r7, 48 ; CHECK-P8-NEXT: li r7, 48
; CHECK-P8-NEXT: lvx v5, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs3, 0, r4
; CHECK-P8-NEXT: lvx v2, r4, r5 ; CHECK-P8-NEXT: lxvd2x vs0, r4, r5
; CHECK-P8-NEXT: lvx v3, r4, r6 ; CHECK-P8-NEXT: lxvd2x vs1, r4, r6
; CHECK-P8-NEXT: lvx v4, r4, r7 ; CHECK-P8-NEXT: lxvd2x vs2, r4, r7
; CHECK-P8-NEXT: xvcvspsxws v5, v5 ; CHECK-P8-NEXT: xvcvspsxws vs3, vs3
; CHECK-P8-NEXT: xvcvspsxws v2, v2 ; CHECK-P8-NEXT: xvcvspsxws vs0, vs0
; CHECK-P8-NEXT: xvcvspsxws v3, v3 ; CHECK-P8-NEXT: xvcvspsxws vs1, vs1
; CHECK-P8-NEXT: xvcvspsxws v4, v4 ; CHECK-P8-NEXT: xvcvspsxws vs2, vs2
; CHECK-P8-NEXT: stvx v5, 0, r3 ; CHECK-P8-NEXT: stxvd2x vs2, r3, r7
; CHECK-P8-NEXT: stvx v2, r3, r5 ; CHECK-P8-NEXT: stxvd2x vs1, r3, r6
; CHECK-P8-NEXT: stvx v3, r3, r6 ; CHECK-P8-NEXT: stxvd2x vs0, r3, r5
; CHECK-P8-NEXT: stvx v4, r3, r7 ; CHECK-P8-NEXT: stxvd2x vs3, 0, r3
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test16elt_signed: ; CHECK-P9-LABEL: test16elt_signed:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lxv vs0, 48(r4) ; CHECK-P9-NEXT: lxv vs0, 48(r4)
; CHECK-P9-NEXT: lxv vs1, 32(r4) ; CHECK-P9-NEXT: lxv vs1, 32(r4)
; CHECK-P9-NEXT: lxv vs2, 16(r4) ; CHECK-P9-NEXT: lxv vs2, 16(r4)
; CHECK-P9-NEXT: lxv vs3, 0(r4) ; CHECK-P9-NEXT: lxv vs3, 0(r4)
Show All 31 Lines

llvm/test/CodeGen/PowerPC/vec_conv_i16_to_fp32_elts.ll

Show First 20 Lines • Show All 95 Lines • ▼ Show 20 Lines
define void @test8elt(<8 x float>* noalias nocapture sret(<8 x float>) %agg.result, <8 x i16> %a) local_unnamed_addr #2 { define void @test8elt(<8 x float>* noalias nocapture sret(<8 x float>) %agg.result, <8 x i16> %a) local_unnamed_addr #2 {
; CHECK-P8-LABEL: test8elt: ; CHECK-P8-LABEL: test8elt:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: xxlxor v3, v3, v3 ; CHECK-P8-NEXT: xxlxor v3, v3, v3
; CHECK-P8-NEXT: li r4, 16 ; CHECK-P8-NEXT: li r4, 16
; CHECK-P8-NEXT: vmrglh v4, v3, v2 ; CHECK-P8-NEXT: vmrglh v4, v3, v2
; CHECK-P8-NEXT: vmrghh v2, v3, v2 ; CHECK-P8-NEXT: vmrghh v2, v3, v2
; CHECK-P8-NEXT: xvcvuxwsp v3, v4 ; CHECK-P8-NEXT: xvcvuxwsp vs0, v4
; CHECK-P8-NEXT: xvcvuxwsp v2, v2 ; CHECK-P8-NEXT: xvcvuxwsp vs1, v2
; CHECK-P8-NEXT: stvx v3, 0, r3 ; CHECK-P8-NEXT: xxswapd vs0, vs0
; CHECK-P8-NEXT: stvx v2, r3, r4 ; CHECK-P8-NEXT: xxswapd vs1, vs1
; CHECK-P8-NEXT: stxvd2x vs1, r3, r4
; CHECK-P8-NEXT: stxvd2x vs0, 0, r3
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test8elt: ; CHECK-P9-LABEL: test8elt:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: xxlxor v3, v3, v3 ; CHECK-P9-NEXT: xxlxor v3, v3, v3
; CHECK-P9-NEXT: vmrglh v4, v3, v2 ; CHECK-P9-NEXT: vmrglh v4, v3, v2
; CHECK-P9-NEXT: vmrghh v2, v3, v2 ; CHECK-P9-NEXT: vmrghh v2, v3, v2
; CHECK-P9-NEXT: xvcvuxwsp vs0, v4 ; CHECK-P9-NEXT: xvcvuxwsp vs0, v4
Show All 17 Linesentry:
store <8 x float> %0, <8 x float>* %agg.result, align 32 store <8 x float> %0, <8 x float>* %agg.result, align 32
ret void ret void
} }
define void @test16elt(<16 x float>* noalias nocapture sret(<16 x float>) %agg.result, <16 x i16>* nocapture readonly) local_unnamed_addr #3 { define void @test16elt(<16 x float>* noalias nocapture sret(<16 x float>) %agg.result, <16 x i16>* nocapture readonly) local_unnamed_addr #3 {
; CHECK-P8-LABEL: test16elt: ; CHECK-P8-LABEL: test16elt:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: addis r5, r2, .LCPI3_0@toc@ha ; CHECK-P8-NEXT: addis r5, r2, .LCPI3_0@toc@ha
; CHECK-P8-NEXT: addis r6, r2, .LCPI3_1@toc@ha ; CHECK-P8-NEXT: li r6, 16
; CHECK-P8-NEXT: xxlxor v3, v3, v3 ; CHECK-P8-NEXT: lxvd2x vs1, 0, r4
; CHECK-P8-NEXT: lvx v4, 0, r4 ; CHECK-P8-NEXT: xxlxor v4, v4, v4
; CHECK-P8-NEXT: addi r5, r5, .LCPI3_0@toc@l ; CHECK-P8-NEXT: addi r5, r5, .LCPI3_0@toc@l
; CHECK-P8-NEXT: addi r6, r6, .LCPI3_1@toc@l ; CHECK-P8-NEXT: lxvd2x vs2, r4, r6
; CHECK-P8-NEXT: lvx v2, 0, r5 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r5
; CHECK-P8-NEXT: li r5, 16 ; CHECK-P8-NEXT: addis r5, r2, .LCPI3_1@toc@ha
; CHECK-P8-NEXT: lvx v0, 0, r6 ; CHECK-P8-NEXT: addi r4, r5, .LCPI3_1@toc@l
; CHECK-P8-NEXT: li r6, 32 ; CHECK-P8-NEXT: xxswapd v2, vs1
; CHECK-P8-NEXT: lvx v5, r4, r5 ; CHECK-P8-NEXT: li r5, 32
; CHECK-P8-NEXT: lxvd2x vs3, 0, r4
; CHECK-P8-NEXT: xxswapd v5, vs2
; CHECK-P8-NEXT: li r4, 48 ; CHECK-P8-NEXT: li r4, 48
; CHECK-P8-NEXT: vperm v1, v3, v4, v2 ; CHECK-P8-NEXT: xxswapd v3, vs0
; CHECK-P8-NEXT: vperm v2, v3, v5, v2 ; CHECK-P8-NEXT: xxswapd v0, vs3
; CHECK-P8-NEXT: vperm v5, v3, v5, v0 ; CHECK-P8-NEXT: vperm v1, v4, v2, v3
; CHECK-P8-NEXT: vperm v3, v3, v4, v0 ; CHECK-P8-NEXT: vperm v3, v4, v5, v3
; CHECK-P8-NEXT: xvcvuxwsp v4, v1 ; CHECK-P8-NEXT: vperm v5, v4, v5, v0
; CHECK-P8-NEXT: xvcvuxwsp v2, v2 ; CHECK-P8-NEXT: vperm v2, v4, v2, v0
; CHECK-P8-NEXT: xvcvuxwsp v5, v5 ; CHECK-P8-NEXT: xvcvuxwsp vs0, v1
; CHECK-P8-NEXT: xvcvuxwsp v3, v3 ; CHECK-P8-NEXT: xvcvuxwsp vs1, v3
; CHECK-P8-NEXT: stvx v4, 0, r3 ; CHECK-P8-NEXT: xvcvuxwsp vs2, v5
; CHECK-P8-NEXT: stvx v2, r3, r6 ; CHECK-P8-NEXT: xvcvuxwsp vs3, v2
; CHECK-P8-NEXT: stvx v5, r3, r4 ; CHECK-P8-NEXT: xxswapd vs0, vs0
; CHECK-P8-NEXT: stvx v3, r3, r5 ; CHECK-P8-NEXT: xxswapd vs1, vs1
; CHECK-P8-NEXT: xxswapd vs2, vs2
; CHECK-P8-NEXT: xxswapd vs3, vs3
; CHECK-P8-NEXT: stxvd2x vs2, r3, r4
; CHECK-P8-NEXT: stxvd2x vs1, r3, r5
; CHECK-P8-NEXT: stxvd2x vs3, r3, r6
; CHECK-P8-NEXT: stxvd2x vs0, 0, r3
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test16elt: ; CHECK-P9-LABEL: test16elt:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lxv v2, 16(r4) ; CHECK-P9-NEXT: lxv v2, 16(r4)
; CHECK-P9-NEXT: lxv v3, 0(r4) ; CHECK-P9-NEXT: lxv v3, 0(r4)
; CHECK-P9-NEXT: addis r4, r2, .LCPI3_0@toc@ha ; CHECK-P9-NEXT: addis r4, r2, .LCPI3_0@toc@ha
; CHECK-P9-NEXT: xxlxor v5, v5, v5 ; CHECK-P9-NEXT: xxlxor v5, v5, v5
▲ Show 20 Lines • Show All 140 Lines • ▼ Show 20 Lines
; CHECK-P8-NEXT: vspltisw v3, 8 ; CHECK-P8-NEXT: vspltisw v3, 8
; CHECK-P8-NEXT: li r4, 16 ; CHECK-P8-NEXT: li r4, 16
; CHECK-P8-NEXT: vmrghh v2, v2, v2 ; CHECK-P8-NEXT: vmrghh v2, v2, v2
; CHECK-P8-NEXT: vadduwm v3, v3, v3 ; CHECK-P8-NEXT: vadduwm v3, v3, v3
; CHECK-P8-NEXT: vslw v4, v4, v3 ; CHECK-P8-NEXT: vslw v4, v4, v3
; CHECK-P8-NEXT: vslw v2, v2, v3 ; CHECK-P8-NEXT: vslw v2, v2, v3
; CHECK-P8-NEXT: vsraw v4, v4, v3 ; CHECK-P8-NEXT: vsraw v4, v4, v3
; CHECK-P8-NEXT: vsraw v2, v2, v3 ; CHECK-P8-NEXT: vsraw v2, v2, v3
; CHECK-P8-NEXT: xvcvsxwsp v3, v4 ; CHECK-P8-NEXT: xvcvsxwsp vs0, v4
; CHECK-P8-NEXT: xvcvsxwsp v2, v2 ; CHECK-P8-NEXT: xvcvsxwsp vs1, v2
; CHECK-P8-NEXT: stvx v3, 0, r3 ; CHECK-P8-NEXT: xxswapd vs0, vs0
; CHECK-P8-NEXT: stvx v2, r3, r4 ; CHECK-P8-NEXT: xxswapd vs1, vs1
; CHECK-P8-NEXT: stxvd2x vs1, r3, r4
; CHECK-P8-NEXT: stxvd2x vs0, 0, r3
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test8elt_signed: ; CHECK-P9-LABEL: test8elt_signed:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: vmrglh v3, v2, v2 ; CHECK-P9-NEXT: vmrglh v3, v2, v2
; CHECK-P9-NEXT: vmrghh v2, v2, v2 ; CHECK-P9-NEXT: vmrghh v2, v2, v2
; CHECK-P9-NEXT: vextsh2w v3, v3 ; CHECK-P9-NEXT: vextsh2w v3, v3
; CHECK-P9-NEXT: vextsh2w v2, v2 ; CHECK-P9-NEXT: vextsh2w v2, v2
Show All 19 Linesentry:
store <8 x float> %0, <8 x float>* %agg.result, align 32 store <8 x float> %0, <8 x float>* %agg.result, align 32
ret void ret void
} }
define void @test16elt_signed(<16 x float>* noalias nocapture sret(<16 x float>) %agg.result, <16 x i16>* nocapture readonly) local_unnamed_addr #3 { define void @test16elt_signed(<16 x float>* noalias nocapture sret(<16 x float>) %agg.result, <16 x i16>* nocapture readonly) local_unnamed_addr #3 {
; CHECK-P8-LABEL: test16elt_signed: ; CHECK-P8-LABEL: test16elt_signed:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: li r5, 16 ; CHECK-P8-NEXT: li r5, 16
; CHECK-P8-NEXT: lvx v2, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r4
; CHECK-P8-NEXT: vspltisw v5, 8 ; CHECK-P8-NEXT: vspltisw v5, 8
; CHECK-P8-NEXT: li r6, 32 ; CHECK-P8-NEXT: li r6, 32
; CHECK-P8-NEXT: lvx v3, r4, r5 ; CHECK-P8-NEXT: lxvd2x vs1, r4, r5
; CHECK-P8-NEXT: li r4, 48 ; CHECK-P8-NEXT: li r4, 48
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: vadduwm v5, v5, v5
; CHECK-P8-NEXT: xxswapd v3, vs1
; CHECK-P8-NEXT: vmrglh v4, v2, v2 ; CHECK-P8-NEXT: vmrglh v4, v2, v2
; CHECK-P8-NEXT: vmrglh v0, v3, v3 ; CHECK-P8-NEXT: vmrglh v0, v3, v3
; CHECK-P8-NEXT: vmrghh v3, v3, v3 ; CHECK-P8-NEXT: vmrghh v3, v3, v3
; CHECK-P8-NEXT: vmrghh v2, v2, v2 ; CHECK-P8-NEXT: vmrghh v2, v2, v2
; CHECK-P8-NEXT: vadduwm v5, v5, v5
; CHECK-P8-NEXT: vslw v4, v4, v5 ; CHECK-P8-NEXT: vslw v4, v4, v5
; CHECK-P8-NEXT: vslw v0, v0, v5 ; CHECK-P8-NEXT: vslw v0, v0, v5
; CHECK-P8-NEXT: vslw v3, v3, v5 ; CHECK-P8-NEXT: vslw v3, v3, v5
; CHECK-P8-NEXT: vslw v2, v2, v5 ; CHECK-P8-NEXT: vslw v2, v2, v5
; CHECK-P8-NEXT: vsraw v4, v4, v5 ; CHECK-P8-NEXT: vsraw v4, v4, v5
; CHECK-P8-NEXT: vsraw v0, v0, v5 ; CHECK-P8-NEXT: vsraw v0, v0, v5
; CHECK-P8-NEXT: vsraw v3, v3, v5 ; CHECK-P8-NEXT: vsraw v3, v3, v5
; CHECK-P8-NEXT: vsraw v2, v2, v5 ; CHECK-P8-NEXT: vsraw v2, v2, v5
; CHECK-P8-NEXT: xvcvsxwsp v4, v4 ; CHECK-P8-NEXT: xvcvsxwsp vs0, v4
; CHECK-P8-NEXT: xvcvsxwsp v5, v0 ; CHECK-P8-NEXT: xvcvsxwsp vs1, v0
; CHECK-P8-NEXT: xvcvsxwsp v3, v3 ; CHECK-P8-NEXT: xvcvsxwsp vs2, v3
; CHECK-P8-NEXT: xvcvsxwsp v2, v2 ; CHECK-P8-NEXT: xvcvsxwsp vs3, v2
; CHECK-P8-NEXT: stvx v4, 0, r3 ; CHECK-P8-NEXT: xxswapd vs0, vs0
; CHECK-P8-NEXT: stvx v5, r3, r6 ; CHECK-P8-NEXT: xxswapd vs1, vs1
; CHECK-P8-NEXT: stvx v3, r3, r4 ; CHECK-P8-NEXT: xxswapd vs2, vs2
; CHECK-P8-NEXT: stvx v2, r3, r5 ; CHECK-P8-NEXT: xxswapd vs3, vs3
; CHECK-P8-NEXT: stxvd2x vs2, r3, r4
; CHECK-P8-NEXT: stxvd2x vs1, r3, r6
; CHECK-P8-NEXT: stxvd2x vs3, r3, r5
; CHECK-P8-NEXT: stxvd2x vs0, 0, r3
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test16elt_signed: ; CHECK-P9-LABEL: test16elt_signed:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lxv v3, 0(r4) ; CHECK-P9-NEXT: lxv v3, 0(r4)
; CHECK-P9-NEXT: lxv v2, 16(r4) ; CHECK-P9-NEXT: lxv v2, 16(r4)
; CHECK-P9-NEXT: vmrglh v4, v3, v3 ; CHECK-P9-NEXT: vmrglh v4, v3, v3
; CHECK-P9-NEXT: vmrghh v3, v3, v3 ; CHECK-P9-NEXT: vmrghh v3, v3, v3
▲ Show 20 Lines • Show All 43 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/vec_conv_i16_to_fp64_elts.ll

Show All 10 Lines
define <2 x double> @test2elt(i32 %a.coerce) local_unnamed_addr #0 { define <2 x double> @test2elt(i32 %a.coerce) local_unnamed_addr #0 {
; CHECK-P8-LABEL: test2elt: ; CHECK-P8-LABEL: test2elt:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: addis r4, r2, .LCPI0_0@toc@ha ; CHECK-P8-NEXT: addis r4, r2, .LCPI0_0@toc@ha
; CHECK-P8-NEXT: mtvsrwz v2, r3 ; CHECK-P8-NEXT: mtvsrwz v2, r3
; CHECK-P8-NEXT: addi r4, r4, .LCPI0_0@toc@l ; CHECK-P8-NEXT: addi r4, r4, .LCPI0_0@toc@l
; CHECK-P8-NEXT: xxlxor v4, v4, v4 ; CHECK-P8-NEXT: xxlxor v4, v4, v4
; CHECK-P8-NEXT: lvx v3, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r4
; CHECK-P8-NEXT: xxswapd v3, vs0
; CHECK-P8-NEXT: vperm v2, v4, v2, v3 ; CHECK-P8-NEXT: vperm v2, v4, v2, v3
; CHECK-P8-NEXT: xvcvuxddp v2, v2 ; CHECK-P8-NEXT: xvcvuxddp v2, v2
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test2elt: ; CHECK-P9-LABEL: test2elt:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtvsrwz v2, r3 ; CHECK-P9-NEXT: mtvsrwz v2, r3
; CHECK-P9-NEXT: addis r3, r2, .LCPI0_0@toc@ha ; CHECK-P9-NEXT: addis r3, r2, .LCPI0_0@toc@ha
Show All 20 Linesentry:
ret <2 x double> %1 ret <2 x double> %1
} }
define void @test4elt(<4 x double>* noalias nocapture sret(<4 x double>) %agg.result, i64 %a.coerce) local_unnamed_addr #1 { define void @test4elt(<4 x double>* noalias nocapture sret(<4 x double>) %agg.result, i64 %a.coerce) local_unnamed_addr #1 {
; CHECK-P8-LABEL: test4elt: ; CHECK-P8-LABEL: test4elt:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: addis r5, r2, .LCPI1_0@toc@ha ; CHECK-P8-NEXT: addis r5, r2, .LCPI1_0@toc@ha
; CHECK-P8-NEXT: addis r6, r2, .LCPI1_1@toc@ha ; CHECK-P8-NEXT: addis r6, r2, .LCPI1_1@toc@ha
; CHECK-P8-NEXT: mtvsrd v2, r4 ; CHECK-P8-NEXT: xxlxor v2, v2, v2
; CHECK-P8-NEXT: addi r5, r5, .LCPI1_0@toc@l ; CHECK-P8-NEXT: addi r5, r5, .LCPI1_0@toc@l
; CHECK-P8-NEXT: addi r4, r6, .LCPI1_1@toc@l ; CHECK-P8-NEXT: mtvsrd v4, r4
; CHECK-P8-NEXT: xxlxor v4, v4, v4
; CHECK-P8-NEXT: lvx v3, 0, r5
; CHECK-P8-NEXT: lvx v5, 0, r4
; CHECK-P8-NEXT: li r4, 16 ; CHECK-P8-NEXT: li r4, 16
; CHECK-P8-NEXT: vperm v3, v4, v2, v3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r5
; CHECK-P8-NEXT: vperm v2, v4, v2, v5 ; CHECK-P8-NEXT: addi r5, r6, .LCPI1_1@toc@l
; CHECK-P8-NEXT: lxvd2x vs1, 0, r5
; CHECK-P8-NEXT: xxswapd v3, vs0
; CHECK-P8-NEXT: xxswapd v5, vs1
; CHECK-P8-NEXT: vperm v3, v2, v4, v3
; CHECK-P8-NEXT: vperm v2, v2, v4, v5
; CHECK-P8-NEXT: xvcvuxddp vs0, v3 ; CHECK-P8-NEXT: xvcvuxddp vs0, v3
; CHECK-P8-NEXT: xvcvuxddp vs1, v2 ; CHECK-P8-NEXT: xvcvuxddp vs1, v2
; CHECK-P8-NEXT: xxswapd vs0, vs0 ; CHECK-P8-NEXT: xxswapd vs0, vs0
; CHECK-P8-NEXT: xxswapd vs1, vs1 ; CHECK-P8-NEXT: xxswapd vs1, vs1
; CHECK-P8-NEXT: stxvd2x vs1, r3, r4 ; CHECK-P8-NEXT: stxvd2x vs1, r3, r4
; CHECK-P8-NEXT: stxvd2x vs0, 0, r3 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r3
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
▲ Show 20 Lines • Show All 42 Lines • ▼ Show 20 Lines
define void @test8elt(<8 x double>* noalias nocapture sret(<8 x double>) %agg.result, <8 x i16> %a) local_unnamed_addr #2 { define void @test8elt(<8 x double>* noalias nocapture sret(<8 x double>) %agg.result, <8 x i16> %a) local_unnamed_addr #2 {
; CHECK-P8-LABEL: test8elt: ; CHECK-P8-LABEL: test8elt:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: addis r4, r2, .LCPI2_0@toc@ha ; CHECK-P8-NEXT: addis r4, r2, .LCPI2_0@toc@ha
; CHECK-P8-NEXT: addis r5, r2, .LCPI2_2@toc@ha ; CHECK-P8-NEXT: addis r5, r2, .LCPI2_2@toc@ha
; CHECK-P8-NEXT: xxlxor v4, v4, v4 ; CHECK-P8-NEXT: xxlxor v4, v4, v4
; CHECK-P8-NEXT: addi r4, r4, .LCPI2_0@toc@l ; CHECK-P8-NEXT: addi r4, r4, .LCPI2_0@toc@l
; CHECK-P8-NEXT: addi r5, r5, .LCPI2_2@toc@l ; CHECK-P8-NEXT: addi r5, r5, .LCPI2_2@toc@l
; CHECK-P8-NEXT: lvx v3, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r4
; CHECK-P8-NEXT: addis r4, r2, .LCPI2_3@toc@ha ; CHECK-P8-NEXT: addis r4, r2, .LCPI2_3@toc@ha
; CHECK-P8-NEXT: lvx v5, 0, r5 ; CHECK-P8-NEXT: lxvd2x vs1, 0, r5
; CHECK-P8-NEXT: addis r5, r2, .LCPI2_1@toc@ha ; CHECK-P8-NEXT: addis r5, r2, .LCPI2_1@toc@ha
; CHECK-P8-NEXT: addi r4, r4, .LCPI2_3@toc@l ; CHECK-P8-NEXT: addi r4, r4, .LCPI2_3@toc@l
; CHECK-P8-NEXT: addi r5, r5, .LCPI2_1@toc@l ; CHECK-P8-NEXT: addi r5, r5, .LCPI2_1@toc@l
; CHECK-P8-NEXT: lvx v0, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs2, 0, r4
; CHECK-P8-NEXT: lvx v1, 0, r5 ; CHECK-P8-NEXT: lxvd2x vs3, 0, r5
; CHECK-P8-NEXT: li r4, 48 ; CHECK-P8-NEXT: li r4, 48
; CHECK-P8-NEXT: li r5, 32 ; CHECK-P8-NEXT: li r5, 32
; CHECK-P8-NEXT: xxswapd v3, vs0
; CHECK-P8-NEXT: xxswapd v5, vs1
; CHECK-P8-NEXT: xxswapd v0, vs2
; CHECK-P8-NEXT: xxswapd v1, vs3
; CHECK-P8-NEXT: vperm v3, v4, v2, v3 ; CHECK-P8-NEXT: vperm v3, v4, v2, v3
; CHECK-P8-NEXT: vperm v5, v4, v2, v5 ; CHECK-P8-NEXT: vperm v5, v4, v2, v5
; CHECK-P8-NEXT: vperm v0, v4, v2, v0 ; CHECK-P8-NEXT: vperm v0, v4, v2, v0
; CHECK-P8-NEXT: vperm v2, v4, v2, v1 ; CHECK-P8-NEXT: vperm v2, v4, v2, v1
; CHECK-P8-NEXT: xvcvuxddp vs0, v3 ; CHECK-P8-NEXT: xvcvuxddp vs0, v3
; CHECK-P8-NEXT: xvcvuxddp vs1, v5 ; CHECK-P8-NEXT: xvcvuxddp vs1, v5
; CHECK-P8-NEXT: xvcvuxddp vs2, v0 ; CHECK-P8-NEXT: xvcvuxddp vs2, v0
; CHECK-P8-NEXT: xvcvuxddp vs3, v2 ; CHECK-P8-NEXT: xvcvuxddp vs3, v2
▲ Show 20 Lines • Show All 69 Lines • ▼ Show 20 Linesentry:
%0 = uitofp <8 x i16> %a to <8 x double> %0 = uitofp <8 x i16> %a to <8 x double>
store <8 x double> %0, <8 x double>* %agg.result, align 64 store <8 x double> %0, <8 x double>* %agg.result, align 64
ret void ret void
} }
define void @test16elt(<16 x double>* noalias nocapture sret(<16 x double>) %agg.result, <16 x i16>* nocapture readonly) local_unnamed_addr #3 { define void @test16elt(<16 x double>* noalias nocapture sret(<16 x double>) %agg.result, <16 x i16>* nocapture readonly) local_unnamed_addr #3 {
; CHECK-P8-LABEL: test16elt: ; CHECK-P8-LABEL: test16elt:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: addis r6, r2, .LCPI3_2@toc@ha
; CHECK-P8-NEXT: addis r5, r2, .LCPI3_0@toc@ha ; CHECK-P8-NEXT: addis r5, r2, .LCPI3_0@toc@ha
; CHECK-P8-NEXT: lvx v4, 0, r4 ; CHECK-P8-NEXT: addis r6, r2, .LCPI3_2@toc@ha
; CHECK-P8-NEXT: xxlxor v3, v3, v3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r4
; CHECK-P8-NEXT: addi r6, r6, .LCPI3_2@toc@l ; CHECK-P8-NEXT: xxlxor v4, v4, v4
; CHECK-P8-NEXT: addi r5, r5, .LCPI3_0@toc@l ; CHECK-P8-NEXT: addi r5, r5, .LCPI3_0@toc@l
; CHECK-P8-NEXT: lvx v5, 0, r6 ; CHECK-P8-NEXT: addi r6, r6, .LCPI3_2@toc@l
; CHECK-P8-NEXT: li r6, 16 ; CHECK-P8-NEXT: lxvd2x vs1, 0, r5
; CHECK-P8-NEXT: lvx v2, 0, r5 ; CHECK-P8-NEXT: li r5, 16
; CHECK-P8-NEXT: addis r5, r2, .LCPI3_1@toc@ha ; CHECK-P8-NEXT: lxvd2x vs2, 0, r6
; CHECK-P8-NEXT: lvx v0, r4, r6 ; CHECK-P8-NEXT: addis r6, r2, .LCPI3_1@toc@ha
; CHECK-P8-NEXT: addis r4, r2, .LCPI3_3@toc@ha ; CHECK-P8-NEXT: lxvd2x vs3, r4, r5
; CHECK-P8-NEXT: addi r5, r5, .LCPI3_1@toc@l ; CHECK-P8-NEXT: addi r4, r6, .LCPI3_1@toc@l
; CHECK-P8-NEXT: addi r4, r4, .LCPI3_3@toc@l ; CHECK-P8-NEXT: addis r6, r2, .LCPI3_3@toc@ha
; CHECK-P8-NEXT: lvx v1, 0, r5 ; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: li r5, 96 ; CHECK-P8-NEXT: lxvd2x vs4, 0, r4
; CHECK-P8-NEXT: lvx v8, 0, r4 ; CHECK-P8-NEXT: addi r4, r6, .LCPI3_3@toc@l
; CHECK-P8-NEXT: vperm v6, v3, v4, v2 ; CHECK-P8-NEXT: li r6, 96
; CHECK-P8-NEXT: lxvd2x vs0, 0, r4
; CHECK-P8-NEXT: xxswapd v3, vs1
; CHECK-P8-NEXT: xxswapd v5, vs2
; CHECK-P8-NEXT: li r4, 112 ; CHECK-P8-NEXT: li r4, 112
; CHECK-P8-NEXT: vperm v7, v3, v4, v5 ; CHECK-P8-NEXT: xxswapd v0, vs3
; CHECK-P8-NEXT: vperm v2, v3, v0, v2 ; CHECK-P8-NEXT: xxswapd v1, vs4
; CHECK-P8-NEXT: vperm v9, v3, v0, v1 ; CHECK-P8-NEXT: xxswapd v8, vs0
; CHECK-P8-NEXT: vperm v5, v3, v0, v5 ; CHECK-P8-NEXT: vperm v6, v4, v2, v3
; CHECK-P8-NEXT: vperm v0, v3, v0, v8 ; CHECK-P8-NEXT: vperm v7, v4, v2, v5
; CHECK-P8-NEXT: vperm v1, v3, v4, v1 ; CHECK-P8-NEXT: vperm v3, v4, v0, v3
; CHECK-P8-NEXT: vperm v3, v3, v4, v8 ; CHECK-P8-NEXT: vperm v9, v4, v0, v1
; CHECK-P8-NEXT: xvcvuxddp vs1, v2 ; CHECK-P8-NEXT: vperm v5, v4, v0, v5
; CHECK-P8-NEXT: vperm v0, v4, v0, v8
; CHECK-P8-NEXT: vperm v1, v4, v2, v1
; CHECK-P8-NEXT: vperm v2, v4, v2, v8
; CHECK-P8-NEXT: xvcvuxddp vs1, v3
; CHECK-P8-NEXT: xvcvuxddp vs4, v9 ; CHECK-P8-NEXT: xvcvuxddp vs4, v9
; CHECK-P8-NEXT: xvcvuxddp vs2, v5 ; CHECK-P8-NEXT: xvcvuxddp vs2, v5
; CHECK-P8-NEXT: xvcvuxddp vs3, v0 ; CHECK-P8-NEXT: xvcvuxddp vs3, v0
; CHECK-P8-NEXT: xvcvuxddp vs0, v7 ; CHECK-P8-NEXT: xvcvuxddp vs0, v7
; CHECK-P8-NEXT: xvcvuxddp vs5, v3 ; CHECK-P8-NEXT: xvcvuxddp vs5, v2
; CHECK-P8-NEXT: xvcvuxddp vs6, v6 ; CHECK-P8-NEXT: xvcvuxddp vs6, v6
; CHECK-P8-NEXT: xxswapd vs1, vs1 ; CHECK-P8-NEXT: xxswapd vs1, vs1
; CHECK-P8-NEXT: xvcvuxddp vs7, v1 ; CHECK-P8-NEXT: xvcvuxddp vs7, v1
; CHECK-P8-NEXT: xxswapd vs4, vs4 ; CHECK-P8-NEXT: xxswapd vs4, vs4
; CHECK-P8-NEXT: xxswapd vs2, vs2 ; CHECK-P8-NEXT: xxswapd vs2, vs2
; CHECK-P8-NEXT: xxswapd vs3, vs3 ; CHECK-P8-NEXT: xxswapd vs3, vs3
; CHECK-P8-NEXT: xxswapd vs0, vs0 ; CHECK-P8-NEXT: xxswapd vs0, vs0
; CHECK-P8-NEXT: xxswapd vs5, vs5 ; CHECK-P8-NEXT: xxswapd vs5, vs5
; CHECK-P8-NEXT: stxvd2x vs3, r3, r4 ; CHECK-P8-NEXT: stxvd2x vs3, r3, r4
; CHECK-P8-NEXT: stxvd2x vs2, r3, r5 ; CHECK-P8-NEXT: stxvd2x vs2, r3, r6
; CHECK-P8-NEXT: li r4, 80 ; CHECK-P8-NEXT: li r4, 80
; CHECK-P8-NEXT: li r5, 64 ; CHECK-P8-NEXT: li r6, 64
; CHECK-P8-NEXT: xxswapd vs2, vs7 ; CHECK-P8-NEXT: xxswapd vs2, vs7
; CHECK-P8-NEXT: xxswapd vs3, vs6 ; CHECK-P8-NEXT: xxswapd vs3, vs6
; CHECK-P8-NEXT: stxvd2x vs4, r3, r4 ; CHECK-P8-NEXT: stxvd2x vs4, r3, r4
; CHECK-P8-NEXT: li r4, 48 ; CHECK-P8-NEXT: li r4, 48
; CHECK-P8-NEXT: stxvd2x vs1, r3, r5 ; CHECK-P8-NEXT: stxvd2x vs1, r3, r6
; CHECK-P8-NEXT: li r5, 32 ; CHECK-P8-NEXT: li r6, 32
; CHECK-P8-NEXT: stxvd2x vs5, r3, r4 ; CHECK-P8-NEXT: stxvd2x vs5, r3, r4
; CHECK-P8-NEXT: stxvd2x vs0, r3, r5 ; CHECK-P8-NEXT: stxvd2x vs0, r3, r6
; CHECK-P8-NEXT: stxvd2x vs2, r3, r6 ; CHECK-P8-NEXT: stxvd2x vs2, r3, r5
; CHECK-P8-NEXT: stxvd2x vs3, 0, r3 ; CHECK-P8-NEXT: stxvd2x vs3, 0, r3
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test16elt: ; CHECK-P9-LABEL: test16elt:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lxv v2, 16(r4) ; CHECK-P9-NEXT: lxv v2, 16(r4)
; CHECK-P9-NEXT: lxv v3, 0(r4) ; CHECK-P9-NEXT: lxv v3, 0(r4)
; CHECK-P9-NEXT: addis r4, r2, .LCPI3_0@toc@ha ; CHECK-P9-NEXT: addis r4, r2, .LCPI3_0@toc@ha
▲ Show 20 Lines • Show All 87 Lines • ▼ Show 20 Lines
define <2 x double> @test2elt_signed(i32 %a.coerce) local_unnamed_addr #0 { define <2 x double> @test2elt_signed(i32 %a.coerce) local_unnamed_addr #0 {
; CHECK-P8-LABEL: test2elt_signed: ; CHECK-P8-LABEL: test2elt_signed:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: addis r4, r2, .LCPI4_0@toc@ha ; CHECK-P8-NEXT: addis r4, r2, .LCPI4_0@toc@ha
; CHECK-P8-NEXT: mtvsrwz v3, r3 ; CHECK-P8-NEXT: mtvsrwz v3, r3
; CHECK-P8-NEXT: addis r3, r2, .LCPI4_1@toc@ha ; CHECK-P8-NEXT: addis r3, r2, .LCPI4_1@toc@ha
; CHECK-P8-NEXT: addi r4, r4, .LCPI4_0@toc@l ; CHECK-P8-NEXT: addi r4, r4, .LCPI4_0@toc@l
; CHECK-P8-NEXT: addi r3, r3, .LCPI4_1@toc@l ; CHECK-P8-NEXT: addi r3, r3, .LCPI4_1@toc@l
; CHECK-P8-NEXT: lvx v2, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r4
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: lxvd2x vs0, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: vperm v2, v3, v3, v2 ; CHECK-P8-NEXT: vperm v2, v3, v3, v2
; CHECK-P8-NEXT: xxswapd v3, vs0 ; CHECK-P8-NEXT: xxswapd v3, vs0
; CHECK-P8-NEXT: vsld v2, v2, v3 ; CHECK-P8-NEXT: vsld v2, v2, v3
; CHECK-P8-NEXT: vsrad v2, v2, v3 ; CHECK-P8-NEXT: vsrad v2, v2, v3
; CHECK-P8-NEXT: xvcvsxddp v2, v2 ; CHECK-P8-NEXT: xvcvsxddp v2, v2
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
Show All 28 Lines
; CHECK-P8-LABEL: test4elt_signed: ; CHECK-P8-LABEL: test4elt_signed:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: addis r5, r2, .LCPI5_0@toc@ha ; CHECK-P8-NEXT: addis r5, r2, .LCPI5_0@toc@ha
; CHECK-P8-NEXT: addis r6, r2, .LCPI5_2@toc@ha ; CHECK-P8-NEXT: addis r6, r2, .LCPI5_2@toc@ha
; CHECK-P8-NEXT: mtvsrd v3, r4 ; CHECK-P8-NEXT: mtvsrd v3, r4
; CHECK-P8-NEXT: addis r4, r2, .LCPI5_1@toc@ha ; CHECK-P8-NEXT: addis r4, r2, .LCPI5_1@toc@ha
; CHECK-P8-NEXT: addi r5, r5, .LCPI5_0@toc@l ; CHECK-P8-NEXT: addi r5, r5, .LCPI5_0@toc@l
; CHECK-P8-NEXT: addi r4, r4, .LCPI5_1@toc@l ; CHECK-P8-NEXT: addi r4, r4, .LCPI5_1@toc@l
; CHECK-P8-NEXT: lvx v2, 0, r5 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r5
; CHECK-P8-NEXT: addi r5, r6, .LCPI5_2@toc@l ; CHECK-P8-NEXT: addi r5, r6, .LCPI5_2@toc@l
; CHECK-P8-NEXT: lxvd2x vs1, 0, r5
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: lxvd2x vs0, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r4
; CHECK-P8-NEXT: li r4, 16 ; CHECK-P8-NEXT: li r4, 16
; CHECK-P8-NEXT: lvx v4, 0, r5 ; CHECK-P8-NEXT: xxswapd v4, vs1
; CHECK-P8-NEXT: vperm v2, v3, v3, v2 ; CHECK-P8-NEXT: vperm v2, v3, v3, v2
; CHECK-P8-NEXT: vperm v3, v3, v3, v4 ; CHECK-P8-NEXT: vperm v3, v3, v3, v4
; CHECK-P8-NEXT: xxswapd v4, vs0 ; CHECK-P8-NEXT: xxswapd v4, vs0
; CHECK-P8-NEXT: vsld v2, v2, v4 ; CHECK-P8-NEXT: vsld v2, v2, v4
; CHECK-P8-NEXT: vsld v3, v3, v4 ; CHECK-P8-NEXT: vsld v3, v3, v4
; CHECK-P8-NEXT: vsrad v2, v2, v4 ; CHECK-P8-NEXT: vsrad v2, v2, v4
; CHECK-P8-NEXT: vsrad v3, v3, v4 ; CHECK-P8-NEXT: vsrad v3, v3, v4
; CHECK-P8-NEXT: xvcvsxddp vs0, v2 ; CHECK-P8-NEXT: xvcvsxddp vs0, v2
▲ Show 20 Lines • Show All 46 Lines • ▼ Show 20 Linesentry:
%1 = sitofp <4 x i16> %0 to <4 x double> %1 = sitofp <4 x i16> %0 to <4 x double>
store <4 x double> %1, <4 x double>* %agg.result, align 32 store <4 x double> %1, <4 x double>* %agg.result, align 32
ret void ret void
} }
define void @test8elt_signed(<8 x double>* noalias nocapture sret(<8 x double>) %agg.result, <8 x i16> %a) local_unnamed_addr #2 { define void @test8elt_signed(<8 x double>* noalias nocapture sret(<8 x double>) %agg.result, <8 x i16> %a) local_unnamed_addr #2 {
; CHECK-P8-LABEL: test8elt_signed: ; CHECK-P8-LABEL: test8elt_signed:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: addis r5, r2, .LCPI6_2@toc@ha
; CHECK-P8-NEXT: addis r4, r2, .LCPI6_0@toc@ha ; CHECK-P8-NEXT: addis r4, r2, .LCPI6_0@toc@ha
; CHECK-P8-NEXT: addis r6, r2, .LCPI6_3@toc@ha ; CHECK-P8-NEXT: addis r5, r2, .LCPI6_2@toc@ha
; CHECK-P8-NEXT: addi r5, r5, .LCPI6_2@toc@l
; CHECK-P8-NEXT: addi r4, r4, .LCPI6_0@toc@l ; CHECK-P8-NEXT: addi r4, r4, .LCPI6_0@toc@l
; CHECK-P8-NEXT: addi r6, r6, .LCPI6_3@toc@l ; CHECK-P8-NEXT: addi r5, r5, .LCPI6_2@toc@l
; CHECK-P8-NEXT: lvx v4, 0, r5 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r4
; CHECK-P8-NEXT: addis r4, r2, .LCPI6_3@toc@ha
; CHECK-P8-NEXT: lxvd2x vs1, 0, r5
; CHECK-P8-NEXT: addis r5, r2, .LCPI6_4@toc@ha ; CHECK-P8-NEXT: addis r5, r2, .LCPI6_4@toc@ha
; CHECK-P8-NEXT: lvx v3, 0, r4 ; CHECK-P8-NEXT: addi r4, r4, .LCPI6_3@toc@l
; CHECK-P8-NEXT: lvx v5, 0, r6
; CHECK-P8-NEXT: addis r4, r2, .LCPI6_1@toc@ha
; CHECK-P8-NEXT: addi r5, r5, .LCPI6_4@toc@l ; CHECK-P8-NEXT: addi r5, r5, .LCPI6_4@toc@l
; CHECK-P8-NEXT: lxvd2x vs2, 0, r4
; CHECK-P8-NEXT: lxvd2x vs3, 0, r5
; CHECK-P8-NEXT: addis r4, r2, .LCPI6_1@toc@ha
; CHECK-P8-NEXT: li r5, 32
; CHECK-P8-NEXT: xxswapd v3, vs0
; CHECK-P8-NEXT: xxswapd v4, vs1
; CHECK-P8-NEXT: addi r4, r4, .LCPI6_1@toc@l ; CHECK-P8-NEXT: addi r4, r4, .LCPI6_1@toc@l
; CHECK-P8-NEXT: lvx v0, 0, r5
; CHECK-P8-NEXT: lxvd2x vs0, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r4
; CHECK-P8-NEXT: li r4, 48 ; CHECK-P8-NEXT: li r4, 48
; CHECK-P8-NEXT: li r5, 32 ; CHECK-P8-NEXT: xxswapd v5, vs2
; CHECK-P8-NEXT: xxswapd v0, vs3
; CHECK-P8-NEXT: vperm v3, v2, v2, v3 ; CHECK-P8-NEXT: vperm v3, v2, v2, v3
; CHECK-P8-NEXT: vperm v4, v2, v2, v4 ; CHECK-P8-NEXT: vperm v4, v2, v2, v4
; CHECK-P8-NEXT: vperm v5, v2, v2, v5 ; CHECK-P8-NEXT: vperm v5, v2, v2, v5
; CHECK-P8-NEXT: vperm v2, v2, v2, v0 ; CHECK-P8-NEXT: vperm v2, v2, v2, v0
; CHECK-P8-NEXT: xxswapd v0, vs0 ; CHECK-P8-NEXT: xxswapd v0, vs0
; CHECK-P8-NEXT: vsld v3, v3, v0 ; CHECK-P8-NEXT: vsld v3, v3, v0
; CHECK-P8-NEXT: vsld v4, v4, v0 ; CHECK-P8-NEXT: vsld v4, v4, v0
; CHECK-P8-NEXT: vsld v5, v5, v0 ; CHECK-P8-NEXT: vsld v5, v5, v0
▲ Show 20 Lines • Show All 86 Lines • ▼ Show 20 Linesentry:
ret void ret void
} }
define void @test16elt_signed(<16 x double>* noalias nocapture sret(<16 x double>) %agg.result, <16 x i16>* nocapture readonly) local_unnamed_addr #3 { define void @test16elt_signed(<16 x double>* noalias nocapture sret(<16 x double>) %agg.result, <16 x i16>* nocapture readonly) local_unnamed_addr #3 {
; CHECK-P8-LABEL: test16elt_signed: ; CHECK-P8-LABEL: test16elt_signed:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: addis r5, r2, .LCPI7_0@toc@ha ; CHECK-P8-NEXT: addis r5, r2, .LCPI7_0@toc@ha
; CHECK-P8-NEXT: addis r6, r2, .LCPI7_2@toc@ha ; CHECK-P8-NEXT: addis r6, r2, .LCPI7_2@toc@ha
; CHECK-P8-NEXT: lvx v4, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs1, 0, r4
; CHECK-P8-NEXT: addi r5, r5, .LCPI7_0@toc@l ; CHECK-P8-NEXT: addi r5, r5, .LCPI7_0@toc@l
; CHECK-P8-NEXT: addi r6, r6, .LCPI7_2@toc@l ; CHECK-P8-NEXT: addi r6, r6, .LCPI7_2@toc@l
; CHECK-P8-NEXT: lvx v2, 0, r5 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r5
; CHECK-P8-NEXT: addis r5, r2, .LCPI7_3@toc@ha ; CHECK-P8-NEXT: addis r5, r2, .LCPI7_3@toc@ha
; CHECK-P8-NEXT: lvx v3, 0, r6 ; CHECK-P8-NEXT: lxvd2x vs2, 0, r6
; CHECK-P8-NEXT: addis r6, r2, .LCPI7_4@toc@ha ; CHECK-P8-NEXT: addis r6, r2, .LCPI7_4@toc@ha
; CHECK-P8-NEXT: addi r5, r5, .LCPI7_3@toc@l ; CHECK-P8-NEXT: addi r5, r5, .LCPI7_3@toc@l
; CHECK-P8-NEXT: addi r6, r6, .LCPI7_4@toc@l ; CHECK-P8-NEXT: addi r6, r6, .LCPI7_4@toc@l
; CHECK-P8-NEXT: lvx v5, 0, r5 ; CHECK-P8-NEXT: xxswapd v2, vs1
; CHECK-P8-NEXT: lvx v0, 0, r6 ; CHECK-P8-NEXT: lxvd2x vs3, 0, r5
; CHECK-P8-NEXT: li r6, 16 ; CHECK-P8-NEXT: li r5, 16
; CHECK-P8-NEXT: addis r5, r2, .LCPI7_1@toc@ha ; CHECK-P8-NEXT: lxvd2x vs4, 0, r6
; CHECK-P8-NEXT: lvx v7, r4, r6 ; CHECK-P8-NEXT: li r6, 96
; CHECK-P8-NEXT: addi r5, r5, .LCPI7_1@toc@l ; CHECK-P8-NEXT: xxswapd v3, vs0
; CHECK-P8-NEXT: vperm v1, v4, v4, v2 ; CHECK-P8-NEXT: lxvd2x vs0, r4, r5
; CHECK-P8-NEXT: xxswapd v4, vs2
; CHECK-P8-NEXT: addis r4, r2, .LCPI7_1@toc@ha
; CHECK-P8-NEXT: addi r4, r4, .LCPI7_1@toc@l
; CHECK-P8-NEXT: xxswapd v5, vs3
; CHECK-P8-NEXT: xxswapd v0, vs4
; CHECK-P8-NEXT: xxswapd v6, vs0
; CHECK-P8-NEXT: vperm v1, v2, v2, v3
; CHECK-P8-NEXT: lxvd2x vs0, 0, r4
; CHECK-P8-NEXT: li r4, 112 ; CHECK-P8-NEXT: li r4, 112
; CHECK-P8-NEXT: vperm v6, v4, v4, v3 ; CHECK-P8-NEXT: vperm v7, v2, v2, v4
; CHECK-P8-NEXT: lxvd2x vs0, 0, r5 ; CHECK-P8-NEXT: vperm v8, v2, v2, v5
; CHECK-P8-NEXT: li r5, 96 ; CHECK-P8-NEXT: vperm v2, v2, v2, v0
; CHECK-P8-NEXT: vperm v8, v4, v4, v5
; CHECK-P8-NEXT: vperm v4, v4, v4, v0
; CHECK-P8-NEXT: vperm v5, v7, v7, v5
; CHECK-P8-NEXT: xxswapd v9, vs0 ; CHECK-P8-NEXT: xxswapd v9, vs0
; CHECK-P8-NEXT: vperm v0, v7, v7, v0 ; CHECK-P8-NEXT: vperm v5, v6, v6, v5
; CHECK-P8-NEXT: vperm v2, v7, v7, v2 ; CHECK-P8-NEXT: vperm v0, v6, v6, v0
; CHECK-P8-NEXT: vperm v3, v7, v7, v3 ; CHECK-P8-NEXT: vperm v3, v6, v6, v3
; CHECK-P8-NEXT: vperm v4, v6, v6, v4
; CHECK-P8-NEXT: vsld v1, v1, v9 ; CHECK-P8-NEXT: vsld v1, v1, v9
; CHECK-P8-NEXT: vsld v6, v6, v9 ; CHECK-P8-NEXT: vsld v6, v7, v9
; CHECK-P8-NEXT: vsld v5, v5, v9 ; CHECK-P8-NEXT: vsld v5, v5, v9
; CHECK-P8-NEXT: vsld v0, v0, v9 ; CHECK-P8-NEXT: vsld v0, v0, v9
; CHECK-P8-NEXT: vsld v2, v2, v9
; CHECK-P8-NEXT: vsld v3, v3, v9 ; CHECK-P8-NEXT: vsld v3, v3, v9
; CHECK-P8-NEXT: vsld v4, v4, v9
; CHECK-P8-NEXT: vsrad v5, v5, v9 ; CHECK-P8-NEXT: vsrad v5, v5, v9
; CHECK-P8-NEXT: vsrad v0, v0, v9 ; CHECK-P8-NEXT: vsrad v0, v0, v9
; CHECK-P8-NEXT: vsld v7, v8, v9 ; CHECK-P8-NEXT: vsld v7, v8, v9
; CHECK-P8-NEXT: vsld v4, v4, v9 ; CHECK-P8-NEXT: vsld v2, v2, v9
; CHECK-P8-NEXT: vsrad v2, v2, v9
; CHECK-P8-NEXT: vsrad v3, v3, v9 ; CHECK-P8-NEXT: vsrad v3, v3, v9
; CHECK-P8-NEXT: vsrad v4, v4, v9
; CHECK-P8-NEXT: xvcvsxddp vs2, v5 ; CHECK-P8-NEXT: xvcvsxddp vs2, v5
; CHECK-P8-NEXT: xvcvsxddp vs3, v0 ; CHECK-P8-NEXT: xvcvsxddp vs3, v0
; CHECK-P8-NEXT: vsrad v1, v1, v9 ; CHECK-P8-NEXT: vsrad v1, v1, v9
; CHECK-P8-NEXT: vsrad v6, v6, v9 ; CHECK-P8-NEXT: vsrad v6, v6, v9
; CHECK-P8-NEXT: vsrad v7, v7, v9 ; CHECK-P8-NEXT: vsrad v7, v7, v9
; CHECK-P8-NEXT: vsrad v4, v4, v9 ; CHECK-P8-NEXT: vsrad v2, v2, v9
; CHECK-P8-NEXT: xvcvsxddp vs1, v2 ; CHECK-P8-NEXT: xvcvsxddp vs1, v3
; CHECK-P8-NEXT: xxswapd vs2, vs2 ; CHECK-P8-NEXT: xxswapd vs2, vs2
; CHECK-P8-NEXT: xvcvsxddp vs4, v3 ; CHECK-P8-NEXT: xvcvsxddp vs4, v4
; CHECK-P8-NEXT: xxswapd vs3, vs3 ; CHECK-P8-NEXT: xxswapd vs3, vs3
; CHECK-P8-NEXT: xvcvsxddp vs0, v7 ; CHECK-P8-NEXT: xvcvsxddp vs0, v7
; CHECK-P8-NEXT: xvcvsxddp vs5, v4 ; CHECK-P8-NEXT: xvcvsxddp vs5, v2
; CHECK-P8-NEXT: xvcvsxddp vs6, v1 ; CHECK-P8-NEXT: xvcvsxddp vs6, v1
; CHECK-P8-NEXT: stxvd2x vs3, r3, r4 ; CHECK-P8-NEXT: stxvd2x vs3, r3, r4
; CHECK-P8-NEXT: li r4, 80 ; CHECK-P8-NEXT: li r4, 80
; CHECK-P8-NEXT: xvcvsxddp vs7, v6 ; CHECK-P8-NEXT: xvcvsxddp vs7, v6
; CHECK-P8-NEXT: stxvd2x vs2, r3, r5 ; CHECK-P8-NEXT: stxvd2x vs2, r3, r6
; CHECK-P8-NEXT: li r5, 64 ; CHECK-P8-NEXT: li r6, 64
; CHECK-P8-NEXT: xxswapd vs1, vs1 ; CHECK-P8-NEXT: xxswapd vs1, vs1
; CHECK-P8-NEXT: xxswapd vs4, vs4 ; CHECK-P8-NEXT: xxswapd vs4, vs4
; CHECK-P8-NEXT: xxswapd vs0, vs0 ; CHECK-P8-NEXT: xxswapd vs0, vs0
; CHECK-P8-NEXT: xxswapd vs5, vs5 ; CHECK-P8-NEXT: xxswapd vs5, vs5
; CHECK-P8-NEXT: xxswapd vs3, vs6 ; CHECK-P8-NEXT: xxswapd vs3, vs6
; CHECK-P8-NEXT: stxvd2x vs4, r3, r4 ; CHECK-P8-NEXT: stxvd2x vs4, r3, r4
; CHECK-P8-NEXT: li r4, 48 ; CHECK-P8-NEXT: li r4, 48
; CHECK-P8-NEXT: xxswapd vs2, vs7 ; CHECK-P8-NEXT: xxswapd vs2, vs7
; CHECK-P8-NEXT: stxvd2x vs1, r3, r5 ; CHECK-P8-NEXT: stxvd2x vs1, r3, r6
; CHECK-P8-NEXT: li r5, 32 ; CHECK-P8-NEXT: li r6, 32
; CHECK-P8-NEXT: stxvd2x vs5, r3, r4 ; CHECK-P8-NEXT: stxvd2x vs5, r3, r4
; CHECK-P8-NEXT: stxvd2x vs0, r3, r5 ; CHECK-P8-NEXT: stxvd2x vs0, r3, r6
; CHECK-P8-NEXT: stxvd2x vs2, r3, r6 ; CHECK-P8-NEXT: stxvd2x vs2, r3, r5
; CHECK-P8-NEXT: stxvd2x vs3, 0, r3 ; CHECK-P8-NEXT: stxvd2x vs3, 0, r3
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test16elt_signed: ; CHECK-P9-LABEL: test16elt_signed:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: addis r5, r2, .LCPI7_0@toc@ha ; CHECK-P9-NEXT: addis r5, r2, .LCPI7_0@toc@ha
; CHECK-P9-NEXT: lxv v2, 0(r4) ; CHECK-P9-NEXT: lxv v2, 0(r4)
; CHECK-P9-NEXT: addi r5, r5, .LCPI7_0@toc@l ; CHECK-P9-NEXT: addi r5, r5, .LCPI7_0@toc@l
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llvm/test/CodeGen/PowerPC/vec_conv_i32_to_fp64_elts.ll

Show First 20 Lines • Show All 75 Lines • ▼ Show 20 Linesentry:
store <4 x double> %0, <4 x double>* %agg.result, align 32 store <4 x double> %0, <4 x double>* %agg.result, align 32
ret void ret void
} }
define void @test8elt(<8 x double>* noalias nocapture sret(<8 x double>) %agg.result, <8 x i32>* nocapture readonly) local_unnamed_addr #2 { define void @test8elt(<8 x double>* noalias nocapture sret(<8 x double>) %agg.result, <8 x i32>* nocapture readonly) local_unnamed_addr #2 {
; CHECK-P8-LABEL: test8elt: ; CHECK-P8-LABEL: test8elt:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: li r5, 16 ; CHECK-P8-NEXT: li r5, 16
; CHECK-P8-NEXT: lvx v3, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs1, 0, r4
; CHECK-P8-NEXT: li r6, 32 ; CHECK-P8-NEXT: li r6, 32
; CHECK-P8-NEXT: lvx v2, r4, r5 ; CHECK-P8-NEXT: lxvd2x vs0, r4, r5
; CHECK-P8-NEXT: li r4, 48 ; CHECK-P8-NEXT: li r4, 48
; CHECK-P8-NEXT: xxswapd v3, vs1
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: xxmrglw v5, v3, v3 ; CHECK-P8-NEXT: xxmrglw v5, v3, v3
; CHECK-P8-NEXT: xxmrghw v3, v3, v3 ; CHECK-P8-NEXT: xxmrghw v3, v3, v3
; CHECK-P8-NEXT: xxmrglw v4, v2, v2 ; CHECK-P8-NEXT: xxmrglw v4, v2, v2
; CHECK-P8-NEXT: xxmrghw v2, v2, v2 ; CHECK-P8-NEXT: xxmrghw v2, v2, v2
; CHECK-P8-NEXT: xvcvuxwdp vs2, v5 ; CHECK-P8-NEXT: xvcvuxwdp vs2, v5
; CHECK-P8-NEXT: xvcvuxwdp vs0, v4 ; CHECK-P8-NEXT: xvcvuxwdp vs0, v4
; CHECK-P8-NEXT: xvcvuxwdp vs1, v2 ; CHECK-P8-NEXT: xvcvuxwdp vs1, v2
; CHECK-P8-NEXT: xvcvuxwdp vs3, v3 ; CHECK-P8-NEXT: xvcvuxwdp vs3, v3
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define void @test16elt(<16 x double>* noalias nocapture sret(<16 x double>) %agg.result, <16 x i32>* nocapture readonly) local_unnamed_addr #2 { define void @test16elt(<16 x double>* noalias nocapture sret(<16 x double>) %agg.result, <16 x i32>* nocapture readonly) local_unnamed_addr #2 {
; CHECK-P8-LABEL: test16elt: ; CHECK-P8-LABEL: test16elt:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: li r5, 16 ; CHECK-P8-NEXT: li r5, 16
; CHECK-P8-NEXT: li r6, 48 ; CHECK-P8-NEXT: li r6, 48
; CHECK-P8-NEXT: li r7, 32 ; CHECK-P8-NEXT: li r7, 32
; CHECK-P8-NEXT: li r8, 64 ; CHECK-P8-NEXT: li r8, 64
; CHECK-P8-NEXT: lvx v2, r4, r5 ; CHECK-P8-NEXT: lxvd2x vs0, r4, r5
; CHECK-P8-NEXT: lvx v3, r4, r6 ; CHECK-P8-NEXT: lxvd2x vs1, r4, r6
; CHECK-P8-NEXT: lvx v0, r4, r7 ; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: xxswapd v3, vs1
; CHECK-P8-NEXT: lxvd2x vs0, r4, r7
; CHECK-P8-NEXT: lxvd2x vs1, 0, r4
; CHECK-P8-NEXT: li r4, 112
; CHECK-P8-NEXT: xxmrglw v4, v2, v2 ; CHECK-P8-NEXT: xxmrglw v4, v2, v2
; CHECK-P8-NEXT: xxmrghw v5, v3, v3 ; CHECK-P8-NEXT: xxmrghw v0, v3, v3
; CHECK-P8-NEXT: xxswapd v5, vs0
; CHECK-P8-NEXT: xxmrghw v2, v2, v2 ; CHECK-P8-NEXT: xxmrghw v2, v2, v2
; CHECK-P8-NEXT: xxmrglw v3, v3, v3 ; CHECK-P8-NEXT: xxmrglw v3, v3, v3
; CHECK-P8-NEXT: xvcvuxwdp vs0, v4 ; CHECK-P8-NEXT: xvcvuxwdp vs0, v4
; CHECK-P8-NEXT: lvx v4, 0, r4 ; CHECK-P8-NEXT: xxswapd v4, vs1
; CHECK-P8-NEXT: li r4, 112 ; CHECK-P8-NEXT: xvcvuxwdp vs1, v0
; CHECK-P8-NEXT: xvcvuxwdp vs1, v5 ; CHECK-P8-NEXT: xxmrghw v0, v5, v5
; CHECK-P8-NEXT: xxmrghw v5, v0, v0 ; CHECK-P8-NEXT: xxmrglw v5, v5, v5
; CHECK-P8-NEXT: xxmrglw v0, v0, v0
; CHECK-P8-NEXT: xvcvuxwdp vs2, v2 ; CHECK-P8-NEXT: xvcvuxwdp vs2, v2
; CHECK-P8-NEXT: xxmrglw v2, v4, v4 ; CHECK-P8-NEXT: xxmrglw v2, v4, v4
; CHECK-P8-NEXT: xvcvuxwdp vs3, v3 ; CHECK-P8-NEXT: xvcvuxwdp vs3, v3
; CHECK-P8-NEXT: xxmrghw v3, v4, v4 ; CHECK-P8-NEXT: xxmrghw v3, v4, v4
; CHECK-P8-NEXT: xvcvuxwdp vs4, v5 ; CHECK-P8-NEXT: xvcvuxwdp vs4, v0
; CHECK-P8-NEXT: xvcvuxwdp vs5, v0 ; CHECK-P8-NEXT: xvcvuxwdp vs5, v5
; CHECK-P8-NEXT: xvcvuxwdp vs6, v2 ; CHECK-P8-NEXT: xvcvuxwdp vs6, v2
; CHECK-P8-NEXT: xxswapd vs0, vs0 ; CHECK-P8-NEXT: xxswapd vs0, vs0
; CHECK-P8-NEXT: xvcvuxwdp vs7, v3 ; CHECK-P8-NEXT: xvcvuxwdp vs7, v3
; CHECK-P8-NEXT: xxswapd vs1, vs1 ; CHECK-P8-NEXT: xxswapd vs1, vs1
; CHECK-P8-NEXT: xxswapd vs2, vs2 ; CHECK-P8-NEXT: xxswapd vs2, vs2
; CHECK-P8-NEXT: xxswapd vs3, vs3 ; CHECK-P8-NEXT: xxswapd vs3, vs3
; CHECK-P8-NEXT: stxvd2x vs1, r3, r4 ; CHECK-P8-NEXT: stxvd2x vs1, r3, r4
; CHECK-P8-NEXT: li r4, 96 ; CHECK-P8-NEXT: li r4, 96
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store <4 x double> %0, <4 x double>* %agg.result, align 32 store <4 x double> %0, <4 x double>* %agg.result, align 32
ret void ret void
} }
define void @test8elt_signed(<8 x double>* noalias nocapture sret(<8 x double>) %agg.result, <8 x i32>* nocapture readonly) local_unnamed_addr #2 { define void @test8elt_signed(<8 x double>* noalias nocapture sret(<8 x double>) %agg.result, <8 x i32>* nocapture readonly) local_unnamed_addr #2 {
; CHECK-P8-LABEL: test8elt_signed: ; CHECK-P8-LABEL: test8elt_signed:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: li r5, 16 ; CHECK-P8-NEXT: li r5, 16
; CHECK-P8-NEXT: lvx v3, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs1, 0, r4
; CHECK-P8-NEXT: li r6, 32 ; CHECK-P8-NEXT: li r6, 32
; CHECK-P8-NEXT: lvx v2, r4, r5 ; CHECK-P8-NEXT: lxvd2x vs0, r4, r5
; CHECK-P8-NEXT: li r4, 48 ; CHECK-P8-NEXT: li r4, 48
; CHECK-P8-NEXT: xxswapd v3, vs1
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: xxmrglw v5, v3, v3 ; CHECK-P8-NEXT: xxmrglw v5, v3, v3
; CHECK-P8-NEXT: xxmrghw v3, v3, v3 ; CHECK-P8-NEXT: xxmrghw v3, v3, v3
; CHECK-P8-NEXT: xxmrglw v4, v2, v2 ; CHECK-P8-NEXT: xxmrglw v4, v2, v2
; CHECK-P8-NEXT: xxmrghw v2, v2, v2 ; CHECK-P8-NEXT: xxmrghw v2, v2, v2
; CHECK-P8-NEXT: xvcvsxwdp vs2, v5 ; CHECK-P8-NEXT: xvcvsxwdp vs2, v5
; CHECK-P8-NEXT: xvcvsxwdp vs0, v4 ; CHECK-P8-NEXT: xvcvsxwdp vs0, v4
; CHECK-P8-NEXT: xvcvsxwdp vs1, v2 ; CHECK-P8-NEXT: xvcvsxwdp vs1, v2
; CHECK-P8-NEXT: xvcvsxwdp vs3, v3 ; CHECK-P8-NEXT: xvcvsxwdp vs3, v3
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define void @test16elt_signed(<16 x double>* noalias nocapture sret(<16 x double>) %agg.result, <16 x i32>* nocapture readonly) local_unnamed_addr #2 { define void @test16elt_signed(<16 x double>* noalias nocapture sret(<16 x double>) %agg.result, <16 x i32>* nocapture readonly) local_unnamed_addr #2 {
; CHECK-P8-LABEL: test16elt_signed: ; CHECK-P8-LABEL: test16elt_signed:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: li r5, 16 ; CHECK-P8-NEXT: li r5, 16
; CHECK-P8-NEXT: li r6, 48 ; CHECK-P8-NEXT: li r6, 48
; CHECK-P8-NEXT: li r7, 32 ; CHECK-P8-NEXT: li r7, 32
; CHECK-P8-NEXT: li r8, 64 ; CHECK-P8-NEXT: li r8, 64
; CHECK-P8-NEXT: lvx v2, r4, r5 ; CHECK-P8-NEXT: lxvd2x vs0, r4, r5
; CHECK-P8-NEXT: lvx v3, r4, r6 ; CHECK-P8-NEXT: lxvd2x vs1, r4, r6
; CHECK-P8-NEXT: lvx v0, r4, r7 ; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: xxswapd v3, vs1
; CHECK-P8-NEXT: lxvd2x vs0, r4, r7
; CHECK-P8-NEXT: lxvd2x vs1, 0, r4
; CHECK-P8-NEXT: li r4, 112
; CHECK-P8-NEXT: xxmrglw v4, v2, v2 ; CHECK-P8-NEXT: xxmrglw v4, v2, v2
; CHECK-P8-NEXT: xxmrghw v5, v3, v3 ; CHECK-P8-NEXT: xxmrghw v0, v3, v3
; CHECK-P8-NEXT: xxswapd v5, vs0
; CHECK-P8-NEXT: xxmrghw v2, v2, v2 ; CHECK-P8-NEXT: xxmrghw v2, v2, v2
; CHECK-P8-NEXT: xxmrglw v3, v3, v3 ; CHECK-P8-NEXT: xxmrglw v3, v3, v3
; CHECK-P8-NEXT: xvcvsxwdp vs0, v4 ; CHECK-P8-NEXT: xvcvsxwdp vs0, v4
; CHECK-P8-NEXT: lvx v4, 0, r4 ; CHECK-P8-NEXT: xxswapd v4, vs1
; CHECK-P8-NEXT: li r4, 112 ; CHECK-P8-NEXT: xvcvsxwdp vs1, v0
; CHECK-P8-NEXT: xvcvsxwdp vs1, v5 ; CHECK-P8-NEXT: xxmrghw v0, v5, v5
; CHECK-P8-NEXT: xxmrghw v5, v0, v0 ; CHECK-P8-NEXT: xxmrglw v5, v5, v5
; CHECK-P8-NEXT: xxmrglw v0, v0, v0
; CHECK-P8-NEXT: xvcvsxwdp vs2, v2 ; CHECK-P8-NEXT: xvcvsxwdp vs2, v2
; CHECK-P8-NEXT: xxmrglw v2, v4, v4 ; CHECK-P8-NEXT: xxmrglw v2, v4, v4
; CHECK-P8-NEXT: xvcvsxwdp vs3, v3 ; CHECK-P8-NEXT: xvcvsxwdp vs3, v3
; CHECK-P8-NEXT: xxmrghw v3, v4, v4 ; CHECK-P8-NEXT: xxmrghw v3, v4, v4
; CHECK-P8-NEXT: xvcvsxwdp vs4, v5 ; CHECK-P8-NEXT: xvcvsxwdp vs4, v0
; CHECK-P8-NEXT: xvcvsxwdp vs5, v0 ; CHECK-P8-NEXT: xvcvsxwdp vs5, v5
; CHECK-P8-NEXT: xvcvsxwdp vs6, v2 ; CHECK-P8-NEXT: xvcvsxwdp vs6, v2
; CHECK-P8-NEXT: xxswapd vs0, vs0 ; CHECK-P8-NEXT: xxswapd vs0, vs0
; CHECK-P8-NEXT: xvcvsxwdp vs7, v3 ; CHECK-P8-NEXT: xvcvsxwdp vs7, v3
; CHECK-P8-NEXT: xxswapd vs1, vs1 ; CHECK-P8-NEXT: xxswapd vs1, vs1
; CHECK-P8-NEXT: xxswapd vs2, vs2 ; CHECK-P8-NEXT: xxswapd vs2, vs2
; CHECK-P8-NEXT: xxswapd vs3, vs3 ; CHECK-P8-NEXT: xxswapd vs3, vs3
; CHECK-P8-NEXT: stxvd2x vs1, r3, r4 ; CHECK-P8-NEXT: stxvd2x vs1, r3, r4
; CHECK-P8-NEXT: li r4, 96 ; CHECK-P8-NEXT: li r4, 96
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llvm/test/CodeGen/PowerPC/vec_conv_i64_to_fp32_elts.ll

Show First 20 Lines • Show All 109 Lines • ▼ Show 20 Lines
; CHECK-P8-NEXT: xvcvuxdsp vs1, v3 ; CHECK-P8-NEXT: xvcvuxdsp vs1, v3
; CHECK-P8-NEXT: xvcvuxdsp vs2, v4 ; CHECK-P8-NEXT: xvcvuxdsp vs2, v4
; CHECK-P8-NEXT: xxsldwi v5, vs3, vs3, 3 ; CHECK-P8-NEXT: xxsldwi v5, vs3, vs3, 3
; CHECK-P8-NEXT: xxsldwi v2, vs0, vs0, 3 ; CHECK-P8-NEXT: xxsldwi v2, vs0, vs0, 3
; CHECK-P8-NEXT: xxsldwi v3, vs1, vs1, 3 ; CHECK-P8-NEXT: xxsldwi v3, vs1, vs1, 3
; CHECK-P8-NEXT: xxsldwi v4, vs2, vs2, 3 ; CHECK-P8-NEXT: xxsldwi v4, vs2, vs2, 3
; CHECK-P8-NEXT: vpkudum v2, v3, v2 ; CHECK-P8-NEXT: vpkudum v2, v3, v2
; CHECK-P8-NEXT: vpkudum v3, v4, v5 ; CHECK-P8-NEXT: vpkudum v3, v4, v5
; CHECK-P8-NEXT: stvx v2, r3, r5 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: stvx v3, 0, r3 ; CHECK-P8-NEXT: xxswapd vs1, v3
; CHECK-P8-NEXT: stxvd2x vs0, r3, r5
; CHECK-P8-NEXT: stxvd2x vs1, 0, r3
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test8elt: ; CHECK-P9-LABEL: test8elt:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lxv v5, 0(r4) ; CHECK-P9-NEXT: lxv v5, 0(r4)
; CHECK-P9-NEXT: lxv v4, 16(r4) ; CHECK-P9-NEXT: lxv v4, 16(r4)
; CHECK-P9-NEXT: lxv v3, 32(r4) ; CHECK-P9-NEXT: lxv v3, 32(r4)
; CHECK-P9-NEXT: lxv v2, 48(r4) ; CHECK-P9-NEXT: lxv v2, 48(r4)
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; CHECK-P8-NEXT: xxsldwi v0, vs4, vs4, 3 ; CHECK-P8-NEXT: xxsldwi v0, vs4, vs4, 3
; CHECK-P8-NEXT: vpkudum v2, v3, v2 ; CHECK-P8-NEXT: vpkudum v2, v3, v2
; CHECK-P8-NEXT: xxsldwi v1, vs5, vs5, 3 ; CHECK-P8-NEXT: xxsldwi v1, vs5, vs5, 3
; CHECK-P8-NEXT: xxsldwi v6, vs6, vs6, 3 ; CHECK-P8-NEXT: xxsldwi v6, vs6, vs6, 3
; CHECK-P8-NEXT: vpkudum v3, v5, v4 ; CHECK-P8-NEXT: vpkudum v3, v5, v4
; CHECK-P8-NEXT: xxsldwi v7, vs7, vs7, 3 ; CHECK-P8-NEXT: xxsldwi v7, vs7, vs7, 3
; CHECK-P8-NEXT: vpkudum v4, v1, v0 ; CHECK-P8-NEXT: vpkudum v4, v1, v0
; CHECK-P8-NEXT: vpkudum v5, v6, v7 ; CHECK-P8-NEXT: vpkudum v5, v6, v7
; CHECK-P8-NEXT: stvx v2, r3, r7 ; CHECK-P8-NEXT: xxswapd vs2, v2
; CHECK-P8-NEXT: stvx v3, r3, r5 ; CHECK-P8-NEXT: xxswapd vs1, v3
; CHECK-P8-NEXT: stvx v4, r3, r6 ; CHECK-P8-NEXT: xxswapd vs0, v4
; CHECK-P8-NEXT: stvx v5, 0, r3 ; CHECK-P8-NEXT: xxswapd vs3, v5
; CHECK-P8-NEXT: stxvd2x vs0, r3, r6
; CHECK-P8-NEXT: stxvd2x vs1, r3, r5
; CHECK-P8-NEXT: stxvd2x vs2, r3, r7
; CHECK-P8-NEXT: stxvd2x vs3, 0, r3
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test16elt: ; CHECK-P9-LABEL: test16elt:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lxv v7, 0(r4) ; CHECK-P9-NEXT: lxv v7, 0(r4)
; CHECK-P9-NEXT: lxv v6, 16(r4) ; CHECK-P9-NEXT: lxv v6, 16(r4)
; CHECK-P9-NEXT: lxv v1, 32(r4) ; CHECK-P9-NEXT: lxv v1, 32(r4)
; CHECK-P9-NEXT: lxv v0, 48(r4) ; CHECK-P9-NEXT: lxv v0, 48(r4)
▲ Show 20 Lines • Show All 170 Lines • ▼ Show 20 Lines
; CHECK-P8-NEXT: xvcvsxdsp vs1, v3 ; CHECK-P8-NEXT: xvcvsxdsp vs1, v3
; CHECK-P8-NEXT: xvcvsxdsp vs2, v4 ; CHECK-P8-NEXT: xvcvsxdsp vs2, v4
; CHECK-P8-NEXT: xxsldwi v5, vs3, vs3, 3 ; CHECK-P8-NEXT: xxsldwi v5, vs3, vs3, 3
; CHECK-P8-NEXT: xxsldwi v2, vs0, vs0, 3 ; CHECK-P8-NEXT: xxsldwi v2, vs0, vs0, 3
; CHECK-P8-NEXT: xxsldwi v3, vs1, vs1, 3 ; CHECK-P8-NEXT: xxsldwi v3, vs1, vs1, 3
; CHECK-P8-NEXT: xxsldwi v4, vs2, vs2, 3 ; CHECK-P8-NEXT: xxsldwi v4, vs2, vs2, 3
; CHECK-P8-NEXT: vpkudum v2, v3, v2 ; CHECK-P8-NEXT: vpkudum v2, v3, v2
; CHECK-P8-NEXT: vpkudum v3, v4, v5 ; CHECK-P8-NEXT: vpkudum v3, v4, v5
; CHECK-P8-NEXT: stvx v2, r3, r5 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: stvx v3, 0, r3 ; CHECK-P8-NEXT: xxswapd vs1, v3
; CHECK-P8-NEXT: stxvd2x vs0, r3, r5
; CHECK-P8-NEXT: stxvd2x vs1, 0, r3
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test8elt_signed: ; CHECK-P9-LABEL: test8elt_signed:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lxv v5, 0(r4) ; CHECK-P9-NEXT: lxv v5, 0(r4)
; CHECK-P9-NEXT: lxv v4, 16(r4) ; CHECK-P9-NEXT: lxv v4, 16(r4)
; CHECK-P9-NEXT: lxv v3, 32(r4) ; CHECK-P9-NEXT: lxv v3, 32(r4)
; CHECK-P9-NEXT: lxv v2, 48(r4) ; CHECK-P9-NEXT: lxv v2, 48(r4)
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; CHECK-P8-NEXT: xxsldwi v0, vs4, vs4, 3 ; CHECK-P8-NEXT: xxsldwi v0, vs4, vs4, 3
; CHECK-P8-NEXT: vpkudum v2, v3, v2 ; CHECK-P8-NEXT: vpkudum v2, v3, v2
; CHECK-P8-NEXT: xxsldwi v1, vs5, vs5, 3 ; CHECK-P8-NEXT: xxsldwi v1, vs5, vs5, 3
; CHECK-P8-NEXT: xxsldwi v6, vs6, vs6, 3 ; CHECK-P8-NEXT: xxsldwi v6, vs6, vs6, 3
; CHECK-P8-NEXT: vpkudum v3, v5, v4 ; CHECK-P8-NEXT: vpkudum v3, v5, v4
; CHECK-P8-NEXT: xxsldwi v7, vs7, vs7, 3 ; CHECK-P8-NEXT: xxsldwi v7, vs7, vs7, 3
; CHECK-P8-NEXT: vpkudum v4, v1, v0 ; CHECK-P8-NEXT: vpkudum v4, v1, v0
; CHECK-P8-NEXT: vpkudum v5, v6, v7 ; CHECK-P8-NEXT: vpkudum v5, v6, v7
; CHECK-P8-NEXT: stvx v2, r3, r7 ; CHECK-P8-NEXT: xxswapd vs2, v2
; CHECK-P8-NEXT: stvx v3, r3, r5 ; CHECK-P8-NEXT: xxswapd vs1, v3
; CHECK-P8-NEXT: stvx v4, r3, r6 ; CHECK-P8-NEXT: xxswapd vs0, v4
; CHECK-P8-NEXT: stvx v5, 0, r3 ; CHECK-P8-NEXT: xxswapd vs3, v5
; CHECK-P8-NEXT: stxvd2x vs0, r3, r6
; CHECK-P8-NEXT: stxvd2x vs1, r3, r5
; CHECK-P8-NEXT: stxvd2x vs2, r3, r7
; CHECK-P8-NEXT: stxvd2x vs3, 0, r3
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test16elt_signed: ; CHECK-P9-LABEL: test16elt_signed:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lxv v7, 0(r4) ; CHECK-P9-NEXT: lxv v7, 0(r4)
; CHECK-P9-NEXT: lxv v6, 16(r4) ; CHECK-P9-NEXT: lxv v6, 16(r4)
; CHECK-P9-NEXT: lxv v1, 32(r4) ; CHECK-P9-NEXT: lxv v1, 32(r4)
; CHECK-P9-NEXT: lxv v0, 48(r4) ; CHECK-P9-NEXT: lxv v0, 48(r4)
▲ Show 20 Lines • Show All 71 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/vec_conv_i8_to_fp32_elts.ll

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define <4 x float> @test4elt(i32 %a.coerce) local_unnamed_addr #1 { define <4 x float> @test4elt(i32 %a.coerce) local_unnamed_addr #1 {
; CHECK-P8-LABEL: test4elt: ; CHECK-P8-LABEL: test4elt:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: addis r4, r2, .LCPI1_0@toc@ha ; CHECK-P8-NEXT: addis r4, r2, .LCPI1_0@toc@ha
; CHECK-P8-NEXT: mtvsrwz v2, r3 ; CHECK-P8-NEXT: mtvsrwz v2, r3
; CHECK-P8-NEXT: addi r4, r4, .LCPI1_0@toc@l ; CHECK-P8-NEXT: addi r4, r4, .LCPI1_0@toc@l
; CHECK-P8-NEXT: xxlxor v4, v4, v4 ; CHECK-P8-NEXT: xxlxor v4, v4, v4
; CHECK-P8-NEXT: lvx v3, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r4
; CHECK-P8-NEXT: xxswapd v3, vs0
; CHECK-P8-NEXT: vperm v2, v4, v2, v3 ; CHECK-P8-NEXT: vperm v2, v4, v2, v3
; CHECK-P8-NEXT: xvcvuxwsp v2, v2 ; CHECK-P8-NEXT: xvcvuxwsp v2, v2
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test4elt: ; CHECK-P9-LABEL: test4elt:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtvsrwz v2, r3 ; CHECK-P9-NEXT: mtvsrwz v2, r3
; CHECK-P9-NEXT: addis r3, r2, .LCPI1_0@toc@ha ; CHECK-P9-NEXT: addis r3, r2, .LCPI1_0@toc@ha
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ret <4 x float> %1 ret <4 x float> %1
} }
define void @test8elt(<8 x float>* noalias nocapture sret(<8 x float>) %agg.result, i64 %a.coerce) local_unnamed_addr #2 { define void @test8elt(<8 x float>* noalias nocapture sret(<8 x float>) %agg.result, i64 %a.coerce) local_unnamed_addr #2 {
; CHECK-P8-LABEL: test8elt: ; CHECK-P8-LABEL: test8elt:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: addis r5, r2, .LCPI2_0@toc@ha ; CHECK-P8-NEXT: addis r5, r2, .LCPI2_0@toc@ha
; CHECK-P8-NEXT: addis r6, r2, .LCPI2_1@toc@ha ; CHECK-P8-NEXT: addis r6, r2, .LCPI2_1@toc@ha
; CHECK-P8-NEXT: mtvsrd v2, r4 ; CHECK-P8-NEXT: xxlxor v2, v2, v2
; CHECK-P8-NEXT: addi r5, r5, .LCPI2_0@toc@l ; CHECK-P8-NEXT: addi r5, r5, .LCPI2_0@toc@l
; CHECK-P8-NEXT: addi r4, r6, .LCPI2_1@toc@l ; CHECK-P8-NEXT: mtvsrd v4, r4
; CHECK-P8-NEXT: xxlxor v4, v4, v4
; CHECK-P8-NEXT: lvx v3, 0, r5
; CHECK-P8-NEXT: lvx v5, 0, r4
; CHECK-P8-NEXT: li r4, 16 ; CHECK-P8-NEXT: li r4, 16
; CHECK-P8-NEXT: vperm v3, v4, v2, v3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r5
; CHECK-P8-NEXT: vperm v2, v4, v2, v5 ; CHECK-P8-NEXT: addi r5, r6, .LCPI2_1@toc@l
; CHECK-P8-NEXT: xvcvuxwsp v3, v3 ; CHECK-P8-NEXT: lxvd2x vs1, 0, r5
; CHECK-P8-NEXT: xvcvuxwsp v2, v2 ; CHECK-P8-NEXT: xxswapd v3, vs0
; CHECK-P8-NEXT: stvx v3, 0, r3 ; CHECK-P8-NEXT: xxswapd v5, vs1
; CHECK-P8-NEXT: stvx v2, r3, r4 ; CHECK-P8-NEXT: vperm v3, v2, v4, v3
; CHECK-P8-NEXT: vperm v2, v2, v4, v5
; CHECK-P8-NEXT: xvcvuxwsp vs0, v3
; CHECK-P8-NEXT: xvcvuxwsp vs1, v2
; CHECK-P8-NEXT: xxswapd vs0, vs0
; CHECK-P8-NEXT: xxswapd vs1, vs1
; CHECK-P8-NEXT: stxvd2x vs1, r3, r4
; CHECK-P8-NEXT: stxvd2x vs0, 0, r3
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test8elt: ; CHECK-P9-LABEL: test8elt:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtvsrd v2, r4 ; CHECK-P9-NEXT: mtvsrd v2, r4
; CHECK-P9-NEXT: addis r4, r2, .LCPI2_0@toc@ha ; CHECK-P9-NEXT: addis r4, r2, .LCPI2_0@toc@ha
; CHECK-P9-NEXT: xxlxor v4, v4, v4 ; CHECK-P9-NEXT: xxlxor v4, v4, v4
; CHECK-P9-NEXT: addi r4, r4, .LCPI2_0@toc@l ; CHECK-P9-NEXT: addi r4, r4, .LCPI2_0@toc@l
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define void @test16elt(<16 x float>* noalias nocapture sret(<16 x float>) %agg.result, <16 x i8> %a) local_unnamed_addr #3 { define void @test16elt(<16 x float>* noalias nocapture sret(<16 x float>) %agg.result, <16 x i8> %a) local_unnamed_addr #3 {
; CHECK-P8-LABEL: test16elt: ; CHECK-P8-LABEL: test16elt:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: addis r4, r2, .LCPI3_0@toc@ha ; CHECK-P8-NEXT: addis r4, r2, .LCPI3_0@toc@ha
; CHECK-P8-NEXT: addis r5, r2, .LCPI3_2@toc@ha ; CHECK-P8-NEXT: addis r5, r2, .LCPI3_2@toc@ha
; CHECK-P8-NEXT: xxlxor v4, v4, v4 ; CHECK-P8-NEXT: xxlxor v4, v4, v4
; CHECK-P8-NEXT: addi r4, r4, .LCPI3_0@toc@l ; CHECK-P8-NEXT: addi r4, r4, .LCPI3_0@toc@l
; CHECK-P8-NEXT: addi r5, r5, .LCPI3_2@toc@l ; CHECK-P8-NEXT: addi r5, r5, .LCPI3_2@toc@l
; CHECK-P8-NEXT: lvx v3, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r4
; CHECK-P8-NEXT: addis r4, r2, .LCPI3_3@toc@ha ; CHECK-P8-NEXT: addis r4, r2, .LCPI3_3@toc@ha
; CHECK-P8-NEXT: lvx v5, 0, r5 ; CHECK-P8-NEXT: lxvd2x vs1, 0, r5
; CHECK-P8-NEXT: addis r5, r2, .LCPI3_1@toc@ha ; CHECK-P8-NEXT: addis r5, r2, .LCPI3_1@toc@ha
; CHECK-P8-NEXT: addi r4, r4, .LCPI3_3@toc@l ; CHECK-P8-NEXT: addi r4, r4, .LCPI3_3@toc@l
; CHECK-P8-NEXT: addi r5, r5, .LCPI3_1@toc@l ; CHECK-P8-NEXT: addi r5, r5, .LCPI3_1@toc@l
; CHECK-P8-NEXT: lvx v0, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs2, 0, r4
; CHECK-P8-NEXT: lvx v1, 0, r5 ; CHECK-P8-NEXT: lxvd2x vs3, 0, r5
; CHECK-P8-NEXT: li r4, 48 ; CHECK-P8-NEXT: li r4, 48
; CHECK-P8-NEXT: li r5, 32 ; CHECK-P8-NEXT: li r5, 32
; CHECK-P8-NEXT: vperm v5, v4, v2, v5 ; CHECK-P8-NEXT: xxswapd v3, vs0
; CHECK-P8-NEXT: xxswapd v5, vs1
; CHECK-P8-NEXT: xxswapd v0, vs2
; CHECK-P8-NEXT: xxswapd v1, vs3
; CHECK-P8-NEXT: vperm v3, v4, v2, v3 ; CHECK-P8-NEXT: vperm v3, v4, v2, v3
; CHECK-P8-NEXT: vperm v5, v4, v2, v5
; CHECK-P8-NEXT: vperm v0, v4, v2, v0 ; CHECK-P8-NEXT: vperm v0, v4, v2, v0
; CHECK-P8-NEXT: vperm v2, v4, v2, v1 ; CHECK-P8-NEXT: vperm v2, v4, v2, v1
; CHECK-P8-NEXT: xvcvuxwsp v4, v5 ; CHECK-P8-NEXT: xvcvuxwsp vs0, v3
; CHECK-P8-NEXT: xvcvuxwsp v3, v3 ; CHECK-P8-NEXT: xvcvuxwsp vs1, v5
; CHECK-P8-NEXT: xvcvuxwsp v5, v0 ; CHECK-P8-NEXT: xvcvuxwsp vs2, v0
; CHECK-P8-NEXT: xvcvuxwsp v2, v2 ; CHECK-P8-NEXT: xvcvuxwsp vs3, v2
; CHECK-P8-NEXT: stvx v4, r3, r5 ; CHECK-P8-NEXT: xxswapd vs0, vs0
; CHECK-P8-NEXT: stvx v3, 0, r3 ; CHECK-P8-NEXT: xxswapd vs1, vs1
; CHECK-P8-NEXT: stvx v5, r3, r4 ; CHECK-P8-NEXT: xxswapd vs2, vs2
; CHECK-P8-NEXT: xxswapd vs3, vs3
; CHECK-P8-NEXT: stxvd2x vs2, r3, r4
; CHECK-P8-NEXT: li r4, 16 ; CHECK-P8-NEXT: li r4, 16
; CHECK-P8-NEXT: stvx v2, r3, r4 ; CHECK-P8-NEXT: stxvd2x vs1, r3, r5
; CHECK-P8-NEXT: stxvd2x vs3, r3, r4
; CHECK-P8-NEXT: stxvd2x vs0, 0, r3
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test16elt: ; CHECK-P9-LABEL: test16elt:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: addis r4, r2, .LCPI3_0@toc@ha ; CHECK-P9-NEXT: addis r4, r2, .LCPI3_0@toc@ha
; CHECK-P9-NEXT: xxlxor v4, v4, v4 ; CHECK-P9-NEXT: xxlxor v4, v4, v4
; CHECK-P9-NEXT: addi r4, r4, .LCPI3_0@toc@l ; CHECK-P9-NEXT: addi r4, r4, .LCPI3_0@toc@l
; CHECK-P9-NEXT: lxv v3, 0(r4) ; CHECK-P9-NEXT: lxv v3, 0(r4)
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} }
define <4 x float> @test4elt_signed(i32 %a.coerce) local_unnamed_addr #1 { define <4 x float> @test4elt_signed(i32 %a.coerce) local_unnamed_addr #1 {
; CHECK-P8-LABEL: test4elt_signed: ; CHECK-P8-LABEL: test4elt_signed:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: addis r4, r2, .LCPI5_0@toc@ha ; CHECK-P8-NEXT: addis r4, r2, .LCPI5_0@toc@ha
; CHECK-P8-NEXT: mtvsrwz v3, r3 ; CHECK-P8-NEXT: mtvsrwz v3, r3
; CHECK-P8-NEXT: addi r4, r4, .LCPI5_0@toc@l ; CHECK-P8-NEXT: addi r4, r4, .LCPI5_0@toc@l
; CHECK-P8-NEXT: lvx v2, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r4
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: vperm v2, v3, v3, v2 ; CHECK-P8-NEXT: vperm v2, v3, v3, v2
; CHECK-P8-NEXT: vspltisw v3, 12 ; CHECK-P8-NEXT: vspltisw v3, 12
; CHECK-P8-NEXT: vadduwm v3, v3, v3 ; CHECK-P8-NEXT: vadduwm v3, v3, v3
; CHECK-P8-NEXT: vslw v2, v2, v3 ; CHECK-P8-NEXT: vslw v2, v2, v3
; CHECK-P8-NEXT: vsraw v2, v2, v3 ; CHECK-P8-NEXT: vsraw v2, v2, v3
; CHECK-P8-NEXT: xvcvsxwsp v2, v2 ; CHECK-P8-NEXT: xvcvsxwsp v2, v2
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
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} }
define void @test8elt_signed(<8 x float>* noalias nocapture sret(<8 x float>) %agg.result, i64 %a.coerce) local_unnamed_addr #2 { define void @test8elt_signed(<8 x float>* noalias nocapture sret(<8 x float>) %agg.result, i64 %a.coerce) local_unnamed_addr #2 {
; CHECK-P8-LABEL: test8elt_signed: ; CHECK-P8-LABEL: test8elt_signed:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: addis r5, r2, .LCPI6_0@toc@ha ; CHECK-P8-NEXT: addis r5, r2, .LCPI6_0@toc@ha
; CHECK-P8-NEXT: addis r6, r2, .LCPI6_1@toc@ha ; CHECK-P8-NEXT: addis r6, r2, .LCPI6_1@toc@ha
; CHECK-P8-NEXT: mtvsrd v3, r4 ; CHECK-P8-NEXT: mtvsrd v3, r4
; CHECK-P8-NEXT: vspltisw v5, 12
; CHECK-P8-NEXT: li r4, 16 ; CHECK-P8-NEXT: li r4, 16
; CHECK-P8-NEXT: addi r5, r5, .LCPI6_0@toc@l ; CHECK-P8-NEXT: addi r5, r5, .LCPI6_0@toc@l
; CHECK-P8-NEXT: lvx v2, 0, r5 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r5
; CHECK-P8-NEXT: addi r5, r6, .LCPI6_1@toc@l ; CHECK-P8-NEXT: addi r5, r6, .LCPI6_1@toc@l
; CHECK-P8-NEXT: lvx v4, 0, r5 ; CHECK-P8-NEXT: lxvd2x vs1, 0, r5
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: xxswapd v4, vs1
; CHECK-P8-NEXT: vperm v2, v3, v3, v2 ; CHECK-P8-NEXT: vperm v2, v3, v3, v2
; CHECK-P8-NEXT: vperm v3, v3, v3, v4 ; CHECK-P8-NEXT: vperm v3, v3, v3, v4
; CHECK-P8-NEXT: vadduwm v4, v5, v5 ; CHECK-P8-NEXT: vspltisw v4, 12
; CHECK-P8-NEXT: vadduwm v4, v4, v4
; CHECK-P8-NEXT: vslw v2, v2, v4 ; CHECK-P8-NEXT: vslw v2, v2, v4
; CHECK-P8-NEXT: vslw v3, v3, v4 ; CHECK-P8-NEXT: vslw v3, v3, v4
; CHECK-P8-NEXT: vsraw v2, v2, v4 ; CHECK-P8-NEXT: vsraw v2, v2, v4
; CHECK-P8-NEXT: vsraw v3, v3, v4 ; CHECK-P8-NEXT: vsraw v3, v3, v4
; CHECK-P8-NEXT: xvcvsxwsp v2, v2 ; CHECK-P8-NEXT: xvcvsxwsp vs0, v2
; CHECK-P8-NEXT: xvcvsxwsp v3, v3 ; CHECK-P8-NEXT: xvcvsxwsp vs1, v3
; CHECK-P8-NEXT: stvx v2, 0, r3 ; CHECK-P8-NEXT: xxswapd vs0, vs0
; CHECK-P8-NEXT: stvx v3, r3, r4 ; CHECK-P8-NEXT: xxswapd vs1, vs1
; CHECK-P8-NEXT: stxvd2x vs1, r3, r4
; CHECK-P8-NEXT: stxvd2x vs0, 0, r3
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test8elt_signed: ; CHECK-P9-LABEL: test8elt_signed:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtvsrd v2, r4 ; CHECK-P9-NEXT: mtvsrd v2, r4
; CHECK-P9-NEXT: addis r4, r2, .LCPI6_0@toc@ha ; CHECK-P9-NEXT: addis r4, r2, .LCPI6_0@toc@ha
; CHECK-P9-NEXT: addi r4, r4, .LCPI6_0@toc@l ; CHECK-P9-NEXT: addi r4, r4, .LCPI6_0@toc@l
; CHECK-P9-NEXT: lxv v3, 0(r4) ; CHECK-P9-NEXT: lxv v3, 0(r4)
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define void @test16elt_signed(<16 x float>* noalias nocapture sret(<16 x float>) %agg.result, <16 x i8> %a) local_unnamed_addr #3 { define void @test16elt_signed(<16 x float>* noalias nocapture sret(<16 x float>) %agg.result, <16 x i8> %a) local_unnamed_addr #3 {
; CHECK-P8-LABEL: test16elt_signed: ; CHECK-P8-LABEL: test16elt_signed:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: addis r4, r2, .LCPI7_0@toc@ha ; CHECK-P8-NEXT: addis r4, r2, .LCPI7_0@toc@ha
; CHECK-P8-NEXT: addis r5, r2, .LCPI7_2@toc@ha ; CHECK-P8-NEXT: addis r5, r2, .LCPI7_2@toc@ha
; CHECK-P8-NEXT: vspltisw v1, 12 ; CHECK-P8-NEXT: vspltisw v1, 12
; CHECK-P8-NEXT: addi r4, r4, .LCPI7_0@toc@l ; CHECK-P8-NEXT: addi r4, r4, .LCPI7_0@toc@l
; CHECK-P8-NEXT: addi r5, r5, .LCPI7_2@toc@l ; CHECK-P8-NEXT: addi r5, r5, .LCPI7_2@toc@l
; CHECK-P8-NEXT: lvx v3, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r4
; CHECK-P8-NEXT: addis r4, r2, .LCPI7_3@toc@ha ; CHECK-P8-NEXT: addis r4, r2, .LCPI7_3@toc@ha
; CHECK-P8-NEXT: lvx v4, 0, r5 ; CHECK-P8-NEXT: lxvd2x vs1, 0, r5
; CHECK-P8-NEXT: addis r5, r2, .LCPI7_1@toc@ha ; CHECK-P8-NEXT: addis r5, r2, .LCPI7_1@toc@ha
; CHECK-P8-NEXT: addi r4, r4, .LCPI7_3@toc@l ; CHECK-P8-NEXT: addi r4, r4, .LCPI7_3@toc@l
; CHECK-P8-NEXT: addi r5, r5, .LCPI7_1@toc@l ; CHECK-P8-NEXT: addi r5, r5, .LCPI7_1@toc@l
; CHECK-P8-NEXT: lvx v5, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs2, 0, r4
; CHECK-P8-NEXT: lvx v0, 0, r5 ; CHECK-P8-NEXT: lxvd2x vs3, 0, r5
; CHECK-P8-NEXT: li r4, 48 ; CHECK-P8-NEXT: li r4, 48
; CHECK-P8-NEXT: li r5, 32 ; CHECK-P8-NEXT: li r5, 32
; CHECK-P8-NEXT: xxswapd v3, vs0
; CHECK-P8-NEXT: xxswapd v4, vs1
; CHECK-P8-NEXT: xxswapd v5, vs2
; CHECK-P8-NEXT: xxswapd v0, vs3
; CHECK-P8-NEXT: vperm v3, v2, v2, v3 ; CHECK-P8-NEXT: vperm v3, v2, v2, v3
; CHECK-P8-NEXT: vperm v4, v2, v2, v4 ; CHECK-P8-NEXT: vperm v4, v2, v2, v4
; CHECK-P8-NEXT: vperm v5, v2, v2, v5 ; CHECK-P8-NEXT: vperm v5, v2, v2, v5
; CHECK-P8-NEXT: vperm v2, v2, v2, v0 ; CHECK-P8-NEXT: vperm v2, v2, v2, v0
; CHECK-P8-NEXT: vadduwm v0, v1, v1 ; CHECK-P8-NEXT: vadduwm v0, v1, v1
; CHECK-P8-NEXT: vslw v3, v3, v0 ; CHECK-P8-NEXT: vslw v3, v3, v0
; CHECK-P8-NEXT: vslw v4, v4, v0 ; CHECK-P8-NEXT: vslw v4, v4, v0
; CHECK-P8-NEXT: vslw v5, v5, v0 ; CHECK-P8-NEXT: vslw v5, v5, v0
; CHECK-P8-NEXT: vslw v2, v2, v0 ; CHECK-P8-NEXT: vslw v2, v2, v0
; CHECK-P8-NEXT: vsraw v3, v3, v0 ; CHECK-P8-NEXT: vsraw v3, v3, v0
; CHECK-P8-NEXT: vsraw v4, v4, v0 ; CHECK-P8-NEXT: vsraw v4, v4, v0
; CHECK-P8-NEXT: vsraw v5, v5, v0 ; CHECK-P8-NEXT: vsraw v5, v5, v0
; CHECK-P8-NEXT: vsraw v2, v2, v0 ; CHECK-P8-NEXT: vsraw v2, v2, v0
; CHECK-P8-NEXT: xvcvsxwsp v3, v3 ; CHECK-P8-NEXT: xvcvsxwsp vs0, v3
; CHECK-P8-NEXT: xvcvsxwsp v4, v4 ; CHECK-P8-NEXT: xvcvsxwsp vs1, v4
; CHECK-P8-NEXT: xvcvsxwsp v5, v5 ; CHECK-P8-NEXT: xvcvsxwsp vs2, v5
; CHECK-P8-NEXT: xvcvsxwsp v2, v2 ; CHECK-P8-NEXT: xvcvsxwsp vs3, v2
; CHECK-P8-NEXT: stvx v3, 0, r3 ; CHECK-P8-NEXT: xxswapd vs0, vs0
; CHECK-P8-NEXT: stvx v4, r3, r5 ; CHECK-P8-NEXT: xxswapd vs1, vs1
; CHECK-P8-NEXT: stvx v5, r3, r4 ; CHECK-P8-NEXT: xxswapd vs2, vs2
; CHECK-P8-NEXT: xxswapd vs3, vs3
; CHECK-P8-NEXT: stxvd2x vs2, r3, r4
; CHECK-P8-NEXT: li r4, 16 ; CHECK-P8-NEXT: li r4, 16
; CHECK-P8-NEXT: stvx v2, r3, r4 ; CHECK-P8-NEXT: stxvd2x vs1, r3, r5
; CHECK-P8-NEXT: stxvd2x vs3, r3, r4
; CHECK-P8-NEXT: stxvd2x vs0, 0, r3
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test16elt_signed: ; CHECK-P9-LABEL: test16elt_signed:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: addis r4, r2, .LCPI7_0@toc@ha ; CHECK-P9-NEXT: addis r4, r2, .LCPI7_0@toc@ha
; CHECK-P9-NEXT: addi r4, r4, .LCPI7_0@toc@l ; CHECK-P9-NEXT: addi r4, r4, .LCPI7_0@toc@l
; CHECK-P9-NEXT: lxv v3, 0(r4) ; CHECK-P9-NEXT: lxv v3, 0(r4)
; CHECK-P9-NEXT: addis r4, r2, .LCPI7_1@toc@ha ; CHECK-P9-NEXT: addis r4, r2, .LCPI7_1@toc@ha
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llvm/test/CodeGen/PowerPC/vec_conv_i8_to_fp64_elts.ll

Show All 10 Lines
define <2 x double> @test2elt(i16 %a.coerce) local_unnamed_addr #0 { define <2 x double> @test2elt(i16 %a.coerce) local_unnamed_addr #0 {
; CHECK-P8-LABEL: test2elt: ; CHECK-P8-LABEL: test2elt:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: addis r4, r2, .LCPI0_0@toc@ha ; CHECK-P8-NEXT: addis r4, r2, .LCPI0_0@toc@ha
; CHECK-P8-NEXT: mtvsrwz v2, r3 ; CHECK-P8-NEXT: mtvsrwz v2, r3
; CHECK-P8-NEXT: addi r4, r4, .LCPI0_0@toc@l ; CHECK-P8-NEXT: addi r4, r4, .LCPI0_0@toc@l
; CHECK-P8-NEXT: xxlxor v4, v4, v4 ; CHECK-P8-NEXT: xxlxor v4, v4, v4
; CHECK-P8-NEXT: lvx v3, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r4
; CHECK-P8-NEXT: xxswapd v3, vs0
; CHECK-P8-NEXT: vperm v2, v4, v2, v3 ; CHECK-P8-NEXT: vperm v2, v4, v2, v3
; CHECK-P8-NEXT: xvcvuxddp v2, v2 ; CHECK-P8-NEXT: xvcvuxddp v2, v2
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test2elt: ; CHECK-P9-LABEL: test2elt:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtvsrwz v2, r3 ; CHECK-P9-NEXT: mtvsrwz v2, r3
; CHECK-P9-NEXT: addis r3, r2, .LCPI0_0@toc@ha ; CHECK-P9-NEXT: addis r3, r2, .LCPI0_0@toc@ha
Show All 20 Linesentry:
ret <2 x double> %1 ret <2 x double> %1
} }
define void @test4elt(<4 x double>* noalias nocapture sret(<4 x double>) %agg.result, i32 %a.coerce) local_unnamed_addr #1 { define void @test4elt(<4 x double>* noalias nocapture sret(<4 x double>) %agg.result, i32 %a.coerce) local_unnamed_addr #1 {
; CHECK-P8-LABEL: test4elt: ; CHECK-P8-LABEL: test4elt:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: addis r5, r2, .LCPI1_0@toc@ha ; CHECK-P8-NEXT: addis r5, r2, .LCPI1_0@toc@ha
; CHECK-P8-NEXT: addis r6, r2, .LCPI1_1@toc@ha ; CHECK-P8-NEXT: addis r6, r2, .LCPI1_1@toc@ha
; CHECK-P8-NEXT: mtvsrwz v2, r4 ; CHECK-P8-NEXT: xxlxor v2, v2, v2
; CHECK-P8-NEXT: addi r5, r5, .LCPI1_0@toc@l ; CHECK-P8-NEXT: addi r5, r5, .LCPI1_0@toc@l
; CHECK-P8-NEXT: addi r4, r6, .LCPI1_1@toc@l ; CHECK-P8-NEXT: mtvsrwz v4, r4
; CHECK-P8-NEXT: xxlxor v4, v4, v4
; CHECK-P8-NEXT: lvx v3, 0, r5
; CHECK-P8-NEXT: lvx v5, 0, r4
; CHECK-P8-NEXT: li r4, 16 ; CHECK-P8-NEXT: li r4, 16
; CHECK-P8-NEXT: vperm v3, v4, v2, v3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r5
; CHECK-P8-NEXT: vperm v2, v4, v2, v5 ; CHECK-P8-NEXT: addi r5, r6, .LCPI1_1@toc@l
; CHECK-P8-NEXT: lxvd2x vs1, 0, r5
; CHECK-P8-NEXT: xxswapd v3, vs0
; CHECK-P8-NEXT: xxswapd v5, vs1
; CHECK-P8-NEXT: vperm v3, v2, v4, v3
; CHECK-P8-NEXT: vperm v2, v2, v4, v5
; CHECK-P8-NEXT: xvcvuxddp vs0, v3 ; CHECK-P8-NEXT: xvcvuxddp vs0, v3
; CHECK-P8-NEXT: xvcvuxddp vs1, v2 ; CHECK-P8-NEXT: xvcvuxddp vs1, v2
; CHECK-P8-NEXT: xxswapd vs0, vs0 ; CHECK-P8-NEXT: xxswapd vs0, vs0
; CHECK-P8-NEXT: xxswapd vs1, vs1 ; CHECK-P8-NEXT: xxswapd vs1, vs1
; CHECK-P8-NEXT: stxvd2x vs1, r3, r4 ; CHECK-P8-NEXT: stxvd2x vs1, r3, r4
; CHECK-P8-NEXT: stxvd2x vs0, 0, r3 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r3
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
Show All 39 Linesentry:
ret void ret void
} }
define void @test8elt(<8 x double>* noalias nocapture sret(<8 x double>) %agg.result, i64 %a.coerce) local_unnamed_addr #1 { define void @test8elt(<8 x double>* noalias nocapture sret(<8 x double>) %agg.result, i64 %a.coerce) local_unnamed_addr #1 {
; CHECK-P8-LABEL: test8elt: ; CHECK-P8-LABEL: test8elt:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: addis r5, r2, .LCPI2_0@toc@ha ; CHECK-P8-NEXT: addis r5, r2, .LCPI2_0@toc@ha
; CHECK-P8-NEXT: addis r6, r2, .LCPI2_2@toc@ha ; CHECK-P8-NEXT: addis r6, r2, .LCPI2_2@toc@ha
; CHECK-P8-NEXT: mtvsrd v2, r4 ; CHECK-P8-NEXT: xxlxor v2, v2, v2
; CHECK-P8-NEXT: addis r4, r2, .LCPI2_3@toc@ha
; CHECK-P8-NEXT: addi r5, r5, .LCPI2_0@toc@l ; CHECK-P8-NEXT: addi r5, r5, .LCPI2_0@toc@l
; CHECK-P8-NEXT: addi r4, r4, .LCPI2_3@toc@l ; CHECK-P8-NEXT: addi r6, r6, .LCPI2_2@toc@l
; CHECK-P8-NEXT: xxlxor v4, v4, v4 ; CHECK-P8-NEXT: mtvsrd v4, r4
; CHECK-P8-NEXT: lvx v3, 0, r5
; CHECK-P8-NEXT: addi r5, r6, .LCPI2_2@toc@l
; CHECK-P8-NEXT: lvx v0, 0, r4
; CHECK-P8-NEXT: li r4, 48 ; CHECK-P8-NEXT: li r4, 48
; CHECK-P8-NEXT: lvx v5, 0, r5 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r5
; CHECK-P8-NEXT: addis r5, r2, .LCPI2_1@toc@ha ; CHECK-P8-NEXT: addis r5, r2, .LCPI2_3@toc@ha
; CHECK-P8-NEXT: addi r5, r5, .LCPI2_1@toc@l ; CHECK-P8-NEXT: lxvd2x vs1, 0, r6
; CHECK-P8-NEXT: lvx v1, 0, r5 ; CHECK-P8-NEXT: addis r6, r2, .LCPI2_1@toc@ha
; CHECK-P8-NEXT: vperm v0, v4, v2, v0 ; CHECK-P8-NEXT: addi r5, r5, .LCPI2_3@toc@l
; CHECK-P8-NEXT: lxvd2x vs2, 0, r5
; CHECK-P8-NEXT: addi r5, r6, .LCPI2_1@toc@l
; CHECK-P8-NEXT: lxvd2x vs3, 0, r5
; CHECK-P8-NEXT: xxswapd v3, vs0
; CHECK-P8-NEXT: xxswapd v5, vs1
; CHECK-P8-NEXT: li r5, 32 ; CHECK-P8-NEXT: li r5, 32
; CHECK-P8-NEXT: vperm v3, v4, v2, v3 ; CHECK-P8-NEXT: xxswapd v0, vs2
; CHECK-P8-NEXT: vperm v5, v4, v2, v5 ; CHECK-P8-NEXT: xxswapd v1, vs3
; CHECK-P8-NEXT: vperm v2, v4, v2, v1 ; CHECK-P8-NEXT: vperm v3, v2, v4, v3
; CHECK-P8-NEXT: xvcvuxddp vs2, v0 ; CHECK-P8-NEXT: vperm v5, v2, v4, v5
; CHECK-P8-NEXT: vperm v0, v2, v4, v0
; CHECK-P8-NEXT: vperm v2, v2, v4, v1
; CHECK-P8-NEXT: xvcvuxddp vs0, v3 ; CHECK-P8-NEXT: xvcvuxddp vs0, v3
; CHECK-P8-NEXT: xvcvuxddp vs1, v5 ; CHECK-P8-NEXT: xvcvuxddp vs1, v5
; CHECK-P8-NEXT: xvcvuxddp vs2, v0
; CHECK-P8-NEXT: xvcvuxddp vs3, v2 ; CHECK-P8-NEXT: xvcvuxddp vs3, v2
; CHECK-P8-NEXT: xxswapd vs2, vs2
; CHECK-P8-NEXT: xxswapd vs0, vs0 ; CHECK-P8-NEXT: xxswapd vs0, vs0
; CHECK-P8-NEXT: xxswapd vs1, vs1 ; CHECK-P8-NEXT: xxswapd vs1, vs1
; CHECK-P8-NEXT: xxswapd vs2, vs2
; CHECK-P8-NEXT: xxswapd vs3, vs3 ; CHECK-P8-NEXT: xxswapd vs3, vs3
; CHECK-P8-NEXT: stxvd2x vs2, r3, r4 ; CHECK-P8-NEXT: stxvd2x vs2, r3, r4
; CHECK-P8-NEXT: li r4, 16 ; CHECK-P8-NEXT: li r4, 16
; CHECK-P8-NEXT: stxvd2x vs1, r3, r5 ; CHECK-P8-NEXT: stxvd2x vs1, r3, r5
; CHECK-P8-NEXT: stxvd2x vs3, r3, r4 ; CHECK-P8-NEXT: stxvd2x vs3, r3, r4
; CHECK-P8-NEXT: stxvd2x vs0, 0, r3 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r3
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
▲ Show 20 Lines • Show All 66 Lines • ▼ Show 20 Lines
define void @test16elt(<16 x double>* noalias nocapture sret(<16 x double>) %agg.result, <16 x i8> %a) local_unnamed_addr #2 { define void @test16elt(<16 x double>* noalias nocapture sret(<16 x double>) %agg.result, <16 x i8> %a) local_unnamed_addr #2 {
; CHECK-P8-LABEL: test16elt: ; CHECK-P8-LABEL: test16elt:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: addis r4, r2, .LCPI3_0@toc@ha ; CHECK-P8-NEXT: addis r4, r2, .LCPI3_0@toc@ha
; CHECK-P8-NEXT: addis r5, r2, .LCPI3_1@toc@ha ; CHECK-P8-NEXT: addis r5, r2, .LCPI3_1@toc@ha
; CHECK-P8-NEXT: xxlxor v4, v4, v4 ; CHECK-P8-NEXT: xxlxor v4, v4, v4
; CHECK-P8-NEXT: addi r4, r4, .LCPI3_0@toc@l ; CHECK-P8-NEXT: addi r4, r4, .LCPI3_0@toc@l
; CHECK-P8-NEXT: addi r5, r5, .LCPI3_1@toc@l ; CHECK-P8-NEXT: addi r5, r5, .LCPI3_1@toc@l
; CHECK-P8-NEXT: lvx v3, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r4
; CHECK-P8-NEXT: addis r4, r2, .LCPI3_2@toc@ha ; CHECK-P8-NEXT: addis r4, r2, .LCPI3_2@toc@ha
; CHECK-P8-NEXT: lvx v5, 0, r5 ; CHECK-P8-NEXT: lxvd2x vs1, 0, r5
; CHECK-P8-NEXT: addis r5, r2, .LCPI3_4@toc@ha ; CHECK-P8-NEXT: addis r5, r2, .LCPI3_4@toc@ha
; CHECK-P8-NEXT: addi r4, r4, .LCPI3_2@toc@l ; CHECK-P8-NEXT: addi r4, r4, .LCPI3_2@toc@l
; CHECK-P8-NEXT: addi r5, r5, .LCPI3_4@toc@l ; CHECK-P8-NEXT: addi r5, r5, .LCPI3_4@toc@l
; CHECK-P8-NEXT: lvx v0, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs2, 0, r4
; CHECK-P8-NEXT: addis r4, r2, .LCPI3_6@toc@ha ; CHECK-P8-NEXT: addis r4, r2, .LCPI3_6@toc@ha
; CHECK-P8-NEXT: lvx v1, 0, r5 ; CHECK-P8-NEXT: lxvd2x vs3, 0, r5
; CHECK-P8-NEXT: addis r5, r2, .LCPI3_7@toc@ha ; CHECK-P8-NEXT: addis r5, r2, .LCPI3_7@toc@ha
; CHECK-P8-NEXT: addi r4, r4, .LCPI3_6@toc@l ; CHECK-P8-NEXT: addi r4, r4, .LCPI3_6@toc@l
; CHECK-P8-NEXT: xxswapd v3, vs0
; CHECK-P8-NEXT: addi r5, r5, .LCPI3_7@toc@l ; CHECK-P8-NEXT: addi r5, r5, .LCPI3_7@toc@l
; CHECK-P8-NEXT: vperm v3, v4, v2, v3 ; CHECK-P8-NEXT: xxswapd v5, vs1
; CHECK-P8-NEXT: lvx v6, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r4
; CHECK-P8-NEXT: addis r4, r2, .LCPI3_5@toc@ha ; CHECK-P8-NEXT: addis r4, r2, .LCPI3_5@toc@ha
; CHECK-P8-NEXT: lvx v7, 0, r5 ; CHECK-P8-NEXT: lxvd2x vs1, 0, r5
; CHECK-P8-NEXT: addis r5, r2, .LCPI3_3@toc@ha ; CHECK-P8-NEXT: addis r5, r2, .LCPI3_3@toc@ha
; CHECK-P8-NEXT: vperm v5, v4, v2, v5
; CHECK-P8-NEXT: addi r4, r4, .LCPI3_5@toc@l ; CHECK-P8-NEXT: addi r4, r4, .LCPI3_5@toc@l
; CHECK-P8-NEXT: xxswapd v0, vs2
; CHECK-P8-NEXT: addi r5, r5, .LCPI3_3@toc@l ; CHECK-P8-NEXT: addi r5, r5, .LCPI3_3@toc@l
; CHECK-P8-NEXT: vperm v0, v4, v2, v0 ; CHECK-P8-NEXT: xxswapd v1, vs3
; CHECK-P8-NEXT: lvx v8, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs2, 0, r4
; CHECK-P8-NEXT: lvx v9, 0, r5 ; CHECK-P8-NEXT: lxvd2x vs3, 0, r5
; CHECK-P8-NEXT: vperm v1, v4, v2, v1 ; CHECK-P8-NEXT: vperm v3, v4, v2, v3
; CHECK-P8-NEXT: li r4, 112 ; CHECK-P8-NEXT: li r4, 112
; CHECK-P8-NEXT: li r5, 96 ; CHECK-P8-NEXT: li r5, 96
; CHECK-P8-NEXT: xxswapd v6, vs0
; CHECK-P8-NEXT: xxswapd v7, vs1
; CHECK-P8-NEXT: vperm v5, v4, v2, v5
; CHECK-P8-NEXT: xxswapd v8, vs2
; CHECK-P8-NEXT: xxswapd v9, vs3
; CHECK-P8-NEXT: vperm v6, v4, v2, v6 ; CHECK-P8-NEXT: vperm v6, v4, v2, v6
; CHECK-P8-NEXT: vperm v7, v4, v2, v7 ; CHECK-P8-NEXT: vperm v7, v4, v2, v7
; CHECK-P8-NEXT: vperm v8, v4, v2, v8 ; CHECK-P8-NEXT: vperm v8, v4, v2, v8
; CHECK-P8-NEXT: vperm v0, v4, v2, v0
; CHECK-P8-NEXT: vperm v1, v4, v2, v1
; CHECK-P8-NEXT: vperm v2, v4, v2, v9 ; CHECK-P8-NEXT: vperm v2, v4, v2, v9
; CHECK-P8-NEXT: xvcvuxddp vs0, v0
; CHECK-P8-NEXT: xvcvuxddp vs1, v1
; CHECK-P8-NEXT: xvcvuxddp vs2, v6 ; CHECK-P8-NEXT: xvcvuxddp vs2, v6
; CHECK-P8-NEXT: xvcvuxddp vs3, v7 ; CHECK-P8-NEXT: xvcvuxddp vs3, v7
; CHECK-P8-NEXT: xvcvuxddp vs4, v8 ; CHECK-P8-NEXT: xvcvuxddp vs4, v8
; CHECK-P8-NEXT: xvcvuxddp vs0, v0
; CHECK-P8-NEXT: xvcvuxddp vs1, v1
; CHECK-P8-NEXT: xvcvuxddp vs5, v2 ; CHECK-P8-NEXT: xvcvuxddp vs5, v2
; CHECK-P8-NEXT: xvcvuxddp vs6, v3 ; CHECK-P8-NEXT: xvcvuxddp vs6, v3
; CHECK-P8-NEXT: xxswapd vs0, vs0
; CHECK-P8-NEXT: xvcvuxddp vs7, v5
; CHECK-P8-NEXT: xxswapd vs1, vs1
; CHECK-P8-NEXT: xxswapd vs2, vs2 ; CHECK-P8-NEXT: xxswapd vs2, vs2
; CHECK-P8-NEXT: xvcvuxddp vs7, v5
; CHECK-P8-NEXT: xxswapd vs3, vs3 ; CHECK-P8-NEXT: xxswapd vs3, vs3
; CHECK-P8-NEXT: xxswapd vs4, vs4 ; CHECK-P8-NEXT: xxswapd vs4, vs4
; CHECK-P8-NEXT: xxswapd vs5, vs5 ; CHECK-P8-NEXT: xxswapd vs0, vs0
; CHECK-P8-NEXT: xxswapd vs1, vs1
; CHECK-P8-NEXT: stxvd2x vs3, r3, r4 ; CHECK-P8-NEXT: stxvd2x vs3, r3, r4
; CHECK-P8-NEXT: stxvd2x vs2, r3, r5
; CHECK-P8-NEXT: li r4, 80 ; CHECK-P8-NEXT: li r4, 80
; CHECK-P8-NEXT: xxswapd vs5, vs5
; CHECK-P8-NEXT: stxvd2x vs2, r3, r5
; CHECK-P8-NEXT: li r5, 64 ; CHECK-P8-NEXT: li r5, 64
; CHECK-P8-NEXT: xxswapd vs2, vs7
; CHECK-P8-NEXT: xxswapd vs3, vs6 ; CHECK-P8-NEXT: xxswapd vs3, vs6
; CHECK-P8-NEXT: stxvd2x vs4, r3, r4 ; CHECK-P8-NEXT: stxvd2x vs4, r3, r4
; CHECK-P8-NEXT: li r4, 48 ; CHECK-P8-NEXT: li r4, 48
; CHECK-P8-NEXT: xxswapd vs2, vs7
; CHECK-P8-NEXT: stxvd2x vs1, r3, r5 ; CHECK-P8-NEXT: stxvd2x vs1, r3, r5
; CHECK-P8-NEXT: li r5, 32 ; CHECK-P8-NEXT: li r5, 32
; CHECK-P8-NEXT: stxvd2x vs5, r3, r4 ; CHECK-P8-NEXT: stxvd2x vs5, r3, r4
; CHECK-P8-NEXT: li r4, 16 ; CHECK-P8-NEXT: li r4, 16
; CHECK-P8-NEXT: stxvd2x vs0, r3, r5 ; CHECK-P8-NEXT: stxvd2x vs0, r3, r5
; CHECK-P8-NEXT: stxvd2x vs2, r3, r4 ; CHECK-P8-NEXT: stxvd2x vs2, r3, r4
; CHECK-P8-NEXT: stxvd2x vs3, 0, r3 ; CHECK-P8-NEXT: stxvd2x vs3, 0, r3
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
▲ Show 20 Lines • Show All 112 Lines • ▼ Show 20 Lines
define <2 x double> @test2elt_signed(i16 %a.coerce) local_unnamed_addr #0 { define <2 x double> @test2elt_signed(i16 %a.coerce) local_unnamed_addr #0 {
; CHECK-P8-LABEL: test2elt_signed: ; CHECK-P8-LABEL: test2elt_signed:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: addis r4, r2, .LCPI4_0@toc@ha ; CHECK-P8-NEXT: addis r4, r2, .LCPI4_0@toc@ha
; CHECK-P8-NEXT: mtvsrwz v3, r3 ; CHECK-P8-NEXT: mtvsrwz v3, r3
; CHECK-P8-NEXT: addis r3, r2, .LCPI4_1@toc@ha ; CHECK-P8-NEXT: addis r3, r2, .LCPI4_1@toc@ha
; CHECK-P8-NEXT: addi r4, r4, .LCPI4_0@toc@l ; CHECK-P8-NEXT: addi r4, r4, .LCPI4_0@toc@l
; CHECK-P8-NEXT: addi r3, r3, .LCPI4_1@toc@l ; CHECK-P8-NEXT: addi r3, r3, .LCPI4_1@toc@l
; CHECK-P8-NEXT: lvx v2, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r4
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: lxvd2x vs0, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: vperm v2, v3, v3, v2 ; CHECK-P8-NEXT: vperm v2, v3, v3, v2
; CHECK-P8-NEXT: xxswapd v3, vs0 ; CHECK-P8-NEXT: xxswapd v3, vs0
; CHECK-P8-NEXT: vsld v2, v2, v3 ; CHECK-P8-NEXT: vsld v2, v2, v3
; CHECK-P8-NEXT: vsrad v2, v2, v3 ; CHECK-P8-NEXT: vsrad v2, v2, v3
; CHECK-P8-NEXT: xvcvsxddp v2, v2 ; CHECK-P8-NEXT: xvcvsxddp v2, v2
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
Show All 28 Lines
; CHECK-P8-LABEL: test4elt_signed: ; CHECK-P8-LABEL: test4elt_signed:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: addis r5, r2, .LCPI5_0@toc@ha ; CHECK-P8-NEXT: addis r5, r2, .LCPI5_0@toc@ha
; CHECK-P8-NEXT: addis r6, r2, .LCPI5_2@toc@ha ; CHECK-P8-NEXT: addis r6, r2, .LCPI5_2@toc@ha
; CHECK-P8-NEXT: mtvsrwz v3, r4 ; CHECK-P8-NEXT: mtvsrwz v3, r4
; CHECK-P8-NEXT: addis r4, r2, .LCPI5_1@toc@ha ; CHECK-P8-NEXT: addis r4, r2, .LCPI5_1@toc@ha
; CHECK-P8-NEXT: addi r5, r5, .LCPI5_0@toc@l ; CHECK-P8-NEXT: addi r5, r5, .LCPI5_0@toc@l
; CHECK-P8-NEXT: addi r4, r4, .LCPI5_1@toc@l ; CHECK-P8-NEXT: addi r4, r4, .LCPI5_1@toc@l
; CHECK-P8-NEXT: lvx v2, 0, r5 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r5
; CHECK-P8-NEXT: addi r5, r6, .LCPI5_2@toc@l ; CHECK-P8-NEXT: addi r5, r6, .LCPI5_2@toc@l
; CHECK-P8-NEXT: lxvd2x vs1, 0, r5
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: lxvd2x vs0, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r4
; CHECK-P8-NEXT: li r4, 16 ; CHECK-P8-NEXT: li r4, 16
; CHECK-P8-NEXT: lvx v4, 0, r5 ; CHECK-P8-NEXT: xxswapd v4, vs1
; CHECK-P8-NEXT: vperm v2, v3, v3, v2 ; CHECK-P8-NEXT: vperm v2, v3, v3, v2
; CHECK-P8-NEXT: vperm v3, v3, v3, v4 ; CHECK-P8-NEXT: vperm v3, v3, v3, v4
; CHECK-P8-NEXT: xxswapd v4, vs0 ; CHECK-P8-NEXT: xxswapd v4, vs0
; CHECK-P8-NEXT: vsld v2, v2, v4 ; CHECK-P8-NEXT: vsld v2, v2, v4
; CHECK-P8-NEXT: vsld v3, v3, v4 ; CHECK-P8-NEXT: vsld v3, v3, v4
; CHECK-P8-NEXT: vsrad v2, v2, v4 ; CHECK-P8-NEXT: vsrad v2, v2, v4
; CHECK-P8-NEXT: vsrad v3, v3, v4 ; CHECK-P8-NEXT: vsrad v3, v3, v4
; CHECK-P8-NEXT: xvcvsxddp vs0, v2 ; CHECK-P8-NEXT: xvcvsxddp vs0, v2
▲ Show 20 Lines • Show All 49 Lines • ▼ Show 20 Lines
} }
define void @test8elt_signed(<8 x double>* noalias nocapture sret(<8 x double>) %agg.result, i64 %a.coerce) local_unnamed_addr #1 { define void @test8elt_signed(<8 x double>* noalias nocapture sret(<8 x double>) %agg.result, i64 %a.coerce) local_unnamed_addr #1 {
; CHECK-P8-LABEL: test8elt_signed: ; CHECK-P8-LABEL: test8elt_signed:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: addis r5, r2, .LCPI6_0@toc@ha ; CHECK-P8-NEXT: addis r5, r2, .LCPI6_0@toc@ha
; CHECK-P8-NEXT: addis r6, r2, .LCPI6_2@toc@ha ; CHECK-P8-NEXT: addis r6, r2, .LCPI6_2@toc@ha
; CHECK-P8-NEXT: mtvsrd v3, r4 ; CHECK-P8-NEXT: mtvsrd v3, r4
; CHECK-P8-NEXT: addis r4, r2, .LCPI6_1@toc@ha
; CHECK-P8-NEXT: addi r5, r5, .LCPI6_0@toc@l ; CHECK-P8-NEXT: addi r5, r5, .LCPI6_0@toc@l
; CHECK-P8-NEXT: addi r6, r6, .LCPI6_2@toc@l ; CHECK-P8-NEXT: addi r6, r6, .LCPI6_2@toc@l
; CHECK-P8-NEXT: addi r4, r4, .LCPI6_1@toc@l ; CHECK-P8-NEXT: lxvd2x vs0, 0, r5
; CHECK-P8-NEXT: lvx v2, 0, r5
; CHECK-P8-NEXT: addis r5, r2, .LCPI6_3@toc@ha ; CHECK-P8-NEXT: addis r5, r2, .LCPI6_3@toc@ha
; CHECK-P8-NEXT: lvx v4, 0, r6 ; CHECK-P8-NEXT: lxvd2x vs1, 0, r6
; CHECK-P8-NEXT: addis r6, r2, .LCPI6_4@toc@ha ; CHECK-P8-NEXT: addis r6, r2, .LCPI6_4@toc@ha
; CHECK-P8-NEXT: lxvd2x vs0, 0, r4
; CHECK-P8-NEXT: li r4, 48
; CHECK-P8-NEXT: addi r5, r5, .LCPI6_3@toc@l ; CHECK-P8-NEXT: addi r5, r5, .LCPI6_3@toc@l
; CHECK-P8-NEXT: lvx v5, 0, r5 ; CHECK-P8-NEXT: lxvd2x vs2, 0, r5
; CHECK-P8-NEXT: addi r5, r6, .LCPI6_4@toc@l ; CHECK-P8-NEXT: addi r5, r6, .LCPI6_4@toc@l
; CHECK-P8-NEXT: lvx v0, 0, r5 ; CHECK-P8-NEXT: lxvd2x vs3, 0, r5
; CHECK-P8-NEXT: vperm v2, v3, v3, v2 ; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: xxswapd v4, vs1
; CHECK-P8-NEXT: addis r5, r2, .LCPI6_1@toc@ha
; CHECK-P8-NEXT: addi r4, r5, .LCPI6_1@toc@l
; CHECK-P8-NEXT: li r5, 32 ; CHECK-P8-NEXT: li r5, 32
; CHECK-P8-NEXT: xxswapd v5, vs2
; CHECK-P8-NEXT: lxvd2x vs0, 0, r4
; CHECK-P8-NEXT: li r4, 48
; CHECK-P8-NEXT: xxswapd v0, vs3
; CHECK-P8-NEXT: vperm v2, v3, v3, v2
; CHECK-P8-NEXT: vperm v4, v3, v3, v4 ; CHECK-P8-NEXT: vperm v4, v3, v3, v4
; CHECK-P8-NEXT: vperm v5, v3, v3, v5 ; CHECK-P8-NEXT: vperm v5, v3, v3, v5
; CHECK-P8-NEXT: vperm v3, v3, v3, v0 ; CHECK-P8-NEXT: vperm v3, v3, v3, v0
; CHECK-P8-NEXT: xxswapd v0, vs0 ; CHECK-P8-NEXT: xxswapd v0, vs0
; CHECK-P8-NEXT: vsld v2, v2, v0 ; CHECK-P8-NEXT: vsld v2, v2, v0
; CHECK-P8-NEXT: vsld v4, v4, v0 ; CHECK-P8-NEXT: vsld v4, v4, v0
; CHECK-P8-NEXT: vsld v5, v5, v0 ; CHECK-P8-NEXT: vsld v5, v5, v0
; CHECK-P8-NEXT: vsld v3, v3, v0 ; CHECK-P8-NEXT: vsld v3, v3, v0
▲ Show 20 Lines • Show All 88 Lines • ▼ Show 20 Linesentry:
ret void ret void
} }
define void @test16elt_signed(<16 x double>* noalias nocapture sret(<16 x double>) %agg.result, <16 x i8> %a) local_unnamed_addr #2 { define void @test16elt_signed(<16 x double>* noalias nocapture sret(<16 x double>) %agg.result, <16 x i8> %a) local_unnamed_addr #2 {
; CHECK-P8-LABEL: test16elt_signed: ; CHECK-P8-LABEL: test16elt_signed:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: addis r4, r2, .LCPI7_0@toc@ha ; CHECK-P8-NEXT: addis r4, r2, .LCPI7_0@toc@ha
; CHECK-P8-NEXT: addis r5, r2, .LCPI7_2@toc@ha ; CHECK-P8-NEXT: addis r5, r2, .LCPI7_2@toc@ha
; CHECK-P8-NEXT: addis r6, r2, .LCPI7_3@toc@ha
; CHECK-P8-NEXT: addi r4, r4, .LCPI7_0@toc@l ; CHECK-P8-NEXT: addi r4, r4, .LCPI7_0@toc@l
; CHECK-P8-NEXT: addi r5, r5, .LCPI7_2@toc@l ; CHECK-P8-NEXT: addi r5, r5, .LCPI7_2@toc@l
; CHECK-P8-NEXT: addi r6, r6, .LCPI7_3@toc@l ; CHECK-P8-NEXT: lxvd2x vs0, 0, r4
; CHECK-P8-NEXT: lvx v3, 0, r4 ; CHECK-P8-NEXT: addis r4, r2, .LCPI7_3@toc@ha
; CHECK-P8-NEXT: addis r4, r2, .LCPI7_4@toc@ha ; CHECK-P8-NEXT: lxvd2x vs1, 0, r5
; CHECK-P8-NEXT: lvx v4, 0, r5 ; CHECK-P8-NEXT: addis r5, r2, .LCPI7_4@toc@ha
; CHECK-P8-NEXT: addis r5, r2, .LCPI7_5@toc@ha ; CHECK-P8-NEXT: addi r4, r4, .LCPI7_3@toc@l
; CHECK-P8-NEXT: lvx v5, 0, r6 ; CHECK-P8-NEXT: addi r5, r5, .LCPI7_4@toc@l
; CHECK-P8-NEXT: addis r6, r2, .LCPI7_1@toc@ha ; CHECK-P8-NEXT: lxvd2x vs2, 0, r4
; CHECK-P8-NEXT: addi r4, r4, .LCPI7_4@toc@l ; CHECK-P8-NEXT: addis r4, r2, .LCPI7_5@toc@ha
; CHECK-P8-NEXT: addi r5, r5, .LCPI7_5@toc@l ; CHECK-P8-NEXT: lxvd2x vs3, 0, r5
; CHECK-P8-NEXT: addi r6, r6, .LCPI7_1@toc@l ; CHECK-P8-NEXT: addis r5, r2, .LCPI7_6@toc@ha
; CHECK-P8-NEXT: lvx v0, 0, r4 ; CHECK-P8-NEXT: addi r4, r4, .LCPI7_5@toc@l
; CHECK-P8-NEXT: addis r4, r2, .LCPI7_6@toc@ha ; CHECK-P8-NEXT: addi r5, r5, .LCPI7_6@toc@l
; CHECK-P8-NEXT: lvx v1, 0, r5 ; CHECK-P8-NEXT: xxswapd v3, vs0
; CHECK-P8-NEXT: addis r5, r2, .LCPI7_7@toc@ha ; CHECK-P8-NEXT: xxswapd v4, vs1
; CHECK-P8-NEXT: lxvd2x vs0, 0, r6 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r4
; CHECK-P8-NEXT: addi r4, r4, .LCPI7_6@toc@l ; CHECK-P8-NEXT: addis r4, r2, .LCPI7_7@toc@ha
; CHECK-P8-NEXT: addi r5, r5, .LCPI7_7@toc@l ; CHECK-P8-NEXT: lxvd2x vs1, 0, r5
; CHECK-P8-NEXT: addis r5, r2, .LCPI7_8@toc@ha
; CHECK-P8-NEXT: addi r4, r4, .LCPI7_7@toc@l
; CHECK-P8-NEXT: addi r5, r5, .LCPI7_8@toc@l
; CHECK-P8-NEXT: xxswapd v5, vs2
; CHECK-P8-NEXT: xxswapd v0, vs3
; CHECK-P8-NEXT: lxvd2x vs2, 0, r4
; CHECK-P8-NEXT: lxvd2x vs3, 0, r5
; CHECK-P8-NEXT: addis r4, r2, .LCPI7_1@toc@ha
; CHECK-P8-NEXT: vperm v3, v2, v2, v3 ; CHECK-P8-NEXT: vperm v3, v2, v2, v3
; CHECK-P8-NEXT: lvx v6, 0, r4
; CHECK-P8-NEXT: addis r4, r2, .LCPI7_8@toc@ha
; CHECK-P8-NEXT: lvx v7, 0, r5
; CHECK-P8-NEXT: vperm v4, v2, v2, v4
; CHECK-P8-NEXT: li r5, 96 ; CHECK-P8-NEXT: li r5, 96
; CHECK-P8-NEXT: addi r4, r4, .LCPI7_8@toc@l ; CHECK-P8-NEXT: xxswapd v1, vs0
; CHECK-P8-NEXT: xxswapd v6, vs1
; CHECK-P8-NEXT: addi r4, r4, .LCPI7_1@toc@l
; CHECK-P8-NEXT: vperm v4, v2, v2, v4
; CHECK-P8-NEXT: lxvd2x vs0, 0, r4
; CHECK-P8-NEXT: li r4, 112
; CHECK-P8-NEXT: xxswapd v7, vs2
; CHECK-P8-NEXT: xxswapd v8, vs3
; CHECK-P8-NEXT: vperm v5, v2, v2, v5 ; CHECK-P8-NEXT: vperm v5, v2, v2, v5
; CHECK-P8-NEXT: xxswapd v9, vs0
; CHECK-P8-NEXT: lvx v8, 0, r4
; CHECK-P8-NEXT: vperm v0, v2, v2, v0 ; CHECK-P8-NEXT: vperm v0, v2, v2, v0
; CHECK-P8-NEXT: li r4, 112 ; CHECK-P8-NEXT: xxswapd v9, vs0
; CHECK-P8-NEXT: vperm v1, v2, v2, v1 ; CHECK-P8-NEXT: vperm v1, v2, v2, v1
; CHECK-P8-NEXT: vperm v6, v2, v2, v6 ; CHECK-P8-NEXT: vperm v6, v2, v2, v6
; CHECK-P8-NEXT: vperm v7, v2, v2, v7 ; CHECK-P8-NEXT: vperm v7, v2, v2, v7
; CHECK-P8-NEXT: vperm v2, v2, v2, v8 ; CHECK-P8-NEXT: vperm v2, v2, v2, v8
; CHECK-P8-NEXT: vsld v3, v3, v9 ; CHECK-P8-NEXT: vsld v3, v3, v9
; CHECK-P8-NEXT: vsld v0, v0, v9 ; CHECK-P8-NEXT: vsld v0, v0, v9
; CHECK-P8-NEXT: vsld v1, v1, v9 ; CHECK-P8-NEXT: vsld v1, v1, v9
; CHECK-P8-NEXT: vsld v6, v6, v9 ; CHECK-P8-NEXT: vsld v6, v6, v9
▲ Show 20 Lines • Show All 167 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/vec_conv_i_to_fp_4byte_elts.ll

Show First 20 Lines • Show All 58 Lines • ▼ Show 20 Linesentry:
%0 = uitofp <4 x i32> %a to <4 x float> %0 = uitofp <4 x i32> %a to <4 x float>
ret <4 x float> %0 ret <4 x float> %0
} }
define void @test8elt(<8 x float>* noalias nocapture sret(<8 x float>) %agg.result, <8 x i32>* nocapture readonly) local_unnamed_addr #2 { define void @test8elt(<8 x float>* noalias nocapture sret(<8 x float>) %agg.result, <8 x i32>* nocapture readonly) local_unnamed_addr #2 {
; CHECK-P8-LABEL: test8elt: ; CHECK-P8-LABEL: test8elt:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: li r5, 16 ; CHECK-P8-NEXT: li r5, 16
; CHECK-P8-NEXT: lvx v3, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs1, 0, r4
; CHECK-P8-NEXT: lvx v2, r4, r5 ; CHECK-P8-NEXT: lxvd2x vs0, r4, r5
; CHECK-P8-NEXT: xvcvuxwsp v3, v3 ; CHECK-P8-NEXT: xvcvuxwsp vs1, vs1
; CHECK-P8-NEXT: xvcvuxwsp v2, v2 ; CHECK-P8-NEXT: xvcvuxwsp vs0, vs0
; CHECK-P8-NEXT: stvx v3, 0, r3 ; CHECK-P8-NEXT: stxvd2x vs0, r3, r5
; CHECK-P8-NEXT: stvx v2, r3, r5 ; CHECK-P8-NEXT: stxvd2x vs1, 0, r3
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test8elt: ; CHECK-P9-LABEL: test8elt:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lxv vs0, 16(r4) ; CHECK-P9-NEXT: lxv vs0, 16(r4)
; CHECK-P9-NEXT: lxv vs1, 0(r4) ; CHECK-P9-NEXT: lxv vs1, 0(r4)
; CHECK-P9-NEXT: xvcvuxwsp vs1, vs1 ; CHECK-P9-NEXT: xvcvuxwsp vs1, vs1
; CHECK-P9-NEXT: xvcvuxwsp vs0, vs0 ; CHECK-P9-NEXT: xvcvuxwsp vs0, vs0
Show All 18 Lines
} }
define void @test16elt(<16 x float>* noalias nocapture sret(<16 x float>) %agg.result, <16 x i32>* nocapture readonly) local_unnamed_addr #2 { define void @test16elt(<16 x float>* noalias nocapture sret(<16 x float>) %agg.result, <16 x i32>* nocapture readonly) local_unnamed_addr #2 {
; CHECK-P8-LABEL: test16elt: ; CHECK-P8-LABEL: test16elt:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: li r5, 16 ; CHECK-P8-NEXT: li r5, 16
; CHECK-P8-NEXT: li r6, 32 ; CHECK-P8-NEXT: li r6, 32
; CHECK-P8-NEXT: li r7, 48 ; CHECK-P8-NEXT: li r7, 48
; CHECK-P8-NEXT: lvx v5, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs3, 0, r4
; CHECK-P8-NEXT: lvx v2, r4, r5 ; CHECK-P8-NEXT: lxvd2x vs0, r4, r5
; CHECK-P8-NEXT: lvx v3, r4, r6 ; CHECK-P8-NEXT: lxvd2x vs1, r4, r6
; CHECK-P8-NEXT: lvx v4, r4, r7 ; CHECK-P8-NEXT: lxvd2x vs2, r4, r7
; CHECK-P8-NEXT: xvcvuxwsp v5, v5 ; CHECK-P8-NEXT: xvcvuxwsp vs3, vs3
; CHECK-P8-NEXT: xvcvuxwsp v2, v2 ; CHECK-P8-NEXT: xvcvuxwsp vs0, vs0
; CHECK-P8-NEXT: xvcvuxwsp v3, v3 ; CHECK-P8-NEXT: xvcvuxwsp vs1, vs1
; CHECK-P8-NEXT: xvcvuxwsp v4, v4 ; CHECK-P8-NEXT: xvcvuxwsp vs2, vs2
; CHECK-P8-NEXT: stvx v5, 0, r3 ; CHECK-P8-NEXT: stxvd2x vs2, r3, r7
; CHECK-P8-NEXT: stvx v2, r3, r5 ; CHECK-P8-NEXT: stxvd2x vs1, r3, r6
; CHECK-P8-NEXT: stvx v3, r3, r6 ; CHECK-P8-NEXT: stxvd2x vs0, r3, r5
; CHECK-P8-NEXT: stvx v4, r3, r7 ; CHECK-P8-NEXT: stxvd2x vs3, 0, r3
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test16elt: ; CHECK-P9-LABEL: test16elt:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lxv vs0, 48(r4) ; CHECK-P9-NEXT: lxv vs0, 48(r4)
; CHECK-P9-NEXT: lxv vs1, 32(r4) ; CHECK-P9-NEXT: lxv vs1, 32(r4)
; CHECK-P9-NEXT: lxv vs2, 16(r4) ; CHECK-P9-NEXT: lxv vs2, 16(r4)
; CHECK-P9-NEXT: lxv vs3, 0(r4) ; CHECK-P9-NEXT: lxv vs3, 0(r4)
▲ Show 20 Lines • Show All 79 Lines • ▼ Show 20 Linesentry:
%0 = sitofp <4 x i32> %a to <4 x float> %0 = sitofp <4 x i32> %a to <4 x float>
ret <4 x float> %0 ret <4 x float> %0
} }
define void @test8elt_signed(<8 x float>* noalias nocapture sret(<8 x float>) %agg.result, <8 x i32>* nocapture readonly) local_unnamed_addr #2 { define void @test8elt_signed(<8 x float>* noalias nocapture sret(<8 x float>) %agg.result, <8 x i32>* nocapture readonly) local_unnamed_addr #2 {
; CHECK-P8-LABEL: test8elt_signed: ; CHECK-P8-LABEL: test8elt_signed:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: li r5, 16 ; CHECK-P8-NEXT: li r5, 16
; CHECK-P8-NEXT: lvx v3, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs1, 0, r4
; CHECK-P8-NEXT: lvx v2, r4, r5 ; CHECK-P8-NEXT: lxvd2x vs0, r4, r5
; CHECK-P8-NEXT: xvcvsxwsp v3, v3 ; CHECK-P8-NEXT: xvcvsxwsp vs1, vs1
; CHECK-P8-NEXT: xvcvsxwsp v2, v2 ; CHECK-P8-NEXT: xvcvsxwsp vs0, vs0
; CHECK-P8-NEXT: stvx v3, 0, r3 ; CHECK-P8-NEXT: stxvd2x vs0, r3, r5
; CHECK-P8-NEXT: stvx v2, r3, r5 ; CHECK-P8-NEXT: stxvd2x vs1, 0, r3
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test8elt_signed: ; CHECK-P9-LABEL: test8elt_signed:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lxv vs0, 16(r4) ; CHECK-P9-NEXT: lxv vs0, 16(r4)
; CHECK-P9-NEXT: lxv vs1, 0(r4) ; CHECK-P9-NEXT: lxv vs1, 0(r4)
; CHECK-P9-NEXT: xvcvsxwsp vs1, vs1 ; CHECK-P9-NEXT: xvcvsxwsp vs1, vs1
; CHECK-P9-NEXT: xvcvsxwsp vs0, vs0 ; CHECK-P9-NEXT: xvcvsxwsp vs0, vs0
Show All 18 Lines
} }
define void @test16elt_signed(<16 x float>* noalias nocapture sret(<16 x float>) %agg.result, <16 x i32>* nocapture readonly) local_unnamed_addr #2 { define void @test16elt_signed(<16 x float>* noalias nocapture sret(<16 x float>) %agg.result, <16 x i32>* nocapture readonly) local_unnamed_addr #2 {
; CHECK-P8-LABEL: test16elt_signed: ; CHECK-P8-LABEL: test16elt_signed:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: li r5, 16 ; CHECK-P8-NEXT: li r5, 16
; CHECK-P8-NEXT: li r6, 32 ; CHECK-P8-NEXT: li r6, 32
; CHECK-P8-NEXT: li r7, 48 ; CHECK-P8-NEXT: li r7, 48
; CHECK-P8-NEXT: lvx v5, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs3, 0, r4
; CHECK-P8-NEXT: lvx v2, r4, r5 ; CHECK-P8-NEXT: lxvd2x vs0, r4, r5
; CHECK-P8-NEXT: lvx v3, r4, r6 ; CHECK-P8-NEXT: lxvd2x vs1, r4, r6
; CHECK-P8-NEXT: lvx v4, r4, r7 ; CHECK-P8-NEXT: lxvd2x vs2, r4, r7
; CHECK-P8-NEXT: xvcvsxwsp v5, v5 ; CHECK-P8-NEXT: xvcvsxwsp vs3, vs3
; CHECK-P8-NEXT: xvcvsxwsp v2, v2 ; CHECK-P8-NEXT: xvcvsxwsp vs0, vs0
; CHECK-P8-NEXT: xvcvsxwsp v3, v3 ; CHECK-P8-NEXT: xvcvsxwsp vs1, vs1
; CHECK-P8-NEXT: xvcvsxwsp v4, v4 ; CHECK-P8-NEXT: xvcvsxwsp vs2, vs2
; CHECK-P8-NEXT: stvx v5, 0, r3 ; CHECK-P8-NEXT: stxvd2x vs2, r3, r7
; CHECK-P8-NEXT: stvx v2, r3, r5 ; CHECK-P8-NEXT: stxvd2x vs1, r3, r6
; CHECK-P8-NEXT: stvx v3, r3, r6 ; CHECK-P8-NEXT: stxvd2x vs0, r3, r5
; CHECK-P8-NEXT: stvx v4, r3, r7 ; CHECK-P8-NEXT: stxvd2x vs3, 0, r3
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test16elt_signed: ; CHECK-P9-LABEL: test16elt_signed:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lxv vs0, 48(r4) ; CHECK-P9-NEXT: lxv vs0, 48(r4)
; CHECK-P9-NEXT: lxv vs1, 32(r4) ; CHECK-P9-NEXT: lxv vs1, 32(r4)
; CHECK-P9-NEXT: lxv vs2, 16(r4) ; CHECK-P9-NEXT: lxv vs2, 16(r4)
; CHECK-P9-NEXT: lxv vs3, 0(r4) ; CHECK-P9-NEXT: lxv vs3, 0(r4)
Show All 31 Lines

llvm/test/CodeGen/PowerPC/vec_shuffle_p8vector_le.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mtriple=powerpc64le-unknown-linux-gnu -mattr=+power8-vector < %s | FileCheck %s ; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mtriple=powerpc64le-unknown-linux-gnu -mattr=+power8-vector < %s | FileCheck %s
define void @VPKUDUM_unary(<2 x i64>* %A) { define void @VPKUDUM_unary(<2 x i64>* %A) {
; CHECK-LABEL: VPKUDUM_unary: ; CHECK-LABEL: VPKUDUM_unary:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lvx 2, 0, 3 ; CHECK-NEXT: lxvd2x 0, 0, 3
; CHECK-NEXT: xxswapd 34, 0
; CHECK-NEXT: vpkudum 2, 2, 2 ; CHECK-NEXT: vpkudum 2, 2, 2
; CHECK-NEXT: stvx 2, 0, 3 ; CHECK-NEXT: xxswapd 0, 34
; CHECK-NEXT: stxvd2x 0, 0, 3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%tmp = load <2 x i64>, <2 x i64>* %A %tmp = load <2 x i64>, <2 x i64>* %A
%tmp2 = bitcast <2 x i64> %tmp to <4 x i32> %tmp2 = bitcast <2 x i64> %tmp to <4 x i32>
%tmp3 = extractelement <4 x i32> %tmp2, i32 0 %tmp3 = extractelement <4 x i32> %tmp2, i32 0
%tmp4 = extractelement <4 x i32> %tmp2, i32 2 %tmp4 = extractelement <4 x i32> %tmp2, i32 2
%tmp5 = insertelement <4 x i32> undef, i32 %tmp3, i32 0 %tmp5 = insertelement <4 x i32> undef, i32 %tmp3, i32 0
%tmp6 = insertelement <4 x i32> %tmp5, i32 %tmp4, i32 1 %tmp6 = insertelement <4 x i32> %tmp5, i32 %tmp4, i32 1
%tmp7 = insertelement <4 x i32> %tmp6, i32 %tmp3, i32 2 %tmp7 = insertelement <4 x i32> %tmp6, i32 %tmp3, i32 2
%tmp8 = insertelement <4 x i32> %tmp7, i32 %tmp4, i32 3 %tmp8 = insertelement <4 x i32> %tmp7, i32 %tmp4, i32 3
%tmp9 = bitcast <4 x i32> %tmp8 to <2 x i64> %tmp9 = bitcast <4 x i32> %tmp8 to <2 x i64>
store <2 x i64> %tmp9, <2 x i64>* %A store <2 x i64> %tmp9, <2 x i64>* %A
ret void ret void
} }
define void @VPKUDUM(<2 x i64>* %A, <2 x i64>* %B) { define void @VPKUDUM(<2 x i64>* %A, <2 x i64>* %B) {
; CHECK-LABEL: VPKUDUM: ; CHECK-LABEL: VPKUDUM:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lvx 2, 0, 3 ; CHECK-NEXT: lxvd2x 0, 0, 3
; CHECK-NEXT: lvx 3, 0, 4 ; CHECK-NEXT: lxvd2x 1, 0, 4
; CHECK-NEXT: xxswapd 34, 0
; CHECK-NEXT: xxswapd 35, 1
; CHECK-NEXT: vpkudum 2, 3, 2 ; CHECK-NEXT: vpkudum 2, 3, 2
; CHECK-NEXT: stvx 2, 0, 3 ; CHECK-NEXT: xxswapd 0, 34
; CHECK-NEXT: stxvd2x 0, 0, 3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%tmp = load <2 x i64>, <2 x i64>* %A %tmp = load <2 x i64>, <2 x i64>* %A
%tmp2 = bitcast <2 x i64> %tmp to <4 x i32> %tmp2 = bitcast <2 x i64> %tmp to <4 x i32>
%tmp3 = load <2 x i64>, <2 x i64>* %B %tmp3 = load <2 x i64>, <2 x i64>* %B
%tmp4 = bitcast <2 x i64> %tmp3 to <4 x i32> %tmp4 = bitcast <2 x i64> %tmp3 to <4 x i32>
%tmp5 = extractelement <4 x i32> %tmp2, i32 0 %tmp5 = extractelement <4 x i32> %tmp2, i32 0
%tmp6 = extractelement <4 x i32> %tmp2, i32 2 %tmp6 = extractelement <4 x i32> %tmp2, i32 2
Show All 11 Lines

llvm/test/CodeGen/PowerPC/vector-constrained-fp-intrinsics.ll

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 45 Lines • ▼ Show 20 Lines
; PC64LE-NEXT: xxswapd 0, 35 ; PC64LE-NEXT: xxswapd 0, 35
; PC64LE-NEXT: xxsldwi 1, 35, 35, 3 ; PC64LE-NEXT: xxsldwi 1, 35, 35, 3
; PC64LE-NEXT: addis 3, 2, .LCPI2_0@toc@ha ; PC64LE-NEXT: addis 3, 2, .LCPI2_0@toc@ha
; PC64LE-NEXT: xxsldwi 2, 34, 34, 3 ; PC64LE-NEXT: xxsldwi 2, 34, 34, 3
; PC64LE-NEXT: xxswapd 3, 34 ; PC64LE-NEXT: xxswapd 3, 34
; PC64LE-NEXT: addi 3, 3, .LCPI2_0@toc@l ; PC64LE-NEXT: addi 3, 3, .LCPI2_0@toc@l
; PC64LE-NEXT: xxsldwi 4, 35, 35, 1 ; PC64LE-NEXT: xxsldwi 4, 35, 35, 1
; PC64LE-NEXT: xxsldwi 5, 34, 34, 1 ; PC64LE-NEXT: xxsldwi 5, 34, 34, 1
; PC64LE-NEXT: lvx 4, 0, 3
; PC64LE-NEXT: xscvspdpn 0, 0 ; PC64LE-NEXT: xscvspdpn 0, 0
; PC64LE-NEXT: xscvspdpn 1, 1 ; PC64LE-NEXT: xscvspdpn 1, 1
; PC64LE-NEXT: xscvspdpn 2, 2 ; PC64LE-NEXT: xscvspdpn 2, 2
; PC64LE-NEXT: xscvspdpn 3, 3 ; PC64LE-NEXT: xscvspdpn 3, 3
; PC64LE-NEXT: xscvspdpn 4, 4 ; PC64LE-NEXT: xscvspdpn 4, 4
; PC64LE-NEXT: xscvspdpn 5, 5 ; PC64LE-NEXT: xscvspdpn 5, 5
; PC64LE-NEXT: xsdivsp 1, 2, 1 ; PC64LE-NEXT: xsdivsp 1, 2, 1
; PC64LE-NEXT: xsdivsp 0, 3, 0 ; PC64LE-NEXT: xsdivsp 0, 3, 0
; PC64LE-NEXT: xsdivsp 2, 5, 4 ; PC64LE-NEXT: xsdivsp 2, 5, 4
; PC64LE-NEXT: xscvdpspn 1, 1 ; PC64LE-NEXT: xscvdpspn 1, 1
; PC64LE-NEXT: xscvdpspn 0, 0 ; PC64LE-NEXT: xscvdpspn 0, 0
; PC64LE-NEXT: xscvdpspn 34, 2 ; PC64LE-NEXT: xscvdpspn 34, 2
; PC64LE-NEXT: lxvd2x 2, 0, 3
; PC64LE-NEXT: xxswapd 36, 2
; PC64LE-NEXT: xxmrghw 35, 0, 1 ; PC64LE-NEXT: xxmrghw 35, 0, 1
; PC64LE-NEXT: vperm 2, 2, 3, 4 ; PC64LE-NEXT: vperm 2, 2, 3, 4
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_fdiv_v3f32: ; PC64LE9-LABEL: constrained_vector_fdiv_v3f32:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: xxsldwi 0, 35, 35, 1 ; PC64LE9-NEXT: xxsldwi 0, 35, 35, 1
; PC64LE9-NEXT: xxsldwi 1, 34, 34, 1 ; PC64LE9-NEXT: xxsldwi 1, 34, 34, 1
▲ Show 20 Lines • Show All 233 Lines • ▼ Show 20 Lines
; PC64LE-NEXT: bl fmodf ; PC64LE-NEXT: bl fmodf
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: xscvdpspn 0, 30 ; PC64LE-NEXT: xscvdpspn 0, 30
; PC64LE-NEXT: addis 3, 2, .LCPI7_0@toc@ha ; PC64LE-NEXT: addis 3, 2, .LCPI7_0@toc@ha
; PC64LE-NEXT: lfd 30, 80(1) # 8-byte Folded Reload ; PC64LE-NEXT: lfd 30, 80(1) # 8-byte Folded Reload
; PC64LE-NEXT: xscvdpspn 1, 1 ; PC64LE-NEXT: xscvdpspn 1, 1
; PC64LE-NEXT: addi 3, 3, .LCPI7_0@toc@l ; PC64LE-NEXT: addi 3, 3, .LCPI7_0@toc@l
; PC64LE-NEXT: xscvdpspn 34, 31 ; PC64LE-NEXT: xscvdpspn 34, 31
; PC64LE-NEXT: lvx 4, 0, 3 ; PC64LE-NEXT: lxvd2x 2, 0, 3
; PC64LE-NEXT: li 3, 64 ; PC64LE-NEXT: li 3, 64
; PC64LE-NEXT: lfd 31, 88(1) # 8-byte Folded Reload ; PC64LE-NEXT: lfd 31, 88(1) # 8-byte Folded Reload
; PC64LE-NEXT: lxvd2x 63, 1, 3 # 16-byte Folded Reload ; PC64LE-NEXT: lxvd2x 63, 1, 3 # 16-byte Folded Reload
; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: li 3, 48
; PC64LE-NEXT: lxvd2x 62, 1, 3 # 16-byte Folded Reload ; PC64LE-NEXT: lxvd2x 62, 1, 3 # 16-byte Folded Reload
; PC64LE-NEXT: xxswapd 36, 2
; PC64LE-NEXT: xxmrghw 35, 0, 1 ; PC64LE-NEXT: xxmrghw 35, 0, 1
; PC64LE-NEXT: vperm 2, 2, 3, 4 ; PC64LE-NEXT: vperm 2, 2, 3, 4
; PC64LE-NEXT: addi 1, 1, 96 ; PC64LE-NEXT: addi 1, 1, 96
; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: ld 0, 16(1)
; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: mtlr 0
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_frem_v3f32: ; PC64LE9-LABEL: constrained_vector_frem_v3f32:
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; PC64LE-NEXT: xxswapd 0, 35 ; PC64LE-NEXT: xxswapd 0, 35
; PC64LE-NEXT: xxsldwi 1, 35, 35, 3 ; PC64LE-NEXT: xxsldwi 1, 35, 35, 3
; PC64LE-NEXT: addis 3, 2, .LCPI12_0@toc@ha ; PC64LE-NEXT: addis 3, 2, .LCPI12_0@toc@ha
; PC64LE-NEXT: xxsldwi 2, 34, 34, 3 ; PC64LE-NEXT: xxsldwi 2, 34, 34, 3
; PC64LE-NEXT: xxswapd 3, 34 ; PC64LE-NEXT: xxswapd 3, 34
; PC64LE-NEXT: addi 3, 3, .LCPI12_0@toc@l ; PC64LE-NEXT: addi 3, 3, .LCPI12_0@toc@l
; PC64LE-NEXT: xxsldwi 4, 35, 35, 1 ; PC64LE-NEXT: xxsldwi 4, 35, 35, 1
; PC64LE-NEXT: xxsldwi 5, 34, 34, 1 ; PC64LE-NEXT: xxsldwi 5, 34, 34, 1
; PC64LE-NEXT: lvx 4, 0, 3
; PC64LE-NEXT: xscvspdpn 0, 0 ; PC64LE-NEXT: xscvspdpn 0, 0
; PC64LE-NEXT: xscvspdpn 1, 1 ; PC64LE-NEXT: xscvspdpn 1, 1
; PC64LE-NEXT: xscvspdpn 2, 2 ; PC64LE-NEXT: xscvspdpn 2, 2
; PC64LE-NEXT: xscvspdpn 3, 3 ; PC64LE-NEXT: xscvspdpn 3, 3
; PC64LE-NEXT: xscvspdpn 4, 4 ; PC64LE-NEXT: xscvspdpn 4, 4
; PC64LE-NEXT: xscvspdpn 5, 5 ; PC64LE-NEXT: xscvspdpn 5, 5
; PC64LE-NEXT: xsmulsp 1, 2, 1 ; PC64LE-NEXT: xsmulsp 1, 2, 1
; PC64LE-NEXT: xsmulsp 0, 3, 0 ; PC64LE-NEXT: xsmulsp 0, 3, 0
; PC64LE-NEXT: xsmulsp 2, 5, 4 ; PC64LE-NEXT: xsmulsp 2, 5, 4
; PC64LE-NEXT: xscvdpspn 1, 1 ; PC64LE-NEXT: xscvdpspn 1, 1
; PC64LE-NEXT: xscvdpspn 0, 0 ; PC64LE-NEXT: xscvdpspn 0, 0
; PC64LE-NEXT: xscvdpspn 34, 2 ; PC64LE-NEXT: xscvdpspn 34, 2
; PC64LE-NEXT: lxvd2x 2, 0, 3
; PC64LE-NEXT: xxswapd 36, 2
; PC64LE-NEXT: xxmrghw 35, 0, 1 ; PC64LE-NEXT: xxmrghw 35, 0, 1
; PC64LE-NEXT: vperm 2, 2, 3, 4 ; PC64LE-NEXT: vperm 2, 2, 3, 4
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_fmul_v3f32: ; PC64LE9-LABEL: constrained_vector_fmul_v3f32:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: xxsldwi 0, 35, 35, 1 ; PC64LE9-NEXT: xxsldwi 0, 35, 35, 1
; PC64LE9-NEXT: xxsldwi 1, 34, 34, 1 ; PC64LE9-NEXT: xxsldwi 1, 34, 34, 1
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; PC64LE-NEXT: xxswapd 0, 35 ; PC64LE-NEXT: xxswapd 0, 35
; PC64LE-NEXT: xxsldwi 1, 35, 35, 3 ; PC64LE-NEXT: xxsldwi 1, 35, 35, 3
; PC64LE-NEXT: addis 3, 2, .LCPI17_0@toc@ha ; PC64LE-NEXT: addis 3, 2, .LCPI17_0@toc@ha
; PC64LE-NEXT: xxsldwi 2, 34, 34, 3 ; PC64LE-NEXT: xxsldwi 2, 34, 34, 3
; PC64LE-NEXT: xxswapd 3, 34 ; PC64LE-NEXT: xxswapd 3, 34
; PC64LE-NEXT: addi 3, 3, .LCPI17_0@toc@l ; PC64LE-NEXT: addi 3, 3, .LCPI17_0@toc@l
; PC64LE-NEXT: xxsldwi 4, 35, 35, 1 ; PC64LE-NEXT: xxsldwi 4, 35, 35, 1
; PC64LE-NEXT: xxsldwi 5, 34, 34, 1 ; PC64LE-NEXT: xxsldwi 5, 34, 34, 1
; PC64LE-NEXT: lvx 4, 0, 3
; PC64LE-NEXT: xscvspdpn 0, 0 ; PC64LE-NEXT: xscvspdpn 0, 0
; PC64LE-NEXT: xscvspdpn 1, 1 ; PC64LE-NEXT: xscvspdpn 1, 1
; PC64LE-NEXT: xscvspdpn 2, 2 ; PC64LE-NEXT: xscvspdpn 2, 2
; PC64LE-NEXT: xscvspdpn 3, 3 ; PC64LE-NEXT: xscvspdpn 3, 3
; PC64LE-NEXT: xscvspdpn 4, 4 ; PC64LE-NEXT: xscvspdpn 4, 4
; PC64LE-NEXT: xscvspdpn 5, 5 ; PC64LE-NEXT: xscvspdpn 5, 5
; PC64LE-NEXT: xsaddsp 1, 2, 1 ; PC64LE-NEXT: xsaddsp 1, 2, 1
; PC64LE-NEXT: xsaddsp 0, 3, 0 ; PC64LE-NEXT: xsaddsp 0, 3, 0
; PC64LE-NEXT: xsaddsp 2, 5, 4 ; PC64LE-NEXT: xsaddsp 2, 5, 4
; PC64LE-NEXT: xscvdpspn 1, 1 ; PC64LE-NEXT: xscvdpspn 1, 1
; PC64LE-NEXT: xscvdpspn 0, 0 ; PC64LE-NEXT: xscvdpspn 0, 0
; PC64LE-NEXT: xscvdpspn 34, 2 ; PC64LE-NEXT: xscvdpspn 34, 2
; PC64LE-NEXT: lxvd2x 2, 0, 3
; PC64LE-NEXT: xxswapd 36, 2
; PC64LE-NEXT: xxmrghw 35, 0, 1 ; PC64LE-NEXT: xxmrghw 35, 0, 1
; PC64LE-NEXT: vperm 2, 2, 3, 4 ; PC64LE-NEXT: vperm 2, 2, 3, 4
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_fadd_v3f32: ; PC64LE9-LABEL: constrained_vector_fadd_v3f32:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: xxsldwi 0, 35, 35, 1 ; PC64LE9-NEXT: xxsldwi 0, 35, 35, 1
; PC64LE9-NEXT: xxsldwi 1, 34, 34, 1 ; PC64LE9-NEXT: xxsldwi 1, 34, 34, 1
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; PC64LE-NEXT: xxswapd 0, 35 ; PC64LE-NEXT: xxswapd 0, 35
; PC64LE-NEXT: xxsldwi 1, 35, 35, 3 ; PC64LE-NEXT: xxsldwi 1, 35, 35, 3
; PC64LE-NEXT: addis 3, 2, .LCPI22_0@toc@ha ; PC64LE-NEXT: addis 3, 2, .LCPI22_0@toc@ha
; PC64LE-NEXT: xxsldwi 2, 34, 34, 3 ; PC64LE-NEXT: xxsldwi 2, 34, 34, 3
; PC64LE-NEXT: xxswapd 3, 34 ; PC64LE-NEXT: xxswapd 3, 34
; PC64LE-NEXT: addi 3, 3, .LCPI22_0@toc@l ; PC64LE-NEXT: addi 3, 3, .LCPI22_0@toc@l
; PC64LE-NEXT: xxsldwi 4, 35, 35, 1 ; PC64LE-NEXT: xxsldwi 4, 35, 35, 1
; PC64LE-NEXT: xxsldwi 5, 34, 34, 1 ; PC64LE-NEXT: xxsldwi 5, 34, 34, 1
; PC64LE-NEXT: lvx 4, 0, 3
; PC64LE-NEXT: xscvspdpn 0, 0 ; PC64LE-NEXT: xscvspdpn 0, 0
; PC64LE-NEXT: xscvspdpn 1, 1 ; PC64LE-NEXT: xscvspdpn 1, 1
; PC64LE-NEXT: xscvspdpn 2, 2 ; PC64LE-NEXT: xscvspdpn 2, 2
; PC64LE-NEXT: xscvspdpn 3, 3 ; PC64LE-NEXT: xscvspdpn 3, 3
; PC64LE-NEXT: xscvspdpn 4, 4 ; PC64LE-NEXT: xscvspdpn 4, 4
; PC64LE-NEXT: xscvspdpn 5, 5 ; PC64LE-NEXT: xscvspdpn 5, 5
; PC64LE-NEXT: xssubsp 1, 2, 1 ; PC64LE-NEXT: xssubsp 1, 2, 1
; PC64LE-NEXT: xssubsp 0, 3, 0 ; PC64LE-NEXT: xssubsp 0, 3, 0
; PC64LE-NEXT: xssubsp 2, 5, 4 ; PC64LE-NEXT: xssubsp 2, 5, 4
; PC64LE-NEXT: xscvdpspn 1, 1 ; PC64LE-NEXT: xscvdpspn 1, 1
; PC64LE-NEXT: xscvdpspn 0, 0 ; PC64LE-NEXT: xscvdpspn 0, 0
; PC64LE-NEXT: xscvdpspn 34, 2 ; PC64LE-NEXT: xscvdpspn 34, 2
; PC64LE-NEXT: lxvd2x 2, 0, 3
; PC64LE-NEXT: xxswapd 36, 2
; PC64LE-NEXT: xxmrghw 35, 0, 1 ; PC64LE-NEXT: xxmrghw 35, 0, 1
; PC64LE-NEXT: vperm 2, 2, 3, 4 ; PC64LE-NEXT: vperm 2, 2, 3, 4
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_fsub_v3f32: ; PC64LE9-LABEL: constrained_vector_fsub_v3f32:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: xxsldwi 0, 35, 35, 1 ; PC64LE9-NEXT: xxsldwi 0, 35, 35, 1
; PC64LE9-NEXT: xxsldwi 1, 34, 34, 1 ; PC64LE9-NEXT: xxsldwi 1, 34, 34, 1
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define <3 x float> @constrained_vector_sqrt_v3f32(<3 x float> %x) #0 { define <3 x float> @constrained_vector_sqrt_v3f32(<3 x float> %x) #0 {
; PC64LE-LABEL: constrained_vector_sqrt_v3f32: ; PC64LE-LABEL: constrained_vector_sqrt_v3f32:
; PC64LE: # %bb.0: # %entry ; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: xxsldwi 0, 34, 34, 3 ; PC64LE-NEXT: xxsldwi 0, 34, 34, 3
; PC64LE-NEXT: xxswapd 1, 34 ; PC64LE-NEXT: xxswapd 1, 34
; PC64LE-NEXT: addis 3, 2, .LCPI27_0@toc@ha ; PC64LE-NEXT: addis 3, 2, .LCPI27_0@toc@ha
; PC64LE-NEXT: xxsldwi 2, 34, 34, 1 ; PC64LE-NEXT: xxsldwi 2, 34, 34, 1
; PC64LE-NEXT: addi 3, 3, .LCPI27_0@toc@l ; PC64LE-NEXT: addi 3, 3, .LCPI27_0@toc@l
; PC64LE-NEXT: lvx 4, 0, 3 ; PC64LE-NEXT: lxvd2x 3, 0, 3
; PC64LE-NEXT: xscvspdpn 0, 0 ; PC64LE-NEXT: xscvspdpn 0, 0
; PC64LE-NEXT: xscvspdpn 1, 1 ; PC64LE-NEXT: xscvspdpn 1, 1
; PC64LE-NEXT: xscvspdpn 2, 2 ; PC64LE-NEXT: xscvspdpn 2, 2
; PC64LE-NEXT: xxswapd 36, 3
; PC64LE-NEXT: xssqrtsp 0, 0 ; PC64LE-NEXT: xssqrtsp 0, 0
; PC64LE-NEXT: xssqrtsp 1, 1 ; PC64LE-NEXT: xssqrtsp 1, 1
; PC64LE-NEXT: xssqrtsp 2, 2 ; PC64LE-NEXT: xssqrtsp 2, 2
; PC64LE-NEXT: xscvdpspn 0, 0 ; PC64LE-NEXT: xscvdpspn 0, 0
; PC64LE-NEXT: xscvdpspn 1, 1 ; PC64LE-NEXT: xscvdpspn 1, 1
; PC64LE-NEXT: xscvdpspn 34, 2 ; PC64LE-NEXT: xscvdpspn 34, 2
; PC64LE-NEXT: xxmrghw 35, 1, 0 ; PC64LE-NEXT: xxmrghw 35, 1, 0
; PC64LE-NEXT: vperm 2, 2, 3, 4 ; PC64LE-NEXT: vperm 2, 2, 3, 4
▲ Show 20 Lines • Show All 224 Lines • ▼ Show 20 Lines
; PC64LE-NEXT: bl powf ; PC64LE-NEXT: bl powf
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: xscvdpspn 0, 30 ; PC64LE-NEXT: xscvdpspn 0, 30
; PC64LE-NEXT: addis 3, 2, .LCPI32_0@toc@ha ; PC64LE-NEXT: addis 3, 2, .LCPI32_0@toc@ha
; PC64LE-NEXT: lfd 30, 80(1) # 8-byte Folded Reload ; PC64LE-NEXT: lfd 30, 80(1) # 8-byte Folded Reload
; PC64LE-NEXT: xscvdpspn 1, 1 ; PC64LE-NEXT: xscvdpspn 1, 1
; PC64LE-NEXT: addi 3, 3, .LCPI32_0@toc@l ; PC64LE-NEXT: addi 3, 3, .LCPI32_0@toc@l
; PC64LE-NEXT: xscvdpspn 34, 31 ; PC64LE-NEXT: xscvdpspn 34, 31
; PC64LE-NEXT: lvx 4, 0, 3 ; PC64LE-NEXT: lxvd2x 2, 0, 3
; PC64LE-NEXT: li 3, 64 ; PC64LE-NEXT: li 3, 64
; PC64LE-NEXT: lfd 31, 88(1) # 8-byte Folded Reload ; PC64LE-NEXT: lfd 31, 88(1) # 8-byte Folded Reload
; PC64LE-NEXT: lxvd2x 63, 1, 3 # 16-byte Folded Reload ; PC64LE-NEXT: lxvd2x 63, 1, 3 # 16-byte Folded Reload
; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: li 3, 48
; PC64LE-NEXT: lxvd2x 62, 1, 3 # 16-byte Folded Reload ; PC64LE-NEXT: lxvd2x 62, 1, 3 # 16-byte Folded Reload
; PC64LE-NEXT: xxswapd 36, 2
; PC64LE-NEXT: xxmrghw 35, 0, 1 ; PC64LE-NEXT: xxmrghw 35, 0, 1
; PC64LE-NEXT: vperm 2, 2, 3, 4 ; PC64LE-NEXT: vperm 2, 2, 3, 4
; PC64LE-NEXT: addi 1, 1, 96 ; PC64LE-NEXT: addi 1, 1, 96
; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: ld 0, 16(1)
; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: mtlr 0
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_pow_v3f32: ; PC64LE9-LABEL: constrained_vector_pow_v3f32:
▲ Show 20 Lines • Show All 410 Lines • ▼ Show 20 Lines
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: xscvdpspn 0, 30 ; PC64LE-NEXT: xscvdpspn 0, 30
; PC64LE-NEXT: addis 3, 2, .LCPI37_0@toc@ha ; PC64LE-NEXT: addis 3, 2, .LCPI37_0@toc@ha
; PC64LE-NEXT: lfd 30, 80(1) # 8-byte Folded Reload ; PC64LE-NEXT: lfd 30, 80(1) # 8-byte Folded Reload
; PC64LE-NEXT: ld 30, 64(1) # 8-byte Folded Reload ; PC64LE-NEXT: ld 30, 64(1) # 8-byte Folded Reload
; PC64LE-NEXT: xscvdpspn 1, 1 ; PC64LE-NEXT: xscvdpspn 1, 1
; PC64LE-NEXT: addi 3, 3, .LCPI37_0@toc@l ; PC64LE-NEXT: addi 3, 3, .LCPI37_0@toc@l
; PC64LE-NEXT: xscvdpspn 34, 31 ; PC64LE-NEXT: xscvdpspn 34, 31
; PC64LE-NEXT: lvx 4, 0, 3 ; PC64LE-NEXT: lxvd2x 2, 0, 3
; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: li 3, 48
; PC64LE-NEXT: lfd 31, 88(1) # 8-byte Folded Reload ; PC64LE-NEXT: lfd 31, 88(1) # 8-byte Folded Reload
; PC64LE-NEXT: lxvd2x 63, 1, 3 # 16-byte Folded Reload ; PC64LE-NEXT: lxvd2x 63, 1, 3 # 16-byte Folded Reload
; PC64LE-NEXT: xxswapd 36, 2
; PC64LE-NEXT: xxmrghw 35, 0, 1 ; PC64LE-NEXT: xxmrghw 35, 0, 1
; PC64LE-NEXT: vperm 2, 2, 3, 4 ; PC64LE-NEXT: vperm 2, 2, 3, 4
; PC64LE-NEXT: addi 1, 1, 96 ; PC64LE-NEXT: addi 1, 1, 96
; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: ld 0, 16(1)
; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: mtlr 0
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_powi_v3f32: ; PC64LE9-LABEL: constrained_vector_powi_v3f32:
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; PC64LE-NEXT: xscvspdpn 1, 0 ; PC64LE-NEXT: xscvspdpn 1, 0
; PC64LE-NEXT: bl sinf ; PC64LE-NEXT: bl sinf
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: xscvdpspn 0, 30 ; PC64LE-NEXT: xscvdpspn 0, 30
; PC64LE-NEXT: addis 3, 2, .LCPI42_0@toc@ha ; PC64LE-NEXT: addis 3, 2, .LCPI42_0@toc@ha
; PC64LE-NEXT: lfd 30, 64(1) # 8-byte Folded Reload ; PC64LE-NEXT: lfd 30, 64(1) # 8-byte Folded Reload
; PC64LE-NEXT: xscvdpspn 1, 1 ; PC64LE-NEXT: xscvdpspn 1, 1
; PC64LE-NEXT: addi 3, 3, .LCPI42_0@toc@l ; PC64LE-NEXT: addi 3, 3, .LCPI42_0@toc@l
; PC64LE-NEXT: lxvd2x 2, 0, 3
; PC64LE-NEXT: xscvdpspn 34, 31 ; PC64LE-NEXT: xscvdpspn 34, 31
; PC64LE-NEXT: lvx 4, 0, 3
; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: li 3, 48
; PC64LE-NEXT: lfd 31, 72(1) # 8-byte Folded Reload ; PC64LE-NEXT: lfd 31, 72(1) # 8-byte Folded Reload
; PC64LE-NEXT: lxvd2x 63, 1, 3 # 16-byte Folded Reload ; PC64LE-NEXT: lxvd2x 63, 1, 3 # 16-byte Folded Reload
; PC64LE-NEXT: xxswapd 36, 2
; PC64LE-NEXT: xxmrghw 35, 0, 1 ; PC64LE-NEXT: xxmrghw 35, 0, 1
; PC64LE-NEXT: vperm 2, 2, 3, 4 ; PC64LE-NEXT: vperm 2, 2, 3, 4
; PC64LE-NEXT: addi 1, 1, 80 ; PC64LE-NEXT: addi 1, 1, 80
; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: ld 0, 16(1)
; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: mtlr 0
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_sin_v3f32: ; PC64LE9-LABEL: constrained_vector_sin_v3f32:
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; PC64LE-NEXT: xscvspdpn 1, 0 ; PC64LE-NEXT: xscvspdpn 1, 0
; PC64LE-NEXT: bl cosf ; PC64LE-NEXT: bl cosf
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: xscvdpspn 0, 30 ; PC64LE-NEXT: xscvdpspn 0, 30
; PC64LE-NEXT: addis 3, 2, .LCPI47_0@toc@ha ; PC64LE-NEXT: addis 3, 2, .LCPI47_0@toc@ha
; PC64LE-NEXT: lfd 30, 64(1) # 8-byte Folded Reload ; PC64LE-NEXT: lfd 30, 64(1) # 8-byte Folded Reload
; PC64LE-NEXT: xscvdpspn 1, 1 ; PC64LE-NEXT: xscvdpspn 1, 1
; PC64LE-NEXT: addi 3, 3, .LCPI47_0@toc@l ; PC64LE-NEXT: addi 3, 3, .LCPI47_0@toc@l
; PC64LE-NEXT: lxvd2x 2, 0, 3
; PC64LE-NEXT: xscvdpspn 34, 31 ; PC64LE-NEXT: xscvdpspn 34, 31
; PC64LE-NEXT: lvx 4, 0, 3
; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: li 3, 48
; PC64LE-NEXT: lfd 31, 72(1) # 8-byte Folded Reload ; PC64LE-NEXT: lfd 31, 72(1) # 8-byte Folded Reload
; PC64LE-NEXT: lxvd2x 63, 1, 3 # 16-byte Folded Reload ; PC64LE-NEXT: lxvd2x 63, 1, 3 # 16-byte Folded Reload
; PC64LE-NEXT: xxswapd 36, 2
; PC64LE-NEXT: xxmrghw 35, 0, 1 ; PC64LE-NEXT: xxmrghw 35, 0, 1
; PC64LE-NEXT: vperm 2, 2, 3, 4 ; PC64LE-NEXT: vperm 2, 2, 3, 4
; PC64LE-NEXT: addi 1, 1, 80 ; PC64LE-NEXT: addi 1, 1, 80
; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: ld 0, 16(1)
; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: mtlr 0
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_cos_v3f32: ; PC64LE9-LABEL: constrained_vector_cos_v3f32:
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; PC64LE-NEXT: xscvspdpn 1, 0 ; PC64LE-NEXT: xscvspdpn 1, 0
; PC64LE-NEXT: bl expf ; PC64LE-NEXT: bl expf
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: xscvdpspn 0, 30 ; PC64LE-NEXT: xscvdpspn 0, 30
; PC64LE-NEXT: addis 3, 2, .LCPI52_0@toc@ha ; PC64LE-NEXT: addis 3, 2, .LCPI52_0@toc@ha
; PC64LE-NEXT: lfd 30, 64(1) # 8-byte Folded Reload ; PC64LE-NEXT: lfd 30, 64(1) # 8-byte Folded Reload
; PC64LE-NEXT: xscvdpspn 1, 1 ; PC64LE-NEXT: xscvdpspn 1, 1
; PC64LE-NEXT: addi 3, 3, .LCPI52_0@toc@l ; PC64LE-NEXT: addi 3, 3, .LCPI52_0@toc@l
; PC64LE-NEXT: lxvd2x 2, 0, 3
; PC64LE-NEXT: xscvdpspn 34, 31 ; PC64LE-NEXT: xscvdpspn 34, 31
; PC64LE-NEXT: lvx 4, 0, 3
; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: li 3, 48
; PC64LE-NEXT: lfd 31, 72(1) # 8-byte Folded Reload ; PC64LE-NEXT: lfd 31, 72(1) # 8-byte Folded Reload
; PC64LE-NEXT: lxvd2x 63, 1, 3 # 16-byte Folded Reload ; PC64LE-NEXT: lxvd2x 63, 1, 3 # 16-byte Folded Reload
; PC64LE-NEXT: xxswapd 36, 2
; PC64LE-NEXT: xxmrghw 35, 0, 1 ; PC64LE-NEXT: xxmrghw 35, 0, 1
; PC64LE-NEXT: vperm 2, 2, 3, 4 ; PC64LE-NEXT: vperm 2, 2, 3, 4
; PC64LE-NEXT: addi 1, 1, 80 ; PC64LE-NEXT: addi 1, 1, 80
; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: ld 0, 16(1)
; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: mtlr 0
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_exp_v3f32: ; PC64LE9-LABEL: constrained_vector_exp_v3f32:
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; PC64LE-NEXT: xscvspdpn 1, 0 ; PC64LE-NEXT: xscvspdpn 1, 0
; PC64LE-NEXT: bl exp2f ; PC64LE-NEXT: bl exp2f
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: xscvdpspn 0, 30 ; PC64LE-NEXT: xscvdpspn 0, 30
; PC64LE-NEXT: addis 3, 2, .LCPI57_0@toc@ha ; PC64LE-NEXT: addis 3, 2, .LCPI57_0@toc@ha
; PC64LE-NEXT: lfd 30, 64(1) # 8-byte Folded Reload ; PC64LE-NEXT: lfd 30, 64(1) # 8-byte Folded Reload
; PC64LE-NEXT: xscvdpspn 1, 1 ; PC64LE-NEXT: xscvdpspn 1, 1
; PC64LE-NEXT: addi 3, 3, .LCPI57_0@toc@l ; PC64LE-NEXT: addi 3, 3, .LCPI57_0@toc@l
; PC64LE-NEXT: lxvd2x 2, 0, 3
; PC64LE-NEXT: xscvdpspn 34, 31 ; PC64LE-NEXT: xscvdpspn 34, 31
; PC64LE-NEXT: lvx 4, 0, 3
; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: li 3, 48
; PC64LE-NEXT: lfd 31, 72(1) # 8-byte Folded Reload ; PC64LE-NEXT: lfd 31, 72(1) # 8-byte Folded Reload
; PC64LE-NEXT: lxvd2x 63, 1, 3 # 16-byte Folded Reload ; PC64LE-NEXT: lxvd2x 63, 1, 3 # 16-byte Folded Reload
; PC64LE-NEXT: xxswapd 36, 2
; PC64LE-NEXT: xxmrghw 35, 0, 1 ; PC64LE-NEXT: xxmrghw 35, 0, 1
; PC64LE-NEXT: vperm 2, 2, 3, 4 ; PC64LE-NEXT: vperm 2, 2, 3, 4
; PC64LE-NEXT: addi 1, 1, 80 ; PC64LE-NEXT: addi 1, 1, 80
; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: ld 0, 16(1)
; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: mtlr 0
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_exp2_v3f32: ; PC64LE9-LABEL: constrained_vector_exp2_v3f32:
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; PC64LE-NEXT: xscvspdpn 1, 0 ; PC64LE-NEXT: xscvspdpn 1, 0
; PC64LE-NEXT: bl logf ; PC64LE-NEXT: bl logf
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: xscvdpspn 0, 30 ; PC64LE-NEXT: xscvdpspn 0, 30
; PC64LE-NEXT: addis 3, 2, .LCPI62_0@toc@ha ; PC64LE-NEXT: addis 3, 2, .LCPI62_0@toc@ha
; PC64LE-NEXT: lfd 30, 64(1) # 8-byte Folded Reload ; PC64LE-NEXT: lfd 30, 64(1) # 8-byte Folded Reload
; PC64LE-NEXT: xscvdpspn 1, 1 ; PC64LE-NEXT: xscvdpspn 1, 1
; PC64LE-NEXT: addi 3, 3, .LCPI62_0@toc@l ; PC64LE-NEXT: addi 3, 3, .LCPI62_0@toc@l
; PC64LE-NEXT: lxvd2x 2, 0, 3
; PC64LE-NEXT: xscvdpspn 34, 31 ; PC64LE-NEXT: xscvdpspn 34, 31
; PC64LE-NEXT: lvx 4, 0, 3
; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: li 3, 48
; PC64LE-NEXT: lfd 31, 72(1) # 8-byte Folded Reload ; PC64LE-NEXT: lfd 31, 72(1) # 8-byte Folded Reload
; PC64LE-NEXT: lxvd2x 63, 1, 3 # 16-byte Folded Reload ; PC64LE-NEXT: lxvd2x 63, 1, 3 # 16-byte Folded Reload
; PC64LE-NEXT: xxswapd 36, 2
; PC64LE-NEXT: xxmrghw 35, 0, 1 ; PC64LE-NEXT: xxmrghw 35, 0, 1
; PC64LE-NEXT: vperm 2, 2, 3, 4 ; PC64LE-NEXT: vperm 2, 2, 3, 4
; PC64LE-NEXT: addi 1, 1, 80 ; PC64LE-NEXT: addi 1, 1, 80
; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: ld 0, 16(1)
; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: mtlr 0
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_log_v3f32: ; PC64LE9-LABEL: constrained_vector_log_v3f32:
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; PC64LE-NEXT: xscvspdpn 1, 0 ; PC64LE-NEXT: xscvspdpn 1, 0
; PC64LE-NEXT: bl log10f ; PC64LE-NEXT: bl log10f
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: xscvdpspn 0, 30 ; PC64LE-NEXT: xscvdpspn 0, 30
; PC64LE-NEXT: addis 3, 2, .LCPI67_0@toc@ha ; PC64LE-NEXT: addis 3, 2, .LCPI67_0@toc@ha
; PC64LE-NEXT: lfd 30, 64(1) # 8-byte Folded Reload ; PC64LE-NEXT: lfd 30, 64(1) # 8-byte Folded Reload
; PC64LE-NEXT: xscvdpspn 1, 1 ; PC64LE-NEXT: xscvdpspn 1, 1
; PC64LE-NEXT: addi 3, 3, .LCPI67_0@toc@l ; PC64LE-NEXT: addi 3, 3, .LCPI67_0@toc@l
; PC64LE-NEXT: lxvd2x 2, 0, 3
; PC64LE-NEXT: xscvdpspn 34, 31 ; PC64LE-NEXT: xscvdpspn 34, 31
; PC64LE-NEXT: lvx 4, 0, 3
; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: li 3, 48
; PC64LE-NEXT: lfd 31, 72(1) # 8-byte Folded Reload ; PC64LE-NEXT: lfd 31, 72(1) # 8-byte Folded Reload
; PC64LE-NEXT: lxvd2x 63, 1, 3 # 16-byte Folded Reload ; PC64LE-NEXT: lxvd2x 63, 1, 3 # 16-byte Folded Reload
; PC64LE-NEXT: xxswapd 36, 2
; PC64LE-NEXT: xxmrghw 35, 0, 1 ; PC64LE-NEXT: xxmrghw 35, 0, 1
; PC64LE-NEXT: vperm 2, 2, 3, 4 ; PC64LE-NEXT: vperm 2, 2, 3, 4
; PC64LE-NEXT: addi 1, 1, 80 ; PC64LE-NEXT: addi 1, 1, 80
; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: ld 0, 16(1)
; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: mtlr 0
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_log10_v3f32: ; PC64LE9-LABEL: constrained_vector_log10_v3f32:
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; PC64LE-NEXT: xscvspdpn 1, 0 ; PC64LE-NEXT: xscvspdpn 1, 0
; PC64LE-NEXT: bl log2f ; PC64LE-NEXT: bl log2f
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: xscvdpspn 0, 30 ; PC64LE-NEXT: xscvdpspn 0, 30
; PC64LE-NEXT: addis 3, 2, .LCPI72_0@toc@ha ; PC64LE-NEXT: addis 3, 2, .LCPI72_0@toc@ha
; PC64LE-NEXT: lfd 30, 64(1) # 8-byte Folded Reload ; PC64LE-NEXT: lfd 30, 64(1) # 8-byte Folded Reload
; PC64LE-NEXT: xscvdpspn 1, 1 ; PC64LE-NEXT: xscvdpspn 1, 1
; PC64LE-NEXT: addi 3, 3, .LCPI72_0@toc@l ; PC64LE-NEXT: addi 3, 3, .LCPI72_0@toc@l
; PC64LE-NEXT: lxvd2x 2, 0, 3
; PC64LE-NEXT: xscvdpspn 34, 31 ; PC64LE-NEXT: xscvdpspn 34, 31
; PC64LE-NEXT: lvx 4, 0, 3
; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: li 3, 48
; PC64LE-NEXT: lfd 31, 72(1) # 8-byte Folded Reload ; PC64LE-NEXT: lfd 31, 72(1) # 8-byte Folded Reload
; PC64LE-NEXT: lxvd2x 63, 1, 3 # 16-byte Folded Reload ; PC64LE-NEXT: lxvd2x 63, 1, 3 # 16-byte Folded Reload
; PC64LE-NEXT: xxswapd 36, 2
; PC64LE-NEXT: xxmrghw 35, 0, 1 ; PC64LE-NEXT: xxmrghw 35, 0, 1
; PC64LE-NEXT: vperm 2, 2, 3, 4 ; PC64LE-NEXT: vperm 2, 2, 3, 4
; PC64LE-NEXT: addi 1, 1, 80 ; PC64LE-NEXT: addi 1, 1, 80
; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: ld 0, 16(1)
; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: mtlr 0
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_log2_v3f32: ; PC64LE9-LABEL: constrained_vector_log2_v3f32:
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define <3 x float> @constrained_vector_rint_v3f32(<3 x float> %x) #0 { define <3 x float> @constrained_vector_rint_v3f32(<3 x float> %x) #0 {
; PC64LE-LABEL: constrained_vector_rint_v3f32: ; PC64LE-LABEL: constrained_vector_rint_v3f32:
; PC64LE: # %bb.0: # %entry ; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: xxsldwi 0, 34, 34, 3 ; PC64LE-NEXT: xxsldwi 0, 34, 34, 3
; PC64LE-NEXT: xxswapd 1, 34 ; PC64LE-NEXT: xxswapd 1, 34
; PC64LE-NEXT: addis 3, 2, .LCPI77_0@toc@ha ; PC64LE-NEXT: addis 3, 2, .LCPI77_0@toc@ha
; PC64LE-NEXT: xxsldwi 2, 34, 34, 1 ; PC64LE-NEXT: xxsldwi 2, 34, 34, 1
; PC64LE-NEXT: addi 3, 3, .LCPI77_0@toc@l ; PC64LE-NEXT: addi 3, 3, .LCPI77_0@toc@l
; PC64LE-NEXT: lvx 4, 0, 3 ; PC64LE-NEXT: lxvd2x 3, 0, 3
; PC64LE-NEXT: xscvspdpn 0, 0 ; PC64LE-NEXT: xscvspdpn 0, 0
; PC64LE-NEXT: xscvspdpn 1, 1 ; PC64LE-NEXT: xscvspdpn 1, 1
; PC64LE-NEXT: xscvspdpn 2, 2 ; PC64LE-NEXT: xscvspdpn 2, 2
; PC64LE-NEXT: xxswapd 36, 3
; PC64LE-NEXT: xsrdpic 0, 0 ; PC64LE-NEXT: xsrdpic 0, 0
; PC64LE-NEXT: xsrdpic 1, 1 ; PC64LE-NEXT: xsrdpic 1, 1
; PC64LE-NEXT: xsrdpic 2, 2 ; PC64LE-NEXT: xsrdpic 2, 2
; PC64LE-NEXT: xscvdpspn 0, 0 ; PC64LE-NEXT: xscvdpspn 0, 0
; PC64LE-NEXT: xscvdpspn 1, 1 ; PC64LE-NEXT: xscvdpspn 1, 1
; PC64LE-NEXT: xscvdpspn 34, 2 ; PC64LE-NEXT: xscvdpspn 34, 2
; PC64LE-NEXT: xxmrghw 35, 1, 0 ; PC64LE-NEXT: xxmrghw 35, 1, 0
; PC64LE-NEXT: vperm 2, 2, 3, 4 ; PC64LE-NEXT: vperm 2, 2, 3, 4
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; PC64LE-NEXT: xscvspdpn 1, 0 ; PC64LE-NEXT: xscvspdpn 1, 0
; PC64LE-NEXT: bl nearbyintf ; PC64LE-NEXT: bl nearbyintf
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: xscvdpspn 0, 30 ; PC64LE-NEXT: xscvdpspn 0, 30
; PC64LE-NEXT: addis 3, 2, .LCPI82_0@toc@ha ; PC64LE-NEXT: addis 3, 2, .LCPI82_0@toc@ha
; PC64LE-NEXT: lfd 30, 64(1) # 8-byte Folded Reload ; PC64LE-NEXT: lfd 30, 64(1) # 8-byte Folded Reload
; PC64LE-NEXT: xscvdpspn 1, 1 ; PC64LE-NEXT: xscvdpspn 1, 1
; PC64LE-NEXT: addi 3, 3, .LCPI82_0@toc@l ; PC64LE-NEXT: addi 3, 3, .LCPI82_0@toc@l
; PC64LE-NEXT: lxvd2x 2, 0, 3
; PC64LE-NEXT: xscvdpspn 34, 31 ; PC64LE-NEXT: xscvdpspn 34, 31
; PC64LE-NEXT: lvx 4, 0, 3
; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: li 3, 48
; PC64LE-NEXT: lfd 31, 72(1) # 8-byte Folded Reload ; PC64LE-NEXT: lfd 31, 72(1) # 8-byte Folded Reload
; PC64LE-NEXT: lxvd2x 63, 1, 3 # 16-byte Folded Reload ; PC64LE-NEXT: lxvd2x 63, 1, 3 # 16-byte Folded Reload
; PC64LE-NEXT: xxswapd 36, 2
; PC64LE-NEXT: xxmrghw 35, 0, 1 ; PC64LE-NEXT: xxmrghw 35, 0, 1
; PC64LE-NEXT: vperm 2, 2, 3, 4 ; PC64LE-NEXT: vperm 2, 2, 3, 4
; PC64LE-NEXT: addi 1, 1, 80 ; PC64LE-NEXT: addi 1, 1, 80
; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: ld 0, 16(1)
; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: mtlr 0
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_nearbyint_v3f32: ; PC64LE9-LABEL: constrained_vector_nearbyint_v3f32:
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; PC64LE-NEXT: bl fmaxf ; PC64LE-NEXT: bl fmaxf
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: xscvdpspn 0, 30 ; PC64LE-NEXT: xscvdpspn 0, 30
; PC64LE-NEXT: addis 3, 2, .LCPI87_0@toc@ha ; PC64LE-NEXT: addis 3, 2, .LCPI87_0@toc@ha
; PC64LE-NEXT: lfd 30, 80(1) # 8-byte Folded Reload ; PC64LE-NEXT: lfd 30, 80(1) # 8-byte Folded Reload
; PC64LE-NEXT: xscvdpspn 1, 1 ; PC64LE-NEXT: xscvdpspn 1, 1
; PC64LE-NEXT: addi 3, 3, .LCPI87_0@toc@l ; PC64LE-NEXT: addi 3, 3, .LCPI87_0@toc@l
; PC64LE-NEXT: xscvdpspn 34, 31 ; PC64LE-NEXT: xscvdpspn 34, 31
; PC64LE-NEXT: lvx 4, 0, 3 ; PC64LE-NEXT: lxvd2x 2, 0, 3
; PC64LE-NEXT: li 3, 64 ; PC64LE-NEXT: li 3, 64
; PC64LE-NEXT: lfd 31, 88(1) # 8-byte Folded Reload ; PC64LE-NEXT: lfd 31, 88(1) # 8-byte Folded Reload
; PC64LE-NEXT: lxvd2x 63, 1, 3 # 16-byte Folded Reload ; PC64LE-NEXT: lxvd2x 63, 1, 3 # 16-byte Folded Reload
; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: li 3, 48
; PC64LE-NEXT: lxvd2x 62, 1, 3 # 16-byte Folded Reload ; PC64LE-NEXT: lxvd2x 62, 1, 3 # 16-byte Folded Reload
; PC64LE-NEXT: xxswapd 36, 2
; PC64LE-NEXT: xxmrghw 35, 0, 1 ; PC64LE-NEXT: xxmrghw 35, 0, 1
; PC64LE-NEXT: vperm 2, 2, 3, 4 ; PC64LE-NEXT: vperm 2, 2, 3, 4
; PC64LE-NEXT: addi 1, 1, 96 ; PC64LE-NEXT: addi 1, 1, 96
; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: ld 0, 16(1)
; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: mtlr 0
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_maxnum_v3f32: ; PC64LE9-LABEL: constrained_vector_maxnum_v3f32:
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; PC64LE-NEXT: bl fminf ; PC64LE-NEXT: bl fminf
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: xscvdpspn 0, 30 ; PC64LE-NEXT: xscvdpspn 0, 30
; PC64LE-NEXT: addis 3, 2, .LCPI92_0@toc@ha ; PC64LE-NEXT: addis 3, 2, .LCPI92_0@toc@ha
; PC64LE-NEXT: lfd 30, 80(1) # 8-byte Folded Reload ; PC64LE-NEXT: lfd 30, 80(1) # 8-byte Folded Reload
; PC64LE-NEXT: xscvdpspn 1, 1 ; PC64LE-NEXT: xscvdpspn 1, 1
; PC64LE-NEXT: addi 3, 3, .LCPI92_0@toc@l ; PC64LE-NEXT: addi 3, 3, .LCPI92_0@toc@l
; PC64LE-NEXT: xscvdpspn 34, 31 ; PC64LE-NEXT: xscvdpspn 34, 31
; PC64LE-NEXT: lvx 4, 0, 3 ; PC64LE-NEXT: lxvd2x 2, 0, 3
; PC64LE-NEXT: li 3, 64 ; PC64LE-NEXT: li 3, 64
; PC64LE-NEXT: lfd 31, 88(1) # 8-byte Folded Reload ; PC64LE-NEXT: lfd 31, 88(1) # 8-byte Folded Reload
; PC64LE-NEXT: lxvd2x 63, 1, 3 # 16-byte Folded Reload ; PC64LE-NEXT: lxvd2x 63, 1, 3 # 16-byte Folded Reload
; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: li 3, 48
; PC64LE-NEXT: lxvd2x 62, 1, 3 # 16-byte Folded Reload ; PC64LE-NEXT: lxvd2x 62, 1, 3 # 16-byte Folded Reload
; PC64LE-NEXT: xxswapd 36, 2
; PC64LE-NEXT: xxmrghw 35, 0, 1 ; PC64LE-NEXT: xxmrghw 35, 0, 1
; PC64LE-NEXT: vperm 2, 2, 3, 4 ; PC64LE-NEXT: vperm 2, 2, 3, 4
; PC64LE-NEXT: addi 1, 1, 96 ; PC64LE-NEXT: addi 1, 1, 96
; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: ld 0, 16(1)
; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: mtlr 0
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_minnum_v3f32: ; PC64LE9-LABEL: constrained_vector_minnum_v3f32:
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define <3 x i32> @constrained_vector_fptosi_v3i32_v3f32(<3 x float> %x) #0 { define <3 x i32> @constrained_vector_fptosi_v3i32_v3f32(<3 x float> %x) #0 {
; PC64LE-LABEL: constrained_vector_fptosi_v3i32_v3f32: ; PC64LE-LABEL: constrained_vector_fptosi_v3i32_v3f32:
; PC64LE: # %bb.0: # %entry ; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: xxsldwi 0, 34, 34, 3 ; PC64LE-NEXT: xxsldwi 0, 34, 34, 3
; PC64LE-NEXT: xxswapd 1, 34 ; PC64LE-NEXT: xxswapd 1, 34
; PC64LE-NEXT: addis 3, 2, .LCPI97_0@toc@ha ; PC64LE-NEXT: addis 3, 2, .LCPI97_0@toc@ha
; PC64LE-NEXT: xxsldwi 2, 34, 34, 1 ; PC64LE-NEXT: xxsldwi 2, 34, 34, 1
; PC64LE-NEXT: addi 3, 3, .LCPI97_0@toc@l ; PC64LE-NEXT: addi 3, 3, .LCPI97_0@toc@l
; PC64LE-NEXT: lvx 2, 0, 3
; PC64LE-NEXT: xscvspdpn 0, 0 ; PC64LE-NEXT: xscvspdpn 0, 0
; PC64LE-NEXT: xscvspdpn 1, 1 ; PC64LE-NEXT: xscvspdpn 1, 1
; PC64LE-NEXT: xscvspdpn 2, 2 ; PC64LE-NEXT: xscvspdpn 2, 2
; PC64LE-NEXT: xscvdpsxws 0, 0 ; PC64LE-NEXT: xscvdpsxws 0, 0
; PC64LE-NEXT: xscvdpsxws 1, 1 ; PC64LE-NEXT: xscvdpsxws 1, 1
; PC64LE-NEXT: xscvdpsxws 2, 2 ; PC64LE-NEXT: xscvdpsxws 2, 2
; PC64LE-NEXT: mffprwz 4, 0 ; PC64LE-NEXT: mffprwz 4, 0
; PC64LE-NEXT: lxvd2x 0, 0, 3
; PC64LE-NEXT: mffprwz 5, 1 ; PC64LE-NEXT: mffprwz 5, 1
; PC64LE-NEXT: mtfprwz 0, 4 ; PC64LE-NEXT: mtfprwz 1, 4
; PC64LE-NEXT: mtfprwz 1, 5 ; PC64LE-NEXT: mtfprwz 3, 5
; PC64LE-NEXT: mffprwz 4, 2 ; PC64LE-NEXT: xxswapd 35, 0
; PC64LE-NEXT: xxmrghw 35, 1, 0 ; PC64LE-NEXT: mffprwz 3, 2
; PC64LE-NEXT: mtvsrwz 36, 4 ; PC64LE-NEXT: xxmrghw 34, 3, 1
; PC64LE-NEXT: vperm 2, 4, 3, 2 ; PC64LE-NEXT: mtvsrwz 36, 3
; PC64LE-NEXT: vperm 2, 4, 2, 3
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_fptosi_v3i32_v3f32: ; PC64LE9-LABEL: constrained_vector_fptosi_v3i32_v3f32:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: xxsldwi 0, 34, 34, 3 ; PC64LE9-NEXT: xxsldwi 0, 34, 34, 3
; PC64LE9-NEXT: xxswapd 1, 34 ; PC64LE9-NEXT: xxswapd 1, 34
; PC64LE9-NEXT: xscvspdpn 0, 0 ; PC64LE9-NEXT: xscvspdpn 0, 0
; PC64LE9-NEXT: xscvspdpn 1, 1 ; PC64LE9-NEXT: xscvspdpn 1, 1
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define <3 x i32> @constrained_vector_fptosi_v3i32_v3f64(<3 x double> %x) #0 { define <3 x i32> @constrained_vector_fptosi_v3i32_v3f64(<3 x double> %x) #0 {
; PC64LE-LABEL: constrained_vector_fptosi_v3i32_v3f64: ; PC64LE-LABEL: constrained_vector_fptosi_v3i32_v3f64:
; PC64LE: # %bb.0: # %entry ; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: xscvdpsxws 0, 1 ; PC64LE-NEXT: xscvdpsxws 0, 1
; PC64LE-NEXT: addis 3, 2, .LCPI105_0@toc@ha ; PC64LE-NEXT: addis 3, 2, .LCPI105_0@toc@ha
; PC64LE-NEXT: xscvdpsxws 1, 2 ; PC64LE-NEXT: xscvdpsxws 1, 2
; PC64LE-NEXT: addi 3, 3, .LCPI105_0@toc@l ; PC64LE-NEXT: addi 3, 3, .LCPI105_0@toc@l
; PC64LE-NEXT: xscvdpsxws 2, 3 ; PC64LE-NEXT: xscvdpsxws 2, 3
; PC64LE-NEXT: lvx 2, 0, 3
; PC64LE-NEXT: mffprwz 4, 0 ; PC64LE-NEXT: mffprwz 4, 0
; PC64LE-NEXT: lxvd2x 0, 0, 3
; PC64LE-NEXT: mffprwz 5, 1 ; PC64LE-NEXT: mffprwz 5, 1
; PC64LE-NEXT: mtfprwz 0, 4 ; PC64LE-NEXT: mtfprwz 1, 4
; PC64LE-NEXT: mtfprwz 1, 5 ; PC64LE-NEXT: mtfprwz 3, 5
; PC64LE-NEXT: mffprwz 4, 2 ; PC64LE-NEXT: xxswapd 35, 0
; PC64LE-NEXT: xxmrghw 35, 1, 0 ; PC64LE-NEXT: mffprwz 3, 2
; PC64LE-NEXT: mtvsrwz 36, 4 ; PC64LE-NEXT: xxmrghw 34, 3, 1
; PC64LE-NEXT: vperm 2, 4, 3, 2 ; PC64LE-NEXT: mtvsrwz 36, 3
; PC64LE-NEXT: vperm 2, 4, 2, 3
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_fptosi_v3i32_v3f64: ; PC64LE9-LABEL: constrained_vector_fptosi_v3i32_v3f64:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: xscvdpsxws 0, 1 ; PC64LE9-NEXT: xscvdpsxws 0, 1
; PC64LE9-NEXT: xscvdpsxws 1, 2 ; PC64LE9-NEXT: xscvdpsxws 1, 2
; PC64LE9-NEXT: mffprwz 3, 0 ; PC64LE9-NEXT: mffprwz 3, 0
; PC64LE9-NEXT: mtfprwz 0, 3 ; PC64LE9-NEXT: mtfprwz 0, 3
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define <3 x i32> @constrained_vector_fptoui_v3i32_v3f32(<3 x float> %x) #0 { define <3 x i32> @constrained_vector_fptoui_v3i32_v3f32(<3 x float> %x) #0 {
; PC64LE-LABEL: constrained_vector_fptoui_v3i32_v3f32: ; PC64LE-LABEL: constrained_vector_fptoui_v3i32_v3f32:
; PC64LE: # %bb.0: # %entry ; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: xxsldwi 0, 34, 34, 3 ; PC64LE-NEXT: xxsldwi 0, 34, 34, 3
; PC64LE-NEXT: xxswapd 1, 34 ; PC64LE-NEXT: xxswapd 1, 34
; PC64LE-NEXT: addis 3, 2, .LCPI113_0@toc@ha ; PC64LE-NEXT: addis 3, 2, .LCPI113_0@toc@ha
; PC64LE-NEXT: xxsldwi 2, 34, 34, 1 ; PC64LE-NEXT: xxsldwi 2, 34, 34, 1
; PC64LE-NEXT: addi 3, 3, .LCPI113_0@toc@l ; PC64LE-NEXT: addi 3, 3, .LCPI113_0@toc@l
; PC64LE-NEXT: lvx 2, 0, 3
; PC64LE-NEXT: xscvspdpn 0, 0 ; PC64LE-NEXT: xscvspdpn 0, 0
; PC64LE-NEXT: xscvspdpn 1, 1 ; PC64LE-NEXT: xscvspdpn 1, 1
; PC64LE-NEXT: xscvspdpn 2, 2 ; PC64LE-NEXT: xscvspdpn 2, 2
; PC64LE-NEXT: xscvdpuxws 0, 0 ; PC64LE-NEXT: xscvdpuxws 0, 0
; PC64LE-NEXT: xscvdpuxws 1, 1 ; PC64LE-NEXT: xscvdpuxws 1, 1
; PC64LE-NEXT: xscvdpuxws 2, 2 ; PC64LE-NEXT: xscvdpuxws 2, 2
; PC64LE-NEXT: mffprwz 4, 0 ; PC64LE-NEXT: mffprwz 4, 0
; PC64LE-NEXT: lxvd2x 0, 0, 3
; PC64LE-NEXT: mffprwz 5, 1 ; PC64LE-NEXT: mffprwz 5, 1
; PC64LE-NEXT: mtfprwz 0, 4 ; PC64LE-NEXT: mtfprwz 1, 4
; PC64LE-NEXT: mtfprwz 1, 5 ; PC64LE-NEXT: mtfprwz 3, 5
; PC64LE-NEXT: mffprwz 4, 2 ; PC64LE-NEXT: xxswapd 35, 0
; PC64LE-NEXT: xxmrghw 35, 1, 0 ; PC64LE-NEXT: mffprwz 3, 2
; PC64LE-NEXT: mtvsrwz 36, 4 ; PC64LE-NEXT: xxmrghw 34, 3, 1
; PC64LE-NEXT: vperm 2, 4, 3, 2 ; PC64LE-NEXT: mtvsrwz 36, 3
; PC64LE-NEXT: vperm 2, 4, 2, 3
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_fptoui_v3i32_v3f32: ; PC64LE9-LABEL: constrained_vector_fptoui_v3i32_v3f32:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: xxsldwi 0, 34, 34, 3 ; PC64LE9-NEXT: xxsldwi 0, 34, 34, 3
; PC64LE9-NEXT: xxswapd 1, 34 ; PC64LE9-NEXT: xxswapd 1, 34
; PC64LE9-NEXT: xscvspdpn 0, 0 ; PC64LE9-NEXT: xscvspdpn 0, 0
; PC64LE9-NEXT: xscvspdpn 1, 1 ; PC64LE9-NEXT: xscvspdpn 1, 1
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define <3 x i32> @constrained_vector_fptoui_v3i32_v3f64(<3 x double> %x) #0 { define <3 x i32> @constrained_vector_fptoui_v3i32_v3f64(<3 x double> %x) #0 {
; PC64LE-LABEL: constrained_vector_fptoui_v3i32_v3f64: ; PC64LE-LABEL: constrained_vector_fptoui_v3i32_v3f64:
; PC64LE: # %bb.0: # %entry ; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: xscvdpuxws 0, 1 ; PC64LE-NEXT: xscvdpuxws 0, 1
; PC64LE-NEXT: addis 3, 2, .LCPI121_0@toc@ha ; PC64LE-NEXT: addis 3, 2, .LCPI121_0@toc@ha
; PC64LE-NEXT: xscvdpuxws 1, 2 ; PC64LE-NEXT: xscvdpuxws 1, 2
; PC64LE-NEXT: addi 3, 3, .LCPI121_0@toc@l ; PC64LE-NEXT: addi 3, 3, .LCPI121_0@toc@l
; PC64LE-NEXT: xscvdpuxws 2, 3 ; PC64LE-NEXT: xscvdpuxws 2, 3
; PC64LE-NEXT: lvx 2, 0, 3
; PC64LE-NEXT: mffprwz 4, 0 ; PC64LE-NEXT: mffprwz 4, 0
; PC64LE-NEXT: lxvd2x 0, 0, 3
; PC64LE-NEXT: mffprwz 5, 1 ; PC64LE-NEXT: mffprwz 5, 1
; PC64LE-NEXT: mtfprwz 0, 4 ; PC64LE-NEXT: mtfprwz 1, 4
; PC64LE-NEXT: mtfprwz 1, 5 ; PC64LE-NEXT: mtfprwz 3, 5
; PC64LE-NEXT: mffprwz 4, 2 ; PC64LE-NEXT: xxswapd 35, 0
; PC64LE-NEXT: xxmrghw 35, 1, 0 ; PC64LE-NEXT: mffprwz 3, 2
; PC64LE-NEXT: mtvsrwz 36, 4 ; PC64LE-NEXT: xxmrghw 34, 3, 1
; PC64LE-NEXT: vperm 2, 4, 3, 2 ; PC64LE-NEXT: mtvsrwz 36, 3
; PC64LE-NEXT: vperm 2, 4, 2, 3
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_fptoui_v3i32_v3f64: ; PC64LE9-LABEL: constrained_vector_fptoui_v3i32_v3f64:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: xscvdpuxws 0, 1 ; PC64LE9-NEXT: xscvdpuxws 0, 1
; PC64LE9-NEXT: xscvdpuxws 1, 2 ; PC64LE9-NEXT: xscvdpuxws 1, 2
; PC64LE9-NEXT: mffprwz 3, 0 ; PC64LE9-NEXT: mffprwz 3, 0
; PC64LE9-NEXT: mtfprwz 0, 3 ; PC64LE9-NEXT: mtfprwz 0, 3
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define <3 x float> @constrained_vector_fptrunc_v3f64(<3 x double> %x) #0 { define <3 x float> @constrained_vector_fptrunc_v3f64(<3 x double> %x) #0 {
; PC64LE-LABEL: constrained_vector_fptrunc_v3f64: ; PC64LE-LABEL: constrained_vector_fptrunc_v3f64:
; PC64LE: # %bb.0: # %entry ; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: xsrsp 0, 1 ; PC64LE-NEXT: xsrsp 0, 1
; PC64LE-NEXT: addis 3, 2, .LCPI129_0@toc@ha ; PC64LE-NEXT: addis 3, 2, .LCPI129_0@toc@ha
; PC64LE-NEXT: xsrsp 1, 2 ; PC64LE-NEXT: xsrsp 1, 2
; PC64LE-NEXT: addi 3, 3, .LCPI129_0@toc@l ; PC64LE-NEXT: addi 3, 3, .LCPI129_0@toc@l
; PC64LE-NEXT: xsrsp 2, 3 ; PC64LE-NEXT: xsrsp 2, 3
; PC64LE-NEXT: lvx 4, 0, 3
; PC64LE-NEXT: xscvdpspn 0, 0 ; PC64LE-NEXT: xscvdpspn 0, 0
; PC64LE-NEXT: xscvdpspn 1, 1 ; PC64LE-NEXT: xscvdpspn 1, 1
; PC64LE-NEXT: xscvdpspn 34, 2 ; PC64LE-NEXT: xscvdpspn 34, 2
; PC64LE-NEXT: lxvd2x 2, 0, 3
; PC64LE-NEXT: xxswapd 36, 2
; PC64LE-NEXT: xxmrghw 35, 1, 0 ; PC64LE-NEXT: xxmrghw 35, 1, 0
; PC64LE-NEXT: vperm 2, 2, 3, 4 ; PC64LE-NEXT: vperm 2, 2, 3, 4
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_fptrunc_v3f64: ; PC64LE9-LABEL: constrained_vector_fptrunc_v3f64:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: xsrsp 0, 1 ; PC64LE9-NEXT: xsrsp 0, 1
; PC64LE9-NEXT: xsrsp 1, 2 ; PC64LE9-NEXT: xsrsp 1, 2
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define <3 x float> @constrained_vector_ceil_v3f32(<3 x float> %x) #0 { define <3 x float> @constrained_vector_ceil_v3f32(<3 x float> %x) #0 {
; PC64LE-LABEL: constrained_vector_ceil_v3f32: ; PC64LE-LABEL: constrained_vector_ceil_v3f32:
; PC64LE: # %bb.0: # %entry ; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: xxsldwi 0, 34, 34, 3 ; PC64LE-NEXT: xxsldwi 0, 34, 34, 3
; PC64LE-NEXT: xxswapd 1, 34 ; PC64LE-NEXT: xxswapd 1, 34
; PC64LE-NEXT: addis 3, 2, .LCPI137_0@toc@ha ; PC64LE-NEXT: addis 3, 2, .LCPI137_0@toc@ha
; PC64LE-NEXT: xxsldwi 2, 34, 34, 1 ; PC64LE-NEXT: xxsldwi 2, 34, 34, 1
; PC64LE-NEXT: addi 3, 3, .LCPI137_0@toc@l ; PC64LE-NEXT: addi 3, 3, .LCPI137_0@toc@l
; PC64LE-NEXT: lvx 4, 0, 3 ; PC64LE-NEXT: lxvd2x 3, 0, 3
; PC64LE-NEXT: xscvspdpn 0, 0 ; PC64LE-NEXT: xscvspdpn 0, 0
; PC64LE-NEXT: xscvspdpn 1, 1 ; PC64LE-NEXT: xscvspdpn 1, 1
; PC64LE-NEXT: xscvspdpn 2, 2 ; PC64LE-NEXT: xscvspdpn 2, 2
; PC64LE-NEXT: xxswapd 36, 3
; PC64LE-NEXT: xsrdpip 0, 0 ; PC64LE-NEXT: xsrdpip 0, 0
; PC64LE-NEXT: xsrdpip 1, 1 ; PC64LE-NEXT: xsrdpip 1, 1
; PC64LE-NEXT: xsrdpip 2, 2 ; PC64LE-NEXT: xsrdpip 2, 2
; PC64LE-NEXT: xscvdpspn 0, 0 ; PC64LE-NEXT: xscvdpspn 0, 0
; PC64LE-NEXT: xscvdpspn 1, 1 ; PC64LE-NEXT: xscvdpspn 1, 1
; PC64LE-NEXT: xscvdpspn 34, 2 ; PC64LE-NEXT: xscvdpspn 34, 2
; PC64LE-NEXT: xxmrghw 35, 1, 0 ; PC64LE-NEXT: xxmrghw 35, 1, 0
; PC64LE-NEXT: vperm 2, 2, 3, 4 ; PC64LE-NEXT: vperm 2, 2, 3, 4
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define <3 x float> @constrained_vector_floor_v3f32(<3 x float> %x) #0 { define <3 x float> @constrained_vector_floor_v3f32(<3 x float> %x) #0 {
; PC64LE-LABEL: constrained_vector_floor_v3f32: ; PC64LE-LABEL: constrained_vector_floor_v3f32:
; PC64LE: # %bb.0: # %entry ; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: xxsldwi 0, 34, 34, 3 ; PC64LE-NEXT: xxsldwi 0, 34, 34, 3
; PC64LE-NEXT: xxswapd 1, 34 ; PC64LE-NEXT: xxswapd 1, 34
; PC64LE-NEXT: addis 3, 2, .LCPI141_0@toc@ha ; PC64LE-NEXT: addis 3, 2, .LCPI141_0@toc@ha
; PC64LE-NEXT: xxsldwi 2, 34, 34, 1 ; PC64LE-NEXT: xxsldwi 2, 34, 34, 1
; PC64LE-NEXT: addi 3, 3, .LCPI141_0@toc@l ; PC64LE-NEXT: addi 3, 3, .LCPI141_0@toc@l
; PC64LE-NEXT: lvx 4, 0, 3 ; PC64LE-NEXT: lxvd2x 3, 0, 3
; PC64LE-NEXT: xscvspdpn 0, 0 ; PC64LE-NEXT: xscvspdpn 0, 0
; PC64LE-NEXT: xscvspdpn 1, 1 ; PC64LE-NEXT: xscvspdpn 1, 1
; PC64LE-NEXT: xscvspdpn 2, 2 ; PC64LE-NEXT: xscvspdpn 2, 2
; PC64LE-NEXT: xxswapd 36, 3
; PC64LE-NEXT: xsrdpim 0, 0 ; PC64LE-NEXT: xsrdpim 0, 0
; PC64LE-NEXT: xsrdpim 1, 1 ; PC64LE-NEXT: xsrdpim 1, 1
; PC64LE-NEXT: xsrdpim 2, 2 ; PC64LE-NEXT: xsrdpim 2, 2
; PC64LE-NEXT: xscvdpspn 0, 0 ; PC64LE-NEXT: xscvdpspn 0, 0
; PC64LE-NEXT: xscvdpspn 1, 1 ; PC64LE-NEXT: xscvdpspn 1, 1
; PC64LE-NEXT: xscvdpspn 34, 2 ; PC64LE-NEXT: xscvdpspn 34, 2
; PC64LE-NEXT: xxmrghw 35, 1, 0 ; PC64LE-NEXT: xxmrghw 35, 1, 0
; PC64LE-NEXT: vperm 2, 2, 3, 4 ; PC64LE-NEXT: vperm 2, 2, 3, 4
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define <3 x float> @constrained_vector_round_v3f32(<3 x float> %x) #0 { define <3 x float> @constrained_vector_round_v3f32(<3 x float> %x) #0 {
; PC64LE-LABEL: constrained_vector_round_v3f32: ; PC64LE-LABEL: constrained_vector_round_v3f32:
; PC64LE: # %bb.0: # %entry ; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: xxsldwi 0, 34, 34, 3 ; PC64LE-NEXT: xxsldwi 0, 34, 34, 3
; PC64LE-NEXT: xxswapd 1, 34 ; PC64LE-NEXT: xxswapd 1, 34
; PC64LE-NEXT: addis 3, 2, .LCPI145_0@toc@ha ; PC64LE-NEXT: addis 3, 2, .LCPI145_0@toc@ha
; PC64LE-NEXT: xxsldwi 2, 34, 34, 1 ; PC64LE-NEXT: xxsldwi 2, 34, 34, 1
; PC64LE-NEXT: addi 3, 3, .LCPI145_0@toc@l ; PC64LE-NEXT: addi 3, 3, .LCPI145_0@toc@l
; PC64LE-NEXT: lvx 4, 0, 3 ; PC64LE-NEXT: lxvd2x 3, 0, 3
; PC64LE-NEXT: xscvspdpn 0, 0 ; PC64LE-NEXT: xscvspdpn 0, 0
; PC64LE-NEXT: xscvspdpn 1, 1 ; PC64LE-NEXT: xscvspdpn 1, 1
; PC64LE-NEXT: xscvspdpn 2, 2 ; PC64LE-NEXT: xscvspdpn 2, 2
; PC64LE-NEXT: xxswapd 36, 3
; PC64LE-NEXT: xsrdpi 0, 0 ; PC64LE-NEXT: xsrdpi 0, 0
; PC64LE-NEXT: xsrdpi 1, 1 ; PC64LE-NEXT: xsrdpi 1, 1
; PC64LE-NEXT: xsrdpi 2, 2 ; PC64LE-NEXT: xsrdpi 2, 2
; PC64LE-NEXT: xscvdpspn 0, 0 ; PC64LE-NEXT: xscvdpspn 0, 0
; PC64LE-NEXT: xscvdpspn 1, 1 ; PC64LE-NEXT: xscvdpspn 1, 1
; PC64LE-NEXT: xscvdpspn 34, 2 ; PC64LE-NEXT: xscvdpspn 34, 2
; PC64LE-NEXT: xxmrghw 35, 1, 0 ; PC64LE-NEXT: xxmrghw 35, 1, 0
; PC64LE-NEXT: vperm 2, 2, 3, 4 ; PC64LE-NEXT: vperm 2, 2, 3, 4
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define <3 x float> @constrained_vector_trunc_v3f32(<3 x float> %x) #0 { define <3 x float> @constrained_vector_trunc_v3f32(<3 x float> %x) #0 {
; PC64LE-LABEL: constrained_vector_trunc_v3f32: ; PC64LE-LABEL: constrained_vector_trunc_v3f32:
; PC64LE: # %bb.0: # %entry ; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: xxsldwi 0, 34, 34, 3 ; PC64LE-NEXT: xxsldwi 0, 34, 34, 3
; PC64LE-NEXT: xxswapd 1, 34 ; PC64LE-NEXT: xxswapd 1, 34
; PC64LE-NEXT: addis 3, 2, .LCPI149_0@toc@ha ; PC64LE-NEXT: addis 3, 2, .LCPI149_0@toc@ha
; PC64LE-NEXT: xxsldwi 2, 34, 34, 1 ; PC64LE-NEXT: xxsldwi 2, 34, 34, 1
; PC64LE-NEXT: addi 3, 3, .LCPI149_0@toc@l ; PC64LE-NEXT: addi 3, 3, .LCPI149_0@toc@l
; PC64LE-NEXT: lvx 4, 0, 3 ; PC64LE-NEXT: lxvd2x 3, 0, 3
; PC64LE-NEXT: xscvspdpn 0, 0 ; PC64LE-NEXT: xscvspdpn 0, 0
; PC64LE-NEXT: xscvspdpn 1, 1 ; PC64LE-NEXT: xscvspdpn 1, 1
; PC64LE-NEXT: xscvspdpn 2, 2 ; PC64LE-NEXT: xscvspdpn 2, 2
; PC64LE-NEXT: xxswapd 36, 3
; PC64LE-NEXT: xsrdpiz 0, 0 ; PC64LE-NEXT: xsrdpiz 0, 0
; PC64LE-NEXT: xsrdpiz 1, 1 ; PC64LE-NEXT: xsrdpiz 1, 1
; PC64LE-NEXT: xsrdpiz 2, 2 ; PC64LE-NEXT: xsrdpiz 2, 2
; PC64LE-NEXT: xscvdpspn 0, 0 ; PC64LE-NEXT: xscvdpspn 0, 0
; PC64LE-NEXT: xscvdpspn 1, 1 ; PC64LE-NEXT: xscvdpspn 1, 1
; PC64LE-NEXT: xscvdpspn 34, 2 ; PC64LE-NEXT: xscvdpspn 34, 2
; PC64LE-NEXT: xxmrghw 35, 1, 0 ; PC64LE-NEXT: xxmrghw 35, 1, 0
; PC64LE-NEXT: vperm 2, 2, 3, 4 ; PC64LE-NEXT: vperm 2, 2, 3, 4
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ret <1 x float> %result ret <1 x float> %result
} }
define <2 x double> @constrained_vector_sitofp_v2f64_v2i16(<2 x i16> %x) #0 { define <2 x double> @constrained_vector_sitofp_v2f64_v2i16(<2 x i16> %x) #0 {
; PC64LE-LABEL: constrained_vector_sitofp_v2f64_v2i16: ; PC64LE-LABEL: constrained_vector_sitofp_v2f64_v2i16:
; PC64LE: # %bb.0: # %entry ; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: addis 3, 2, .LCPI155_0@toc@ha ; PC64LE-NEXT: addis 3, 2, .LCPI155_0@toc@ha
; PC64LE-NEXT: addi 3, 3, .LCPI155_0@toc@l ; PC64LE-NEXT: addi 3, 3, .LCPI155_0@toc@l
; PC64LE-NEXT: lvx 3, 0, 3 ; PC64LE-NEXT: lxvd2x 0, 0, 3
; PC64LE-NEXT: addis 3, 2, .LCPI155_1@toc@ha ; PC64LE-NEXT: addis 3, 2, .LCPI155_1@toc@ha
; PC64LE-NEXT: addi 3, 3, .LCPI155_1@toc@l ; PC64LE-NEXT: addi 3, 3, .LCPI155_1@toc@l
; PC64LE-NEXT: xxswapd 35, 0
; PC64LE-NEXT: lxvd2x 0, 0, 3 ; PC64LE-NEXT: lxvd2x 0, 0, 3
; PC64LE-NEXT: vperm 2, 2, 2, 3 ; PC64LE-NEXT: vperm 2, 2, 2, 3
; PC64LE-NEXT: xxswapd 35, 0 ; PC64LE-NEXT: xxswapd 35, 0
; PC64LE-NEXT: vsld 2, 2, 3 ; PC64LE-NEXT: vsld 2, 2, 3
; PC64LE-NEXT: vsrad 2, 2, 3 ; PC64LE-NEXT: vsrad 2, 2, 3
; PC64LE-NEXT: xvcvsxddp 34, 34 ; PC64LE-NEXT: xvcvsxddp 34, 34
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
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define <3 x float> @constrained_vector_sitofp_v3f32_v3i32(<3 x i32> %x) #0 { define <3 x float> @constrained_vector_sitofp_v3f32_v3i32(<3 x i32> %x) #0 {
; PC64LE-LABEL: constrained_vector_sitofp_v3f32_v3i32: ; PC64LE-LABEL: constrained_vector_sitofp_v3f32_v3i32:
; PC64LE: # %bb.0: # %entry ; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: xxswapd 0, 34 ; PC64LE-NEXT: xxswapd 0, 34
; PC64LE-NEXT: xxsldwi 1, 34, 34, 1 ; PC64LE-NEXT: xxsldwi 1, 34, 34, 1
; PC64LE-NEXT: addis 3, 2, .LCPI161_0@toc@ha ; PC64LE-NEXT: addis 3, 2, .LCPI161_0@toc@ha
; PC64LE-NEXT: addi 3, 3, .LCPI161_0@toc@l ; PC64LE-NEXT: addi 3, 3, .LCPI161_0@toc@l
; PC64LE-NEXT: lvx 4, 0, 3 ; PC64LE-NEXT: lxvd2x 3, 0, 3
; PC64LE-NEXT: mffprwz 4, 0 ; PC64LE-NEXT: mffprwz 4, 0
; PC64LE-NEXT: mffprwz 5, 1 ; PC64LE-NEXT: mffprwz 5, 1
; PC64LE-NEXT: mtfprwa 0, 4 ; PC64LE-NEXT: mtfprwa 0, 4
; PC64LE-NEXT: xxswapd 36, 3
; PC64LE-NEXT: mtfprwa 1, 5 ; PC64LE-NEXT: mtfprwa 1, 5
; PC64LE-NEXT: mfvsrwz 4, 34 ; PC64LE-NEXT: mfvsrwz 4, 34
; PC64LE-NEXT: xscvsxdsp 0, 0 ; PC64LE-NEXT: xscvsxdsp 0, 0
; PC64LE-NEXT: xscvsxdsp 1, 1 ; PC64LE-NEXT: xscvsxdsp 1, 1
; PC64LE-NEXT: mtfprwa 2, 4 ; PC64LE-NEXT: mtfprwa 2, 4
; PC64LE-NEXT: xscvsxdsp 2, 2 ; PC64LE-NEXT: xscvsxdsp 2, 2
; PC64LE-NEXT: xscvdpspn 0, 0 ; PC64LE-NEXT: xscvdpspn 0, 0
; PC64LE-NEXT: xscvdpspn 1, 1 ; PC64LE-NEXT: xscvdpspn 1, 1
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define <3 x float> @constrained_vector_sitofp_v3f32_v3i64(<3 x i64> %x) #0 { define <3 x float> @constrained_vector_sitofp_v3f32_v3i64(<3 x i64> %x) #0 {
; PC64LE-LABEL: constrained_vector_sitofp_v3f32_v3i64: ; PC64LE-LABEL: constrained_vector_sitofp_v3f32_v3i64:
; PC64LE: # %bb.0: # %entry ; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: mtfprd 0, 3 ; PC64LE-NEXT: mtfprd 0, 3
; PC64LE-NEXT: addis 6, 2, .LCPI163_0@toc@ha ; PC64LE-NEXT: addis 6, 2, .LCPI163_0@toc@ha
; PC64LE-NEXT: mtfprd 1, 4 ; PC64LE-NEXT: mtfprd 1, 4
; PC64LE-NEXT: addi 3, 6, .LCPI163_0@toc@l ; PC64LE-NEXT: addi 3, 6, .LCPI163_0@toc@l
; PC64LE-NEXT: xscvsxdsp 0, 0 ; PC64LE-NEXT: xscvsxdsp 0, 0
; PC64LE-NEXT: lvx 4, 0, 3
; PC64LE-NEXT: xscvsxdsp 1, 1 ; PC64LE-NEXT: xscvsxdsp 1, 1
; PC64LE-NEXT: mtfprd 2, 5 ; PC64LE-NEXT: mtfprd 2, 5
; PC64LE-NEXT: xscvsxdsp 2, 2 ; PC64LE-NEXT: xscvsxdsp 2, 2
; PC64LE-NEXT: xscvdpspn 0, 0 ; PC64LE-NEXT: xscvdpspn 0, 0
; PC64LE-NEXT: xscvdpspn 1, 1 ; PC64LE-NEXT: xscvdpspn 1, 1
; PC64LE-NEXT: xscvdpspn 34, 2 ; PC64LE-NEXT: xscvdpspn 34, 2
; PC64LE-NEXT: lxvd2x 2, 0, 3
; PC64LE-NEXT: xxmrghw 35, 1, 0 ; PC64LE-NEXT: xxmrghw 35, 1, 0
; PC64LE-NEXT: xxswapd 36, 2
; PC64LE-NEXT: vperm 2, 2, 3, 4 ; PC64LE-NEXT: vperm 2, 2, 3, 4
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_sitofp_v3f32_v3i64: ; PC64LE9-LABEL: constrained_vector_sitofp_v3f32_v3i64:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: mtfprd 0, 3 ; PC64LE9-NEXT: mtfprd 0, 3
; PC64LE9-NEXT: mtfprd 1, 4 ; PC64LE9-NEXT: mtfprd 1, 4
; PC64LE9-NEXT: addis 3, 2, .LCPI163_0@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI163_0@toc@ha
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} }
define <2 x double> @constrained_vector_uitofp_v2f64_v2i16(<2 x i16> %x) #0 { define <2 x double> @constrained_vector_uitofp_v2f64_v2i16(<2 x i16> %x) #0 {
; PC64LE-LABEL: constrained_vector_uitofp_v2f64_v2i16: ; PC64LE-LABEL: constrained_vector_uitofp_v2f64_v2i16:
; PC64LE: # %bb.0: # %entry ; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: addis 3, 2, .LCPI173_0@toc@ha ; PC64LE-NEXT: addis 3, 2, .LCPI173_0@toc@ha
; PC64LE-NEXT: xxlxor 36, 36, 36 ; PC64LE-NEXT: xxlxor 36, 36, 36
; PC64LE-NEXT: addi 3, 3, .LCPI173_0@toc@l ; PC64LE-NEXT: addi 3, 3, .LCPI173_0@toc@l
; PC64LE-NEXT: lvx 3, 0, 3 ; PC64LE-NEXT: lxvd2x 0, 0, 3
; PC64LE-NEXT: xxswapd 35, 0
; PC64LE-NEXT: vperm 2, 4, 2, 3 ; PC64LE-NEXT: vperm 2, 4, 2, 3
; PC64LE-NEXT: xvcvuxddp 34, 34 ; PC64LE-NEXT: xvcvuxddp 34, 34
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_uitofp_v2f64_v2i16: ; PC64LE9-LABEL: constrained_vector_uitofp_v2f64_v2i16:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: addis 3, 2, .LCPI173_0@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI173_0@toc@ha
; PC64LE9-NEXT: xxlxor 36, 36, 36 ; PC64LE9-NEXT: xxlxor 36, 36, 36
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define <3 x float> @constrained_vector_uitofp_v3f32_v3i32(<3 x i32> %x) #0 { define <3 x float> @constrained_vector_uitofp_v3f32_v3i32(<3 x i32> %x) #0 {
; PC64LE-LABEL: constrained_vector_uitofp_v3f32_v3i32: ; PC64LE-LABEL: constrained_vector_uitofp_v3f32_v3i32:
; PC64LE: # %bb.0: # %entry ; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: xxswapd 0, 34 ; PC64LE-NEXT: xxswapd 0, 34
; PC64LE-NEXT: xxsldwi 1, 34, 34, 1 ; PC64LE-NEXT: xxsldwi 1, 34, 34, 1
; PC64LE-NEXT: addis 3, 2, .LCPI179_0@toc@ha ; PC64LE-NEXT: addis 3, 2, .LCPI179_0@toc@ha
; PC64LE-NEXT: addi 3, 3, .LCPI179_0@toc@l ; PC64LE-NEXT: addi 3, 3, .LCPI179_0@toc@l
; PC64LE-NEXT: lvx 4, 0, 3 ; PC64LE-NEXT: lxvd2x 3, 0, 3
; PC64LE-NEXT: mffprwz 4, 0 ; PC64LE-NEXT: mffprwz 4, 0
; PC64LE-NEXT: mffprwz 5, 1 ; PC64LE-NEXT: mffprwz 5, 1
; PC64LE-NEXT: mtfprwz 0, 4 ; PC64LE-NEXT: mtfprwz 0, 4
; PC64LE-NEXT: xxswapd 36, 3
; PC64LE-NEXT: mtfprwz 1, 5 ; PC64LE-NEXT: mtfprwz 1, 5
; PC64LE-NEXT: mfvsrwz 4, 34 ; PC64LE-NEXT: mfvsrwz 4, 34
; PC64LE-NEXT: xscvuxdsp 0, 0 ; PC64LE-NEXT: xscvuxdsp 0, 0
; PC64LE-NEXT: xscvuxdsp 1, 1 ; PC64LE-NEXT: xscvuxdsp 1, 1
; PC64LE-NEXT: mtfprwz 2, 4 ; PC64LE-NEXT: mtfprwz 2, 4
; PC64LE-NEXT: xscvuxdsp 2, 2 ; PC64LE-NEXT: xscvuxdsp 2, 2
; PC64LE-NEXT: xscvdpspn 0, 0 ; PC64LE-NEXT: xscvdpspn 0, 0
; PC64LE-NEXT: xscvdpspn 1, 1 ; PC64LE-NEXT: xscvdpspn 1, 1
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define <3 x float> @constrained_vector_uitofp_v3f32_v3i64(<3 x i64> %x) #0 { define <3 x float> @constrained_vector_uitofp_v3f32_v3i64(<3 x i64> %x) #0 {
; PC64LE-LABEL: constrained_vector_uitofp_v3f32_v3i64: ; PC64LE-LABEL: constrained_vector_uitofp_v3f32_v3i64:
; PC64LE: # %bb.0: # %entry ; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: mtfprd 0, 3 ; PC64LE-NEXT: mtfprd 0, 3
; PC64LE-NEXT: addis 6, 2, .LCPI181_0@toc@ha ; PC64LE-NEXT: addis 6, 2, .LCPI181_0@toc@ha
; PC64LE-NEXT: mtfprd 1, 4 ; PC64LE-NEXT: mtfprd 1, 4
; PC64LE-NEXT: addi 3, 6, .LCPI181_0@toc@l ; PC64LE-NEXT: addi 3, 6, .LCPI181_0@toc@l
; PC64LE-NEXT: xscvuxdsp 0, 0 ; PC64LE-NEXT: xscvuxdsp 0, 0
; PC64LE-NEXT: lvx 4, 0, 3
; PC64LE-NEXT: xscvuxdsp 1, 1 ; PC64LE-NEXT: xscvuxdsp 1, 1
; PC64LE-NEXT: mtfprd 2, 5 ; PC64LE-NEXT: mtfprd 2, 5
; PC64LE-NEXT: xscvuxdsp 2, 2 ; PC64LE-NEXT: xscvuxdsp 2, 2
; PC64LE-NEXT: xscvdpspn 0, 0 ; PC64LE-NEXT: xscvdpspn 0, 0
; PC64LE-NEXT: xscvdpspn 1, 1 ; PC64LE-NEXT: xscvdpspn 1, 1
; PC64LE-NEXT: xscvdpspn 34, 2 ; PC64LE-NEXT: xscvdpspn 34, 2
; PC64LE-NEXT: lxvd2x 2, 0, 3
; PC64LE-NEXT: xxmrghw 35, 1, 0 ; PC64LE-NEXT: xxmrghw 35, 1, 0
; PC64LE-NEXT: xxswapd 36, 2
; PC64LE-NEXT: vperm 2, 2, 3, 4 ; PC64LE-NEXT: vperm 2, 2, 3, 4
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_uitofp_v3f32_v3i64: ; PC64LE9-LABEL: constrained_vector_uitofp_v3f32_v3i64:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: mtfprd 0, 3 ; PC64LE9-NEXT: mtfprd 0, 3
; PC64LE9-NEXT: mtfprd 1, 4 ; PC64LE9-NEXT: mtfprd 1, 4
; PC64LE9-NEXT: addis 3, 2, .LCPI181_0@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI181_0@toc@ha
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llvm/test/CodeGen/PowerPC/vector-ldst.ll

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define dso_local <16 x i8> @ld_0_vector(i64 %ptr) { define dso_local <16 x i8> @ld_0_vector(i64 %ptr) {
; CHECK-LABEL: ld_0_vector: ; CHECK-LABEL: ld_0_vector:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lxv v2, 0(r3) ; CHECK-NEXT: lxv v2, 0(r3)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LE-LABEL: ld_0_vector: ; CHECK-P8-LE-LABEL: ld_0_vector:
; CHECK-P8-LE: # %bb.0: # %entry ; CHECK-P8-LE: # %bb.0: # %entry
; CHECK-P8-LE-NEXT: lvx v2, 0, r3 ; CHECK-P8-LE-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-LE-NEXT: xxswapd v2, vs0
; CHECK-P8-LE-NEXT: blr ; CHECK-P8-LE-NEXT: blr
; ;
; CHECK-P8-BE-LABEL: ld_0_vector: ; CHECK-P8-BE-LABEL: ld_0_vector:
; CHECK-P8-BE: # %bb.0: # %entry ; CHECK-P8-BE: # %bb.0: # %entry
; CHECK-P8-BE-NEXT: lxvw4x v2, 0, r3 ; CHECK-P8-BE-NEXT: lxvw4x v2, 0, r3
; CHECK-P8-BE-NEXT: blr ; CHECK-P8-BE-NEXT: blr
entry: entry:
%0 = inttoptr i64 %ptr to <16 x i8>* %0 = inttoptr i64 %ptr to <16 x i8>*
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; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: li r4, 1 ; CHECK-P9-NEXT: li r4, 1
; CHECK-P9-NEXT: lxvx v2, r3, r4 ; CHECK-P9-NEXT: lxvx v2, r3, r4
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-P8-LE-LABEL: ld_unalign16_vector: ; CHECK-P8-LE-LABEL: ld_unalign16_vector:
; CHECK-P8-LE: # %bb.0: # %entry ; CHECK-P8-LE: # %bb.0: # %entry
; CHECK-P8-LE-NEXT: addi r3, r3, 1 ; CHECK-P8-LE-NEXT: addi r3, r3, 1
; CHECK-P8-LE-NEXT: lvx v2, 0, r3 ; CHECK-P8-LE-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-LE-NEXT: xxswapd v2, vs0
; CHECK-P8-LE-NEXT: blr ; CHECK-P8-LE-NEXT: blr
; ;
; CHECK-P8-BE-LABEL: ld_unalign16_vector: ; CHECK-P8-BE-LABEL: ld_unalign16_vector:
; CHECK-P8-BE: # %bb.0: # %entry ; CHECK-P8-BE: # %bb.0: # %entry
; CHECK-P8-BE-NEXT: addi r3, r3, 1 ; CHECK-P8-BE-NEXT: addi r3, r3, 1
; CHECK-P8-BE-NEXT: lxvw4x v2, 0, r3 ; CHECK-P8-BE-NEXT: lxvw4x v2, 0, r3
; CHECK-P8-BE-NEXT: blr ; CHECK-P8-BE-NEXT: blr
entry: entry:
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; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: li r4, 8 ; CHECK-P9-NEXT: li r4, 8
; CHECK-P9-NEXT: lxvx v2, r3, r4 ; CHECK-P9-NEXT: lxvx v2, r3, r4
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-P8-LE-LABEL: ld_align16_vector: ; CHECK-P8-LE-LABEL: ld_align16_vector:
; CHECK-P8-LE: # %bb.0: # %entry ; CHECK-P8-LE: # %bb.0: # %entry
; CHECK-P8-LE-NEXT: addi r3, r3, 8 ; CHECK-P8-LE-NEXT: addi r3, r3, 8
; CHECK-P8-LE-NEXT: lvx v2, 0, r3 ; CHECK-P8-LE-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-LE-NEXT: xxswapd v2, vs0
; CHECK-P8-LE-NEXT: blr ; CHECK-P8-LE-NEXT: blr
; ;
; CHECK-P8-BE-LABEL: ld_align16_vector: ; CHECK-P8-BE-LABEL: ld_align16_vector:
; CHECK-P8-BE: # %bb.0: # %entry ; CHECK-P8-BE: # %bb.0: # %entry
; CHECK-P8-BE-NEXT: addi r3, r3, 8 ; CHECK-P8-BE-NEXT: addi r3, r3, 8
; CHECK-P8-BE-NEXT: lxvw4x v2, 0, r3 ; CHECK-P8-BE-NEXT: lxvw4x v2, 0, r3
; CHECK-P8-BE-NEXT: blr ; CHECK-P8-BE-NEXT: blr
entry: entry:
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; CHECK-P9-NEXT: ori r4, r4, 34463 ; CHECK-P9-NEXT: ori r4, r4, 34463
; CHECK-P9-NEXT: lxvx v2, r3, r4 ; CHECK-P9-NEXT: lxvx v2, r3, r4
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-P8-LE-LABEL: ld_unalign32_vector: ; CHECK-P8-LE-LABEL: ld_unalign32_vector:
; CHECK-P8-LE: # %bb.0: # %entry ; CHECK-P8-LE: # %bb.0: # %entry
; CHECK-P8-LE-NEXT: lis r4, 1 ; CHECK-P8-LE-NEXT: lis r4, 1
; CHECK-P8-LE-NEXT: ori r4, r4, 34463 ; CHECK-P8-LE-NEXT: ori r4, r4, 34463
; CHECK-P8-LE-NEXT: lvx v2, r3, r4 ; CHECK-P8-LE-NEXT: lxvd2x vs0, r3, r4
; CHECK-P8-LE-NEXT: xxswapd v2, vs0
; CHECK-P8-LE-NEXT: blr ; CHECK-P8-LE-NEXT: blr
; ;
; CHECK-P8-BE-LABEL: ld_unalign32_vector: ; CHECK-P8-BE-LABEL: ld_unalign32_vector:
; CHECK-P8-BE: # %bb.0: # %entry ; CHECK-P8-BE: # %bb.0: # %entry
; CHECK-P8-BE-NEXT: lis r4, 1 ; CHECK-P8-BE-NEXT: lis r4, 1
; CHECK-P8-BE-NEXT: ori r4, r4, 34463 ; CHECK-P8-BE-NEXT: ori r4, r4, 34463
; CHECK-P8-BE-NEXT: lxvw4x v2, r3, r4 ; CHECK-P8-BE-NEXT: lxvw4x v2, r3, r4
; CHECK-P8-BE-NEXT: blr ; CHECK-P8-BE-NEXT: blr
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; CHECK-P9-NEXT: ori r4, r4, 56600 ; CHECK-P9-NEXT: ori r4, r4, 56600
; CHECK-P9-NEXT: lxvx v2, r3, r4 ; CHECK-P9-NEXT: lxvx v2, r3, r4
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-P8-LE-LABEL: ld_align32_vector: ; CHECK-P8-LE-LABEL: ld_align32_vector:
; CHECK-P8-LE: # %bb.0: # %entry ; CHECK-P8-LE: # %bb.0: # %entry
; CHECK-P8-LE-NEXT: lis r4, 1525 ; CHECK-P8-LE-NEXT: lis r4, 1525
; CHECK-P8-LE-NEXT: ori r4, r4, 56600 ; CHECK-P8-LE-NEXT: ori r4, r4, 56600
; CHECK-P8-LE-NEXT: lvx v2, r3, r4 ; CHECK-P8-LE-NEXT: lxvd2x vs0, r3, r4
; CHECK-P8-LE-NEXT: xxswapd v2, vs0
; CHECK-P8-LE-NEXT: blr ; CHECK-P8-LE-NEXT: blr
; ;
; CHECK-P8-BE-LABEL: ld_align32_vector: ; CHECK-P8-BE-LABEL: ld_align32_vector:
; CHECK-P8-BE: # %bb.0: # %entry ; CHECK-P8-BE: # %bb.0: # %entry
; CHECK-P8-BE-NEXT: lis r4, 1525 ; CHECK-P8-BE-NEXT: lis r4, 1525
; CHECK-P8-BE-NEXT: ori r4, r4, 56600 ; CHECK-P8-BE-NEXT: ori r4, r4, 56600
; CHECK-P8-BE-NEXT: lxvw4x v2, r3, r4 ; CHECK-P8-BE-NEXT: lxvw4x v2, r3, r4
; CHECK-P8-BE-NEXT: blr ; CHECK-P8-BE-NEXT: blr
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; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-P8-LE-LABEL: ld_unalign64_vector: ; CHECK-P8-LE-LABEL: ld_unalign64_vector:
; CHECK-P8-LE: # %bb.0: # %entry ; CHECK-P8-LE: # %bb.0: # %entry
; CHECK-P8-LE-NEXT: li r4, 29 ; CHECK-P8-LE-NEXT: li r4, 29
; CHECK-P8-LE-NEXT: rldic r4, r4, 35, 24 ; CHECK-P8-LE-NEXT: rldic r4, r4, 35, 24
; CHECK-P8-LE-NEXT: oris r4, r4, 54437 ; CHECK-P8-LE-NEXT: oris r4, r4, 54437
; CHECK-P8-LE-NEXT: ori r4, r4, 4097 ; CHECK-P8-LE-NEXT: ori r4, r4, 4097
; CHECK-P8-LE-NEXT: lvx v2, r3, r4 ; CHECK-P8-LE-NEXT: lxvd2x vs0, r3, r4
; CHECK-P8-LE-NEXT: xxswapd v2, vs0
; CHECK-P8-LE-NEXT: blr ; CHECK-P8-LE-NEXT: blr
; ;
; CHECK-P8-BE-LABEL: ld_unalign64_vector: ; CHECK-P8-BE-LABEL: ld_unalign64_vector:
; CHECK-P8-BE: # %bb.0: # %entry ; CHECK-P8-BE: # %bb.0: # %entry
; CHECK-P8-BE-NEXT: li r4, 29 ; CHECK-P8-BE-NEXT: li r4, 29
; CHECK-P8-BE-NEXT: rldic r4, r4, 35, 24 ; CHECK-P8-BE-NEXT: rldic r4, r4, 35, 24
; CHECK-P8-BE-NEXT: oris r4, r4, 54437 ; CHECK-P8-BE-NEXT: oris r4, r4, 54437
; CHECK-P8-BE-NEXT: ori r4, r4, 4097 ; CHECK-P8-BE-NEXT: ori r4, r4, 4097
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; CHECK-P9-NEXT: lxvx v2, r3, r4 ; CHECK-P9-NEXT: lxvx v2, r3, r4
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-P8-LE-LABEL: ld_align64_vector: ; CHECK-P8-LE-LABEL: ld_align64_vector:
; CHECK-P8-LE: # %bb.0: # %entry ; CHECK-P8-LE: # %bb.0: # %entry
; CHECK-P8-LE-NEXT: lis r4, 3725 ; CHECK-P8-LE-NEXT: lis r4, 3725
; CHECK-P8-LE-NEXT: ori r4, r4, 19025 ; CHECK-P8-LE-NEXT: ori r4, r4, 19025
; CHECK-P8-LE-NEXT: rldic r4, r4, 12, 24 ; CHECK-P8-LE-NEXT: rldic r4, r4, 12, 24
; CHECK-P8-LE-NEXT: lvx v2, r3, r4 ; CHECK-P8-LE-NEXT: lxvd2x vs0, r3, r4
; CHECK-P8-LE-NEXT: xxswapd v2, vs0
; CHECK-P8-LE-NEXT: blr ; CHECK-P8-LE-NEXT: blr
; ;
; CHECK-P8-BE-LABEL: ld_align64_vector: ; CHECK-P8-BE-LABEL: ld_align64_vector:
; CHECK-P8-BE: # %bb.0: # %entry ; CHECK-P8-BE: # %bb.0: # %entry
; CHECK-P8-BE-NEXT: lis r4, 3725 ; CHECK-P8-BE-NEXT: lis r4, 3725
; CHECK-P8-BE-NEXT: ori r4, r4, 19025 ; CHECK-P8-BE-NEXT: ori r4, r4, 19025
; CHECK-P8-BE-NEXT: rldic r4, r4, 12, 24 ; CHECK-P8-BE-NEXT: rldic r4, r4, 12, 24
; CHECK-P8-BE-NEXT: lxvw4x v2, r3, r4 ; CHECK-P8-BE-NEXT: lxvw4x v2, r3, r4
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define dso_local <16 x i8> @ld_reg_vector(i8* nocapture readonly %ptr, i64 %off) { define dso_local <16 x i8> @ld_reg_vector(i8* nocapture readonly %ptr, i64 %off) {
; CHECK-LABEL: ld_reg_vector: ; CHECK-LABEL: ld_reg_vector:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lxvx v2, r3, r4 ; CHECK-NEXT: lxvx v2, r3, r4
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LE-LABEL: ld_reg_vector: ; CHECK-P8-LE-LABEL: ld_reg_vector:
; CHECK-P8-LE: # %bb.0: # %entry ; CHECK-P8-LE: # %bb.0: # %entry
; CHECK-P8-LE-NEXT: lvx v2, r3, r4 ; CHECK-P8-LE-NEXT: lxvd2x vs0, r3, r4
; CHECK-P8-LE-NEXT: xxswapd v2, vs0
; CHECK-P8-LE-NEXT: blr ; CHECK-P8-LE-NEXT: blr
; ;
; CHECK-P8-BE-LABEL: ld_reg_vector: ; CHECK-P8-BE-LABEL: ld_reg_vector:
; CHECK-P8-BE: # %bb.0: # %entry ; CHECK-P8-BE: # %bb.0: # %entry
; CHECK-P8-BE-NEXT: lxvw4x v2, r3, r4 ; CHECK-P8-BE-NEXT: lxvw4x v2, r3, r4
; CHECK-P8-BE-NEXT: blr ; CHECK-P8-BE-NEXT: blr
entry: entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off
%0 = bitcast i8* %add.ptr to <16 x i8>* %0 = bitcast i8* %add.ptr to <16 x i8>*
%1 = load <16 x i8>, <16 x i8>* %0, align 16 %1 = load <16 x i8>, <16 x i8>* %0, align 16
ret <16 x i8> %1 ret <16 x i8> %1
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local <16 x i8> @ld_or_vector(i64 %ptr, i8 zeroext %off) { define dso_local <16 x i8> @ld_or_vector(i64 %ptr, i8 zeroext %off) {
; CHECK-LABEL: ld_or_vector: ; CHECK-LABEL: ld_or_vector:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: or r3, r4, r3 ; CHECK-NEXT: or r3, r4, r3
; CHECK-NEXT: lxv v2, 0(r3) ; CHECK-NEXT: lxv v2, 0(r3)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LE-LABEL: ld_or_vector: ; CHECK-P8-LE-LABEL: ld_or_vector:
; CHECK-P8-LE: # %bb.0: # %entry ; CHECK-P8-LE: # %bb.0: # %entry
; CHECK-P8-LE-NEXT: or r3, r4, r3 ; CHECK-P8-LE-NEXT: or r3, r4, r3
; CHECK-P8-LE-NEXT: lvx v2, 0, r3 ; CHECK-P8-LE-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-LE-NEXT: xxswapd v2, vs0
; CHECK-P8-LE-NEXT: blr ; CHECK-P8-LE-NEXT: blr
; ;
; CHECK-P8-BE-LABEL: ld_or_vector: ; CHECK-P8-BE-LABEL: ld_or_vector:
; CHECK-P8-BE: # %bb.0: # %entry ; CHECK-P8-BE: # %bb.0: # %entry
; CHECK-P8-BE-NEXT: or r3, r4, r3 ; CHECK-P8-BE-NEXT: or r3, r4, r3
; CHECK-P8-BE-NEXT: lxvw4x v2, 0, r3 ; CHECK-P8-BE-NEXT: lxvw4x v2, 0, r3
; CHECK-P8-BE-NEXT: blr ; CHECK-P8-BE-NEXT: blr
entry: entry:
Show All 10 Lines
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: rldicr r3, r3, 0, 51 ; CHECK-NEXT: rldicr r3, r3, 0, 51
; CHECK-NEXT: lxvx v2, r3, r4 ; CHECK-NEXT: lxvx v2, r3, r4
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LE-LABEL: ld_or2_vector: ; CHECK-P8-LE-LABEL: ld_or2_vector:
; CHECK-P8-LE: # %bb.0: # %entry ; CHECK-P8-LE: # %bb.0: # %entry
; CHECK-P8-LE-NEXT: rldicr r3, r3, 0, 51 ; CHECK-P8-LE-NEXT: rldicr r3, r3, 0, 51
; CHECK-P8-LE-NEXT: lvx v2, r3, r4 ; CHECK-P8-LE-NEXT: lxvd2x vs0, r3, r4
; CHECK-P8-LE-NEXT: xxswapd v2, vs0
; CHECK-P8-LE-NEXT: blr ; CHECK-P8-LE-NEXT: blr
; ;
; CHECK-P8-BE-LABEL: ld_or2_vector: ; CHECK-P8-BE-LABEL: ld_or2_vector:
; CHECK-P8-BE: # %bb.0: # %entry ; CHECK-P8-BE: # %bb.0: # %entry
; CHECK-P8-BE-NEXT: rldicr r3, r3, 0, 51 ; CHECK-P8-BE-NEXT: rldicr r3, r3, 0, 51
; CHECK-P8-BE-NEXT: lxvw4x v2, r3, r4 ; CHECK-P8-BE-NEXT: lxvw4x v2, r3, r4
; CHECK-P8-BE-NEXT: blr ; CHECK-P8-BE-NEXT: blr
entry: entry:
Show All 11 Lines
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: ori r3, r3, 6 ; CHECK-NEXT: ori r3, r3, 6
; CHECK-NEXT: lxv v2, 0(r3) ; CHECK-NEXT: lxv v2, 0(r3)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LE-LABEL: ld_not_disjoint16_vector: ; CHECK-P8-LE-LABEL: ld_not_disjoint16_vector:
; CHECK-P8-LE: # %bb.0: # %entry ; CHECK-P8-LE: # %bb.0: # %entry
; CHECK-P8-LE-NEXT: ori r3, r3, 6 ; CHECK-P8-LE-NEXT: ori r3, r3, 6
; CHECK-P8-LE-NEXT: lvx v2, 0, r3 ; CHECK-P8-LE-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-LE-NEXT: xxswapd v2, vs0
; CHECK-P8-LE-NEXT: blr ; CHECK-P8-LE-NEXT: blr
; ;
; CHECK-P8-BE-LABEL: ld_not_disjoint16_vector: ; CHECK-P8-BE-LABEL: ld_not_disjoint16_vector:
; CHECK-P8-BE: # %bb.0: # %entry ; CHECK-P8-BE: # %bb.0: # %entry
; CHECK-P8-BE-NEXT: ori r3, r3, 6 ; CHECK-P8-BE-NEXT: ori r3, r3, 6
; CHECK-P8-BE-NEXT: lxvw4x v2, 0, r3 ; CHECK-P8-BE-NEXT: lxvw4x v2, 0, r3
; CHECK-P8-BE-NEXT: blr ; CHECK-P8-BE-NEXT: blr
entry: entry:
Show All 17 Lines
; CHECK-P9-NEXT: li r4, 6 ; CHECK-P9-NEXT: li r4, 6
; CHECK-P9-NEXT: lxvx v2, r3, r4 ; CHECK-P9-NEXT: lxvx v2, r3, r4
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-P8-LE-LABEL: ld_disjoint_unalign16_vector: ; CHECK-P8-LE-LABEL: ld_disjoint_unalign16_vector:
; CHECK-P8-LE: # %bb.0: # %entry ; CHECK-P8-LE: # %bb.0: # %entry
; CHECK-P8-LE-NEXT: rldicr r3, r3, 0, 51 ; CHECK-P8-LE-NEXT: rldicr r3, r3, 0, 51
; CHECK-P8-LE-NEXT: ori r3, r3, 6 ; CHECK-P8-LE-NEXT: ori r3, r3, 6
; CHECK-P8-LE-NEXT: lvx v2, 0, r3 ; CHECK-P8-LE-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-LE-NEXT: xxswapd v2, vs0
; CHECK-P8-LE-NEXT: blr ; CHECK-P8-LE-NEXT: blr
; ;
; CHECK-P8-BE-LABEL: ld_disjoint_unalign16_vector: ; CHECK-P8-BE-LABEL: ld_disjoint_unalign16_vector:
; CHECK-P8-BE: # %bb.0: # %entry ; CHECK-P8-BE: # %bb.0: # %entry
; CHECK-P8-BE-NEXT: rldicr r3, r3, 0, 51 ; CHECK-P8-BE-NEXT: rldicr r3, r3, 0, 51
; CHECK-P8-BE-NEXT: ori r3, r3, 6 ; CHECK-P8-BE-NEXT: ori r3, r3, 6
; CHECK-P8-BE-NEXT: lxvw4x v2, 0, r3 ; CHECK-P8-BE-NEXT: lxvw4x v2, 0, r3
; CHECK-P8-BE-NEXT: blr ; CHECK-P8-BE-NEXT: blr
Show All 19 Lines
; CHECK-P9-NEXT: li r4, 24 ; CHECK-P9-NEXT: li r4, 24
; CHECK-P9-NEXT: lxvx v2, r3, r4 ; CHECK-P9-NEXT: lxvx v2, r3, r4
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-P8-LE-LABEL: ld_disjoint_align16_vector: ; CHECK-P8-LE-LABEL: ld_disjoint_align16_vector:
; CHECK-P8-LE: # %bb.0: # %entry ; CHECK-P8-LE: # %bb.0: # %entry
; CHECK-P8-LE-NEXT: rldicr r3, r3, 0, 51 ; CHECK-P8-LE-NEXT: rldicr r3, r3, 0, 51
; CHECK-P8-LE-NEXT: ori r3, r3, 24 ; CHECK-P8-LE-NEXT: ori r3, r3, 24
; CHECK-P8-LE-NEXT: lvx v2, 0, r3 ; CHECK-P8-LE-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-LE-NEXT: xxswapd v2, vs0
; CHECK-P8-LE-NEXT: blr ; CHECK-P8-LE-NEXT: blr
; ;
; CHECK-P8-BE-LABEL: ld_disjoint_align16_vector: ; CHECK-P8-BE-LABEL: ld_disjoint_align16_vector:
; CHECK-P8-BE: # %bb.0: # %entry ; CHECK-P8-BE: # %bb.0: # %entry
; CHECK-P8-BE-NEXT: rldicr r3, r3, 0, 51 ; CHECK-P8-BE-NEXT: rldicr r3, r3, 0, 51
; CHECK-P8-BE-NEXT: ori r3, r3, 24 ; CHECK-P8-BE-NEXT: ori r3, r3, 24
; CHECK-P8-BE-NEXT: lxvw4x v2, 0, r3 ; CHECK-P8-BE-NEXT: lxvw4x v2, 0, r3
; CHECK-P8-BE-NEXT: blr ; CHECK-P8-BE-NEXT: blr
Show All 13 Lines
; CHECK-NEXT: oris r3, r3, 1 ; CHECK-NEXT: oris r3, r3, 1
; CHECK-NEXT: lxv v2, 0(r3) ; CHECK-NEXT: lxv v2, 0(r3)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LE-LABEL: ld_not_disjoint32_vector: ; CHECK-P8-LE-LABEL: ld_not_disjoint32_vector:
; CHECK-P8-LE: # %bb.0: # %entry ; CHECK-P8-LE: # %bb.0: # %entry
; CHECK-P8-LE-NEXT: ori r3, r3, 34463 ; CHECK-P8-LE-NEXT: ori r3, r3, 34463
; CHECK-P8-LE-NEXT: oris r3, r3, 1 ; CHECK-P8-LE-NEXT: oris r3, r3, 1
; CHECK-P8-LE-NEXT: lvx v2, 0, r3 ; CHECK-P8-LE-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-LE-NEXT: xxswapd v2, vs0
; CHECK-P8-LE-NEXT: blr ; CHECK-P8-LE-NEXT: blr
; ;
; CHECK-P8-BE-LABEL: ld_not_disjoint32_vector: ; CHECK-P8-BE-LABEL: ld_not_disjoint32_vector:
; CHECK-P8-BE: # %bb.0: # %entry ; CHECK-P8-BE: # %bb.0: # %entry
; CHECK-P8-BE-NEXT: ori r3, r3, 34463 ; CHECK-P8-BE-NEXT: ori r3, r3, 34463
; CHECK-P8-BE-NEXT: oris r3, r3, 1 ; CHECK-P8-BE-NEXT: oris r3, r3, 1
; CHECK-P8-BE-NEXT: lxvw4x v2, 0, r3 ; CHECK-P8-BE-NEXT: lxvw4x v2, 0, r3
; CHECK-P8-BE-NEXT: blr ; CHECK-P8-BE-NEXT: blr
Show All 20 Lines
; CHECK-P9-NEXT: lxvx v2, r3, r4 ; CHECK-P9-NEXT: lxvx v2, r3, r4
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-P8-LE-LABEL: ld_disjoint_unalign32_vector: ; CHECK-P8-LE-LABEL: ld_disjoint_unalign32_vector:
; CHECK-P8-LE: # %bb.0: # %entry ; CHECK-P8-LE: # %bb.0: # %entry
; CHECK-P8-LE-NEXT: lis r4, 1 ; CHECK-P8-LE-NEXT: lis r4, 1
; CHECK-P8-LE-NEXT: rldicr r3, r3, 0, 43 ; CHECK-P8-LE-NEXT: rldicr r3, r3, 0, 43
; CHECK-P8-LE-NEXT: ori r4, r4, 34463 ; CHECK-P8-LE-NEXT: ori r4, r4, 34463
; CHECK-P8-LE-NEXT: lvx v2, r3, r4 ; CHECK-P8-LE-NEXT: lxvd2x vs0, r3, r4
; CHECK-P8-LE-NEXT: xxswapd v2, vs0
; CHECK-P8-LE-NEXT: blr ; CHECK-P8-LE-NEXT: blr
; ;
; CHECK-P8-BE-LABEL: ld_disjoint_unalign32_vector: ; CHECK-P8-BE-LABEL: ld_disjoint_unalign32_vector:
; CHECK-P8-BE: # %bb.0: # %entry ; CHECK-P8-BE: # %bb.0: # %entry
; CHECK-P8-BE-NEXT: lis r4, 1 ; CHECK-P8-BE-NEXT: lis r4, 1
; CHECK-P8-BE-NEXT: rldicr r3, r3, 0, 43 ; CHECK-P8-BE-NEXT: rldicr r3, r3, 0, 43
; CHECK-P8-BE-NEXT: ori r4, r4, 34463 ; CHECK-P8-BE-NEXT: ori r4, r4, 34463
; CHECK-P8-BE-NEXT: lxvw4x v2, r3, r4 ; CHECK-P8-BE-NEXT: lxvw4x v2, r3, r4
Show All 25 Lines
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-P8-LE-LABEL: ld_disjoint_align32_vector: ; CHECK-P8-LE-LABEL: ld_disjoint_align32_vector:
; CHECK-P8-LE: # %bb.0: # %entry ; CHECK-P8-LE: # %bb.0: # %entry
; CHECK-P8-LE-NEXT: lis r4, -15264 ; CHECK-P8-LE-NEXT: lis r4, -15264
; CHECK-P8-LE-NEXT: lis r5, 15258 ; CHECK-P8-LE-NEXT: lis r5, 15258
; CHECK-P8-LE-NEXT: and r3, r3, r4 ; CHECK-P8-LE-NEXT: and r3, r3, r4
; CHECK-P8-LE-NEXT: ori r4, r5, 41712 ; CHECK-P8-LE-NEXT: ori r4, r5, 41712
; CHECK-P8-LE-NEXT: lvx v2, r3, r4 ; CHECK-P8-LE-NEXT: lxvd2x vs0, r3, r4
; CHECK-P8-LE-NEXT: xxswapd v2, vs0
; CHECK-P8-LE-NEXT: blr ; CHECK-P8-LE-NEXT: blr
; ;
; CHECK-P8-BE-LABEL: ld_disjoint_align32_vector: ; CHECK-P8-BE-LABEL: ld_disjoint_align32_vector:
; CHECK-P8-BE: # %bb.0: # %entry ; CHECK-P8-BE: # %bb.0: # %entry
; CHECK-P8-BE-NEXT: lis r4, -15264 ; CHECK-P8-BE-NEXT: lis r4, -15264
; CHECK-P8-BE-NEXT: lis r5, 15258 ; CHECK-P8-BE-NEXT: lis r5, 15258
; CHECK-P8-BE-NEXT: and r3, r3, r4 ; CHECK-P8-BE-NEXT: and r3, r3, r4
; CHECK-P8-BE-NEXT: ori r4, r5, 41712 ; CHECK-P8-BE-NEXT: ori r4, r5, 41712
Show All 30 Lines
; ;
; CHECK-P8-LE-LABEL: ld_not_disjoint64_vector: ; CHECK-P8-LE-LABEL: ld_not_disjoint64_vector:
; CHECK-P8-LE: # %bb.0: # %entry ; CHECK-P8-LE: # %bb.0: # %entry
; CHECK-P8-LE-NEXT: li r4, 29 ; CHECK-P8-LE-NEXT: li r4, 29
; CHECK-P8-LE-NEXT: rldic r4, r4, 35, 24 ; CHECK-P8-LE-NEXT: rldic r4, r4, 35, 24
; CHECK-P8-LE-NEXT: oris r4, r4, 54437 ; CHECK-P8-LE-NEXT: oris r4, r4, 54437
; CHECK-P8-LE-NEXT: ori r4, r4, 4097 ; CHECK-P8-LE-NEXT: ori r4, r4, 4097
; CHECK-P8-LE-NEXT: or r3, r3, r4 ; CHECK-P8-LE-NEXT: or r3, r3, r4
; CHECK-P8-LE-NEXT: lvx v2, 0, r3 ; CHECK-P8-LE-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-LE-NEXT: xxswapd v2, vs0
; CHECK-P8-LE-NEXT: blr ; CHECK-P8-LE-NEXT: blr
; ;
; CHECK-P8-BE-LABEL: ld_not_disjoint64_vector: ; CHECK-P8-BE-LABEL: ld_not_disjoint64_vector:
; CHECK-P8-BE: # %bb.0: # %entry ; CHECK-P8-BE: # %bb.0: # %entry
; CHECK-P8-BE-NEXT: li r4, 29 ; CHECK-P8-BE-NEXT: li r4, 29
; CHECK-P8-BE-NEXT: rldic r4, r4, 35, 24 ; CHECK-P8-BE-NEXT: rldic r4, r4, 35, 24
; CHECK-P8-BE-NEXT: oris r4, r4, 54437 ; CHECK-P8-BE-NEXT: oris r4, r4, 54437
; CHECK-P8-BE-NEXT: ori r4, r4, 4097 ; CHECK-P8-BE-NEXT: ori r4, r4, 4097
Show All 30 Lines
; ;
; CHECK-P8-LE-LABEL: ld_disjoint_unalign64_vector: ; CHECK-P8-LE-LABEL: ld_disjoint_unalign64_vector:
; CHECK-P8-LE: # %bb.0: # %entry ; CHECK-P8-LE: # %bb.0: # %entry
; CHECK-P8-LE-NEXT: li r4, 29 ; CHECK-P8-LE-NEXT: li r4, 29
; CHECK-P8-LE-NEXT: rldicr r3, r3, 0, 23 ; CHECK-P8-LE-NEXT: rldicr r3, r3, 0, 23
; CHECK-P8-LE-NEXT: rldic r4, r4, 35, 24 ; CHECK-P8-LE-NEXT: rldic r4, r4, 35, 24
; CHECK-P8-LE-NEXT: oris r4, r4, 54437 ; CHECK-P8-LE-NEXT: oris r4, r4, 54437
; CHECK-P8-LE-NEXT: ori r4, r4, 4097 ; CHECK-P8-LE-NEXT: ori r4, r4, 4097
; CHECK-P8-LE-NEXT: lvx v2, r3, r4 ; CHECK-P8-LE-NEXT: lxvd2x vs0, r3, r4
; CHECK-P8-LE-NEXT: xxswapd v2, vs0
; CHECK-P8-LE-NEXT: blr ; CHECK-P8-LE-NEXT: blr
; ;
; CHECK-P8-BE-LABEL: ld_disjoint_unalign64_vector: ; CHECK-P8-BE-LABEL: ld_disjoint_unalign64_vector:
; CHECK-P8-BE: # %bb.0: # %entry ; CHECK-P8-BE: # %bb.0: # %entry
; CHECK-P8-BE-NEXT: li r4, 29 ; CHECK-P8-BE-NEXT: li r4, 29
; CHECK-P8-BE-NEXT: rldicr r3, r3, 0, 23 ; CHECK-P8-BE-NEXT: rldicr r3, r3, 0, 23
; CHECK-P8-BE-NEXT: rldic r4, r4, 35, 24 ; CHECK-P8-BE-NEXT: rldic r4, r4, 35, 24
; CHECK-P8-BE-NEXT: oris r4, r4, 54437 ; CHECK-P8-BE-NEXT: oris r4, r4, 54437
Show All 28 Lines
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-P8-LE-LABEL: ld_disjoint_align64_vector: ; CHECK-P8-LE-LABEL: ld_disjoint_align64_vector:
; CHECK-P8-LE: # %bb.0: # %entry ; CHECK-P8-LE: # %bb.0: # %entry
; CHECK-P8-LE-NEXT: lis r4, 3725 ; CHECK-P8-LE-NEXT: lis r4, 3725
; CHECK-P8-LE-NEXT: rldicr r3, r3, 0, 23 ; CHECK-P8-LE-NEXT: rldicr r3, r3, 0, 23
; CHECK-P8-LE-NEXT: ori r4, r4, 19025 ; CHECK-P8-LE-NEXT: ori r4, r4, 19025
; CHECK-P8-LE-NEXT: rldic r4, r4, 12, 24 ; CHECK-P8-LE-NEXT: rldic r4, r4, 12, 24
; CHECK-P8-LE-NEXT: lvx v2, r3, r4 ; CHECK-P8-LE-NEXT: lxvd2x vs0, r3, r4
; CHECK-P8-LE-NEXT: xxswapd v2, vs0
; CHECK-P8-LE-NEXT: blr ; CHECK-P8-LE-NEXT: blr
; ;
; CHECK-P8-BE-LABEL: ld_disjoint_align64_vector: ; CHECK-P8-BE-LABEL: ld_disjoint_align64_vector:
; CHECK-P8-BE: # %bb.0: # %entry ; CHECK-P8-BE: # %bb.0: # %entry
; CHECK-P8-BE-NEXT: lis r4, 3725 ; CHECK-P8-BE-NEXT: lis r4, 3725
; CHECK-P8-BE-NEXT: rldicr r3, r3, 0, 23 ; CHECK-P8-BE-NEXT: rldicr r3, r3, 0, 23
; CHECK-P8-BE-NEXT: ori r4, r4, 19025 ; CHECK-P8-BE-NEXT: ori r4, r4, 19025
; CHECK-P8-BE-NEXT: rldic r4, r4, 12, 24 ; CHECK-P8-BE-NEXT: rldic r4, r4, 12, 24
Show All 13 Lines
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: li r3, 255 ; CHECK-NEXT: li r3, 255
; CHECK-NEXT: lxv v2, 0(r3) ; CHECK-NEXT: lxv v2, 0(r3)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LE-LABEL: ld_cst_unalign16_vector: ; CHECK-P8-LE-LABEL: ld_cst_unalign16_vector:
; CHECK-P8-LE: # %bb.0: # %entry ; CHECK-P8-LE: # %bb.0: # %entry
; CHECK-P8-LE-NEXT: li r3, 255 ; CHECK-P8-LE-NEXT: li r3, 255
; CHECK-P8-LE-NEXT: lvx v2, 0, r3 ; CHECK-P8-LE-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-LE-NEXT: xxswapd v2, vs0
; CHECK-P8-LE-NEXT: blr ; CHECK-P8-LE-NEXT: blr
; ;
; CHECK-P8-BE-LABEL: ld_cst_unalign16_vector: ; CHECK-P8-BE-LABEL: ld_cst_unalign16_vector:
; CHECK-P8-BE: # %bb.0: # %entry ; CHECK-P8-BE: # %bb.0: # %entry
; CHECK-P8-BE-NEXT: li r3, 255 ; CHECK-P8-BE-NEXT: li r3, 255
; CHECK-P8-BE-NEXT: lxvw4x v2, 0, r3 ; CHECK-P8-BE-NEXT: lxvw4x v2, 0, r3
; CHECK-P8-BE-NEXT: blr ; CHECK-P8-BE-NEXT: blr
entry: entry:
%0 = load <16 x i8>, <16 x i8>* inttoptr (i64 255 to <16 x i8>*), align 16 %0 = load <16 x i8>, <16 x i8>* inttoptr (i64 255 to <16 x i8>*), align 16
ret <16 x i8> %0 ret <16 x i8> %0
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local <16 x i8> @ld_cst_align16_vector() { define dso_local <16 x i8> @ld_cst_align16_vector() {
; CHECK-LABEL: ld_cst_align16_vector: ; CHECK-LABEL: ld_cst_align16_vector:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lxv v2, 4080(0) ; CHECK-NEXT: lxv v2, 4080(0)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LE-LABEL: ld_cst_align16_vector: ; CHECK-P8-LE-LABEL: ld_cst_align16_vector:
; CHECK-P8-LE: # %bb.0: # %entry ; CHECK-P8-LE: # %bb.0: # %entry
; CHECK-P8-LE-NEXT: li r3, 4080 ; CHECK-P8-LE-NEXT: li r3, 4080
; CHECK-P8-LE-NEXT: lvx v2, 0, r3 ; CHECK-P8-LE-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-LE-NEXT: xxswapd v2, vs0
; CHECK-P8-LE-NEXT: blr ; CHECK-P8-LE-NEXT: blr
; ;
; CHECK-P8-BE-LABEL: ld_cst_align16_vector: ; CHECK-P8-BE-LABEL: ld_cst_align16_vector:
; CHECK-P8-BE: # %bb.0: # %entry ; CHECK-P8-BE: # %bb.0: # %entry
; CHECK-P8-BE-NEXT: li r3, 4080 ; CHECK-P8-BE-NEXT: li r3, 4080
; CHECK-P8-BE-NEXT: lxvw4x v2, 0, r3 ; CHECK-P8-BE-NEXT: lxvw4x v2, 0, r3
; CHECK-P8-BE-NEXT: blr ; CHECK-P8-BE-NEXT: blr
entry: entry:
Show All 15 Lines
; CHECK-P9-NEXT: ori r3, r3, 34463 ; CHECK-P9-NEXT: ori r3, r3, 34463
; CHECK-P9-NEXT: lxv v2, 0(r3) ; CHECK-P9-NEXT: lxv v2, 0(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-P8-LE-LABEL: ld_cst_unalign32_vector: ; CHECK-P8-LE-LABEL: ld_cst_unalign32_vector:
; CHECK-P8-LE: # %bb.0: # %entry ; CHECK-P8-LE: # %bb.0: # %entry
; CHECK-P8-LE-NEXT: lis r3, 1 ; CHECK-P8-LE-NEXT: lis r3, 1
; CHECK-P8-LE-NEXT: ori r3, r3, 34463 ; CHECK-P8-LE-NEXT: ori r3, r3, 34463
; CHECK-P8-LE-NEXT: lvx v2, 0, r3 ; CHECK-P8-LE-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-LE-NEXT: xxswapd v2, vs0
; CHECK-P8-LE-NEXT: blr ; CHECK-P8-LE-NEXT: blr
; ;
; CHECK-P8-BE-LABEL: ld_cst_unalign32_vector: ; CHECK-P8-BE-LABEL: ld_cst_unalign32_vector:
; CHECK-P8-BE: # %bb.0: # %entry ; CHECK-P8-BE: # %bb.0: # %entry
; CHECK-P8-BE-NEXT: lis r3, 1 ; CHECK-P8-BE-NEXT: lis r3, 1
; CHECK-P8-BE-NEXT: ori r3, r3, 34463 ; CHECK-P8-BE-NEXT: ori r3, r3, 34463
; CHECK-P8-BE-NEXT: lxvw4x v2, 0, r3 ; CHECK-P8-BE-NEXT: lxvw4x v2, 0, r3
; CHECK-P8-BE-NEXT: blr ; CHECK-P8-BE-NEXT: blr
Show All 16 Lines
; CHECK-P9-NEXT: ori r3, r3, 38428 ; CHECK-P9-NEXT: ori r3, r3, 38428
; CHECK-P9-NEXT: lxv v2, 0(r3) ; CHECK-P9-NEXT: lxv v2, 0(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-P8-LE-LABEL: ld_cst_align32_vector: ; CHECK-P8-LE-LABEL: ld_cst_align32_vector:
; CHECK-P8-LE: # %bb.0: # %entry ; CHECK-P8-LE: # %bb.0: # %entry
; CHECK-P8-LE-NEXT: lis r3, 152 ; CHECK-P8-LE-NEXT: lis r3, 152
; CHECK-P8-LE-NEXT: ori r3, r3, 38428 ; CHECK-P8-LE-NEXT: ori r3, r3, 38428
; CHECK-P8-LE-NEXT: lvx v2, 0, r3 ; CHECK-P8-LE-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-LE-NEXT: xxswapd v2, vs0
; CHECK-P8-LE-NEXT: blr ; CHECK-P8-LE-NEXT: blr
; ;
; CHECK-P8-BE-LABEL: ld_cst_align32_vector: ; CHECK-P8-BE-LABEL: ld_cst_align32_vector:
; CHECK-P8-BE: # %bb.0: # %entry ; CHECK-P8-BE: # %bb.0: # %entry
; CHECK-P8-BE-NEXT: lis r3, 152 ; CHECK-P8-BE-NEXT: lis r3, 152
; CHECK-P8-BE-NEXT: ori r3, r3, 38428 ; CHECK-P8-BE-NEXT: ori r3, r3, 38428
; CHECK-P8-BE-NEXT: lxvw4x v2, 0, r3 ; CHECK-P8-BE-NEXT: lxvw4x v2, 0, r3
; CHECK-P8-BE-NEXT: blr ; CHECK-P8-BE-NEXT: blr
Show All 22 Lines
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-P8-LE-LABEL: ld_cst_unalign64_vector: ; CHECK-P8-LE-LABEL: ld_cst_unalign64_vector:
; CHECK-P8-LE: # %bb.0: # %entry ; CHECK-P8-LE: # %bb.0: # %entry
; CHECK-P8-LE-NEXT: li r3, 29 ; CHECK-P8-LE-NEXT: li r3, 29
; CHECK-P8-LE-NEXT: rldic r3, r3, 35, 24 ; CHECK-P8-LE-NEXT: rldic r3, r3, 35, 24
; CHECK-P8-LE-NEXT: oris r3, r3, 54437 ; CHECK-P8-LE-NEXT: oris r3, r3, 54437
; CHECK-P8-LE-NEXT: ori r3, r3, 4097 ; CHECK-P8-LE-NEXT: ori r3, r3, 4097
; CHECK-P8-LE-NEXT: lvx v2, 0, r3 ; CHECK-P8-LE-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-LE-NEXT: xxswapd v2, vs0
; CHECK-P8-LE-NEXT: blr ; CHECK-P8-LE-NEXT: blr
; ;
; CHECK-P8-BE-LABEL: ld_cst_unalign64_vector: ; CHECK-P8-BE-LABEL: ld_cst_unalign64_vector:
; CHECK-P8-BE: # %bb.0: # %entry ; CHECK-P8-BE: # %bb.0: # %entry
; CHECK-P8-BE-NEXT: li r3, 29 ; CHECK-P8-BE-NEXT: li r3, 29
; CHECK-P8-BE-NEXT: rldic r3, r3, 35, 24 ; CHECK-P8-BE-NEXT: rldic r3, r3, 35, 24
; CHECK-P8-BE-NEXT: oris r3, r3, 54437 ; CHECK-P8-BE-NEXT: oris r3, r3, 54437
; CHECK-P8-BE-NEXT: ori r3, r3, 4097 ; CHECK-P8-BE-NEXT: ori r3, r3, 4097
Show All 21 Lines
; CHECK-P9-NEXT: lxv v2, 0(r3) ; CHECK-P9-NEXT: lxv v2, 0(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-P8-LE-LABEL: ld_cst_align64_vector: ; CHECK-P8-LE-LABEL: ld_cst_align64_vector:
; CHECK-P8-LE: # %bb.0: # %entry ; CHECK-P8-LE: # %bb.0: # %entry
; CHECK-P8-LE-NEXT: lis r3, 3725 ; CHECK-P8-LE-NEXT: lis r3, 3725
; CHECK-P8-LE-NEXT: ori r3, r3, 19025 ; CHECK-P8-LE-NEXT: ori r3, r3, 19025
; CHECK-P8-LE-NEXT: rldic r3, r3, 12, 24 ; CHECK-P8-LE-NEXT: rldic r3, r3, 12, 24
; CHECK-P8-LE-NEXT: lvx v2, 0, r3 ; CHECK-P8-LE-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-LE-NEXT: xxswapd v2, vs0
; CHECK-P8-LE-NEXT: blr ; CHECK-P8-LE-NEXT: blr
; ;
; CHECK-P8-BE-LABEL: ld_cst_align64_vector: ; CHECK-P8-BE-LABEL: ld_cst_align64_vector:
; CHECK-P8-BE: # %bb.0: # %entry ; CHECK-P8-BE: # %bb.0: # %entry
; CHECK-P8-BE-NEXT: lis r3, 3725 ; CHECK-P8-BE-NEXT: lis r3, 3725
; CHECK-P8-BE-NEXT: ori r3, r3, 19025 ; CHECK-P8-BE-NEXT: ori r3, r3, 19025
; CHECK-P8-BE-NEXT: rldic r3, r3, 12, 24 ; CHECK-P8-BE-NEXT: rldic r3, r3, 12, 24
; CHECK-P8-BE-NEXT: lxvw4x v2, 0, r3 ; CHECK-P8-BE-NEXT: lxvw4x v2, 0, r3
; CHECK-P8-BE-NEXT: blr ; CHECK-P8-BE-NEXT: blr
entry: entry:
%0 = load <16 x i8>, <16 x i8>* inttoptr (i64 1000000000000 to <16 x i8>*), align 4096 %0 = load <16 x i8>, <16 x i8>* inttoptr (i64 1000000000000 to <16 x i8>*), align 4096
ret <16 x i8> %0 ret <16 x i8> %0
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_0_vector(i64 %ptr, <16 x i8> %str) { define dso_local void @st_0_vector(i64 %ptr, <16 x i8> %str) {
; CHECK-LABEL: st_0_vector: ; CHECK-LABEL: st_0_vector:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: stxv v2, 0(r3) ; CHECK-NEXT: stxv v2, 0(r3)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LE-LABEL: st_0_vector: ; CHECK-P8-LE-LABEL: st_0_vector:
; CHECK-P8-LE: # %bb.0: # %entry ; CHECK-P8-LE: # %bb.0: # %entry
; CHECK-P8-LE-NEXT: stvx v2, 0, r3 ; CHECK-P8-LE-NEXT: xxswapd vs0, v2
; CHECK-P8-LE-NEXT: stxvd2x vs0, 0, r3
; CHECK-P8-LE-NEXT: blr ; CHECK-P8-LE-NEXT: blr
; ;
; CHECK-P8-BE-LABEL: st_0_vector: ; CHECK-P8-BE-LABEL: st_0_vector:
; CHECK-P8-BE: # %bb.0: # %entry ; CHECK-P8-BE: # %bb.0: # %entry
; CHECK-P8-BE-NEXT: stxvw4x v2, 0, r3 ; CHECK-P8-BE-NEXT: stxvw4x v2, 0, r3
; CHECK-P8-BE-NEXT: blr ; CHECK-P8-BE-NEXT: blr
entry: entry:
%0 = inttoptr i64 %ptr to <16 x i8>* %0 = inttoptr i64 %ptr to <16 x i8>*
Show All 11 Lines
; CHECK-P9-LABEL: st_unalign16_vector: ; CHECK-P9-LABEL: st_unalign16_vector:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: li r4, 1 ; CHECK-P9-NEXT: li r4, 1
; CHECK-P9-NEXT: stxvx v2, r3, r4 ; CHECK-P9-NEXT: stxvx v2, r3, r4
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-P8-LE-LABEL: st_unalign16_vector: ; CHECK-P8-LE-LABEL: st_unalign16_vector:
; CHECK-P8-LE: # %bb.0: # %entry ; CHECK-P8-LE: # %bb.0: # %entry
; CHECK-P8-LE-NEXT: xxswapd vs0, v2
; CHECK-P8-LE-NEXT: addi r3, r3, 1 ; CHECK-P8-LE-NEXT: addi r3, r3, 1
; CHECK-P8-LE-NEXT: stvx v2, 0, r3 ; CHECK-P8-LE-NEXT: stxvd2x vs0, 0, r3
; CHECK-P8-LE-NEXT: blr ; CHECK-P8-LE-NEXT: blr
; ;
; CHECK-P8-BE-LABEL: st_unalign16_vector: ; CHECK-P8-BE-LABEL: st_unalign16_vector:
; CHECK-P8-BE: # %bb.0: # %entry ; CHECK-P8-BE: # %bb.0: # %entry
; CHECK-P8-BE-NEXT: addi r3, r3, 1 ; CHECK-P8-BE-NEXT: addi r3, r3, 1
; CHECK-P8-BE-NEXT: stxvw4x v2, 0, r3 ; CHECK-P8-BE-NEXT: stxvw4x v2, 0, r3
; CHECK-P8-BE-NEXT: blr ; CHECK-P8-BE-NEXT: blr
entry: entry:
Show All 13 Lines
; CHECK-P9-LABEL: st_align16_vector: ; CHECK-P9-LABEL: st_align16_vector:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: li r4, 8 ; CHECK-P9-NEXT: li r4, 8
; CHECK-P9-NEXT: stxvx v2, r3, r4 ; CHECK-P9-NEXT: stxvx v2, r3, r4
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-P8-LE-LABEL: st_align16_vector: ; CHECK-P8-LE-LABEL: st_align16_vector:
; CHECK-P8-LE: # %bb.0: # %entry ; CHECK-P8-LE: # %bb.0: # %entry
; CHECK-P8-LE-NEXT: xxswapd vs0, v2
; CHECK-P8-LE-NEXT: addi r3, r3, 8 ; CHECK-P8-LE-NEXT: addi r3, r3, 8
; CHECK-P8-LE-NEXT: stvx v2, 0, r3 ; CHECK-P8-LE-NEXT: stxvd2x vs0, 0, r3
; CHECK-P8-LE-NEXT: blr ; CHECK-P8-LE-NEXT: blr
; ;
; CHECK-P8-BE-LABEL: st_align16_vector: ; CHECK-P8-BE-LABEL: st_align16_vector:
; CHECK-P8-BE: # %bb.0: # %entry ; CHECK-P8-BE: # %bb.0: # %entry
; CHECK-P8-BE-NEXT: addi r3, r3, 8 ; CHECK-P8-BE-NEXT: addi r3, r3, 8
; CHECK-P8-BE-NEXT: stxvw4x v2, 0, r3 ; CHECK-P8-BE-NEXT: stxvw4x v2, 0, r3
; CHECK-P8-BE-NEXT: blr ; CHECK-P8-BE-NEXT: blr
entry: entry:
Show All 14 Lines
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lis r4, 1 ; CHECK-P9-NEXT: lis r4, 1
; CHECK-P9-NEXT: ori r4, r4, 34463 ; CHECK-P9-NEXT: ori r4, r4, 34463
; CHECK-P9-NEXT: stxvx v2, r3, r4 ; CHECK-P9-NEXT: stxvx v2, r3, r4
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-P8-LE-LABEL: st_unalign32_vector: ; CHECK-P8-LE-LABEL: st_unalign32_vector:
; CHECK-P8-LE: # %bb.0: # %entry ; CHECK-P8-LE: # %bb.0: # %entry
; CHECK-P8-LE-NEXT: xxswapd vs0, v2
; CHECK-P8-LE-NEXT: lis r4, 1 ; CHECK-P8-LE-NEXT: lis r4, 1
; CHECK-P8-LE-NEXT: ori r4, r4, 34463 ; CHECK-P8-LE-NEXT: ori r4, r4, 34463
; CHECK-P8-LE-NEXT: stvx v2, r3, r4 ; CHECK-P8-LE-NEXT: stxvd2x vs0, r3, r4
; CHECK-P8-LE-NEXT: blr ; CHECK-P8-LE-NEXT: blr
; ;
; CHECK-P8-BE-LABEL: st_unalign32_vector: ; CHECK-P8-BE-LABEL: st_unalign32_vector:
; CHECK-P8-BE: # %bb.0: # %entry ; CHECK-P8-BE: # %bb.0: # %entry
; CHECK-P8-BE-NEXT: lis r4, 1 ; CHECK-P8-BE-NEXT: lis r4, 1
; CHECK-P8-BE-NEXT: ori r4, r4, 34463 ; CHECK-P8-BE-NEXT: ori r4, r4, 34463
; CHECK-P8-BE-NEXT: stxvw4x v2, r3, r4 ; CHECK-P8-BE-NEXT: stxvw4x v2, r3, r4
; CHECK-P8-BE-NEXT: blr ; CHECK-P8-BE-NEXT: blr
Show All 15 Lines
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lis r4, 1525 ; CHECK-P9-NEXT: lis r4, 1525
; CHECK-P9-NEXT: ori r4, r4, 56600 ; CHECK-P9-NEXT: ori r4, r4, 56600
; CHECK-P9-NEXT: stxvx v2, r3, r4 ; CHECK-P9-NEXT: stxvx v2, r3, r4
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-P8-LE-LABEL: st_align32_vector: ; CHECK-P8-LE-LABEL: st_align32_vector:
; CHECK-P8-LE: # %bb.0: # %entry ; CHECK-P8-LE: # %bb.0: # %entry
; CHECK-P8-LE-NEXT: xxswapd vs0, v2
; CHECK-P8-LE-NEXT: lis r4, 1525 ; CHECK-P8-LE-NEXT: lis r4, 1525
; CHECK-P8-LE-NEXT: ori r4, r4, 56600 ; CHECK-P8-LE-NEXT: ori r4, r4, 56600
; CHECK-P8-LE-NEXT: stvx v2, r3, r4 ; CHECK-P8-LE-NEXT: stxvd2x vs0, r3, r4
; CHECK-P8-LE-NEXT: blr ; CHECK-P8-LE-NEXT: blr
; ;
; CHECK-P8-BE-LABEL: st_align32_vector: ; CHECK-P8-BE-LABEL: st_align32_vector:
; CHECK-P8-BE: # %bb.0: # %entry ; CHECK-P8-BE: # %bb.0: # %entry
; CHECK-P8-BE-NEXT: lis r4, 1525 ; CHECK-P8-BE-NEXT: lis r4, 1525
; CHECK-P8-BE-NEXT: ori r4, r4, 56600 ; CHECK-P8-BE-NEXT: ori r4, r4, 56600
; CHECK-P8-BE-NEXT: stxvw4x v2, r3, r4 ; CHECK-P8-BE-NEXT: stxvw4x v2, r3, r4
; CHECK-P8-BE-NEXT: blr ; CHECK-P8-BE-NEXT: blr
Show All 21 Lines
; CHECK-P9-NEXT: oris r4, r4, 54437 ; CHECK-P9-NEXT: oris r4, r4, 54437
; CHECK-P9-NEXT: ori r4, r4, 4097 ; CHECK-P9-NEXT: ori r4, r4, 4097
; CHECK-P9-NEXT: stxvx v2, r3, r4 ; CHECK-P9-NEXT: stxvx v2, r3, r4
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-P8-LE-LABEL: st_unalign64_vector: ; CHECK-P8-LE-LABEL: st_unalign64_vector:
; CHECK-P8-LE: # %bb.0: # %entry ; CHECK-P8-LE: # %bb.0: # %entry
; CHECK-P8-LE-NEXT: li r4, 29 ; CHECK-P8-LE-NEXT: li r4, 29
; CHECK-P8-LE-NEXT: xxswapd vs0, v2
; CHECK-P8-LE-NEXT: rldic r4, r4, 35, 24 ; CHECK-P8-LE-NEXT: rldic r4, r4, 35, 24
; CHECK-P8-LE-NEXT: oris r4, r4, 54437 ; CHECK-P8-LE-NEXT: oris r4, r4, 54437
; CHECK-P8-LE-NEXT: ori r4, r4, 4097 ; CHECK-P8-LE-NEXT: ori r4, r4, 4097
; CHECK-P8-LE-NEXT: stvx v2, r3, r4 ; CHECK-P8-LE-NEXT: stxvd2x vs0, r3, r4
; CHECK-P8-LE-NEXT: blr ; CHECK-P8-LE-NEXT: blr
; ;
; CHECK-P8-BE-LABEL: st_unalign64_vector: ; CHECK-P8-BE-LABEL: st_unalign64_vector:
; CHECK-P8-BE: # %bb.0: # %entry ; CHECK-P8-BE: # %bb.0: # %entry
; CHECK-P8-BE-NEXT: li r4, 29 ; CHECK-P8-BE-NEXT: li r4, 29
; CHECK-P8-BE-NEXT: rldic r4, r4, 35, 24 ; CHECK-P8-BE-NEXT: rldic r4, r4, 35, 24
; CHECK-P8-BE-NEXT: oris r4, r4, 54437 ; CHECK-P8-BE-NEXT: oris r4, r4, 54437
; CHECK-P8-BE-NEXT: ori r4, r4, 4097 ; CHECK-P8-BE-NEXT: ori r4, r4, 4097
Show All 21 Lines
; CHECK-P9-NEXT: ori r4, r4, 19025 ; CHECK-P9-NEXT: ori r4, r4, 19025
; CHECK-P9-NEXT: rldic r4, r4, 12, 24 ; CHECK-P9-NEXT: rldic r4, r4, 12, 24
; CHECK-P9-NEXT: stxvx v2, r3, r4 ; CHECK-P9-NEXT: stxvx v2, r3, r4
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-P8-LE-LABEL: st_align64_vector: ; CHECK-P8-LE-LABEL: st_align64_vector:
; CHECK-P8-LE: # %bb.0: # %entry ; CHECK-P8-LE: # %bb.0: # %entry
; CHECK-P8-LE-NEXT: lis r4, 3725 ; CHECK-P8-LE-NEXT: lis r4, 3725
; CHECK-P8-LE-NEXT: xxswapd vs0, v2
; CHECK-P8-LE-NEXT: ori r4, r4, 19025 ; CHECK-P8-LE-NEXT: ori r4, r4, 19025
; CHECK-P8-LE-NEXT: rldic r4, r4, 12, 24 ; CHECK-P8-LE-NEXT: rldic r4, r4, 12, 24
; CHECK-P8-LE-NEXT: stvx v2, r3, r4 ; CHECK-P8-LE-NEXT: stxvd2x vs0, r3, r4
; CHECK-P8-LE-NEXT: blr ; CHECK-P8-LE-NEXT: blr
; ;
; CHECK-P8-BE-LABEL: st_align64_vector: ; CHECK-P8-BE-LABEL: st_align64_vector:
; CHECK-P8-BE: # %bb.0: # %entry ; CHECK-P8-BE: # %bb.0: # %entry
; CHECK-P8-BE-NEXT: lis r4, 3725 ; CHECK-P8-BE-NEXT: lis r4, 3725
; CHECK-P8-BE-NEXT: ori r4, r4, 19025 ; CHECK-P8-BE-NEXT: ori r4, r4, 19025
; CHECK-P8-BE-NEXT: rldic r4, r4, 12, 24 ; CHECK-P8-BE-NEXT: rldic r4, r4, 12, 24
; CHECK-P8-BE-NEXT: stxvw4x v2, r3, r4 ; CHECK-P8-BE-NEXT: stxvw4x v2, r3, r4
Show All 9 Lines
define dso_local void @st_reg_vector(i8* nocapture %ptr, i64 %off, <16 x i8> %str) { define dso_local void @st_reg_vector(i8* nocapture %ptr, i64 %off, <16 x i8> %str) {
; CHECK-LABEL: st_reg_vector: ; CHECK-LABEL: st_reg_vector:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: stxvx v2, r3, r4 ; CHECK-NEXT: stxvx v2, r3, r4
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LE-LABEL: st_reg_vector: ; CHECK-P8-LE-LABEL: st_reg_vector:
; CHECK-P8-LE: # %bb.0: # %entry ; CHECK-P8-LE: # %bb.0: # %entry
; CHECK-P8-LE-NEXT: stvx v2, r3, r4 ; CHECK-P8-LE-NEXT: xxswapd vs0, v2
; CHECK-P8-LE-NEXT: stxvd2x vs0, r3, r4
; CHECK-P8-LE-NEXT: blr ; CHECK-P8-LE-NEXT: blr
; ;
; CHECK-P8-BE-LABEL: st_reg_vector: ; CHECK-P8-BE-LABEL: st_reg_vector:
; CHECK-P8-BE: # %bb.0: # %entry ; CHECK-P8-BE: # %bb.0: # %entry
; CHECK-P8-BE-NEXT: stxvw4x v2, r3, r4 ; CHECK-P8-BE-NEXT: stxvw4x v2, r3, r4
; CHECK-P8-BE-NEXT: blr ; CHECK-P8-BE-NEXT: blr
entry: entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off
%0 = bitcast i8* %add.ptr to <16 x i8>* %0 = bitcast i8* %add.ptr to <16 x i8>*
store <16 x i8> %str, <16 x i8>* %0, align 16 store <16 x i8> %str, <16 x i8>* %0, align 16
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_or1_vector(i64 %ptr, i8 zeroext %off, <16 x i8> %str) { define dso_local void @st_or1_vector(i64 %ptr, i8 zeroext %off, <16 x i8> %str) {
; CHECK-LABEL: st_or1_vector: ; CHECK-LABEL: st_or1_vector:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: or r3, r4, r3 ; CHECK-NEXT: or r3, r4, r3
; CHECK-NEXT: stxv v2, 0(r3) ; CHECK-NEXT: stxv v2, 0(r3)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LE-LABEL: st_or1_vector: ; CHECK-P8-LE-LABEL: st_or1_vector:
; CHECK-P8-LE: # %bb.0: # %entry ; CHECK-P8-LE: # %bb.0: # %entry
; CHECK-P8-LE-NEXT: xxswapd vs0, v2
; CHECK-P8-LE-NEXT: or r3, r4, r3 ; CHECK-P8-LE-NEXT: or r3, r4, r3
; CHECK-P8-LE-NEXT: stvx v2, 0, r3 ; CHECK-P8-LE-NEXT: stxvd2x vs0, 0, r3
; CHECK-P8-LE-NEXT: blr ; CHECK-P8-LE-NEXT: blr
; ;
; CHECK-P8-BE-LABEL: st_or1_vector: ; CHECK-P8-BE-LABEL: st_or1_vector:
; CHECK-P8-BE: # %bb.0: # %entry ; CHECK-P8-BE: # %bb.0: # %entry
; CHECK-P8-BE-NEXT: or r3, r4, r3 ; CHECK-P8-BE-NEXT: or r3, r4, r3
; CHECK-P8-BE-NEXT: stxvw4x v2, 0, r3 ; CHECK-P8-BE-NEXT: stxvw4x v2, 0, r3
; CHECK-P8-BE-NEXT: blr ; CHECK-P8-BE-NEXT: blr
entry: entry:
Show All 9 Lines
; CHECK-LABEL: st_or2_vector: ; CHECK-LABEL: st_or2_vector:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: rldicr r3, r3, 0, 51 ; CHECK-NEXT: rldicr r3, r3, 0, 51
; CHECK-NEXT: stxvx v2, r3, r4 ; CHECK-NEXT: stxvx v2, r3, r4
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LE-LABEL: st_or2_vector: ; CHECK-P8-LE-LABEL: st_or2_vector:
; CHECK-P8-LE: # %bb.0: # %entry ; CHECK-P8-LE: # %bb.0: # %entry
; CHECK-P8-LE-NEXT: xxswapd vs0, v2
; CHECK-P8-LE-NEXT: rldicr r3, r3, 0, 51 ; CHECK-P8-LE-NEXT: rldicr r3, r3, 0, 51
; CHECK-P8-LE-NEXT: stvx v2, r3, r4 ; CHECK-P8-LE-NEXT: stxvd2x vs0, r3, r4
; CHECK-P8-LE-NEXT: blr ; CHECK-P8-LE-NEXT: blr
; ;
; CHECK-P8-BE-LABEL: st_or2_vector: ; CHECK-P8-BE-LABEL: st_or2_vector:
; CHECK-P8-BE: # %bb.0: # %entry ; CHECK-P8-BE: # %bb.0: # %entry
; CHECK-P8-BE-NEXT: rldicr r3, r3, 0, 51 ; CHECK-P8-BE-NEXT: rldicr r3, r3, 0, 51
; CHECK-P8-BE-NEXT: stxvw4x v2, r3, r4 ; CHECK-P8-BE-NEXT: stxvw4x v2, r3, r4
; CHECK-P8-BE-NEXT: blr ; CHECK-P8-BE-NEXT: blr
entry: entry:
Show All 10 Lines
; CHECK-LABEL: st_not_disjoint16_vector: ; CHECK-LABEL: st_not_disjoint16_vector:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: ori r3, r3, 6 ; CHECK-NEXT: ori r3, r3, 6
; CHECK-NEXT: stxv v2, 0(r3) ; CHECK-NEXT: stxv v2, 0(r3)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LE-LABEL: st_not_disjoint16_vector: ; CHECK-P8-LE-LABEL: st_not_disjoint16_vector:
; CHECK-P8-LE: # %bb.0: # %entry ; CHECK-P8-LE: # %bb.0: # %entry
; CHECK-P8-LE-NEXT: xxswapd vs0, v2
; CHECK-P8-LE-NEXT: ori r3, r3, 6 ; CHECK-P8-LE-NEXT: ori r3, r3, 6
; CHECK-P8-LE-NEXT: stvx v2, 0, r3 ; CHECK-P8-LE-NEXT: stxvd2x vs0, 0, r3
; CHECK-P8-LE-NEXT: blr ; CHECK-P8-LE-NEXT: blr
; ;
; CHECK-P8-BE-LABEL: st_not_disjoint16_vector: ; CHECK-P8-BE-LABEL: st_not_disjoint16_vector:
; CHECK-P8-BE: # %bb.0: # %entry ; CHECK-P8-BE: # %bb.0: # %entry
; CHECK-P8-BE-NEXT: ori r3, r3, 6 ; CHECK-P8-BE-NEXT: ori r3, r3, 6
; CHECK-P8-BE-NEXT: stxvw4x v2, 0, r3 ; CHECK-P8-BE-NEXT: stxvw4x v2, 0, r3
; CHECK-P8-BE-NEXT: blr ; CHECK-P8-BE-NEXT: blr
entry: entry:
Show All 15 Lines
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: rldicr r3, r3, 0, 51 ; CHECK-P9-NEXT: rldicr r3, r3, 0, 51
; CHECK-P9-NEXT: li r4, 6 ; CHECK-P9-NEXT: li r4, 6
; CHECK-P9-NEXT: stxvx v2, r3, r4 ; CHECK-P9-NEXT: stxvx v2, r3, r4
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-P8-LE-LABEL: st_disjoint_unalign16_vector: ; CHECK-P8-LE-LABEL: st_disjoint_unalign16_vector:
; CHECK-P8-LE: # %bb.0: # %entry ; CHECK-P8-LE: # %bb.0: # %entry
; CHECK-P8-LE-NEXT: xxswapd vs0, v2
; CHECK-P8-LE-NEXT: rldicr r3, r3, 0, 51 ; CHECK-P8-LE-NEXT: rldicr r3, r3, 0, 51
; CHECK-P8-LE-NEXT: ori r3, r3, 6 ; CHECK-P8-LE-NEXT: ori r3, r3, 6
; CHECK-P8-LE-NEXT: stvx v2, 0, r3 ; CHECK-P8-LE-NEXT: stxvd2x vs0, 0, r3
; CHECK-P8-LE-NEXT: blr ; CHECK-P8-LE-NEXT: blr
; ;
; CHECK-P8-BE-LABEL: st_disjoint_unalign16_vector: ; CHECK-P8-BE-LABEL: st_disjoint_unalign16_vector:
; CHECK-P8-BE: # %bb.0: # %entry ; CHECK-P8-BE: # %bb.0: # %entry
; CHECK-P8-BE-NEXT: rldicr r3, r3, 0, 51 ; CHECK-P8-BE-NEXT: rldicr r3, r3, 0, 51
; CHECK-P8-BE-NEXT: ori r3, r3, 6 ; CHECK-P8-BE-NEXT: ori r3, r3, 6
; CHECK-P8-BE-NEXT: stxvw4x v2, 0, r3 ; CHECK-P8-BE-NEXT: stxvw4x v2, 0, r3
; CHECK-P8-BE-NEXT: blr ; CHECK-P8-BE-NEXT: blr
Show All 17 Lines
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: rldicr r3, r3, 0, 51 ; CHECK-P9-NEXT: rldicr r3, r3, 0, 51
; CHECK-P9-NEXT: li r4, 24 ; CHECK-P9-NEXT: li r4, 24
; CHECK-P9-NEXT: stxvx v2, r3, r4 ; CHECK-P9-NEXT: stxvx v2, r3, r4
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-P8-LE-LABEL: st_disjoint_align16_vector: ; CHECK-P8-LE-LABEL: st_disjoint_align16_vector:
; CHECK-P8-LE: # %bb.0: # %entry ; CHECK-P8-LE: # %bb.0: # %entry
; CHECK-P8-LE-NEXT: xxswapd vs0, v2
; CHECK-P8-LE-NEXT: rldicr r3, r3, 0, 51 ; CHECK-P8-LE-NEXT: rldicr r3, r3, 0, 51
; CHECK-P8-LE-NEXT: ori r3, r3, 24 ; CHECK-P8-LE-NEXT: ori r3, r3, 24
; CHECK-P8-LE-NEXT: stvx v2, 0, r3 ; CHECK-P8-LE-NEXT: stxvd2x vs0, 0, r3
; CHECK-P8-LE-NEXT: blr ; CHECK-P8-LE-NEXT: blr
; ;
; CHECK-P8-BE-LABEL: st_disjoint_align16_vector: ; CHECK-P8-BE-LABEL: st_disjoint_align16_vector:
; CHECK-P8-BE: # %bb.0: # %entry ; CHECK-P8-BE: # %bb.0: # %entry
; CHECK-P8-BE-NEXT: rldicr r3, r3, 0, 51 ; CHECK-P8-BE-NEXT: rldicr r3, r3, 0, 51
; CHECK-P8-BE-NEXT: ori r3, r3, 24 ; CHECK-P8-BE-NEXT: ori r3, r3, 24
; CHECK-P8-BE-NEXT: stxvw4x v2, 0, r3 ; CHECK-P8-BE-NEXT: stxvw4x v2, 0, r3
; CHECK-P8-BE-NEXT: blr ; CHECK-P8-BE-NEXT: blr
Show All 11 Lines
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: ori r3, r3, 34463 ; CHECK-NEXT: ori r3, r3, 34463
; CHECK-NEXT: oris r3, r3, 1 ; CHECK-NEXT: oris r3, r3, 1
; CHECK-NEXT: stxv v2, 0(r3) ; CHECK-NEXT: stxv v2, 0(r3)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LE-LABEL: st_not_disjoint32_vector: ; CHECK-P8-LE-LABEL: st_not_disjoint32_vector:
; CHECK-P8-LE: # %bb.0: # %entry ; CHECK-P8-LE: # %bb.0: # %entry
; CHECK-P8-LE-NEXT: xxswapd vs0, v2
; CHECK-P8-LE-NEXT: ori r3, r3, 34463 ; CHECK-P8-LE-NEXT: ori r3, r3, 34463
; CHECK-P8-LE-NEXT: oris r3, r3, 1 ; CHECK-P8-LE-NEXT: oris r3, r3, 1
; CHECK-P8-LE-NEXT: stvx v2, 0, r3 ; CHECK-P8-LE-NEXT: stxvd2x vs0, 0, r3
; CHECK-P8-LE-NEXT: blr ; CHECK-P8-LE-NEXT: blr
; ;
; CHECK-P8-BE-LABEL: st_not_disjoint32_vector: ; CHECK-P8-BE-LABEL: st_not_disjoint32_vector:
; CHECK-P8-BE: # %bb.0: # %entry ; CHECK-P8-BE: # %bb.0: # %entry
; CHECK-P8-BE-NEXT: ori r3, r3, 34463 ; CHECK-P8-BE-NEXT: ori r3, r3, 34463
; CHECK-P8-BE-NEXT: oris r3, r3, 1 ; CHECK-P8-BE-NEXT: oris r3, r3, 1
; CHECK-P8-BE-NEXT: stxvw4x v2, 0, r3 ; CHECK-P8-BE-NEXT: stxvw4x v2, 0, r3
; CHECK-P8-BE-NEXT: blr ; CHECK-P8-BE-NEXT: blr
Show All 17 Lines
; CHECK-P9-NEXT: lis r4, 1 ; CHECK-P9-NEXT: lis r4, 1
; CHECK-P9-NEXT: rldicr r3, r3, 0, 43 ; CHECK-P9-NEXT: rldicr r3, r3, 0, 43
; CHECK-P9-NEXT: ori r4, r4, 34463 ; CHECK-P9-NEXT: ori r4, r4, 34463
; CHECK-P9-NEXT: stxvx v2, r3, r4 ; CHECK-P9-NEXT: stxvx v2, r3, r4
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-P8-LE-LABEL: st_disjoint_unalign32_vector: ; CHECK-P8-LE-LABEL: st_disjoint_unalign32_vector:
; CHECK-P8-LE: # %bb.0: # %entry ; CHECK-P8-LE: # %bb.0: # %entry
; CHECK-P8-LE-NEXT: xxswapd vs0, v2
; CHECK-P8-LE-NEXT: lis r4, 1 ; CHECK-P8-LE-NEXT: lis r4, 1
; CHECK-P8-LE-NEXT: rldicr r3, r3, 0, 43 ; CHECK-P8-LE-NEXT: rldicr r3, r3, 0, 43
; CHECK-P8-LE-NEXT: ori r4, r4, 34463 ; CHECK-P8-LE-NEXT: ori r4, r4, 34463
; CHECK-P8-LE-NEXT: stvx v2, r3, r4 ; CHECK-P8-LE-NEXT: stxvd2x vs0, r3, r4
; CHECK-P8-LE-NEXT: blr ; CHECK-P8-LE-NEXT: blr
; ;
; CHECK-P8-BE-LABEL: st_disjoint_unalign32_vector: ; CHECK-P8-BE-LABEL: st_disjoint_unalign32_vector:
; CHECK-P8-BE: # %bb.0: # %entry ; CHECK-P8-BE: # %bb.0: # %entry
; CHECK-P8-BE-NEXT: lis r4, 1 ; CHECK-P8-BE-NEXT: lis r4, 1
; CHECK-P8-BE-NEXT: rldicr r3, r3, 0, 43 ; CHECK-P8-BE-NEXT: rldicr r3, r3, 0, 43
; CHECK-P8-BE-NEXT: ori r4, r4, 34463 ; CHECK-P8-BE-NEXT: ori r4, r4, 34463
; CHECK-P8-BE-NEXT: stxvw4x v2, r3, r4 ; CHECK-P8-BE-NEXT: stxvw4x v2, r3, r4
Show All 21 Lines
; CHECK-P9-NEXT: and r3, r3, r4 ; CHECK-P9-NEXT: and r3, r3, r4
; CHECK-P9-NEXT: lis r4, 15258 ; CHECK-P9-NEXT: lis r4, 15258
; CHECK-P9-NEXT: ori r4, r4, 41712 ; CHECK-P9-NEXT: ori r4, r4, 41712
; CHECK-P9-NEXT: stxvx v2, r3, r4 ; CHECK-P9-NEXT: stxvx v2, r3, r4
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-P8-LE-LABEL: st_disjoint_align32_vector: ; CHECK-P8-LE-LABEL: st_disjoint_align32_vector:
; CHECK-P8-LE: # %bb.0: # %entry ; CHECK-P8-LE: # %bb.0: # %entry
; CHECK-P8-LE-NEXT: xxswapd vs0, v2
; CHECK-P8-LE-NEXT: lis r4, -15264 ; CHECK-P8-LE-NEXT: lis r4, -15264
; CHECK-P8-LE-NEXT: lis r5, 15258 ; CHECK-P8-LE-NEXT: lis r5, 15258
; CHECK-P8-LE-NEXT: and r3, r3, r4 ; CHECK-P8-LE-NEXT: and r3, r3, r4
; CHECK-P8-LE-NEXT: ori r4, r5, 41712 ; CHECK-P8-LE-NEXT: ori r4, r5, 41712
; CHECK-P8-LE-NEXT: stvx v2, r3, r4 ; CHECK-P8-LE-NEXT: stxvd2x vs0, r3, r4
; CHECK-P8-LE-NEXT: blr ; CHECK-P8-LE-NEXT: blr
; ;
; CHECK-P8-BE-LABEL: st_disjoint_align32_vector: ; CHECK-P8-BE-LABEL: st_disjoint_align32_vector:
; CHECK-P8-BE: # %bb.0: # %entry ; CHECK-P8-BE: # %bb.0: # %entry
; CHECK-P8-BE-NEXT: lis r4, -15264 ; CHECK-P8-BE-NEXT: lis r4, -15264
; CHECK-P8-BE-NEXT: lis r5, 15258 ; CHECK-P8-BE-NEXT: lis r5, 15258
; CHECK-P8-BE-NEXT: and r3, r3, r4 ; CHECK-P8-BE-NEXT: and r3, r3, r4
; CHECK-P8-BE-NEXT: ori r4, r5, 41712 ; CHECK-P8-BE-NEXT: ori r4, r5, 41712
Show All 26 Lines
; CHECK-P9-NEXT: ori r4, r4, 4097 ; CHECK-P9-NEXT: ori r4, r4, 4097
; CHECK-P9-NEXT: or r3, r3, r4 ; CHECK-P9-NEXT: or r3, r3, r4
; CHECK-P9-NEXT: stxv v2, 0(r3) ; CHECK-P9-NEXT: stxv v2, 0(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-P8-LE-LABEL: st_not_disjoint64_vector: ; CHECK-P8-LE-LABEL: st_not_disjoint64_vector:
; CHECK-P8-LE: # %bb.0: # %entry ; CHECK-P8-LE: # %bb.0: # %entry
; CHECK-P8-LE-NEXT: li r4, 29 ; CHECK-P8-LE-NEXT: li r4, 29
; CHECK-P8-LE-NEXT: xxswapd vs0, v2
; CHECK-P8-LE-NEXT: rldic r4, r4, 35, 24 ; CHECK-P8-LE-NEXT: rldic r4, r4, 35, 24
; CHECK-P8-LE-NEXT: oris r4, r4, 54437 ; CHECK-P8-LE-NEXT: oris r4, r4, 54437
; CHECK-P8-LE-NEXT: ori r4, r4, 4097 ; CHECK-P8-LE-NEXT: ori r4, r4, 4097
; CHECK-P8-LE-NEXT: or r3, r3, r4 ; CHECK-P8-LE-NEXT: or r3, r3, r4
; CHECK-P8-LE-NEXT: stvx v2, 0, r3 ; CHECK-P8-LE-NEXT: stxvd2x vs0, 0, r3
; CHECK-P8-LE-NEXT: blr ; CHECK-P8-LE-NEXT: blr
; ;
; CHECK-P8-BE-LABEL: st_not_disjoint64_vector: ; CHECK-P8-BE-LABEL: st_not_disjoint64_vector:
; CHECK-P8-BE: # %bb.0: # %entry ; CHECK-P8-BE: # %bb.0: # %entry
; CHECK-P8-BE-NEXT: li r4, 29 ; CHECK-P8-BE-NEXT: li r4, 29
; CHECK-P8-BE-NEXT: rldic r4, r4, 35, 24 ; CHECK-P8-BE-NEXT: rldic r4, r4, 35, 24
; CHECK-P8-BE-NEXT: oris r4, r4, 54437 ; CHECK-P8-BE-NEXT: oris r4, r4, 54437
; CHECK-P8-BE-NEXT: ori r4, r4, 4097 ; CHECK-P8-BE-NEXT: ori r4, r4, 4097
Show All 26 Lines
; CHECK-P9-NEXT: oris r4, r4, 54437 ; CHECK-P9-NEXT: oris r4, r4, 54437
; CHECK-P9-NEXT: ori r4, r4, 4097 ; CHECK-P9-NEXT: ori r4, r4, 4097
; CHECK-P9-NEXT: stxvx v2, r3, r4 ; CHECK-P9-NEXT: stxvx v2, r3, r4
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-P8-LE-LABEL: st_disjoint_unalign64_vector: ; CHECK-P8-LE-LABEL: st_disjoint_unalign64_vector:
; CHECK-P8-LE: # %bb.0: # %entry ; CHECK-P8-LE: # %bb.0: # %entry
; CHECK-P8-LE-NEXT: li r4, 29 ; CHECK-P8-LE-NEXT: li r4, 29
; CHECK-P8-LE-NEXT: xxswapd vs0, v2
; CHECK-P8-LE-NEXT: rldicr r3, r3, 0, 23 ; CHECK-P8-LE-NEXT: rldicr r3, r3, 0, 23
; CHECK-P8-LE-NEXT: rldic r4, r4, 35, 24 ; CHECK-P8-LE-NEXT: rldic r4, r4, 35, 24
; CHECK-P8-LE-NEXT: oris r4, r4, 54437 ; CHECK-P8-LE-NEXT: oris r4, r4, 54437
; CHECK-P8-LE-NEXT: ori r4, r4, 4097 ; CHECK-P8-LE-NEXT: ori r4, r4, 4097
; CHECK-P8-LE-NEXT: stvx v2, r3, r4 ; CHECK-P8-LE-NEXT: stxvd2x vs0, r3, r4
; CHECK-P8-LE-NEXT: blr ; CHECK-P8-LE-NEXT: blr
; ;
; CHECK-P8-BE-LABEL: st_disjoint_unalign64_vector: ; CHECK-P8-BE-LABEL: st_disjoint_unalign64_vector:
; CHECK-P8-BE: # %bb.0: # %entry ; CHECK-P8-BE: # %bb.0: # %entry
; CHECK-P8-BE-NEXT: li r4, 29 ; CHECK-P8-BE-NEXT: li r4, 29
; CHECK-P8-BE-NEXT: rldicr r3, r3, 0, 23 ; CHECK-P8-BE-NEXT: rldicr r3, r3, 0, 23
; CHECK-P8-BE-NEXT: rldic r4, r4, 35, 24 ; CHECK-P8-BE-NEXT: rldic r4, r4, 35, 24
; CHECK-P8-BE-NEXT: oris r4, r4, 54437 ; CHECK-P8-BE-NEXT: oris r4, r4, 54437
Show All 25 Lines
; CHECK-P9-NEXT: ori r4, r4, 19025 ; CHECK-P9-NEXT: ori r4, r4, 19025
; CHECK-P9-NEXT: rldic r4, r4, 12, 24 ; CHECK-P9-NEXT: rldic r4, r4, 12, 24
; CHECK-P9-NEXT: stxvx v2, r3, r4 ; CHECK-P9-NEXT: stxvx v2, r3, r4
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-P8-LE-LABEL: st_disjoint_align64_vector: ; CHECK-P8-LE-LABEL: st_disjoint_align64_vector:
; CHECK-P8-LE: # %bb.0: # %entry ; CHECK-P8-LE: # %bb.0: # %entry
; CHECK-P8-LE-NEXT: lis r4, 3725 ; CHECK-P8-LE-NEXT: lis r4, 3725
; CHECK-P8-LE-NEXT: xxswapd vs0, v2
; CHECK-P8-LE-NEXT: rldicr r3, r3, 0, 23 ; CHECK-P8-LE-NEXT: rldicr r3, r3, 0, 23
; CHECK-P8-LE-NEXT: ori r4, r4, 19025 ; CHECK-P8-LE-NEXT: ori r4, r4, 19025
; CHECK-P8-LE-NEXT: rldic r4, r4, 12, 24 ; CHECK-P8-LE-NEXT: rldic r4, r4, 12, 24
; CHECK-P8-LE-NEXT: stvx v2, r3, r4 ; CHECK-P8-LE-NEXT: stxvd2x vs0, r3, r4
; CHECK-P8-LE-NEXT: blr ; CHECK-P8-LE-NEXT: blr
; ;
; CHECK-P8-BE-LABEL: st_disjoint_align64_vector: ; CHECK-P8-BE-LABEL: st_disjoint_align64_vector:
; CHECK-P8-BE: # %bb.0: # %entry ; CHECK-P8-BE: # %bb.0: # %entry
; CHECK-P8-BE-NEXT: lis r4, 3725 ; CHECK-P8-BE-NEXT: lis r4, 3725
; CHECK-P8-BE-NEXT: rldicr r3, r3, 0, 23 ; CHECK-P8-BE-NEXT: rldicr r3, r3, 0, 23
; CHECK-P8-BE-NEXT: ori r4, r4, 19025 ; CHECK-P8-BE-NEXT: ori r4, r4, 19025
; CHECK-P8-BE-NEXT: rldic r4, r4, 12, 24 ; CHECK-P8-BE-NEXT: rldic r4, r4, 12, 24
Show All 12 Lines
; CHECK-LABEL: st_cst_unalign16_vector: ; CHECK-LABEL: st_cst_unalign16_vector:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: li r3, 255 ; CHECK-NEXT: li r3, 255
; CHECK-NEXT: stxv v2, 0(r3) ; CHECK-NEXT: stxv v2, 0(r3)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LE-LABEL: st_cst_unalign16_vector: ; CHECK-P8-LE-LABEL: st_cst_unalign16_vector:
; CHECK-P8-LE: # %bb.0: # %entry ; CHECK-P8-LE: # %bb.0: # %entry
; CHECK-P8-LE-NEXT: xxswapd vs0, v2
; CHECK-P8-LE-NEXT: li r3, 255 ; CHECK-P8-LE-NEXT: li r3, 255
; CHECK-P8-LE-NEXT: stvx v2, 0, r3 ; CHECK-P8-LE-NEXT: stxvd2x vs0, 0, r3
; CHECK-P8-LE-NEXT: blr ; CHECK-P8-LE-NEXT: blr
; ;
; CHECK-P8-BE-LABEL: st_cst_unalign16_vector: ; CHECK-P8-BE-LABEL: st_cst_unalign16_vector:
; CHECK-P8-BE: # %bb.0: # %entry ; CHECK-P8-BE: # %bb.0: # %entry
; CHECK-P8-BE-NEXT: li r3, 255 ; CHECK-P8-BE-NEXT: li r3, 255
; CHECK-P8-BE-NEXT: stxvw4x v2, 0, r3 ; CHECK-P8-BE-NEXT: stxvw4x v2, 0, r3
; CHECK-P8-BE-NEXT: blr ; CHECK-P8-BE-NEXT: blr
entry: entry:
store <16 x i8> %str, <16 x i8>* inttoptr (i64 255 to <16 x i8>*), align 16 store <16 x i8> %str, <16 x i8>* inttoptr (i64 255 to <16 x i8>*), align 16
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_cst_align16_vector(<16 x i8> %str) { define dso_local void @st_cst_align16_vector(<16 x i8> %str) {
; CHECK-LABEL: st_cst_align16_vector: ; CHECK-LABEL: st_cst_align16_vector:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: stxv v2, 4080(0) ; CHECK-NEXT: stxv v2, 4080(0)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LE-LABEL: st_cst_align16_vector: ; CHECK-P8-LE-LABEL: st_cst_align16_vector:
; CHECK-P8-LE: # %bb.0: # %entry ; CHECK-P8-LE: # %bb.0: # %entry
; CHECK-P8-LE-NEXT: xxswapd vs0, v2
; CHECK-P8-LE-NEXT: li r3, 4080 ; CHECK-P8-LE-NEXT: li r3, 4080
; CHECK-P8-LE-NEXT: stvx v2, 0, r3 ; CHECK-P8-LE-NEXT: stxvd2x vs0, 0, r3
; CHECK-P8-LE-NEXT: blr ; CHECK-P8-LE-NEXT: blr
; ;
; CHECK-P8-BE-LABEL: st_cst_align16_vector: ; CHECK-P8-BE-LABEL: st_cst_align16_vector:
; CHECK-P8-BE: # %bb.0: # %entry ; CHECK-P8-BE: # %bb.0: # %entry
; CHECK-P8-BE-NEXT: li r3, 4080 ; CHECK-P8-BE-NEXT: li r3, 4080
; CHECK-P8-BE-NEXT: stxvw4x v2, 0, r3 ; CHECK-P8-BE-NEXT: stxvw4x v2, 0, r3
; CHECK-P8-BE-NEXT: blr ; CHECK-P8-BE-NEXT: blr
entry: entry:
Show All 13 Lines
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lis r3, 1 ; CHECK-P9-NEXT: lis r3, 1
; CHECK-P9-NEXT: ori r3, r3, 34463 ; CHECK-P9-NEXT: ori r3, r3, 34463
; CHECK-P9-NEXT: stxv v2, 0(r3) ; CHECK-P9-NEXT: stxv v2, 0(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-P8-LE-LABEL: st_cst_unalign32_vector: ; CHECK-P8-LE-LABEL: st_cst_unalign32_vector:
; CHECK-P8-LE: # %bb.0: # %entry ; CHECK-P8-LE: # %bb.0: # %entry
; CHECK-P8-LE-NEXT: xxswapd vs0, v2
; CHECK-P8-LE-NEXT: lis r3, 1 ; CHECK-P8-LE-NEXT: lis r3, 1
; CHECK-P8-LE-NEXT: ori r3, r3, 34463 ; CHECK-P8-LE-NEXT: ori r3, r3, 34463
; CHECK-P8-LE-NEXT: stvx v2, 0, r3 ; CHECK-P8-LE-NEXT: stxvd2x vs0, 0, r3
; CHECK-P8-LE-NEXT: blr ; CHECK-P8-LE-NEXT: blr
; ;
; CHECK-P8-BE-LABEL: st_cst_unalign32_vector: ; CHECK-P8-BE-LABEL: st_cst_unalign32_vector:
; CHECK-P8-BE: # %bb.0: # %entry ; CHECK-P8-BE: # %bb.0: # %entry
; CHECK-P8-BE-NEXT: lis r3, 1 ; CHECK-P8-BE-NEXT: lis r3, 1
; CHECK-P8-BE-NEXT: ori r3, r3, 34463 ; CHECK-P8-BE-NEXT: ori r3, r3, 34463
; CHECK-P8-BE-NEXT: stxvw4x v2, 0, r3 ; CHECK-P8-BE-NEXT: stxvw4x v2, 0, r3
; CHECK-P8-BE-NEXT: blr ; CHECK-P8-BE-NEXT: blr
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; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lis r3, 152 ; CHECK-P9-NEXT: lis r3, 152
; CHECK-P9-NEXT: ori r3, r3, 38428 ; CHECK-P9-NEXT: ori r3, r3, 38428
; CHECK-P9-NEXT: stxv v2, 0(r3) ; CHECK-P9-NEXT: stxv v2, 0(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-P8-LE-LABEL: st_cst_align32_vector: ; CHECK-P8-LE-LABEL: st_cst_align32_vector:
; CHECK-P8-LE: # %bb.0: # %entry ; CHECK-P8-LE: # %bb.0: # %entry
; CHECK-P8-LE-NEXT: xxswapd vs0, v2
; CHECK-P8-LE-NEXT: lis r3, 152 ; CHECK-P8-LE-NEXT: lis r3, 152
; CHECK-P8-LE-NEXT: ori r3, r3, 38428 ; CHECK-P8-LE-NEXT: ori r3, r3, 38428
; CHECK-P8-LE-NEXT: stvx v2, 0, r3 ; CHECK-P8-LE-NEXT: stxvd2x vs0, 0, r3
; CHECK-P8-LE-NEXT: blr ; CHECK-P8-LE-NEXT: blr
; ;
; CHECK-P8-BE-LABEL: st_cst_align32_vector: ; CHECK-P8-BE-LABEL: st_cst_align32_vector:
; CHECK-P8-BE: # %bb.0: # %entry ; CHECK-P8-BE: # %bb.0: # %entry
; CHECK-P8-BE-NEXT: lis r3, 152 ; CHECK-P8-BE-NEXT: lis r3, 152
; CHECK-P8-BE-NEXT: ori r3, r3, 38428 ; CHECK-P8-BE-NEXT: ori r3, r3, 38428
; CHECK-P8-BE-NEXT: stxvw4x v2, 0, r3 ; CHECK-P8-BE-NEXT: stxvw4x v2, 0, r3
; CHECK-P8-BE-NEXT: blr ; CHECK-P8-BE-NEXT: blr
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; CHECK-P9-NEXT: oris r3, r3, 54437 ; CHECK-P9-NEXT: oris r3, r3, 54437
; CHECK-P9-NEXT: ori r3, r3, 4097 ; CHECK-P9-NEXT: ori r3, r3, 4097
; CHECK-P9-NEXT: stxv v2, 0(r3) ; CHECK-P9-NEXT: stxv v2, 0(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-P8-LE-LABEL: st_cst_unalign64_vector: ; CHECK-P8-LE-LABEL: st_cst_unalign64_vector:
; CHECK-P8-LE: # %bb.0: # %entry ; CHECK-P8-LE: # %bb.0: # %entry
; CHECK-P8-LE-NEXT: li r3, 29 ; CHECK-P8-LE-NEXT: li r3, 29
; CHECK-P8-LE-NEXT: xxswapd vs0, v2
; CHECK-P8-LE-NEXT: rldic r3, r3, 35, 24 ; CHECK-P8-LE-NEXT: rldic r3, r3, 35, 24
; CHECK-P8-LE-NEXT: oris r3, r3, 54437 ; CHECK-P8-LE-NEXT: oris r3, r3, 54437
; CHECK-P8-LE-NEXT: ori r3, r3, 4097 ; CHECK-P8-LE-NEXT: ori r3, r3, 4097
; CHECK-P8-LE-NEXT: stvx v2, 0, r3 ; CHECK-P8-LE-NEXT: stxvd2x vs0, 0, r3
; CHECK-P8-LE-NEXT: blr ; CHECK-P8-LE-NEXT: blr
; ;
; CHECK-P8-BE-LABEL: st_cst_unalign64_vector: ; CHECK-P8-BE-LABEL: st_cst_unalign64_vector:
; CHECK-P8-BE: # %bb.0: # %entry ; CHECK-P8-BE: # %bb.0: # %entry
; CHECK-P8-BE-NEXT: li r3, 29 ; CHECK-P8-BE-NEXT: li r3, 29
; CHECK-P8-BE-NEXT: rldic r3, r3, 35, 24 ; CHECK-P8-BE-NEXT: rldic r3, r3, 35, 24
; CHECK-P8-BE-NEXT: oris r3, r3, 54437 ; CHECK-P8-BE-NEXT: oris r3, r3, 54437
; CHECK-P8-BE-NEXT: ori r3, r3, 4097 ; CHECK-P8-BE-NEXT: ori r3, r3, 4097
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; CHECK-P9-NEXT: ori r3, r3, 19025 ; CHECK-P9-NEXT: ori r3, r3, 19025
; CHECK-P9-NEXT: rldic r3, r3, 12, 24 ; CHECK-P9-NEXT: rldic r3, r3, 12, 24
; CHECK-P9-NEXT: stxv v2, 0(r3) ; CHECK-P9-NEXT: stxv v2, 0(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-P8-LE-LABEL: st_cst_align64_vector: ; CHECK-P8-LE-LABEL: st_cst_align64_vector:
; CHECK-P8-LE: # %bb.0: # %entry ; CHECK-P8-LE: # %bb.0: # %entry
; CHECK-P8-LE-NEXT: lis r3, 3725 ; CHECK-P8-LE-NEXT: lis r3, 3725
; CHECK-P8-LE-NEXT: xxswapd vs0, v2
; CHECK-P8-LE-NEXT: ori r3, r3, 19025 ; CHECK-P8-LE-NEXT: ori r3, r3, 19025
; CHECK-P8-LE-NEXT: rldic r3, r3, 12, 24 ; CHECK-P8-LE-NEXT: rldic r3, r3, 12, 24
; CHECK-P8-LE-NEXT: stvx v2, 0, r3 ; CHECK-P8-LE-NEXT: stxvd2x vs0, 0, r3
; CHECK-P8-LE-NEXT: blr ; CHECK-P8-LE-NEXT: blr
; ;
; CHECK-P8-BE-LABEL: st_cst_align64_vector: ; CHECK-P8-BE-LABEL: st_cst_align64_vector:
; CHECK-P8-BE: # %bb.0: # %entry ; CHECK-P8-BE: # %bb.0: # %entry
; CHECK-P8-BE-NEXT: lis r3, 3725 ; CHECK-P8-BE-NEXT: lis r3, 3725
; CHECK-P8-BE-NEXT: ori r3, r3, 19025 ; CHECK-P8-BE-NEXT: ori r3, r3, 19025
; CHECK-P8-BE-NEXT: rldic r3, r3, 12, 24 ; CHECK-P8-BE-NEXT: rldic r3, r3, 12, 24
; CHECK-P8-BE-NEXT: stxvw4x v2, 0, r3 ; CHECK-P8-BE-NEXT: stxvw4x v2, 0, r3
; CHECK-P8-BE-NEXT: blr ; CHECK-P8-BE-NEXT: blr
entry: entry:
store <16 x i8> %str, <16 x i8>* inttoptr (i64 1000000000000 to <16 x i8>*), align 4096 store <16 x i8> %str, <16 x i8>* inttoptr (i64 1000000000000 to <16 x i8>*), align 4096
ret void ret void
} }

llvm/test/CodeGen/PowerPC/vector-rotates.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -O3 -mtriple=powerpc64le-unknown-unknown -ppc-asm-full-reg-names \ ; RUN: llc -O3 -mtriple=powerpc64le-unknown-unknown -ppc-asm-full-reg-names \
; RUN: -verify-machineinstrs -mcpu=pwr8 < %s | \ ; RUN: -verify-machineinstrs -mcpu=pwr8 < %s | \
; RUN: FileCheck --check-prefix=CHECK-P8 %s ; RUN: FileCheck --check-prefix=CHECK-P8 %s
; RUN: llc -O3 -mtriple=powerpc64-unknown-unknown -ppc-asm-full-reg-names \ ; RUN: llc -O3 -mtriple=powerpc64-unknown-unknown -ppc-asm-full-reg-names \
; RUN: -verify-machineinstrs -mcpu=pwr7 < %s | \ ; RUN: -verify-machineinstrs -mcpu=pwr7 < %s | \
; RUN: FileCheck --check-prefix=CHECK-P7 %s ; RUN: FileCheck --check-prefix=CHECK-P7 %s
define <16 x i8> @rotl_v16i8(<16 x i8> %a) { define <16 x i8> @rotl_v16i8(<16 x i8> %a) {
; CHECK-P8-LABEL: rotl_v16i8: ; CHECK-P8-LABEL: rotl_v16i8:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: addis r3, r2, .LCPI0_0@toc@ha ; CHECK-P8-NEXT: addis r3, r2, .LCPI0_0@toc@ha
; CHECK-P8-NEXT: addi r3, r3, .LCPI0_0@toc@l ; CHECK-P8-NEXT: addi r3, r3, .LCPI0_0@toc@l
; CHECK-P8-NEXT: lvx v3, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: xxswapd vs35, vs0
; CHECK-P8-NEXT: vrlb v2, v2, v3 ; CHECK-P8-NEXT: vrlb v2, v2, v3
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P7-LABEL: rotl_v16i8: ; CHECK-P7-LABEL: rotl_v16i8:
; CHECK-P7: # %bb.0: # %entry ; CHECK-P7: # %bb.0: # %entry
; CHECK-P7-NEXT: addis r3, r2, .LCPI0_0@toc@ha ; CHECK-P7-NEXT: addis r3, r2, .LCPI0_0@toc@ha
; CHECK-P7-NEXT: addi r3, r3, .LCPI0_0@toc@l ; CHECK-P7-NEXT: addi r3, r3, .LCPI0_0@toc@l
; CHECK-P7-NEXT: lxvw4x vs35, 0, r3 ; CHECK-P7-NEXT: lxvw4x vs35, 0, r3
; CHECK-P7-NEXT: vrlb v2, v2, v3 ; CHECK-P7-NEXT: vrlb v2, v2, v3
; CHECK-P7-NEXT: blr ; CHECK-P7-NEXT: blr
entry: entry:
%b = shl <16 x i8> %a, <i8 1, i8 1, i8 2, i8 2, i8 3, i8 3, i8 4, i8 4, i8 5, i8 5, i8 6, i8 6, i8 7, i8 7, i8 8, i8 8> %b = shl <16 x i8> %a, <i8 1, i8 1, i8 2, i8 2, i8 3, i8 3, i8 4, i8 4, i8 5, i8 5, i8 6, i8 6, i8 7, i8 7, i8 8, i8 8>
%c = lshr <16 x i8> %a, <i8 7, i8 7, i8 6, i8 6, i8 5, i8 5, i8 4, i8 4, i8 3, i8 3, i8 2, i8 2, i8 1, i8 1, i8 0, i8 0> %c = lshr <16 x i8> %a, <i8 7, i8 7, i8 6, i8 6, i8 5, i8 5, i8 4, i8 4, i8 3, i8 3, i8 2, i8 2, i8 1, i8 1, i8 0, i8 0>
%d = or <16 x i8> %b, %c %d = or <16 x i8> %b, %c
ret <16 x i8> %d ret <16 x i8> %d
} }
define <8 x i16> @rotl_v8i16(<8 x i16> %a) { define <8 x i16> @rotl_v8i16(<8 x i16> %a) {
; CHECK-P8-LABEL: rotl_v8i16: ; CHECK-P8-LABEL: rotl_v8i16:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: addis r3, r2, .LCPI1_0@toc@ha ; CHECK-P8-NEXT: addis r3, r2, .LCPI1_0@toc@ha
; CHECK-P8-NEXT: addi r3, r3, .LCPI1_0@toc@l ; CHECK-P8-NEXT: addi r3, r3, .LCPI1_0@toc@l
; CHECK-P8-NEXT: lvx v3, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: xxswapd vs35, vs0
; CHECK-P8-NEXT: vrlh v2, v2, v3 ; CHECK-P8-NEXT: vrlh v2, v2, v3
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P7-LABEL: rotl_v8i16: ; CHECK-P7-LABEL: rotl_v8i16:
; CHECK-P7: # %bb.0: # %entry ; CHECK-P7: # %bb.0: # %entry
; CHECK-P7-NEXT: addis r3, r2, .LCPI1_0@toc@ha ; CHECK-P7-NEXT: addis r3, r2, .LCPI1_0@toc@ha
; CHECK-P7-NEXT: addi r3, r3, .LCPI1_0@toc@l ; CHECK-P7-NEXT: addi r3, r3, .LCPI1_0@toc@l
; CHECK-P7-NEXT: lxvw4x vs35, 0, r3 ; CHECK-P7-NEXT: lxvw4x vs35, 0, r3
; CHECK-P7-NEXT: vrlh v2, v2, v3 ; CHECK-P7-NEXT: vrlh v2, v2, v3
; CHECK-P7-NEXT: blr ; CHECK-P7-NEXT: blr
entry: entry:
%b = shl <8 x i16> %a, <i16 1, i16 2, i16 3, i16 5, i16 7, i16 11, i16 13, i16 16> %b = shl <8 x i16> %a, <i16 1, i16 2, i16 3, i16 5, i16 7, i16 11, i16 13, i16 16>
%c = lshr <8 x i16> %a, <i16 15, i16 14, i16 13, i16 11, i16 9, i16 5, i16 3, i16 0> %c = lshr <8 x i16> %a, <i16 15, i16 14, i16 13, i16 11, i16 9, i16 5, i16 3, i16 0>
%d = or <8 x i16> %b, %c %d = or <8 x i16> %b, %c
ret <8 x i16> %d ret <8 x i16> %d
} }
define <4 x i32> @rotl_v4i32_0(<4 x i32> %a) { define <4 x i32> @rotl_v4i32_0(<4 x i32> %a) {
; CHECK-P8-LABEL: rotl_v4i32_0: ; CHECK-P8-LABEL: rotl_v4i32_0:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: addis r3, r2, .LCPI2_0@toc@ha ; CHECK-P8-NEXT: addis r3, r2, .LCPI2_0@toc@ha
; CHECK-P8-NEXT: addi r3, r3, .LCPI2_0@toc@l ; CHECK-P8-NEXT: addi r3, r3, .LCPI2_0@toc@l
; CHECK-P8-NEXT: lvx v3, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: xxswapd vs35, vs0
; CHECK-P8-NEXT: vrlw v2, v2, v3 ; CHECK-P8-NEXT: vrlw v2, v2, v3
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P7-LABEL: rotl_v4i32_0: ; CHECK-P7-LABEL: rotl_v4i32_0:
; CHECK-P7: # %bb.0: # %entry ; CHECK-P7: # %bb.0: # %entry
; CHECK-P7-NEXT: addis r3, r2, .LCPI2_0@toc@ha ; CHECK-P7-NEXT: addis r3, r2, .LCPI2_0@toc@ha
; CHECK-P7-NEXT: addi r3, r3, .LCPI2_0@toc@l ; CHECK-P7-NEXT: addi r3, r3, .LCPI2_0@toc@l
; CHECK-P7-NEXT: lxvw4x vs35, 0, r3 ; CHECK-P7-NEXT: lxvw4x vs35, 0, r3
▲ Show 20 Lines • Show All 61 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/vselect-constants.ll

Show All 10 Lines
; CHECK-LABEL: sel_C1_or_C2_vec: ; CHECK-LABEL: sel_C1_or_C2_vec:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vspltisw 3, -16 ; CHECK-NEXT: vspltisw 3, -16
; CHECK-NEXT: vspltisw 4, 15 ; CHECK-NEXT: vspltisw 4, 15
; CHECK-NEXT: addis 3, 2, .LCPI0_0@toc@ha ; CHECK-NEXT: addis 3, 2, .LCPI0_0@toc@ha
; CHECK-NEXT: addis 4, 2, .LCPI0_1@toc@ha ; CHECK-NEXT: addis 4, 2, .LCPI0_1@toc@ha
; CHECK-NEXT: addi 3, 3, .LCPI0_0@toc@l ; CHECK-NEXT: addi 3, 3, .LCPI0_0@toc@l
; CHECK-NEXT: addi 4, 4, .LCPI0_1@toc@l ; CHECK-NEXT: addi 4, 4, .LCPI0_1@toc@l
; CHECK-NEXT: lxvd2x 0, 0, 3
; CHECK-NEXT: lxvd2x 1, 0, 4
; CHECK-NEXT: vsubuwm 3, 4, 3 ; CHECK-NEXT: vsubuwm 3, 4, 3
; CHECK-NEXT: lvx 4, 0, 4
; CHECK-NEXT: vslw 2, 2, 3 ; CHECK-NEXT: vslw 2, 2, 3
; CHECK-NEXT: xxswapd 36, 1
; CHECK-NEXT: vsraw 2, 2, 3 ; CHECK-NEXT: vsraw 2, 2, 3
; CHECK-NEXT: lvx 3, 0, 3 ; CHECK-NEXT: xxswapd 35, 0
; CHECK-NEXT: xxsel 34, 36, 35, 34 ; CHECK-NEXT: xxsel 34, 36, 35, 34
; CHECK-NEXT: blr ; CHECK-NEXT: blr
%add = select <4 x i1> %cond, <4 x i32> <i32 3000, i32 1, i32 -1, i32 0>, <4 x i32> <i32 42, i32 0, i32 -2, i32 -1> %add = select <4 x i1> %cond, <4 x i32> <i32 3000, i32 1, i32 -1, i32 0>, <4 x i32> <i32 42, i32 0, i32 -2, i32 -1>
ret <4 x i32> %add ret <4 x i32> %add
} }
define <4 x i32> @cmp_sel_C1_or_C2_vec(<4 x i32> %x, <4 x i32> %y) { define <4 x i32> @cmp_sel_C1_or_C2_vec(<4 x i32> %x, <4 x i32> %y) {
; CHECK-LABEL: cmp_sel_C1_or_C2_vec: ; CHECK-LABEL: cmp_sel_C1_or_C2_vec:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vcmpequw 2, 2, 3
; CHECK-NEXT: addis 3, 2, .LCPI1_0@toc@ha ; CHECK-NEXT: addis 3, 2, .LCPI1_0@toc@ha
; CHECK-NEXT: addis 4, 2, .LCPI1_1@toc@ha ; CHECK-NEXT: addis 4, 2, .LCPI1_1@toc@ha
; CHECK-NEXT: vcmpequw 2, 2, 3
; CHECK-NEXT: addi 3, 3, .LCPI1_0@toc@l ; CHECK-NEXT: addi 3, 3, .LCPI1_0@toc@l
; CHECK-NEXT: addi 4, 4, .LCPI1_1@toc@l ; CHECK-NEXT: addi 4, 4, .LCPI1_1@toc@l
; CHECK-NEXT: lvx 3, 0, 3 ; CHECK-NEXT: lxvd2x 0, 0, 3
; CHECK-NEXT: lvx 4, 0, 4 ; CHECK-NEXT: lxvd2x 1, 0, 4
; CHECK-NEXT: xxswapd 35, 0
; CHECK-NEXT: xxswapd 36, 1
; CHECK-NEXT: xxsel 34, 36, 35, 34 ; CHECK-NEXT: xxsel 34, 36, 35, 34
; CHECK-NEXT: blr ; CHECK-NEXT: blr
%cond = icmp eq <4 x i32> %x, %y %cond = icmp eq <4 x i32> %x, %y
%add = select <4 x i1> %cond, <4 x i32> <i32 3000, i32 1, i32 -1, i32 0>, <4 x i32> <i32 42, i32 0, i32 -2, i32 -1> %add = select <4 x i1> %cond, <4 x i32> <i32 3000, i32 1, i32 -1, i32 0>, <4 x i32> <i32 42, i32 0, i32 -2, i32 -1>
ret <4 x i32> %add ret <4 x i32> %add
} }
define <4 x i32> @sel_Cplus1_or_C_vec(<4 x i1> %cond) { define <4 x i32> @sel_Cplus1_or_C_vec(<4 x i1> %cond) {
; CHECK-LABEL: sel_Cplus1_or_C_vec: ; CHECK-LABEL: sel_Cplus1_or_C_vec:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vspltisw 3, 1
; CHECK-NEXT: addis 3, 2, .LCPI2_0@toc@ha ; CHECK-NEXT: addis 3, 2, .LCPI2_0@toc@ha
; CHECK-NEXT: vspltisw 3, 1
; CHECK-NEXT: addi 3, 3, .LCPI2_0@toc@l ; CHECK-NEXT: addi 3, 3, .LCPI2_0@toc@l
; CHECK-NEXT: lxvd2x 0, 0, 3
; CHECK-NEXT: xxland 34, 34, 35 ; CHECK-NEXT: xxland 34, 34, 35
; CHECK-NEXT: lvx 3, 0, 3 ; CHECK-NEXT: xxswapd 36, 0
; CHECK-NEXT: vadduwm 2, 2, 3 ; CHECK-NEXT: vadduwm 2, 2, 4
; CHECK-NEXT: blr ; CHECK-NEXT: blr
%add = select <4 x i1> %cond, <4 x i32> <i32 43, i32 1, i32 -1, i32 0>, <4 x i32> <i32 42, i32 0, i32 -2, i32 -1> %add = select <4 x i1> %cond, <4 x i32> <i32 43, i32 1, i32 -1, i32 0>, <4 x i32> <i32 42, i32 0, i32 -2, i32 -1>
ret <4 x i32> %add ret <4 x i32> %add
} }
define <4 x i32> @cmp_sel_Cplus1_or_C_vec(<4 x i32> %x, <4 x i32> %y) { define <4 x i32> @cmp_sel_Cplus1_or_C_vec(<4 x i32> %x, <4 x i32> %y) {
; CHECK-LABEL: cmp_sel_Cplus1_or_C_vec: ; CHECK-LABEL: cmp_sel_Cplus1_or_C_vec:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vcmpequw 2, 2, 3
; CHECK-NEXT: addis 3, 2, .LCPI3_0@toc@ha ; CHECK-NEXT: addis 3, 2, .LCPI3_0@toc@ha
; CHECK-NEXT: vcmpequw 2, 2, 3
; CHECK-NEXT: addi 3, 3, .LCPI3_0@toc@l ; CHECK-NEXT: addi 3, 3, .LCPI3_0@toc@l
; CHECK-NEXT: lvx 3, 0, 3 ; CHECK-NEXT: lxvd2x 0, 0, 3
; CHECK-NEXT: xxswapd 35, 0
; CHECK-NEXT: vsubuwm 2, 3, 2 ; CHECK-NEXT: vsubuwm 2, 3, 2
; CHECK-NEXT: blr ; CHECK-NEXT: blr
%cond = icmp eq <4 x i32> %x, %y %cond = icmp eq <4 x i32> %x, %y
%add = select <4 x i1> %cond, <4 x i32> <i32 43, i32 1, i32 -1, i32 0>, <4 x i32> <i32 42, i32 0, i32 -2, i32 -1> %add = select <4 x i1> %cond, <4 x i32> <i32 43, i32 1, i32 -1, i32 0>, <4 x i32> <i32 42, i32 0, i32 -2, i32 -1>
ret <4 x i32> %add ret <4 x i32> %add
} }
define <4 x i32> @sel_Cminus1_or_C_vec(<4 x i1> %cond) { define <4 x i32> @sel_Cminus1_or_C_vec(<4 x i1> %cond) {
; CHECK-LABEL: sel_Cminus1_or_C_vec: ; CHECK-LABEL: sel_Cminus1_or_C_vec:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vspltisw 3, -16 ; CHECK-NEXT: vspltisw 3, -16
; CHECK-NEXT: vspltisw 4, 15 ; CHECK-NEXT: vspltisw 4, 15
; CHECK-NEXT: addis 3, 2, .LCPI4_0@toc@ha ; CHECK-NEXT: addis 3, 2, .LCPI4_0@toc@ha
; CHECK-NEXT: addi 3, 3, .LCPI4_0@toc@l ; CHECK-NEXT: addi 3, 3, .LCPI4_0@toc@l
; CHECK-NEXT: lxvd2x 0, 0, 3
; CHECK-NEXT: vsubuwm 3, 4, 3 ; CHECK-NEXT: vsubuwm 3, 4, 3
; CHECK-NEXT: vslw 2, 2, 3 ; CHECK-NEXT: vslw 2, 2, 3
; CHECK-NEXT: vsraw 2, 2, 3 ; CHECK-NEXT: vsraw 2, 2, 3
; CHECK-NEXT: lvx 3, 0, 3 ; CHECK-NEXT: xxswapd 35, 0
; CHECK-NEXT: vadduwm 2, 2, 3 ; CHECK-NEXT: vadduwm 2, 2, 3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
%add = select <4 x i1> %cond, <4 x i32> <i32 43, i32 1, i32 -1, i32 0>, <4 x i32> <i32 44, i32 2, i32 0, i32 1> %add = select <4 x i1> %cond, <4 x i32> <i32 43, i32 1, i32 -1, i32 0>, <4 x i32> <i32 44, i32 2, i32 0, i32 1>
ret <4 x i32> %add ret <4 x i32> %add
} }
define <4 x i32> @cmp_sel_Cminus1_or_C_vec(<4 x i32> %x, <4 x i32> %y) { define <4 x i32> @cmp_sel_Cminus1_or_C_vec(<4 x i32> %x, <4 x i32> %y) {
; CHECK-LABEL: cmp_sel_Cminus1_or_C_vec: ; CHECK-LABEL: cmp_sel_Cminus1_or_C_vec:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vcmpequw 2, 2, 3
; CHECK-NEXT: addis 3, 2, .LCPI5_0@toc@ha ; CHECK-NEXT: addis 3, 2, .LCPI5_0@toc@ha
; CHECK-NEXT: vcmpequw 2, 2, 3
; CHECK-NEXT: addi 3, 3, .LCPI5_0@toc@l ; CHECK-NEXT: addi 3, 3, .LCPI5_0@toc@l
; CHECK-NEXT: lvx 3, 0, 3 ; CHECK-NEXT: lxvd2x 0, 0, 3
; CHECK-NEXT: xxswapd 35, 0
; CHECK-NEXT: vadduwm 2, 2, 3 ; CHECK-NEXT: vadduwm 2, 2, 3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
%cond = icmp eq <4 x i32> %x, %y %cond = icmp eq <4 x i32> %x, %y
%add = select <4 x i1> %cond, <4 x i32> <i32 43, i32 1, i32 -1, i32 0>, <4 x i32> <i32 44, i32 2, i32 0, i32 1> %add = select <4 x i1> %cond, <4 x i32> <i32 43, i32 1, i32 -1, i32 0>, <4 x i32> <i32 44, i32 2, i32 0, i32 1>
ret <4 x i32> %add ret <4 x i32> %add
} }
define <4 x i32> @sel_minus1_or_0_vec(<4 x i1> %cond) { define <4 x i32> @sel_minus1_or_0_vec(<4 x i1> %cond) {
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llvm/test/CodeGen/PowerPC/vsx-ldst.ll

; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mattr=+vsx -O2 \ ; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mattr=+vsx -O2 \
; RUN: -mtriple=powerpc64-unknown-linux-gnu < %s > %t ; RUN: -mtriple=powerpc64-unknown-linux-gnu < %s > %t
; RUN: grep lxvw4x < %t | count 3 ; RUN: grep lxvw4x < %t | count 3
; RUN: grep lxvd2x < %t | count 3 ; RUN: grep lxvd2x < %t | count 3
; RUN: grep stxvw4x < %t | count 3 ; RUN: grep stxvw4x < %t | count 3
; RUN: grep stxvd2x < %t | count 3 ; RUN: grep stxvd2x < %t | count 3
; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mattr=+vsx -O0 -fast-isel=1 \ ; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mattr=+vsx -O0 -fast-isel=1 \
; RUN: -mtriple=powerpc64-unknown-linux-gnu < %s > %t ; RUN: -mtriple=powerpc64-unknown-linux-gnu < %s > %t
; RUN: grep lxvw4x < %t | count 3 ; RUN: grep lxvw4x < %t | count 3
; RUN: grep lxvd2x < %t | count 3 ; RUN: grep lxvd2x < %t | count 3
; RUN: grep stxvw4x < %t | count 3 ; RUN: grep stxvw4x < %t | count 3
; RUN: grep stxvd2x < %t | count 3 ; RUN: grep stxvd2x < %t | count 3
; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mattr=+vsx -O2 \ ; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mattr=+vsx -O2 \
; RUN: -mtriple=powerpc64le-unknown-linux-gnu < %s > %t ; RUN: -mtriple=powerpc64le-unknown-linux-gnu < %s > %t
; RUN: grep lxvd2x < %t | count 3 ; RUN: grep lxvd2x < %t | count 6
; RUN: grep lvx < %t | count 3 ; RUN: grep stxvd2x < %t | count 6
; RUN: grep stxvd2x < %t | count 3
; RUN: grep stvx < %t | count 3
; RUN: llc -verify-machineinstrs -mcpu=pwr9 -O2 \ ; RUN: llc -verify-machineinstrs -mcpu=pwr9 -O2 \
; RUN: -mtriple=powerpc64le-unknown-linux-gnu < %s > %t ; RUN: -mtriple=powerpc64le-unknown-linux-gnu < %s > %t
; RUN: grep lxv < %t | count 6 ; RUN: grep lxv < %t | count 6
; RUN: grep stxv < %t | count 6 ; RUN: grep stxv < %t | count 6
@vsi = global <4 x i32> <i32 -1, i32 2, i32 -3, i32 4>, align 16 @vsi = global <4 x i32> <i32 -1, i32 2, i32 -3, i32 4>, align 16
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llvm/test/CodeGen/PowerPC/vsx.ll

Show First 20 Lines • Show All 1,032 Lines • ▼ Show 20 Lines
; ;
; CHECK-FISL-LABEL: test32: ; CHECK-FISL-LABEL: test32:
; CHECK-FISL: # %bb.0: ; CHECK-FISL: # %bb.0:
; CHECK-FISL-NEXT: lxvw4x v2, 0, r3 ; CHECK-FISL-NEXT: lxvw4x v2, 0, r3
; CHECK-FISL-NEXT: blr ; CHECK-FISL-NEXT: blr
; ;
; CHECK-LE-LABEL: test32: ; CHECK-LE-LABEL: test32:
; CHECK-LE: # %bb.0: ; CHECK-LE: # %bb.0:
; CHECK-LE-NEXT: lvx v2, 0, r3 ; CHECK-LE-NEXT: lxvd2x vs0, 0, r3
; CHECK-LE-NEXT: xxswapd v2, vs0
; CHECK-LE-NEXT: blr ; CHECK-LE-NEXT: blr
%v = load <4 x float>, <4 x float>* %a, align 16 %v = load <4 x float>, <4 x float>* %a, align 16
ret <4 x float> %v ret <4 x float> %v
} }
Show All 10 Lines
; ;
; CHECK-FISL-LABEL: test33: ; CHECK-FISL-LABEL: test33:
; CHECK-FISL: # %bb.0: ; CHECK-FISL: # %bb.0:
; CHECK-FISL-NEXT: stxvw4x v2, 0, r3 ; CHECK-FISL-NEXT: stxvw4x v2, 0, r3
; CHECK-FISL-NEXT: blr ; CHECK-FISL-NEXT: blr
; ;
; CHECK-LE-LABEL: test33: ; CHECK-LE-LABEL: test33:
; CHECK-LE: # %bb.0: ; CHECK-LE: # %bb.0:
; CHECK-LE-NEXT: stvx v2, 0, r3 ; CHECK-LE-NEXT: xxswapd vs0, v2
; CHECK-LE-NEXT: stxvd2x vs0, 0, r3
; CHECK-LE-NEXT: blr ; CHECK-LE-NEXT: blr
store <4 x float> %b, <4 x float>* %a, align 16 store <4 x float> %b, <4 x float>* %a, align 16
ret void ret void
} }
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; ;
; CHECK-FISL-LABEL: test34: ; CHECK-FISL-LABEL: test34:
; CHECK-FISL: # %bb.0: ; CHECK-FISL: # %bb.0:
; CHECK-FISL-NEXT: lxvw4x v2, 0, r3 ; CHECK-FISL-NEXT: lxvw4x v2, 0, r3
; CHECK-FISL-NEXT: blr ; CHECK-FISL-NEXT: blr
; ;
; CHECK-LE-LABEL: test34: ; CHECK-LE-LABEL: test34:
; CHECK-LE: # %bb.0: ; CHECK-LE: # %bb.0:
; CHECK-LE-NEXT: lvx v2, 0, r3 ; CHECK-LE-NEXT: lxvd2x vs0, 0, r3
; CHECK-LE-NEXT: xxswapd v2, vs0
; CHECK-LE-NEXT: blr ; CHECK-LE-NEXT: blr
%v = load <4 x i32>, <4 x i32>* %a, align 16 %v = load <4 x i32>, <4 x i32>* %a, align 16
ret <4 x i32> %v ret <4 x i32> %v
} }
Show All 10 Lines
; ;
; CHECK-FISL-LABEL: test35: ; CHECK-FISL-LABEL: test35:
; CHECK-FISL: # %bb.0: ; CHECK-FISL: # %bb.0:
; CHECK-FISL-NEXT: stxvw4x v2, 0, r3 ; CHECK-FISL-NEXT: stxvw4x v2, 0, r3
; CHECK-FISL-NEXT: blr ; CHECK-FISL-NEXT: blr
; ;
; CHECK-LE-LABEL: test35: ; CHECK-LE-LABEL: test35:
; CHECK-LE: # %bb.0: ; CHECK-LE: # %bb.0:
; CHECK-LE-NEXT: stvx v2, 0, r3 ; CHECK-LE-NEXT: xxswapd vs0, v2
; CHECK-LE-NEXT: stxvd2x vs0, 0, r3
; CHECK-LE-NEXT: blr ; CHECK-LE-NEXT: blr
store <4 x i32> %b, <4 x i32>* %a, align 16 store <4 x i32> %b, <4 x i32>* %a, align 16
ret void ret void
} }
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; CHECK-FISL-NEXT: lxvd2x v2, 0, r3 ; CHECK-FISL-NEXT: lxvd2x v2, 0, r3
; CHECK-FISL-NEXT: xvcvsxddp v2, v2 ; CHECK-FISL-NEXT: xvcvsxddp v2, v2
; CHECK-FISL-NEXT: blr ; CHECK-FISL-NEXT: blr
; ;
; CHECK-LE-LABEL: test69: ; CHECK-LE-LABEL: test69:
; CHECK-LE: # %bb.0: ; CHECK-LE: # %bb.0:
; CHECK-LE-NEXT: addis r3, r2, .LCPI63_0@toc@ha ; CHECK-LE-NEXT: addis r3, r2, .LCPI63_0@toc@ha
; CHECK-LE-NEXT: addi r3, r3, .LCPI63_0@toc@l ; CHECK-LE-NEXT: addi r3, r3, .LCPI63_0@toc@l
; CHECK-LE-NEXT: lvx v3, 0, r3 ; CHECK-LE-NEXT: lxvd2x vs0, 0, r3
; CHECK-LE-NEXT: addis r3, r2, .LCPI63_1@toc@ha ; CHECK-LE-NEXT: addis r3, r2, .LCPI63_1@toc@ha
; CHECK-LE-NEXT: addi r3, r3, .LCPI63_1@toc@l ; CHECK-LE-NEXT: addi r3, r3, .LCPI63_1@toc@l
; CHECK-LE-NEXT: xxswapd v3, vs0
; CHECK-LE-NEXT: lxvd2x vs0, 0, r3 ; CHECK-LE-NEXT: lxvd2x vs0, 0, r3
; CHECK-LE-NEXT: vperm v2, v2, v2, v3 ; CHECK-LE-NEXT: vperm v2, v2, v2, v3
; CHECK-LE-NEXT: xxswapd v3, vs0 ; CHECK-LE-NEXT: xxswapd v3, vs0
; CHECK-LE-NEXT: vsld v2, v2, v3 ; CHECK-LE-NEXT: vsld v2, v2, v3
; CHECK-LE-NEXT: vsrad v2, v2, v3 ; CHECK-LE-NEXT: vsrad v2, v2, v3
; CHECK-LE-NEXT: xvcvsxddp v2, v2 ; CHECK-LE-NEXT: xvcvsxddp v2, v2
; CHECK-LE-NEXT: blr ; CHECK-LE-NEXT: blr
%w = sitofp <2 x i16> %a to <2 x double> %w = sitofp <2 x i16> %a to <2 x double>
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; CHECK-FISL-NEXT: lxvd2x v2, 0, r3 ; CHECK-FISL-NEXT: lxvd2x v2, 0, r3
; CHECK-FISL-NEXT: xvcvsxddp v2, v2 ; CHECK-FISL-NEXT: xvcvsxddp v2, v2
; CHECK-FISL-NEXT: blr ; CHECK-FISL-NEXT: blr
; ;
; CHECK-LE-LABEL: test70: ; CHECK-LE-LABEL: test70:
; CHECK-LE: # %bb.0: ; CHECK-LE: # %bb.0:
; CHECK-LE-NEXT: addis r3, r2, .LCPI64_0@toc@ha ; CHECK-LE-NEXT: addis r3, r2, .LCPI64_0@toc@ha
; CHECK-LE-NEXT: addi r3, r3, .LCPI64_0@toc@l ; CHECK-LE-NEXT: addi r3, r3, .LCPI64_0@toc@l
; CHECK-LE-NEXT: lvx v3, 0, r3 ; CHECK-LE-NEXT: lxvd2x vs0, 0, r3
; CHECK-LE-NEXT: addis r3, r2, .LCPI64_1@toc@ha ; CHECK-LE-NEXT: addis r3, r2, .LCPI64_1@toc@ha
; CHECK-LE-NEXT: addi r3, r3, .LCPI64_1@toc@l ; CHECK-LE-NEXT: addi r3, r3, .LCPI64_1@toc@l
; CHECK-LE-NEXT: xxswapd v3, vs0
; CHECK-LE-NEXT: lxvd2x vs0, 0, r3 ; CHECK-LE-NEXT: lxvd2x vs0, 0, r3
; CHECK-LE-NEXT: vperm v2, v2, v2, v3 ; CHECK-LE-NEXT: vperm v2, v2, v2, v3
; CHECK-LE-NEXT: xxswapd v3, vs0 ; CHECK-LE-NEXT: xxswapd v3, vs0
; CHECK-LE-NEXT: vsld v2, v2, v3 ; CHECK-LE-NEXT: vsld v2, v2, v3
; CHECK-LE-NEXT: vsrad v2, v2, v3 ; CHECK-LE-NEXT: vsrad v2, v2, v3
; CHECK-LE-NEXT: xvcvsxddp v2, v2 ; CHECK-LE-NEXT: xvcvsxddp v2, v2
; CHECK-LE-NEXT: blr ; CHECK-LE-NEXT: blr
%w = sitofp <2 x i8> %a to <2 x double> %w = sitofp <2 x i8> %a to <2 x double>
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; CHECK-FISL-NEXT: addis r3, r2, .LCPI65_0@toc@ha ; CHECK-FISL-NEXT: addis r3, r2, .LCPI65_0@toc@ha
; CHECK-FISL-NEXT: addi r3, r3, .LCPI65_0@toc@l ; CHECK-FISL-NEXT: addi r3, r3, .LCPI65_0@toc@l
; CHECK-FISL-NEXT: lxvw4x v3, 0, r3 ; CHECK-FISL-NEXT: lxvw4x v3, 0, r3
; CHECK-FISL-NEXT: vadduwm v2, v2, v3 ; CHECK-FISL-NEXT: vadduwm v2, v2, v3
; CHECK-FISL-NEXT: blr ; CHECK-FISL-NEXT: blr
; ;
; CHECK-LE-LABEL: test80: ; CHECK-LE-LABEL: test80:
; CHECK-LE: # %bb.0: ; CHECK-LE: # %bb.0:
; CHECK-LE-NEXT: mtfprwz f0, r3
; CHECK-LE-NEXT: addis r4, r2, .LCPI65_0@toc@ha ; CHECK-LE-NEXT: addis r4, r2, .LCPI65_0@toc@ha
; CHECK-LE-NEXT: addi r3, r4, .LCPI65_0@toc@l ; CHECK-LE-NEXT: mtfprwz f1, r3
; CHECK-LE-NEXT: xxspltw v2, vs0, 1 ; CHECK-LE-NEXT: addi r4, r4, .LCPI65_0@toc@l
; CHECK-LE-NEXT: lvx v3, 0, r3 ; CHECK-LE-NEXT: lxvd2x vs0, 0, r4
; CHECK-LE-NEXT: xxspltw v2, vs1, 1
; CHECK-LE-NEXT: xxswapd v3, vs0
; CHECK-LE-NEXT: vadduwm v2, v2, v3 ; CHECK-LE-NEXT: vadduwm v2, v2, v3
; CHECK-LE-NEXT: blr ; CHECK-LE-NEXT: blr
%b1 = insertelement <2 x i32> undef, i32 %v, i32 0 %b1 = insertelement <2 x i32> undef, i32 %v, i32 0
%b2 = shufflevector <2 x i32> %b1, <2 x i32> undef, <2 x i32> zeroinitializer %b2 = shufflevector <2 x i32> %b1, <2 x i32> undef, <2 x i32> zeroinitializer
%i = add <2 x i32> %b2, <i32 2, i32 3> %i = add <2 x i32> %b2, <i32 2, i32 3>
ret <2 x i32> %i ret <2 x i32> %i
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llvm/test/CodeGen/PowerPC/vsx_insert_extract_le.ll

Show First 20 Lines • Show All 88 Lines • ▼ Show 20 Lines; CHECK-P9-NEXT: blr
ret <2 x double> %r ret <2 x double> %r
} }
define double @teste0(<2 x double>* %p1) { define double @teste0(<2 x double>* %p1) {
; CHECK-LABEL: teste0: ; CHECK-LABEL: teste0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lxvd2x vs1, 0, r3 ; CHECK-NEXT: lfd f1, 0(r3)
; CHECK-NEXT: # kill: def $f1 killed $f1 killed $vsl1
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-BE-LABEL: teste0: ; CHECK-P8-BE-LABEL: teste0:
; CHECK-P8-BE: # %bb.0: ; CHECK-P8-BE: # %bb.0:
; CHECK-P8-BE-NEXT: lfd f1, 0(r3) ; CHECK-P8-BE-NEXT: lfd f1, 0(r3)
; CHECK-P8-BE-NEXT: blr ; CHECK-P8-BE-NEXT: blr
; ;
; CHECK-P9-VECTOR-LABEL: teste0: ; CHECK-P9-VECTOR-LABEL: teste0:
; CHECK-P9-VECTOR: # %bb.0: ; CHECK-P9-VECTOR: # %bb.0:
; CHECK-P9-VECTOR-NEXT: lxvd2x vs1, 0, r3 ; CHECK-P9-VECTOR-NEXT: lfd f1, 0(r3)
; CHECK-P9-VECTOR-NEXT: # kill: def $f1 killed $f1 killed $vsl1
; CHECK-P9-VECTOR-NEXT: blr ; CHECK-P9-VECTOR-NEXT: blr
; ;
; CHECK-P9-LABEL: teste0: ; CHECK-P9-LABEL: teste0:
; CHECK-P9: # %bb.0: ; CHECK-P9: # %bb.0:
; CHECK-P9-NEXT: lfd f1, 0(r3) ; CHECK-P9-NEXT: lfd f1, 0(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
%v = load <2 x double>, <2 x double>* %p1 %v = load <2 x double>, <2 x double>* %p1
%r = extractelement <2 x double> %v, i32 0 %r = extractelement <2 x double> %v, i32 0
ret double %r ret double %r
} }
define double @teste1(<2 x double>* %p1) { define double @teste1(<2 x double>* %p1) {
; CHECK-LABEL: teste1: ; CHECK-LABEL: teste1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lxvd2x vs0, 0, r3 ; CHECK-NEXT: lfd f1, 8(r3)
; CHECK-NEXT: xxswapd vs1, vs0
; CHECK-NEXT: # kill: def $f1 killed $f1 killed $vsl1
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-BE-LABEL: teste1: ; CHECK-P8-BE-LABEL: teste1:
; CHECK-P8-BE: # %bb.0: ; CHECK-P8-BE: # %bb.0:
; CHECK-P8-BE-NEXT: lfd f1, 8(r3) ; CHECK-P8-BE-NEXT: lfd f1, 8(r3)
; CHECK-P8-BE-NEXT: blr ; CHECK-P8-BE-NEXT: blr
; ;
; CHECK-P9-VECTOR-LABEL: teste1: ; CHECK-P9-VECTOR-LABEL: teste1:
; CHECK-P9-VECTOR: # %bb.0: ; CHECK-P9-VECTOR: # %bb.0:
; CHECK-P9-VECTOR-NEXT: lxvd2x vs0, 0, r3 ; CHECK-P9-VECTOR-NEXT: lfd f1, 8(r3)
; CHECK-P9-VECTOR-NEXT: xxswapd vs1, vs0
; CHECK-P9-VECTOR-NEXT: # kill: def $f1 killed $f1 killed $vsl1
; CHECK-P9-VECTOR-NEXT: blr ; CHECK-P9-VECTOR-NEXT: blr
; ;
; CHECK-P9-LABEL: teste1: ; CHECK-P9-LABEL: teste1:
; CHECK-P9: # %bb.0: ; CHECK-P9: # %bb.0:
; CHECK-P9-NEXT: lfd f1, 8(r3) ; CHECK-P9-NEXT: lfd f1, 8(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
%v = load <2 x double>, <2 x double>* %p1 %v = load <2 x double>, <2 x double>* %p1
%r = extractelement <2 x double> %v, i32 1 %r = extractelement <2 x double> %v, i32 1
ret double %r ret double %r
} }

llvm/test/CodeGen/PowerPC/vsx_shuffle_le.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mattr=+vsx \ ; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mattr=+vsx \
; RUN: -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s ; RUN: -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s
; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mattr=-power9-vector \ ; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mattr=-power9-vector \
; RUN: -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s ; RUN: -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s
; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mattr=+vsx \ ; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mattr=+vsx \
; RUN: -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s \ ; RUN: -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s \
; RUN: --check-prefix=CHECK-P9 --implicit-check-not xxswapd ; RUN: --check-prefix=CHECK-P9 --implicit-check-not xxswapd
define <2 x double> @test00(<2 x double>* %p1, <2 x double>* %p2) { define <2 x double> @test00(<2 x double>* %p1, <2 x double>* %p2) {
; CHECK-LABEL: test00: ; CHECK-LABEL: test00:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lxvd2x 0, 0, 3 ; CHECK-NEXT: lxvdsx 34, 0, 3
; CHECK-NEXT: xxspltd 34, 0, 0
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P9-LABEL: test00: ; CHECK-P9-LABEL: test00:
; CHECK-P9: # %bb.0: ; CHECK-P9: # %bb.0:
; CHECK-P9-NEXT: lxvdsx 34, 0, 3 ; CHECK-P9-NEXT: lxvdsx 34, 0, 3
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
%v1 = load <2 x double>, <2 x double>* %p1 %v1 = load <2 x double>, <2 x double>* %p1
%v2 = load <2 x double>, <2 x double>* %p2 %v2 = load <2 x double>, <2 x double>* %p2
▲ Show 20 Lines • Show All 76 Lines • ▼ Show 20 Lines; CHECK-P9-NEXT: blr
%v2 = load <2 x double>, <2 x double>* %p2 %v2 = load <2 x double>, <2 x double>* %p2
%v3 = shufflevector <2 x double> %v1, <2 x double> %v2, <2 x i32> < i32 1, i32 0> %v3 = shufflevector <2 x double> %v1, <2 x double> %v2, <2 x i32> < i32 1, i32 0>
ret <2 x double> %v3 ret <2 x double> %v3
} }
define <2 x double> @test11(<2 x double>* %p1, <2 x double>* %p2) { define <2 x double> @test11(<2 x double>* %p1, <2 x double>* %p2) {
; CHECK-LABEL: test11: ; CHECK-LABEL: test11:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lxvd2x 0, 0, 3 ; CHECK-NEXT: addi 3, 3, 8
; CHECK-NEXT: xxspltd 34, 0, 1 ; CHECK-NEXT: lxvdsx 34, 0, 3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P9-LABEL: test11: ; CHECK-P9-LABEL: test11:
; CHECK-P9: # %bb.0: ; CHECK-P9: # %bb.0:
; CHECK-P9-NEXT: addi 3, 3, 8 ; CHECK-P9-NEXT: addi 3, 3, 8
; CHECK-P9-NEXT: lxvdsx 34, 0, 3 ; CHECK-P9-NEXT: lxvdsx 34, 0, 3
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
%v1 = load <2 x double>, <2 x double>* %p1 %v1 = load <2 x double>, <2 x double>* %p1
▲ Show 20 Lines • Show All 88 Lines • ▼ Show 20 Lines; CHECK-P9-NEXT: blr
%v2 = load <2 x double>, <2 x double>* %p2 %v2 = load <2 x double>, <2 x double>* %p2
%v3 = shufflevector <2 x double> %v1, <2 x double> %v2, <2 x i32> < i32 2, i32 1> %v3 = shufflevector <2 x double> %v1, <2 x double> %v2, <2 x i32> < i32 2, i32 1>
ret <2 x double> %v3 ret <2 x double> %v3
} }
define <2 x double> @test22(<2 x double>* %p1, <2 x double>* %p2) { define <2 x double> @test22(<2 x double>* %p1, <2 x double>* %p2) {
; CHECK-LABEL: test22: ; CHECK-LABEL: test22:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lxvd2x 0, 0, 4 ; CHECK-NEXT: lxvdsx 34, 0, 4
; CHECK-NEXT: xxspltd 34, 0, 0
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P9-LABEL: test22: ; CHECK-P9-LABEL: test22:
; CHECK-P9: # %bb.0: ; CHECK-P9: # %bb.0:
; CHECK-P9-NEXT: lxvdsx 34, 0, 4 ; CHECK-P9-NEXT: lxvdsx 34, 0, 4
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
%v1 = load <2 x double>, <2 x double>* %p1 %v1 = load <2 x double>, <2 x double>* %p1
%v2 = load <2 x double>, <2 x double>* %p2 %v2 = load <2 x double>, <2 x double>* %p2
▲ Show 20 Lines • Show All 76 Lines • ▼ Show 20 Lines; CHECK-P9-NEXT: blr
%v2 = load <2 x double>, <2 x double>* %p2 %v2 = load <2 x double>, <2 x double>* %p2
%v3 = shufflevector <2 x double> %v1, <2 x double> %v2, <2 x i32> < i32 3, i32 2> %v3 = shufflevector <2 x double> %v1, <2 x double> %v2, <2 x i32> < i32 3, i32 2>
ret <2 x double> %v3 ret <2 x double> %v3
} }
define <2 x double> @test33(<2 x double>* %p1, <2 x double>* %p2) { define <2 x double> @test33(<2 x double>* %p1, <2 x double>* %p2) {
; CHECK-LABEL: test33: ; CHECK-LABEL: test33:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lxvd2x 0, 0, 4 ; CHECK-NEXT: addi 3, 4, 8
; CHECK-NEXT: xxspltd 34, 0, 1 ; CHECK-NEXT: lxvdsx 34, 0, 3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P9-LABEL: test33: ; CHECK-P9-LABEL: test33:
; CHECK-P9: # %bb.0: ; CHECK-P9: # %bb.0:
; CHECK-P9-NEXT: addi 3, 4, 8 ; CHECK-P9-NEXT: addi 3, 4, 8
; CHECK-P9-NEXT: lxvdsx 34, 0, 3 ; CHECK-P9-NEXT: lxvdsx 34, 0, 3
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
%v1 = load <2 x double>, <2 x double>* %p1 %v1 = load <2 x double>, <2 x double>* %p1
%v2 = load <2 x double>, <2 x double>* %p2 %v2 = load <2 x double>, <2 x double>* %p2
%v3 = shufflevector <2 x double> %v1, <2 x double> %v2, <2 x i32> < i32 3, i32 3> %v3 = shufflevector <2 x double> %v1, <2 x double> %v2, <2 x i32> < i32 3, i32 3>
ret <2 x double> %v3 ret <2 x double> %v3
} }