[WIP][RISCV] Fault first load peephole in InsertVSETVLI

[reames]

Summary

Not for review.

Demonstrating what a peephole based handling of VLENFF would look like for discussion purposes. Main purpose of this review is to demonstrate an idea. It will be immediately closed.

llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp

bool canSkipVSETVLIForLoadStore(const MachineInstr &MI,
   case RISCV::PseudoVSSE64_V_M8_MASK:
     EEW = 64;
     break;
   }
 
   return CurInfo.isCompatibleWithLoadStoreEEW(EEW, Require);
 }
 
+bool isFaultFirstLoad(const MachineInstr &MI) {
+  switch (MI.getOpcode()) {
+  default:
+    return false;
+  case RISCV::PseudoVLE8FF_V_M1:
+  case RISCV::PseudoVLE8FF_V_M1_MASK:
+  case RISCV::PseudoVLE8FF_V_M2:
+  case RISCV::PseudoVLE8FF_V_M2_MASK:
+  case RISCV::PseudoVLE8FF_V_M4:
+  case RISCV::PseudoVLE8FF_V_M4_MASK:
+  case RISCV::PseudoVLE8FF_V_M8:
+  case RISCV::PseudoVLE8FF_V_M8_MASK:
+  case RISCV::PseudoVLE8FF_V_MF2:
+  case RISCV::PseudoVLE8FF_V_MF2_MASK:
+  case RISCV::PseudoVLE8FF_V_MF4:
+  case RISCV::PseudoVLE8FF_V_MF4_MASK:
+  case RISCV::PseudoVLE8FF_V_MF8:
+  case RISCV::PseudoVLE8FF_V_MF8_MASK:
+  case RISCV::PseudoVLE16FF_V_M1:
+  case RISCV::PseudoVLE16FF_V_M1_MASK:
+  case RISCV::PseudoVLE16FF_V_M2:
+  case RISCV::PseudoVLE16FF_V_M2_MASK:
+  case RISCV::PseudoVLE16FF_V_M4:
+  case RISCV::PseudoVLE16FF_V_M4_MASK:
+  case RISCV::PseudoVLE16FF_V_M8:
+  case RISCV::PseudoVLE16FF_V_M8_MASK:
+  case RISCV::PseudoVLE16FF_V_MF2:
+  case RISCV::PseudoVLE16FF_V_MF2_MASK:
+  case RISCV::PseudoVLE16FF_V_MF4:
+  case RISCV::PseudoVLE16FF_V_MF4_MASK:
+  case RISCV::PseudoVLE32FF_V_M1:
+  case RISCV::PseudoVLE32FF_V_M1_MASK:
+  case RISCV::PseudoVLE32FF_V_M2:
+  case RISCV::PseudoVLE32FF_V_M2_MASK:
+  case RISCV::PseudoVLE32FF_V_M4:
+  case RISCV::PseudoVLE32FF_V_M4_MASK:
+  case RISCV::PseudoVLE32FF_V_M8:
+  case RISCV::PseudoVLE32FF_V_M8_MASK:
+  case RISCV::PseudoVLE32FF_V_MF2:
+  case RISCV::PseudoVLE32FF_V_MF2_MASK:
+  case RISCV::PseudoVLE64FF_V_M1:
+  case RISCV::PseudoVLE64FF_V_M1_MASK:
+  case RISCV::PseudoVLE64FF_V_M2:
+  case RISCV::PseudoVLE64FF_V_M2_MASK:
+  case RISCV::PseudoVLE64FF_V_M4:
+  case RISCV::PseudoVLE64FF_V_M4_MASK:
+  case RISCV::PseudoVLE64FF_V_M8:
+  case RISCV::PseudoVLE64FF_V_M8_MASK:
+    return true;
+  };
+}
+
+
 bool RISCVInsertVSETVLI::computeVLVTYPEChanges(const MachineBasicBlock &MBB) {
   bool HadVectorOp = false;
 
   BlockData &BBInfo = BlockInfo[MBB.getNumber()];
   BBInfo.Change = BBInfo.Pred;
   for (const MachineInstr &MI : MBB) {
     // If this is an explicit VSETVLI or VSETIVLI, update our state.
     if (isVectorConfigInstr(MI)) {
if (RISCVII::hasSEWOp(TSFlags)) {
             needVSETVLI(NewInfo, BBInfo.Change))
           BBInfo.Change = NewInfo;
       }
     }
 
     // If this is something that updates VL/VTYPE that we don't know about, set
     // the state to unknown.
     if (MI.isCall() || MI.isInlineAsm() || MI.modifiesRegister(RISCV::VL) ||
-        MI.modifiesRegister(RISCV::VTYPE))
+        MI.modifiesRegister(RISCV::VTYPE)) {
+      bool Handled = false;
+      if (isFaultFirstLoad(MI)) {
+        if (std::next(MI.getIterator()) != MBB.end()) {
+          const MachineInstr &NextMI = *std::next(MI.getIterator());
+          if (NextMI.getOpcode() == RISCV::PseudoReadVL) {
+            BBInfo.Change.setAVLReg(NextMI.getOperand(0).getReg());
+            Handled = true;
+          }
+        }
+      }
+      if (!Handled)
         BBInfo.Change = VSETVLIInfo::getUnknown();
     }
+  }
 
   return HadVectorOp;
 }
 
 void RISCVInsertVSETVLI::computeIncomingVLVTYPE(const MachineBasicBlock &MBB) {
 
   BlockData &BBInfo = BlockInfo[MBB.getNumber()];
 
if (RISCVII::hasSEWOp(TSFlags)) {
       }
       PrevVSETVLIMI = nullptr;
     }
 
     // If this is something that updates VL/VTYPE that we don't know about, set
     // the state to unknown.
     if (MI.isCall() || MI.isInlineAsm() || MI.modifiesRegister(RISCV::VL) ||
         MI.modifiesRegister(RISCV::VTYPE)) {
+      bool Handled = false;
+      if (isFaultFirstLoad(MI)) {
+        if (std::next(MI.getIterator()) != MBB.end()) {
+          const MachineInstr &NextMI = *std::next(MI.getIterator());
+          if (NextMI.getOpcode() == RISCV::PseudoReadVL) {
+            CurInfo.setAVLReg(NextMI.getOperand(0).getReg());
+            Handled = true;
+          }
+        }
+      }
+      if (!Handled)
         CurInfo = VSETVLIInfo::getUnknown();
       PrevVSETVLIMI = nullptr;
     }
   }
 
   // If we reach the end of the block and our current info doesn't match the
   // expected info, insert a vsetvli to correct.
   if (!UseStrictAsserts) {
     const VSETVLIInfo &ExitInfo = BlockInfo[MBB.getNumber()].Exit;
if (RISCVII::hasSEWOp(TSFlags)) {
       }
       CurInfo = computeInfoForInstr(MI, TSFlags, MRI);
       continue;
     }
 
     // If this is something that updates VL/VTYPE that we don't know about,
     // set the state to unknown.
     if (MI.isCall() || MI.isInlineAsm() || MI.modifiesRegister(RISCV::VL) ||
-        MI.modifiesRegister(RISCV::VTYPE))
+        MI.modifiesRegister(RISCV::VTYPE)) {
+      bool Handled = false;
+      if (isFaultFirstLoad(MI)) {
+        if (std::next(MI.getIterator()) != MBB.end()) {
+          const MachineInstr &NextMI = *std::next(MI.getIterator());
+          if (NextMI.getOpcode() == RISCV::PseudoReadVL) {
+            CurInfo.setAVLReg(NextMI.getOperand(0).getReg());
+            Handled = true;
+          }
+        }
+      }
+      if (!Handled)
         CurInfo = VSETVLIInfo::getUnknown();
     }
   }
+}
 
 bool RISCVInsertVSETVLI::runOnMachineFunction(MachineFunction &MF) {
   // Skip if the vector extension is not enabled.
   const RISCVSubtarget &ST = MF.getSubtarget<RISCVSubtarget>();
   if (!ST.hasVInstructions())
     return false;
 
   LLVM_DEBUG(dbgs() << "Entering InsertVSETVLI for " << MF.getName() << "\n");

llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll

 ; TODO: The first and third VSETVLIs are redundant here.
 define <vscale x 1 x i64> @vleNff(i64* %str, i64 %n, i64 %x) {
 ; CHECK-LABEL: vleNff:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli zero, a1, e8, m4, ta, mu
 ; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, mu
 ; CHECK-NEXT:    vle64ff.v v8, (a0)
 ; CHECK-NEXT:    csrr a0, vl
-; CHECK-NEXT:    vsetvli zero, a0, e64, m1, tu, mu
+; CHECK-NEXT:    vsetvli zero, zero, e64, m1, tu, mu
 ; CHECK-NEXT:    vadd.vx v8, v8, a2
 ; CHECK-NEXT:    ret
 entry:
   %0 = tail call i64 @llvm.riscv.vsetvli.i64(i64 %n, i64 0, i64 2)
   %1 = bitcast i64* %str to <vscale x 1 x i64>*
   %2 = tail call { <vscale x 1 x i64>, i64 } @llvm.riscv.vleff.nxv1i64.i64(<vscale x 1 x i64> undef, <vscale x 1 x i64>* %1, i64 %0)
   %3 = extractvalue { <vscale x 1 x i64>, i64 } %2, 0
   %4 = extractvalue { <vscale x 1 x i64>, i64 } %2, 1