[SelectionDAG] Fold abs(undef) to 0 instead of undef.

[craig.topper]

Summary

abs should only produce a positive value or the signed minimum
value. This means we can't fold abs(undef) to undef as that would
allow more values. Fold to 0 instead to match InstSimplify.

Fixes test mentioned in comment on pr55271.

[nikic]

LG

llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

case ISD::SIGN_EXTEND_VECTOR_INREG:
     assert(VT.getVectorMinNumElements() <
                Operand.getValueType().getVectorMinNumElements() &&
            "The destination vector type must have fewer lanes than the input.");
     break;
   case ISD::ABS:
     assert(VT.isInteger() && VT == Operand.getValueType() &&
            "Invalid ABS!");
     if (OpOpcode == ISD::UNDEF)
-      return getUNDEF(VT);
+      return getConstant(0, DL, VT);
     break;
   case ISD::BSWAP:
     assert(VT.isInteger() && VT == Operand.getValueType() &&
            "Invalid BSWAP!");
     assert((VT.getScalarSizeInBits() % 16 == 0) &&
            "BSWAP types must be a multiple of 16 bits!");
     if (OpOpcode == ISD::UNDEF)
       return getUNDEF(VT);

llvm/test/CodeGen/X86/pr55271.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu | FileCheck %s
+
+; abs(undef) should fold to 0 not undef.
+
+declare i32 @llvm.abs.i32(i32, i1 immarg) #0
+
+define i32 @abs(i32 %0) {
+; CHECK-LABEL: abs:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    xorl %eax, %eax
+; CHECK-NEXT:    retq
+  %2 = call i32 @llvm.abs.i32(i32 undef, i1 false)
+  ret i32 %2
+}