[AArch64] Fix the generation of BE Nops

[dmgreen]

Summary

Big endian Nops were being generated as d5 03 20 1f fnmadd s21, s30, s0, s0, getting the bytes of the NOP in the wrong order. This switches the bytes to not be dependant on the endianness.

[john.brawn]

LGTM.

llvm/lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp

bool AArch64AsmBackend::writeNopData(raw_ostream &OS, uint64_t Count,
   // If the count is not 4-byte aligned, we must be writing data into the text
   // section (otherwise we have unaligned instructions, and thus have far
   // bigger problems), so just write zeros instead.
   OS.write_zeros(Count % 4);
 
   // We are properly aligned, so write NOPs as requested.
   Count /= 4;
   for (uint64_t i = 0; i != Count; ++i)
-    support::endian::write<uint32_t>(OS, 0xd503201f, Endian);
+    OS.write("\x1f\x20\x03\xd5", 4);
   return true;
 }
 
 bool AArch64AsmBackend::shouldForceRelocation(const MCAssembler &Asm,
                                               const MCFixup &Fixup,
                                               const MCValue &Target) {
   unsigned Kind = Fixup.getKind();
   if (Kind >= FirstLiteralRelocationKind)

llvm/test/MC/AArch64/align.s

+// RUN: llvm-mc -filetype=obj -triple aarch64-none-eabi %s | llvm-objdump -d - | FileCheck %s
+// RUN: llvm-mc -filetype=obj -triple aarch64_be-none-eabi %s | llvm-objdump -d - | FileCheck %s
+
+// CHECK:   0: 00 00 80 d2   mov     x0, #0
+// CHECK:   4: 00 00 80 d2   mov     x0, #0
+// CHECK:   8: 1f 20 03 d5   nop
+// CHECK:   c: 1f 20 03 d5   nop
+// CHECK:  10: 00 00 80 d2   mov     x0, #0
+
+       .text
+       mov x0, #0
+       mov x0, #0
+       .p2align 4
+       mov x0, #0