[mlir][LLVMIR] Add support for translating from some simple LLVM instructions

[myhsu]

Summary

Add support for translating from llvm::Select, llvm::FNeg, and llvm::Unreachable. This patch also cleans up (NFC) the opcode map for simple instructions and adds // clang-format off/on comments to prevent those lines from being churned by clang-format between commits.

[Mogball]

mlir/lib/Target/LLVMIR/ConvertFromLLVMIR.cpp

591

Not part of this patch?

[ftynse]

Nit: could you please update the commit message to specify the translation _from LLVM IR_. Otherwise, it may trick a casual reader into thinking that we haven't supported translating simple instructions _to LLVM IR_ until this point.

mlir/lib/Target/LLVMIR/ConvertFromLLVMIR.cpp

622

Nit: I'd consider wrapping this block into // clang-format off + // clang-format on and manually formatting it to have one instruction per line. This would reformatting-caused churn on every change and make it easy to find relevant instructions (which can be ordered alphabetically or follow their order in LLVM's LangRef).

[myhsu]

Cleanup the opcode map for simple instructions and add // clang-format off/on comments on those lines (NFC).

[myhsu]

Just a FYI: the simple opcode map is sorted by instruction ordering listed in LangRef.

mlir/lib/Target/LLVMIR/ConvertFromLLVMIR.cpp

591

llvm::Invoke had already been implemented previously. I would like to do some NFC clean up on this block of code as part of the // clang-format off/on Alex suggested below.

622

yes, sounds like a good idea, personally I also prefer one instruction per line.

mlir/lib/Target/LLVMIR/ConvertFromLLVMIR.cpp

 /// Return the MLIR OperationName for the given LLVM opcode.
 static StringRef lookupOperationNameFromOpcode(unsigned opcode) {
 // Maps from LLVM opcode to MLIR OperationName. This is deliberately ordered
 // as in llvm/IR/Instructions.def to aid comprehension and spot missing
 // instructions.
 #define INST(llvm_n, mlir_n)                                                   \
   { llvm::Instruction::llvm_n, LLVM::mlir_n##Op::getOperationName() }
   static const DenseMap<unsigned, StringRef> opcMap = {
-      // Ret is handled specially.
+      // clang-format off
+      INST(Ret, Return),
       // Br is handled specially.
       // Switch is handled specially.
       // FIXME: indirectbr
-      // FIXME: invoke
+      // Invoke is handled specially.
       INST(Resume, Resume),
-      // FIXME: unreachable
+      INST(Unreachable, Unreachable),
       // FIXME: cleanupret
       // FIXME: catchret
       // FIXME: catchswitch
       // FIXME: callbr
-      // FIXME: fneg
-      INST(Add, Add), INST(FAdd, FAdd), INST(Sub, Sub), INST(FSub, FSub),
-      INST(Mul, Mul), INST(FMul, FMul), INST(UDiv, UDiv), INST(SDiv, SDiv),
-      INST(FDiv, FDiv), INST(URem, URem), INST(SRem, SRem), INST(FRem, FRem),
-      INST(Shl, Shl), INST(LShr, LShr), INST(AShr, AShr), INST(And, And),
-      INST(Or, Or), INST(Xor, XOr), INST(Alloca, Alloca), INST(Load, Load),
+      INST(FNeg, FNeg),
+      INST(Add, Add),
+      INST(FAdd, FAdd),
+      INST(Sub, Sub),
+      INST(FSub, FSub),
+      INST(Mul, Mul),
+      INST(FMul, FMul),
+      INST(UDiv, UDiv),
+      INST(SDiv, SDiv),
+      INST(FDiv, FDiv),
+      INST(URem, URem),
+      INST(SRem, SRem),
+      INST(FRem, FRem),
+      INST(Shl, Shl),
+      INST(LShr, LShr),
+      INST(AShr, AShr),
+      INST(And, And),
+      INST(Or, Or),
+      INST(Xor, XOr),
+      INST(ExtractElement, ExtractElement),
+      INST(InsertElement, InsertElement),
+      // ShuffleVector is handled specially.
+      // ExtractValue is handled specially.
+      // InsertValue is handled specially.
+      INST(Alloca, Alloca),
+      INST(Load, Load),
       INST(Store, Store),
-      // Getelementptr is handled specially.
-      INST(Ret, Return), INST(Fence, Fence),
+      INST(Fence, Fence),
       // FIXME: atomiccmpxchg
       // FIXME: atomicrmw
-      INST(Trunc, Trunc), INST(ZExt, ZExt), INST(SExt, SExt),
-      INST(FPToUI, FPToUI), INST(FPToSI, FPToSI), INST(UIToFP, UIToFP),
-      INST(SIToFP, SIToFP), INST(FPTrunc, FPTrunc), INST(FPExt, FPExt),
-      INST(PtrToInt, PtrToInt), INST(IntToPtr, IntToPtr),
-      INST(BitCast, Bitcast), INST(AddrSpaceCast, AddrSpaceCast),
-      // FIXME: cleanuppad
-      // FIXME: catchpad
+      // Getelementptr is handled specially.
+      INST(Trunc, Trunc),
+      INST(ZExt, ZExt),
+      INST(SExt, SExt),
+      INST(FPToUI, FPToUI),
+      INST(FPToSI, FPToSI),
+      INST(UIToFP, UIToFP),
+      INST(SIToFP, SIToFP),
+      INST(FPTrunc, FPTrunc),
+      INST(FPExt, FPExt),
+      INST(PtrToInt, PtrToInt),
+      INST(IntToPtr, IntToPtr),
+      INST(BitCast, Bitcast),
+      INST(AddrSpaceCast, AddrSpaceCast),
       // ICmp is handled specially.
       // FCmp is handled specially.
       // PHI is handled specially.
-      INST(Freeze, Freeze), INST(Call, Call),
-      // FIXME: select
+      INST(Select, Select),
+      INST(Freeze, Freeze),
+      INST(Call, Call),
       // FIXME: vaarg
-      INST(ExtractElement, ExtractElement), INST(InsertElement, InsertElement),
-      // ShuffleVector is handled specially.
-      // InsertValue is handled specially.
-      // ExtractValue is handled specially.
       // FIXME: landingpad
+      // FIXME: catchpad
+      // FIXME: cleanuppad
+      // clang-format on
   };
 #undef INST
 
   return opcMap.lookup(opcode);
 }
 
 static ICmpPredicate getICmpPredicate(llvm::CmpInst::Predicate p) {
   switch (p) {
LogicalResult Importer::processInstruction(llvm::Instruction *inst) {
   case llvm::Instruction::FPTrunc:
   case llvm::Instruction::FPExt:
   case llvm::Instruction::PtrToInt:
   case llvm::Instruction::IntToPtr:
   case llvm::Instruction::AddrSpaceCast:
   case llvm::Instruction::Freeze:
   case llvm::Instruction::BitCast:
   case llvm::Instruction::ExtractElement:
-  case llvm::Instruction::InsertElement: {
+  case llvm::Instruction::InsertElement:
+  case llvm::Instruction::Select:
+  case llvm::Instruction::FNeg:
+  case llvm::Instruction::Unreachable: {
     OperationState state(loc, lookupOperationNameFromOpcode(inst->getOpcode()));
     SmallVector<Value, 4> ops;
     ops.reserve(inst->getNumOperands());
     for (auto *op : inst->operand_values()) {
       Value value = processValue(op);
       if (!value)
         return failure();
       ops.push_back(value);

mlir/test/Target/LLVMIR/Import/basic.ll

define void @FPArithmetic(float %a, float %b, double %c, double %d) {
   ; CHECK: %[[a10:[0-9]+]] = llvm.fdiv %arg0, %arg1 : f32
   %8 = fdiv float %a, %b
   ; CHECK: %[[a12:[0-9]+]] = llvm.fdiv %arg2, %arg3 : f64
   %9 = fdiv double %c, %d
   ; CHECK: %[[a11:[0-9]+]] = llvm.frem %arg0, %arg1 : f32
   %10 = frem float %a, %b
   ; CHECK: %[[a13:[0-9]+]] = llvm.frem %arg2, %arg3 : f64
   %11 = frem double %c, %d
+  ; CHECK: %{{.+}} = llvm.fneg %{{.+}} : f32
+  %12 = fneg float %a
+  ; CHECK: %{{.+}} = llvm.fneg %{{.+}} : f64
+  %13 = fneg double %c
   ret void
 }
 
 ; CHECK-LABEL: llvm.func @FPComparison(%arg0: f32, %arg1: f32)
 define void @FPComparison(float %a, float %b) {
   ; CHECK: llvm.fcmp "_false" %arg0, %arg1
   %1 = fcmp false float %a, %b
   ; CHECK: llvm.fcmp "oeq" %arg0, %arg1

 define <4 x half> @insert_element(<4 x half>* %vec, half %v, i32 %idx) {
   ; CHECK: %[[V0:.+]] = llvm.load %{{.+}} : !llvm.ptr<vector<4xf16>>
   %val0 = load <4 x half>, <4 x half>* %vec
   ; CHECK: %[[V1:.+]] = llvm.insertelement %{{.+}}, %[[V0]][%{{.+}} : i32] : vector<4xf16>
   %r = insertelement <4 x half> %val0, half %v, i32 %idx
   ; CHECK: llvm.return %[[V1]]
   ret <4 x half> %r
 }
+
+; Select
+; CHECK-LABEL: llvm.func @select_inst
+define void @select_inst(i32 %arg0, i32 %arg1, i1 %pred) {
+  ; CHECK: %{{.+}} = llvm.select %{{.+}}, %{{.+}}, %{{.+}} : i1, i32
+  %1 = select i1 %pred, i32 %arg0, i32 %arg1
+  ret void
+}
+
+; Unreachable
+; CHECK-LABEL: llvm.func @unreachable_inst
+define void @unreachable_inst() {
+  ; CHECK: llvm.unreachable
+  unreachable
+}