[llvm-readobj] [COFF] Fix the printout for ARM64 packed homed parameters

[mstorsjo]

Summary

If the function has homed parameters but the number of saved registers
is odd, the homed parameters are aligned at the top of the stack (so
they line up with later varargs on the stack), not tightly after the
other saved registers.

[efriedma]

There definitely can't be a gap between the homing area and the stack arguments. Are we sure there's a gap between the homing area and the saved registers, as opposed to putting the saved registers flush against the homing area?

If we're sure, LGTM

[mstorsjo]

In D125462#3509319, @efriedma wrote:

There definitely can't be a gap between the homing area and the stack arguments. Are we sure there's a gap between the homing area and the saved registers, as opposed to putting the saved registers flush against the homing area?

If we're sure, LGTM

Yep, I've verified that the saved registers are saved aligned to the bottom of the stack even in this case.

llvm/test/MC/AArch64/seh-packed-unwind.s

 // CHECK-NEXT:     FunctionLength: 56
 // CHECK-NEXT:     RegF: 0
 // CHECK-NEXT:     RegI: 1
 // CHECK-NEXT:     HomedParameters: Yes
 // CHECK-NEXT:     CR: 0
 // CHECK-NEXT:     FrameSize: 112
 // CHECK-NEXT:     Prologue [
 // CHECK-NEXT:       sub sp, sp, #32
-// CHECK-NEXT:       stp x6, x7, [sp, #56]
-// CHECK-NEXT:       stp x4, x5, [sp, #40]
-// CHECK-NEXT:       stp x2, x3, [sp, #24]
-// CHECK-NEXT:       stp x0, x1, [sp, #8]
+// CHECK-NEXT:       stp x6, x7, [sp, #64]
+// CHECK-NEXT:       stp x4, x5, [sp, #48]
+// CHECK-NEXT:       stp x2, x3, [sp, #32]
+// CHECK-NEXT:       stp x0, x1, [sp, #16]
 // CHECK-NEXT:       str x19, [sp, #-80]!
 // CHECK-NEXT:       end
 // CHECK-NEXT:     ]
 // CHECK-NEXT:   }
 // CHECK-NEXT:   RuntimeFunction {
 // CHECK-NEXT:     Function: func6
 // CHECK-NEXT:     Fragment: No
 // CHECK-NEXT:     FunctionLength: 24
func4:
     .seh_endepilogue
     ret
     .seh_endproc
 
 func5:
     .seh_proc func5
     str x19, [sp, #-80]!
     .seh_save_reg_x x19, 80
-    stp x0,  x1,  [sp, #8]
+    stp x0,  x1,  [sp, #16]
     .seh_nop
-    stp x2,  x3,  [sp, #24]
+    stp x2,  x3,  [sp, #32]
     .seh_nop
-    stp x4,  x5,  [sp, #40]
+    stp x4,  x5,  [sp, #48]
     .seh_nop
-    stp x6,  x7,  [sp, #56]
+    stp x6,  x7,  [sp, #64]
     .seh_nop
     sub sp,  sp,  #32
     .seh_stackalloc 32
     .seh_endprologue
     nop
     .seh_startepilogue
     add sp,  sp,  #32
     .seh_stackalloc 32

llvm/test/tools/llvm-readobj/COFF/arm64-packed-unwind.s

 // CHECK-NEXT:     FunctionLength: 56
 // CHECK-NEXT:     RegF: 0
 // CHECK-NEXT:     RegI: 1
 // CHECK-NEXT:     HomedParameters: Yes
 // CHECK-NEXT:     CR: 0
 // CHECK-NEXT:     FrameSize: 112
 // CHECK-NEXT:     Prologue [
 // CHECK-NEXT:       sub sp, sp, #32
-// CHECK-NEXT:       stp x6, x7, [sp, #56]
-// CHECK-NEXT:       stp x4, x5, [sp, #40]
-// CHECK-NEXT:       stp x2, x3, [sp, #24]
-// CHECK-NEXT:       stp x0, x1, [sp, #8]
+// CHECK-NEXT:       stp x6, x7, [sp, #64]
+// CHECK-NEXT:       stp x4, x5, [sp, #48]
+// CHECK-NEXT:       stp x2, x3, [sp, #32]
+// CHECK-NEXT:       stp x0, x1, [sp, #16]
 // CHECK-NEXT:       str x19, [sp, #-80]!
 // CHECK-NEXT:       end
 // CHECK-NEXT:     ]
 // CHECK-NEXT:   }
 // CHECK-NEXT:   RuntimeFunction {
 // CHECK-NEXT:     Function: func6
 // CHECK-NEXT:     Fragment: No
 // CHECK-NEXT:     FunctionLength: 48

 // CHECK-NEXT:     FunctionLength: 56
 // CHECK-NEXT:     RegF: 0
 // CHECK-NEXT:     RegI: 0
 // CHECK-NEXT:     HomedParameters: Yes
 // CHECK-NEXT:     CR: 1
 // CHECK-NEXT:     FrameSize: 112
 // CHECK-NEXT:     Prologue [
 // CHECK-NEXT:       sub sp, sp, #32
-// CHECK-NEXT:       stp x6, x7, [sp, #56]
-// CHECK-NEXT:       stp x4, x5, [sp, #40]
-// CHECK-NEXT:       stp x2, x3, [sp, #24]
-// CHECK-NEXT:       stp x0, x1, [sp, #8]
+// CHECK-NEXT:       stp x6, x7, [sp, #64]
+// CHECK-NEXT:       stp x4, x5, [sp, #48]
+// CHECK-NEXT:       stp x2, x3, [sp, #32]
+// CHECK-NEXT:       stp x0, x1, [sp, #16]
 // CHECK-NEXT:       str lr, [sp, #-80]!
 // CHECK-NEXT:       end
 // CHECK-NEXT:     ]
 // CHECK-NEXT:   }
 // CHECK-NEXT: ]
 
         .text
         .globl func1

llvm/tools/llvm-readobj/ARMWinEHPrinter.cpp

bool Decoder::dumpPackedARM64Entry(const object::COFFObjectFile &COFF,
   }
   if (LocSZ > 4080) {
     SW.startLine() << format("sub sp, sp, #%d\n", LocSZ - 4080);
     SW.startLine() << "sub sp, sp, #4080\n";
   } else if ((RF.CR() != 3 && LocSZ > 0) || LocSZ > 512) {
     SW.startLine() << format("sub sp, sp, #%d\n", LocSZ);
   }
   if (RF.H()) {
-    SW.startLine() << format("stp x6, x7, [sp, #%d]\n", IntSZ + FpSZ + 48);
-    SW.startLine() << format("stp x4, x5, [sp, #%d]\n", IntSZ + FpSZ + 32);
-    SW.startLine() << format("stp x2, x3, [sp, #%d]\n", IntSZ + FpSZ + 16);
+    SW.startLine() << format("stp x6, x7, [sp, #%d]\n", SavSZ - 16);
+    SW.startLine() << format("stp x4, x5, [sp, #%d]\n", SavSZ - 32);
+    SW.startLine() << format("stp x2, x3, [sp, #%d]\n", SavSZ - 48);
     if (RF.RegI() > 0 || RF.RegF() > 0 || RF.CR() == 1) {
-      SW.startLine() << format("stp x0, x1, [sp, #%d]\n", IntSZ + FpSZ);
+      SW.startLine() << format("stp x0, x1, [sp, #%d]\n", SavSZ - 64);
     } else {
       // This case isn't documented; if neither RegI nor RegF nor CR=1
       // have decremented the stack pointer by SavSZ, we need to do it here
       // (as the final stack adjustment of LocSZ excludes SavSZ).
       SW.startLine() << format("stp x0, x1, [sp, #-%d]!\n", SavSZ);
     }
   }
   int FloatRegs = RF.RegF() > 0 ? RF.RegF() + 1 : 0;