[AMDGPU] Revert wide LDS DMA support.

[rampitec]

Summary

This reverts ffbee7acdcaaf, see also bug 37653 which it was fixing.
The bug claims this is an undocumented feature which actually works.
In the reality it is documented as not working for a good reason.
It likely does something, but it is useless anyway. These instructions
write into the LDS. The LDS address is:

M0 + inst_offset + (TIDinWave * 4).

For a store wider than a DWORD neighboring lanes will overwrite each
other.

[dp]

LGTM

[arsenm]

llvm/test/MC/AMDGPU/mubuf.s

850

If it actually does something, shouldn't the assembler/disassembler still recognize it? We just wouldn't continue selecting

[foad]

llvm/test/MC/AMDGPU/mubuf.s

850

All the documentation I've seen says you're not allowed to use the lds bit on larger-than-dword loads. Then again, this all comes from https://bugs.llvm.org/show_bug.cgi?id=37653 which says it is a "potentially useful but still undocumented feature"...

[foad]

LGTM - the fact that it's still undocumented and never turned out to be "potentially useful" is good enough for me.

[rampitec]

llvm/test/MC/AMDGPU/mubuf.s

850

Right, all the documentation says it is not allowed. For example https://developer.amd.com/wp-content/resources/Vega_Shader_ISA_28July2017.pdf, 8.1.9 Memory Buffer Load to LDS:

The MUBUF instruction format allows reading data from a memory buffer directly into LDS
without passing through VGPRs. This is supported for the following subset of MUBUF
instructions.
• BUFFER_LOAD_{ubyte, sbyte, ushort, sshort, dword, format_x}.

For a wider operands it does something, but that something data race on store to LDS and corrupted output.

llvm/lib/Target/AMDGPU/BUFInstructions.td

 defm : MUBUF_Pseudo_Load_Pats<"BUFFER_LOAD_USHORT", i32, extloadi16_global>;
 defm : MUBUF_Pseudo_Load_Pats<"BUFFER_LOAD_USHORT", i32, zextloadi16_global>;
 defm : MUBUF_Pseudo_Load_Pats<"BUFFER_LOAD_SSHORT", i32, sextloadi16_global>;
 defm : MUBUF_Pseudo_Load_Pats<"BUFFER_LOAD_DWORD", i32, load_global>;
 defm : MUBUF_Pseudo_Load_Pats<"BUFFER_LOAD_DWORDX2", v2i32, load_global>;
 defm : MUBUF_Pseudo_Load_Pats<"BUFFER_LOAD_DWORDX3", v3i32, load_global>;
 defm : MUBUF_Pseudo_Load_Pats<"BUFFER_LOAD_DWORDX4", v4i32, load_global>;
 
-// This is not described in AMD documentation,
-// but 'lds' versions of these opcodes are available
-// in at least GFX8+ chips. See Bug 37653.
-let SubtargetPredicate = isGFX8GFX9 in {
-defm BUFFER_LOAD_DWORDX2_LDS : MUBUF_Pseudo_Loads <
-  "buffer_load_dwordx2", v2i32, 0, 1
->;
-defm BUFFER_LOAD_DWORDX3_LDS : MUBUF_Pseudo_Loads <
-  "buffer_load_dwordx3", v3i32, 0, 1
->;
-defm BUFFER_LOAD_DWORDX4_LDS : MUBUF_Pseudo_Loads <
-  "buffer_load_dwordx4", v4i32, 0, 1
->;
-}
-
 defm BUFFER_STORE_BYTE : MUBUF_Pseudo_Stores <
   "buffer_store_byte", i32, truncstorei8_global
 >;
 defm BUFFER_STORE_SHORT : MUBUF_Pseudo_Stores <
   "buffer_store_short", i32, truncstorei16_global
 >;
 defm BUFFER_STORE_DWORD : MUBUF_Pseudo_Stores <
   "buffer_store_dword", i32, store_global
let SubtargetPredicate = HasPackedD16VMem in {
   defm BUFFER_STORE_FORMAT_D16_XYZ    : MUBUF_Real_AllAddr_vi <0x0e>;
   defm BUFFER_STORE_FORMAT_D16_XYZW   : MUBUF_Real_AllAddr_vi <0x0f>;
 } // End HasPackedD16VMem.
 defm BUFFER_LOAD_UBYTE          : MUBUF_Real_AllAddr_Lds_vi <0x10>;
 defm BUFFER_LOAD_SBYTE          : MUBUF_Real_AllAddr_Lds_vi <0x11>;
 defm BUFFER_LOAD_USHORT         : MUBUF_Real_AllAddr_Lds_vi <0x12>;
 defm BUFFER_LOAD_SSHORT         : MUBUF_Real_AllAddr_Lds_vi <0x13>;
 defm BUFFER_LOAD_DWORD          : MUBUF_Real_AllAddr_Lds_vi <0x14>;
-defm BUFFER_LOAD_DWORDX2        : MUBUF_Real_AllAddr_Lds_vi <0x15>;
-defm BUFFER_LOAD_DWORDX3        : MUBUF_Real_AllAddr_Lds_vi <0x16>;
-defm BUFFER_LOAD_DWORDX4        : MUBUF_Real_AllAddr_Lds_vi <0x17>;
+defm BUFFER_LOAD_DWORDX2        : MUBUF_Real_AllAddr_vi <0x15>;
+defm BUFFER_LOAD_DWORDX3        : MUBUF_Real_AllAddr_vi <0x16>;
+defm BUFFER_LOAD_DWORDX4        : MUBUF_Real_AllAddr_vi <0x17>;
 defm BUFFER_STORE_BYTE          : MUBUF_Real_AllAddr_vi <0x18>;
 defm BUFFER_STORE_BYTE_D16_HI   : MUBUF_Real_AllAddr_vi <0x19>;
 defm BUFFER_STORE_SHORT         : MUBUF_Real_AllAddr_vi <0x1a>;
 defm BUFFER_STORE_SHORT_D16_HI  : MUBUF_Real_AllAddr_vi <0x1b>;
 defm BUFFER_STORE_DWORD         : MUBUF_Real_AllAddr_vi <0x1c>;
 defm BUFFER_STORE_DWORDX2       : MUBUF_Real_AllAddr_vi <0x1d>;
 defm BUFFER_STORE_DWORDX3       : MUBUF_Real_AllAddr_vi <0x1e>;
 defm BUFFER_STORE_DWORDX4       : MUBUF_Real_AllAddr_vi <0x1f>;

llvm/test/MC/AMDGPU/mubuf.s

 buffer_store_lds_dword s[4:7], s0 offset:4095 lds
 // NOSICI: error: instruction not supported on this GPU
 // VI: buffer_store_lds_dword s[4:7], s0 offset:4095 lds ; encoding: [0xff,0x0f,0xf5,0xe0,0x00,0x00,0x01,0x00]
 
 buffer_store_lds_dword s[4:7], s8 offset:4 lds glc slc
 // NOSICI: error: instruction not supported on this GPU
 // VI: buffer_store_lds_dword s[4:7], s8 offset:4 lds glc slc ; encoding: [0x04,0x40,0xf7,0xe0,0x00,0x00,0x01,0x08]
 
-buffer_load_dwordx2 off, s[4:7], s1 lds
-// NOSICI: error: operands are not valid for this GPU or mode
-// VI:   buffer_load_dwordx2 off, s[4:7], s1 lds ; encoding: [0x00,0x00,0x55,0xe0,0x00,0x00,0x01,0x01]
-
-buffer_load_dwordx3 off, s[4:7], s0 offset:4095 lds
-// NOSICI: error: not a valid operand
-// VI:   buffer_load_dwordx3 off, s[4:7], s0 offset:4095 lds ; encoding: [0xff,0x0f,0x59,0xe0,0x00,0x00,0x01,0x00]
-
-buffer_load_dwordx4 off, s[4:7], s1 lds
-// NOSICI: error: operands are not valid for this GPU or mode
-// VI:   buffer_load_dwordx4 off, s[4:7], s1 lds ; encoding: [0x00,0x00,0x5d,0xe0,0x00,0x00,0x01,0x01]
-
 //===----------------------------------------------------------------------===//
 // Errors handling
 //===----------------------------------------------------------------------===//
 
 buffer_load_sbyte off, s[8:11], s3 lds tfe
 // NOSICIVI: error: invalid operand for instruction
 
 buffer_load_dword off, s[8:11], s3 tfe lds