[riscv] Extend dataflow workaround from D119518 to fallthrough blocks

[reames]

Summary

We've got a lurking problem with our data flow implementation where different phases disagree, resulting in possible workarounds. D119518 extended a workaround, but failed to consider blocks without terminators (e.g. fallthroughs).

I have a deeper rework of the algorithm in flight over in D125232, but this patch is specifically a minimal fix for an active miscompile. That change can be reworked over this once landed.

[MaskRay]

RISC-V changes appear to use the upper case [RISCV] much more than [riscv].

[frasercrmck]

LGTM but yeah I think [RISCV] seems more canonical to me.

llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp

for (MachineInstr &MI : MBB) {
 
     // If this is something that updates VL/VTYPE that we don't know about, set
     // the state to unknown.
     if (MI.isCall() || MI.isInlineAsm() || MI.modifiesRegister(RISCV::VL) ||
         MI.modifiesRegister(RISCV::VTYPE)) {
       CurInfo = VSETVLIInfo::getUnknown();
       PrevVSETVLIMI = nullptr;
     }
+  }
 
-    // If we reach the end of the block and our current info doesn't match the
-    // expected info, insert a vsetvli to correct.
-    if (!UseStrictAsserts && MI.isTerminator()) {
-      const VSETVLIInfo &ExitInfo = BlockInfo[MBB.getNumber()].Exit;
-      if (CurInfo.isValid() && ExitInfo.isValid() && !ExitInfo.isUnknown() &&
-          CurInfo != ExitInfo) {
-        insertVSETVLI(MBB, MI, ExitInfo, CurInfo);
-        CurInfo = ExitInfo;
-      }
-    }
-  }
+  if (!UseStrictAsserts) {
+      // Note there's an implicit assumption here that terminators never use
+      // or modify VL or VTYPE.  Also, fallthrough will return end().
+      auto InsertPt = MBB.getFirstTerminator().getInstrIterator();
+      insertVSETVLI(MBB, InsertPt, MBB.findDebugLoc(InsertPt), ExitInfo, CurInfo);
 
   if (UseStrictAsserts && CurInfo.isValid()) {
     const auto &Info = BlockInfo[MBB.getNumber()];
     if (CurInfo != Info.Exit) {
       LLVM_DEBUG(dbgs() << "in block " << printMBBReference(MBB) << "\n");
       LLVM_DEBUG(dbgs() << "  begin        state: " << Info.Pred << "\n");
       LLVM_DEBUG(dbgs() << "  expected end state: " << Info.Exit << "\n");
       LLVM_DEBUG(dbgs() << "  actual   end state: " << CurInfo << "\n");

llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.mir

body:             |
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT: bb.1:
   ; CHECK-NEXT:   successors: %bb.2(0x80000000)
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT:   [[PHI:%[0-9]+]]:gpr = PHI [[COPY2]], %bb.0, %10, %bb.2
   ; CHECK-NEXT:   [[PseudoVADD_VX_M1_:%[0-9]+]]:vr = PseudoVADD_VX_M1 [[PseudoVID_V_M1_]], [[PHI]], -1, 6 /* e64 */, implicit $vl, implicit $vtype
   ; CHECK-NEXT:   [[MUL:%[0-9]+]]:gpr = MUL [[PHI]], [[SRLI]]
   ; CHECK-NEXT:   [[ADD:%[0-9]+]]:gpr = ADD [[COPY]], [[MUL]]
-  ; FIXME: We insert a SEW=32,LMUL=1/2 VSETVLI here but no SEW=64,LMUL=1
-  ; VSETVLI before the VADD above. This misconfigures the VADD in the case that
-  ; the loop takes its backedge.
   ; CHECK-NEXT:   dead $x0 = PseudoVSETVLIX0 killed $x0, 87 /* e32, mf2, ta, mu */, implicit-def $vl, implicit-def $vtype, implicit $vl
   ; CHECK-NEXT:   PseudoVSE32_V_MF2 killed [[PseudoVADD_VX_M1_]], killed [[ADD]], -1, 5 /* e32 */, implicit $vl, implicit $vtype
   ; CHECK-NEXT:   [[ADDI:%[0-9]+]]:gpr = ADDI [[PHI]], 1
+  ; CHECK-NEXT:   dead $x0 = PseudoVSETVLIX0 killed $x0, 88 /* e64, m1, ta, mu */, implicit-def $vl, implicit-def $vtype, implicit $vl
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT: bb.2:
   ; CHECK-NEXT:   successors: %bb.1(0x40000000), %bb.3(0x40000000)
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT:   BLTU [[ADDI]], [[COPY1]], %bb.1
   ; CHECK-NEXT:   PseudoBR %bb.3
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT: bb.3: