[AMDGPU][GFX10] Support base+soffset+offset SMEM loads.

[kosarev]

Summary

Also makes a step towards resolving
https://github.com/llvm/llvm-project/issues/38652

[kosarev]

llvm/test/MC/Disassembler/AMDGPU/gfx10_dasm_all.txt

11357

SP3 actually decodes these to the form with null.

[foad]

I thought this was a GFX9 feature?

[rampitec]

In D125117#3497537, @foad wrote:

I thought this was a GFX9 feature?

Yes, sp3 allows it on gfx9 (except null of course).

[foad]

Please include a link to https://github.com/llvm/llvm-project/issues/38652 in the commit message, since it seems you are addressing at least part of it.

[kosarev]

Updated commit message as suggested.

[kosarev]

In D125117#3497537, @foad wrote:

I thought this was a GFX9 feature?

GFX9 does support soffset+offset, yes, but the encoding is different and so it probably deserves a separate patch.

In D125117#3498619, @foad wrote:

Please include a link to https://github.com/llvm/llvm-project/issues/38652 in the commit message, since it seems you are addressing at least part of it.

Done.

[foad]

In D125117#3500268, @kosarev wrote:

Updated commit message as suggested.

Unfortunately if you change the commit message, arc diff does not automatically update the summary. You have to do it manually by clicking on Edit Revision.

[foad]

llvm/lib/Target/AMDGPU/SMInstructions.td

751–752

Can you just soffset instead of soffset{7-0}, here and elsewhere?

911–917

These expressions seem over-complicated. Is it really important to set these fields to ? in the "!has_offset && !has_soffset" case, which presumably will never happen? Can you simplify to:

let Inst{52-32} = !if(ps.has_offset, offset{20-0}, 0);
let Inst{63-57} = !if(ps.has_soffset, soffset{6-0}, !cast<int>(SGPR_NULL.HWEncoding));

[foad]

To clarify, you are deliberately only doing this for SMEM loads, not for stores or probes or any other SMEM instruction types? Given that, the patch looks OK to me, but I would appreciate a second opinion maybe from @dp.

[kosarev]

Updated.

[kosarev]

In D125117#3500499, @foad wrote:

To clarify, you are deliberately only doing this for SMEM loads, not for stores or probes or any other SMEM instruction types? Given that, the patch looks OK to me, but I would appreciate a second opinion maybe from @dp.

Yes, that's just for soffset+offset loads. Feels like that's enough for a single patch.

llvm/lib/Target/AMDGPU/SMInstructions.td

751–752

Sure, done.

911–917

There are actually SMEMs that do not employ the fields, e.g., s_dcache_inv and s_memrealtime. So yes, I think we need the ?s. Added a comment explaining that.

[dp]

The patch looks fine to me.

I'd have added a couple of tests for new addressing mode to validate offset limitations, e.g.

s_load_dwordx16 s[20:35], s[4:5], s0 offset:0x1FFFFF
s_buffer_load_dwordx16 s[20:35], s[4:7], s0 offset:-1

should trigger an error.

[kosarev]

Added validation tests.

[dp]

LGTM

llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h

private:
   void printOffset0(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
                     raw_ostream &O);
   void printOffset1(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
                     raw_ostream &O);
   void printSMRDOffset8(const MCInst *MI, unsigned OpNo,
                        const MCSubtargetInfo &STI, raw_ostream &O);
   void printSMEMOffset(const MCInst *MI, unsigned OpNo,
                        const MCSubtargetInfo &STI, raw_ostream &O);
+  void printSMEMOffsetMod(const MCInst *MI, unsigned OpNo,
+                          const MCSubtargetInfo &STI, raw_ostream &O);
   void printSMRDLiteralOffset(const MCInst *MI, unsigned OpNo,
                               const MCSubtargetInfo &STI, raw_ostream &O);
   void printGDS(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
                 raw_ostream &O);
   void printCPol(const MCInst *MI, unsigned OpNo,
                  const MCSubtargetInfo &STI, raw_ostream &O);
   void printSWZ(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
                 raw_ostream &O);

llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp

 }
 
 void AMDGPUInstPrinter::printSMEMOffset(const MCInst *MI, unsigned OpNo,
                                         const MCSubtargetInfo &STI,
                                         raw_ostream &O) {
   O << formatHex(MI->getOperand(OpNo).getImm());
 }
 
+void AMDGPUInstPrinter::printSMEMOffsetMod(const MCInst *MI, unsigned OpNo,
+                                           const MCSubtargetInfo &STI,
+                                           raw_ostream &O) {
+  O << " offset:";
+  printSMEMOffset(MI, OpNo, STI, O);
+}
+
 void AMDGPUInstPrinter::printSMRDLiteralOffset(const MCInst *MI, unsigned OpNo,
                                                const MCSubtargetInfo &STI,
                                                raw_ostream &O) {
   printU32ImmOperand(MI, OpNo, STI, O);
 }
 
 void AMDGPUInstPrinter::printGDS(const MCInst *MI, unsigned OpNo,
                                  const MCSubtargetInfo &STI, raw_ostream &O) {

llvm/lib/Target/AMDGPU/SIInstrInfo.cpp

if (!MI.hasRegisterImplicitUseOperand(AMDGPU::EXEC)) {
       return false;
     }
   }
 
   if (isSMRD(MI)) {
     if (MI.mayStore()) {
       // The register offset form of scalar stores may only use m0 as the
       // soffset register.
-      const MachineOperand *Soff = getNamedOperand(MI, AMDGPU::OpName::soff);
+      const MachineOperand *Soff = getNamedOperand(MI, AMDGPU::OpName::soffset);
       if (Soff && Soff->getReg() != AMDGPU::M0) {
         ErrInfo = "scalar stores must use m0 as offset register";
         return false;
       }
     }
   }
 
   if (isFLAT(MI) && !ST.hasFlatInstOffsets()) {
void SIInstrInfo::legalizeOperandsSMRD(MachineRegisterInfo &MRI,
   // SGPRs using v_readfirstlane.  This is safe because we only select
   // loads with uniform pointers to SMRD instruction so we know the
   // pointer value is uniform.
   MachineOperand *SBase = getNamedOperand(MI, AMDGPU::OpName::sbase);
   if (SBase && !RI.isSGPRClass(MRI.getRegClass(SBase->getReg()))) {
     Register SGPR = readlaneVGPRToSGPR(SBase->getReg(), MI, MRI);
     SBase->setReg(SGPR);
   }
-  MachineOperand *SOff = getNamedOperand(MI, AMDGPU::OpName::soff);
+  MachineOperand *SOff = getNamedOperand(MI, AMDGPU::OpName::soffset);
   if (SOff && !RI.isSGPRClass(MRI.getRegClass(SOff->getReg()))) {
     Register SGPR = readlaneVGPRToSGPR(SOff->getReg(), MI, MRI);
     SOff->setReg(SGPR);
   }
 }
 
 bool SIInstrInfo::moveFlatAddrToVGPR(MachineInstr &Inst) const {
   unsigned Opc = Inst.getOpcode();

llvm/lib/Target/AMDGPU/SMInstructions.td

 //===---- SMInstructions.td - Scalar Memory Instruction Definitions -------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
 def smrd_offset_8 : NamedOperandU32<"SMRDOffset8",
                                   NamedMatchClass<"SMRDOffset8">> {
   let OperandType = "OPERAND_IMMEDIATE";
 }
 
-def smem_offset : NamedOperandU32<"SMEMOffset",
+class SMEMOffset : NamedOperandU32<"SMEMOffset",
                                    NamedMatchClass<"SMEMOffset">> {
   let OperandType = "OPERAND_IMMEDIATE";
   let EncoderMethod = "getSMEMOffsetEncoding";
   let DecoderMethod = "decodeSMEMOffset";
 }
 
+def smem_offset : SMEMOffset;
+
+def smem_offset_mod : SMEMOffset {
+  let PrintMethod = "printSMEMOffsetMod";
+}
+
 //===----------------------------------------------------------------------===//
 // Scalar Memory classes
 //===----------------------------------------------------------------------===//
 
 class SM_Pseudo <string opName, dag outs, dag ins, string asmOps, list<dag> pattern=[]> :
   InstSI <outs, ins, "", pattern>,
   SIMCInstr<opName, SIEncodingFamily.NONE> {
   let isPseudo = 1;
class SM_Pseudo <string opName, dag outs, dag ins, string asmOps, list<dag> pattern=[]> :
 
   string Mnemonic = opName;
   string AsmOperands = asmOps;
 
   bits<1> has_sbase = 1;
   bits<1> has_sdst = 1;
   bit has_glc = 0;
   bit has_dlc = 0;
-  bits<1> has_offset = 1;
-  bits<1> offset_is_imm = 0;
+  bit has_offset = 0;
+  bit has_soffset = 0;
   bit is_buffer = 0;
 }
 
 class SM_Real <SM_Pseudo ps>
   : InstSI<ps.OutOperandList, ps.InOperandList, ps.Mnemonic # ps.AsmOperands, []> {
 
   let isPseudo = 0;
   let isCodeGenOnly = 0;
class SM_Real <SM_Pseudo ps>
   let TSFlags = ps.TSFlags;
 
   bit is_buffer = ps.is_buffer;
 
   // encoding
   bits<7>  sbase;
   bits<7>  sdst;
   bits<32> offset;
-  bits<1> imm = !if(ps.has_offset, ps.offset_is_imm, 0);
+  bits<8>  soffset;
   bits<5> cpol;
 }
 
 class SM_Probe_Pseudo <string opName, dag ins, bit isImm>
-  : SM_Pseudo<opName, (outs), ins, " $sdata, $sbase, $offset"> {
+  : SM_Pseudo<opName, (outs), ins,
+              " $sdata, $sbase, " # !if(isImm, "$offset", "$soffset")> {
   let mayLoad = 0;
   let mayStore = 0;
   let has_glc = 0;
   let LGKM_CNT = 0;
   let ScalarStore = 0;
   let hasSideEffects = 1;
-  let offset_is_imm = isImm;
+  let has_offset = isImm;
+  let has_soffset = !not(isImm);
   let PseudoInstr = opName # !if(isImm, "_IMM", "_SGPR");
 }
 
 class SM_Load_Pseudo <string opName, dag outs, dag ins, string asmOps, list<dag> pattern=[]>
   : SM_Pseudo<opName, outs, ins, asmOps, pattern> {
   RegisterClass BaseClass;
   let mayLoad = 1;
   let mayStore = 0;
   let has_glc = 1;
   let has_dlc = 1;
 }
 
 class SM_Store_Pseudo <string opName, dag ins, string asmOps, list<dag> pattern = []>
   : SM_Pseudo<opName, (outs), ins, asmOps, pattern> {
   RegisterClass BaseClass;
   RegisterClass SrcClass;
   let mayLoad = 0;
   let mayStore = 1;
   let has_glc = 1;
   let has_dlc = 1;
   let ScalarStore = 1;
 }
 
 class SM_Discard_Pseudo <string opName, dag ins, bit isImm>
-  : SM_Pseudo<opName, (outs), ins, " $sbase, $offset"> {
+  : SM_Pseudo<opName, (outs), ins,
+              " $sbase, " # !if(isImm, "$offset", "$soffset")> {
   let mayLoad = 0;
   let mayStore = 0;
   let has_glc = 0;
   let has_sdst = 0;
   let ScalarStore = 0;
   let hasSideEffects = 1;
-  let offset_is_imm = isImm;
+  let has_offset = isImm;
+  let has_soffset = !not(isImm);
   let PseudoInstr = opName # !if(isImm, "_IMM", "_SGPR");
 }
 
 multiclass SM_Pseudo_Loads<string opName,
                            RegisterClass baseClass,
                            RegisterClass dstClass> {
   def _IMM  : SM_Load_Pseudo <opName,
                               (outs dstClass:$sdst),
                               (ins baseClass:$sbase, i32imm:$offset, CPol:$cpol),
                               " $sdst, $sbase, $offset$cpol", []> {
-    let offset_is_imm = 1;
+    let has_offset = 1;
     let BaseClass = baseClass;
     let PseudoInstr = opName # "_IMM";
     let has_glc = 1;
     let has_dlc = 1;
   }
 
   def _SGPR  : SM_Load_Pseudo <opName,
                               (outs dstClass:$sdst),
-                              (ins baseClass:$sbase, SReg_32:$soff, CPol:$cpol),
-                              " $sdst, $sbase, $offset$cpol", []> {
+                              (ins baseClass:$sbase, SReg_32:$soffset, CPol:$cpol),
+                              " $sdst, $sbase, $soffset$cpol", []> {
+    let has_soffset = 1;
     let BaseClass = baseClass;
     let PseudoInstr = opName # "_SGPR";
     let has_glc = 1;
     let has_dlc = 1;
   }
+
+  def _SGPR_IMM  : SM_Load_Pseudo <opName,
+                                   (outs dstClass:$sdst),
+                                   (ins baseClass:$sbase, SReg_32:$soffset,
+                                        i32imm:$offset, CPol:$cpol),
+                                   " $sdst, $sbase, $soffset$offset$cpol", []> {
+    let has_offset = 1;
+    let has_soffset = 1;
+    let BaseClass = baseClass;
+    let PseudoInstr = opName # "_SGPR_IMM";
+    let has_glc = 1;
+    let has_dlc = 1;
+  }
 }
 
 multiclass SM_Pseudo_Stores<string opName,
                            RegisterClass baseClass,
                            RegisterClass srcClass> {
   def _IMM  : SM_Store_Pseudo <opName,
     (ins srcClass:$sdata, baseClass:$sbase, i32imm:$offset, CPol:$cpol),
     " $sdata, $sbase, $offset$cpol", []> {
-    let offset_is_imm = 1;
+    let has_offset = 1;
     let BaseClass = baseClass;
     let SrcClass = srcClass;
     let PseudoInstr = opName # "_IMM";
   }
 
   def _SGPR  : SM_Store_Pseudo <opName,
-    (ins srcClass:$sdata, baseClass:$sbase, SReg_32:$soff, CPol:$cpol),
-    " $sdata, $sbase, $offset$cpol", []> {
+    (ins srcClass:$sdata, baseClass:$sbase, SReg_32:$soffset, CPol:$cpol),
+    " $sdata, $sbase, $soffset$cpol", []> {
+    let has_soffset = 1;
     let BaseClass = baseClass;
     let SrcClass = srcClass;
     let PseudoInstr = opName # "_SGPR";
   }
 }
 
 multiclass SM_Pseudo_Discards<string opName> {
   def _IMM  : SM_Discard_Pseudo <opName, (ins SReg_64:$sbase, smem_offset:$offset), 1>;
-  def _SGPR : SM_Discard_Pseudo <opName, (ins SReg_64:$sbase, SReg_32:$offset), 0>;
+  def _SGPR : SM_Discard_Pseudo <opName, (ins SReg_64:$sbase, SReg_32:$soffset), 0>;
 }
 
 class SM_Time_Pseudo<string opName, SDPatternOperator node = null_frag> : SM_Pseudo<
   opName, (outs SReg_64_XEXEC:$sdst), (ins),
   " $sdst", [(set i64:$sdst, (node))]> {
   let hasSideEffects = 1;
 
   let mayStore = 0;
   let mayLoad = 0;
   let has_sbase = 0;
-  let has_offset = 0;
 }
 
 class SM_Inval_Pseudo <string opName, SDPatternOperator node = null_frag> : SM_Pseudo<
   opName, (outs), (ins), "", [(node)]> {
   let hasSideEffects = 1;
   let mayStore = 0;
   let has_sdst = 0;
   let has_sbase = 0;
-  let has_offset = 0;
 }
 
 multiclass SM_Pseudo_Probe<string opName, RegisterClass baseClass> {
   def _IMM  : SM_Probe_Pseudo <opName, (ins i8imm:$sdata, baseClass:$sbase, smem_offset:$offset), 1>;
-  def _SGPR : SM_Probe_Pseudo <opName, (ins i8imm:$sdata, baseClass:$sbase, SReg_32:$offset), 0>;
+  def _SGPR : SM_Probe_Pseudo <opName, (ins i8imm:$sdata, baseClass:$sbase, SReg_32:$soffset), 0>;
 }
 
 class SM_WaveId_Pseudo<string opName, SDPatternOperator node> : SM_Pseudo<
   opName, (outs SReg_32_XM0_XEXEC:$sdst), (ins),
   " $sdst", [(set i32:$sdst, (node))]> {
   let hasSideEffects = 1;
   let mayStore = 0;
   let mayLoad = 1;
   let has_sbase = 0;
-  let has_offset = 0;
 }
 
 //===----------------------------------------------------------------------===//
 // Scalar Atomic Memory Classes
 //===----------------------------------------------------------------------===//
 
 class SM_Atomic_Pseudo <string opName,
                         dag outs, dag ins, string asmOps, bit isRet>
   : SM_Pseudo<opName, outs, ins, asmOps, []> {
 
   bit glc = isRet;
 
   let mayLoad = 1;
   let mayStore = 1;
   let has_glc = 1;
   let has_dlc = 1;
+  let has_soffset = 1;
 
   // Should these be set?
   let ScalarStore = 1;
   let hasSideEffects = 1;
   let maybeAtomic = 1;
 
   let IsAtomicNoRet = !not(isRet);
   let IsAtomicRet = isRet;
class SM_Pseudo_Atomic<string opName,
                        string opNameWithSuffix = opName # !if(isImm,
                                  !if(isRet, "_IMM_RTN", "_IMM"),
                                  !if(isRet, "_SGPR_RTN", "_SGPR")),
                        Operand CPolTy = !if(isRet, CPol_GLC1, CPol)> :
   SM_Atomic_Pseudo<opName,
                    !if(isRet, (outs dataClass:$sdst), (outs)),
                    !if(isImm,
                        (ins dataClass:$sdata, baseClass:$sbase, smem_offset:$offset, CPolTy:$cpol),
-                       (ins dataClass:$sdata, baseClass:$sbase, SReg_32:$offset, CPolTy:$cpol)),
-                   !if(isRet, " $sdst", " $sdata") # ", $sbase, $offset$cpol",
+                       (ins dataClass:$sdata, baseClass:$sbase, SReg_32:$soffset, CPolTy:$cpol)),
+                   !if(isRet, " $sdst", " $sdata") # ", $sbase, " #
+                     !if(isImm, "$offset", "$soffset") # "$cpol",
                    isRet>,
   AtomicNoRet <opNameWithSuffix, isRet> {
-  let offset_is_imm = isImm;
+  let has_offset = isImm;
+  let has_soffset = !not(isImm);
   let PseudoInstr = opNameWithSuffix;
 
   let Constraints = !if(isRet, "$sdst = $sdata", "");
   let DisableEncoding = !if(isRet, "$sdata", "");
 }
 
 multiclass SM_Pseudo_Atomics<string opName,
                              RegisterClass baseClass,

 class SMRD_Real_si <bits<5> op, SM_Pseudo ps>
   : SM_Real<ps>
   , SIMCInstr<ps.PseudoInstr, SIEncodingFamily.SI>
   , Enc32 {
 
   let AssemblerPredicate = isGFX6GFX7;
   let DecoderNamespace = "GFX6GFX7";
 
-  let Inst{7-0}   = !if(ps.has_offset, offset{7-0}, ?);
-  let Inst{8}     = imm;
+  let Inst{7-0}   = !if(ps.has_offset, offset{7-0}, !if(ps.has_soffset, soffset, ?));
+  let Inst{8}     = ps.has_offset;
   let Inst{14-9}  = !if(ps.has_sbase, sbase{6-1}, ?);
   let Inst{21-15} = !if(ps.has_sdst, sdst{6-0}, ?);
   let Inst{26-22} = op;
   let Inst{31-27} = 0x18; //encoding
 }
 
 // FIXME: Assembler should reject trying to use glc on SMRD
 // instructions on SI.
 multiclass SM_Real_Loads_si<bits<5> op, string ps,
                             SM_Load_Pseudo immPs = !cast<SM_Load_Pseudo>(ps#_IMM),
                             SM_Load_Pseudo sgprPs = !cast<SM_Load_Pseudo>(ps#_SGPR)> {
 
   def _IMM_si : SMRD_Real_si <op, immPs> {
     let InOperandList = (ins immPs.BaseClass:$sbase, smrd_offset_8:$offset, CPol:$cpol);
   }
 
-  // FIXME: The operand name $offset is inconsistent with $soff used
-  // in the pseudo
   def _SGPR_si : SMRD_Real_si <op, sgprPs> {
-    let InOperandList = (ins sgprPs.BaseClass:$sbase, SReg_32:$offset, CPol:$cpol);
+    let InOperandList = (ins sgprPs.BaseClass:$sbase, SReg_32:$soffset, CPol:$cpol);
   }
 
 }
 
 defm S_LOAD_DWORD           : SM_Real_Loads_si <0x00, "S_LOAD_DWORD">;
 defm S_LOAD_DWORDX2         : SM_Real_Loads_si <0x01, "S_LOAD_DWORDX2">;
 defm S_LOAD_DWORDX4         : SM_Real_Loads_si <0x02, "S_LOAD_DWORDX4">;
 defm S_LOAD_DWORDX8         : SM_Real_Loads_si <0x03, "S_LOAD_DWORDX8">;
class SMEM_Real_vi <bits<8> op, SM_Pseudo ps>
   , Enc64 {
   let AssemblerPredicate = isGFX8GFX9;
   let DecoderNamespace = "GFX8";
 
   let Inst{5-0}   = !if(ps.has_sbase, sbase{6-1}, ?);
   let Inst{12-6}  = !if(ps.has_sdst, sdst{6-0}, ?);
 
   let Inst{16} = !if(ps.has_glc, cpol{CPolBit.GLC}, ?);
-  let Inst{17} = imm;
+  let Inst{17} = ps.has_offset;
   let Inst{25-18} = op;
   let Inst{31-26} = 0x30; //encoding
 
   // VI supports 20-bit unsigned offsets while GFX9+ supports 21-bit signed.
   // Offset value is corrected accordingly when offset is encoded/decoded.
-  let Inst{38-32} = !if(ps.has_offset, offset{6-0}, ?);
-  let Inst{52-39} = !if(ps.has_offset, !if(imm, offset{20-7}, ?), ?);
+  let Inst{38-32} = !if(ps.has_offset, offset{6-0}, !if(ps.has_soffset, soffset{6-0}, ?));
+  let Inst{52-39} = !if(ps.has_offset, offset{20-7}, ?);
 }
 
 multiclass SM_Real_Loads_vi<bits<8> op, string ps,
                             SM_Load_Pseudo immPs = !cast<SM_Load_Pseudo>(ps#_IMM),
                             SM_Load_Pseudo sgprPs = !cast<SM_Load_Pseudo>(ps#_SGPR)> {
   def _IMM_vi : SMEM_Real_vi <op, immPs> {
     let InOperandList = (ins immPs.BaseClass:$sbase, smem_offset:$offset, CPol:$cpol);
   }
   def _SGPR_vi : SMEM_Real_vi <op, sgprPs> {
-    let InOperandList = (ins sgprPs.BaseClass:$sbase, SReg_32:$offset, CPol:$cpol);
+    let InOperandList = (ins sgprPs.BaseClass:$sbase, SReg_32:$soffset, CPol:$cpol);
   }
 }
 
 class SMEM_Real_Store_vi <bits<8> op, SM_Pseudo ps> : SMEM_Real_vi <op, ps> {
   // encoding
   bits<7> sdata;
 
   let sdst = ?;
   let Inst{12-6}  = !if(ps.has_sdst, sdata{6-0}, ?);
 }
 
 multiclass SM_Real_Stores_vi<bits<8> op, string ps,
                             SM_Store_Pseudo immPs = !cast<SM_Store_Pseudo>(ps#_IMM),
                             SM_Store_Pseudo sgprPs = !cast<SM_Store_Pseudo>(ps#_SGPR)> {
-  // FIXME: The operand name $offset is inconsistent with $soff used
-  // in the pseudo
   def _IMM_vi : SMEM_Real_Store_vi <op, immPs> {
     let InOperandList = (ins immPs.SrcClass:$sdata, immPs.BaseClass:$sbase, smem_offset:$offset, CPol:$cpol);
   }
 
   def _SGPR_vi : SMEM_Real_Store_vi <op, sgprPs> {
-    let InOperandList = (ins sgprPs.SrcClass:$sdata, sgprPs.BaseClass:$sbase, SReg_32:$offset, CPol:$cpol);
+    let InOperandList = (ins sgprPs.SrcClass:$sdata, sgprPs.BaseClass:$sbase, SReg_32:$soffset, CPol:$cpol);
   }
 }
 
 multiclass SM_Real_Probe_vi<bits<8> op, string ps> {
   def _IMM_vi  : SMEM_Real_Store_vi <op, !cast<SM_Probe_Pseudo>(ps#_IMM)>;
   def _SGPR_vi : SMEM_Real_Store_vi <op, !cast<SM_Probe_Pseudo>(ps#_SGPR)>;
 }
 

 class SMRD_Real_ci <bits<5> op, SM_Pseudo ps>
   : SM_Real<ps>
   , SIMCInstr<ps.PseudoInstr, SIEncodingFamily.SI>
   , Enc32 {
 
   let AssemblerPredicate = isGFX7Only;
   let DecoderNamespace = "GFX7";
 
-  let Inst{7-0}   = !if(ps.has_offset, offset{7-0}, ?);
-  let Inst{8}     = imm;
+  let Inst{7-0}   = !if(ps.has_offset, offset{7-0}, !if(ps.has_soffset, soffset, ?));
+  let Inst{8}     = ps.has_offset;
   let Inst{14-9}  = !if(ps.has_sbase, sbase{6-1}, ?);
   let Inst{21-15} = !if(ps.has_sdst, sdst{6-0}, ?);
   let Inst{26-22} = op;
   let Inst{31-27} = 0x18; //encoding
 }
 
 def S_DCACHE_INV_VOL_ci : SMRD_Real_ci <0x1d, S_DCACHE_INV_VOL>;
 
class SMEM_Real_gfx10<bits<8> op, SM_Pseudo ps> :
   let DecoderNamespace = "GFX10";
 
   let Inst{5-0}   = !if(ps.has_sbase, sbase{6-1}, ?);
   let Inst{12-6}  = !if(ps.has_sdst, sdst{6-0}, ?);
   let Inst{14}    = !if(ps.has_dlc, cpol{CPolBit.DLC}, ?);
   let Inst{16}    = !if(ps.has_glc, cpol{CPolBit.GLC}, ?);
   let Inst{25-18} = op;
   let Inst{31-26} = 0x3d;
-  let Inst{52-32} = !if(ps.offset_is_imm, !if(ps.has_offset, offset{20-0}, ?), ?);
-  let Inst{63-57} = !if(ps.offset_is_imm, !cast<int>(SGPR_NULL.HWEncoding),
-                                          !if(ps.has_offset, offset{6-0}, ?));
+
+  // There are SMEM instructions that do not employ any of the offset
+  // fields, in which case we need them to remain undefined.
+  let Inst{52-32} = !if(ps.has_offset, offset{20-0}, !if(ps.has_soffset, 0, ?));
+  let Inst{63-57} = !if(ps.has_soffset, soffset{6-0},
+                        !if(ps.has_offset, !cast<int>(SGPR_NULL.HWEncoding), ?));
 }
 
 multiclass SM_Real_Loads_gfx10<bits<8> op, string ps,
                                SM_Load_Pseudo immPs = !cast<SM_Load_Pseudo>(ps#_IMM),
                                SM_Load_Pseudo sgprPs = !cast<SM_Load_Pseudo>(ps#_SGPR)> {
   def _IMM_gfx10 : SMEM_Real_gfx10<op, immPs> {
     let InOperandList = (ins immPs.BaseClass:$sbase, smem_offset:$offset, CPol:$cpol);
   }
   def _SGPR_gfx10 : SMEM_Real_gfx10<op, sgprPs> {
-    let InOperandList = (ins sgprPs.BaseClass:$sbase, SReg_32:$offset, CPol:$cpol);
+    let InOperandList = (ins sgprPs.BaseClass:$sbase, SReg_32:$soffset, CPol:$cpol);
+  }
+  def _SGPR_IMM_gfx10 : SMEM_Real_gfx10<op, !cast<SM_Load_Pseudo>(ps#_SGPR_IMM)> {
+    let InOperandList = (ins sgprPs.BaseClass:$sbase, SReg_32:$soffset,
+                             smem_offset_mod:$offset, CPol:$cpol);
   }
 }
 
 class SMEM_Real_Store_gfx10<bits<8> op, SM_Pseudo ps> : SMEM_Real_gfx10<op, ps> {
   bits<7> sdata;
 
   let sdst = ?;
   let Inst{12-6} = !if(ps.has_sdst, sdata{6-0}, ?);
 }
 
 multiclass SM_Real_Stores_gfx10<bits<8> op, string ps,
                                 SM_Store_Pseudo immPs = !cast<SM_Store_Pseudo>(ps#_IMM),
                                 SM_Store_Pseudo sgprPs = !cast<SM_Store_Pseudo>(ps#_SGPR)> {
-  // FIXME: The operand name $offset is inconsistent with $soff used
-  // in the pseudo
   def _IMM_gfx10 : SMEM_Real_Store_gfx10 <op, immPs> {
     let InOperandList = (ins immPs.SrcClass:$sdata, immPs.BaseClass:$sbase, smem_offset:$offset, CPol:$cpol);
   }
 
   def _SGPR_gfx10 : SMEM_Real_Store_gfx10 <op, sgprPs> {
-    let InOperandList = (ins sgprPs.SrcClass:$sdata, sgprPs.BaseClass:$sbase, SReg_32:$offset, CPol:$cpol);
+    let InOperandList = (ins sgprPs.SrcClass:$sdata, sgprPs.BaseClass:$sbase, SReg_32:$soffset, CPol:$cpol);
   }
 }
 
 defm S_LOAD_DWORD            : SM_Real_Loads_gfx10<0x000, "S_LOAD_DWORD">;
 defm S_LOAD_DWORDX2          : SM_Real_Loads_gfx10<0x001, "S_LOAD_DWORDX2">;
 defm S_LOAD_DWORDX4          : SM_Real_Loads_gfx10<0x002, "S_LOAD_DWORDX4">;
 defm S_LOAD_DWORDX8          : SM_Real_Loads_gfx10<0x003, "S_LOAD_DWORDX8">;
 defm S_LOAD_DWORDX16         : SM_Real_Loads_gfx10<0x004, "S_LOAD_DWORDX16">;

llvm/test/MC/AMDGPU/gfx10_asm_smem.s

 // GFX10: encoding: [0x41,0x01,0x00,0xf4,0x00,0x00,0x00,0xd4]
 
 s_load_dword s5, s[2:3], vcc_hi
 // GFX10: encoding: [0x41,0x01,0x00,0xf4,0x00,0x00,0x00,0xd6]
 
 s_load_dword s5, s[2:3], m0
 // GFX10: encoding: [0x41,0x01,0x00,0xf4,0x00,0x00,0x00,0xf8]
 
+s_load_dword s5, s[2:3], null
+// GFX10: encoding: [0x41,0x01,0x00,0xf4,0x00,0x00,0x00,0xfa]
+
 s_load_dword s5, s[2:3], 0x0
 // GFX10: encoding: [0x41,0x01,0x00,0xf4,0x00,0x00,0x00,0xfa]
 
+s_load_dword s5, s[2:3], s0 offset:0x12345
+// GFX10: encoding: [0x41,0x01,0x00,0xf4,0x45,0x23,0x01,0x00]
+
 s_load_dword s5, s[2:3], s0 glc
 // GFX10: encoding: [0x41,0x01,0x01,0xf4,0x00,0x00,0x00,0x00]
 
 s_load_dword s5, s[2:3], s0 dlc
 // GFX10: encoding: [0x41,0x41,0x00,0xf4,0x00,0x00,0x00,0x00]
 
 s_load_dword s5, s[2:3], s0 glc dlc
 // GFX10: encoding: [0x41,0x41,0x01,0xf4,0x00,0x00,0x00,0x00]
 
 s_load_dword s5, s[2:3], 0x1234 glc dlc
 // GFX10: encoding: [0x41,0x41,0x01,0xf4,0x34,0x12,0x00,0xfa]
 
+s_load_dword s5, s[2:3], s0 offset:0x12345 glc dlc
+// GFX10: encoding: [0x41,0x41,0x01,0xf4,0x45,0x23,0x01,0x00]
+
 s_load_dwordx2 s[10:11], s[2:3], s0
 // GFX10: encoding: [0x81,0x02,0x04,0xf4,0x00,0x00,0x00,0x00]
 
 s_load_dwordx2 s[12:13], s[2:3], s0
 // GFX10: encoding: [0x01,0x03,0x04,0xf4,0x00,0x00,0x00,0x00]
 
 s_load_dwordx2 s[100:101], s[2:3], s0
 // GFX10: encoding: [0x01,0x19,0x04,0xf4,0x00,0x00,0x00,0x00]

 // GFX10: encoding: [0x81,0x02,0x04,0xf4,0x00,0x00,0x00,0xd4]
 
 s_load_dwordx2 s[10:11], s[2:3], vcc_hi
 // GFX10: encoding: [0x81,0x02,0x04,0xf4,0x00,0x00,0x00,0xd6]
 
 s_load_dwordx2 s[10:11], s[2:3], m0
 // GFX10: encoding: [0x81,0x02,0x04,0xf4,0x00,0x00,0x00,0xf8]
 
+s_load_dwordx2 s[10:11], s[2:3], null
+// GFX10: encoding: [0x81,0x02,0x04,0xf4,0x00,0x00,0x00,0xfa]
+
 s_load_dwordx2 s[10:11], s[2:3], 0x0
 // GFX10: encoding: [0x81,0x02,0x04,0xf4,0x00,0x00,0x00,0xfa]
 
+s_load_dwordx2 s[10:11], s[2:3], s0 offset:0x12345
+// GFX10: encoding: [0x81,0x02,0x04,0xf4,0x45,0x23,0x01,0x00]
+
 s_load_dwordx2 s[10:11], s[2:3], s0 glc
 // GFX10: encoding: [0x81,0x02,0x05,0xf4,0x00,0x00,0x00,0x00]
 
 s_load_dwordx2 s[10:11], s[2:3], s0 dlc
 // GFX10: encoding: [0x81,0x42,0x04,0xf4,0x00,0x00,0x00,0x00]
 
 s_load_dwordx2 s[10:11], s[2:3], s0 glc dlc
 // GFX10: encoding: [0x81,0x42,0x05,0xf4,0x00,0x00,0x00,0x00]
 
 s_load_dwordx2 s[10:11], s[2:3], 0x1234 glc dlc
 // GFX10: encoding: [0x81,0x42,0x05,0xf4,0x34,0x12,0x00,0xfa]
 
+s_load_dwordx2 s[10:11], s[2:3], s0 offset:0x12345 glc dlc
+// GFX10: encoding: [0x81,0x42,0x05,0xf4,0x45,0x23,0x01,0x00]
+
 s_load_dwordx4 s[20:23], s[2:3], s0
 // GFX10: encoding: [0x01,0x05,0x08,0xf4,0x00,0x00,0x00,0x00]
 
 s_load_dwordx4 s[24:27], s[2:3], s0
 // GFX10: encoding: [0x01,0x06,0x08,0xf4,0x00,0x00,0x00,0x00]
 
 s_load_dwordx4 s[96:99], s[2:3], s0
 // GFX10: encoding: [0x01,0x18,0x08,0xf4,0x00,0x00,0x00,0x00]

 // GFX10: encoding: [0x01,0x05,0x08,0xf4,0x00,0x00,0x00,0xd4]
 
 s_load_dwordx4 s[20:23], s[2:3], vcc_hi
 // GFX10: encoding: [0x01,0x05,0x08,0xf4,0x00,0x00,0x00,0xd6]
 
 s_load_dwordx4 s[20:23], s[2:3], m0
 // GFX10: encoding: [0x01,0x05,0x08,0xf4,0x00,0x00,0x00,0xf8]
 
+s_load_dwordx4 s[20:23], s[2:3], null
+// GFX10: encoding: [0x01,0x05,0x08,0xf4,0x00,0x00,0x00,0xfa]
+
 s_load_dwordx4 s[20:23], s[2:3], 0x0
 // GFX10: encoding: [0x01,0x05,0x08,0xf4,0x00,0x00,0x00,0xfa]
 
+s_load_dwordx4 s[20:23], s[2:3], s0 offset:0x12345
+// GFX10: encoding: [0x01,0x05,0x08,0xf4,0x45,0x23,0x01,0x00]
+
 s_load_dwordx4 s[20:23], s[2:3], s0 glc
 // GFX10: encoding: [0x01,0x05,0x09,0xf4,0x00,0x00,0x00,0x00]
 
 s_load_dwordx4 s[20:23], s[2:3], s0 dlc
 // GFX10: encoding: [0x01,0x45,0x08,0xf4,0x00,0x00,0x00,0x00]
 
 s_load_dwordx4 s[20:23], s[2:3], s0 glc dlc
 // GFX10: encoding: [0x01,0x45,0x09,0xf4,0x00,0x00,0x00,0x00]
 
 s_load_dwordx4 s[20:23], s[2:3], 0x1234 glc dlc
 // GFX10: encoding: [0x01,0x45,0x09,0xf4,0x34,0x12,0x00,0xfa]
 
+s_load_dwordx4 s[20:23], s[2:3], s0 offset:0x12345 glc dlc
+// GFX10: encoding: [0x01,0x45,0x09,0xf4,0x45,0x23,0x01,0x00]
+
 s_load_dwordx8 s[20:27], s[2:3], s0
 // GFX10: encoding: [0x01,0x05,0x0c,0xf4,0x00,0x00,0x00,0x00]
 
 s_load_dwordx8 s[24:31], s[2:3], s0
 // GFX10: encoding: [0x01,0x06,0x0c,0xf4,0x00,0x00,0x00,0x00]
 
 s_load_dwordx8 s[92:99], s[2:3], s0
 // GFX10: encoding: [0x01,0x17,0x0c,0xf4,0x00,0x00,0x00,0x00]

 // GFX10: encoding: [0x01,0x05,0x0c,0xf4,0x00,0x00,0x00,0xd4]
 
 s_load_dwordx8 s[20:27], s[2:3], vcc_hi
 // GFX10: encoding: [0x01,0x05,0x0c,0xf4,0x00,0x00,0x00,0xd6]
 
 s_load_dwordx8 s[20:27], s[2:3], m0
 // GFX10: encoding: [0x01,0x05,0x0c,0xf4,0x00,0x00,0x00,0xf8]
 
+s_load_dwordx8 s[20:27], s[2:3], null
+// GFX10: encoding: [0x01,0x05,0x0c,0xf4,0x00,0x00,0x00,0xfa]
+
 s_load_dwordx8 s[20:27], s[2:3], 0x0
 // GFX10: encoding: [0x01,0x05,0x0c,0xf4,0x00,0x00,0x00,0xfa]
 
+s_load_dwordx8 s[20:27], s[2:3], s0 offset:0x12345
+// GFX10: encoding: [0x01,0x05,0x0c,0xf4,0x45,0x23,0x01,0x00]
+
 s_load_dwordx8 s[20:27], s[2:3], s0 glc
 // GFX10: encoding: [0x01,0x05,0x0d,0xf4,0x00,0x00,0x00,0x00]
 
 s_load_dwordx8 s[20:27], s[2:3], s0 dlc
 // GFX10: encoding: [0x01,0x45,0x0c,0xf4,0x00,0x00,0x00,0x00]
 
 s_load_dwordx8 s[20:27], s[2:3], s0 glc dlc
 // GFX10: encoding: [0x01,0x45,0x0d,0xf4,0x00,0x00,0x00,0x00]
 
 s_load_dwordx8 s[20:27], s[2:3], 0x1234 glc dlc
 // GFX10: encoding: [0x01,0x45,0x0d,0xf4,0x34,0x12,0x00,0xfa]
 
+s_load_dwordx8 s[20:27], s[2:3], s0 offset:0x12345 glc dlc
+// GFX10: encoding: [0x01,0x45,0x0d,0xf4,0x45,0x23,0x01,0x00]
+
 s_load_dwordx16 s[20:35], s[2:3], s0
 // GFX10: encoding: [0x01,0x05,0x10,0xf4,0x00,0x00,0x00,0x00]
 
 s_load_dwordx16 s[24:39], s[2:3], s0
 // GFX10: encoding: [0x01,0x06,0x10,0xf4,0x00,0x00,0x00,0x00]
 
 s_load_dwordx16 s[84:99], s[2:3], s0
 // GFX10: encoding: [0x01,0x15,0x10,0xf4,0x00,0x00,0x00,0x00]

 // GFX10: encoding: [0x01,0x05,0x10,0xf4,0x00,0x00,0x00,0xd4]
 
 s_load_dwordx16 s[20:35], s[2:3], vcc_hi
 // GFX10: encoding: [0x01,0x05,0x10,0xf4,0x00,0x00,0x00,0xd6]
 
 s_load_dwordx16 s[20:35], s[2:3], m0
 // GFX10: encoding: [0x01,0x05,0x10,0xf4,0x00,0x00,0x00,0xf8]
 
+s_load_dwordx16 s[20:35], s[2:3], null
+// GFX10: encoding: [0x01,0x05,0x10,0xf4,0x00,0x00,0x00,0xfa]
+
 s_load_dwordx16 s[20:35], s[2:3], 0x0
 // GFX10: encoding: [0x01,0x05,0x10,0xf4,0x00,0x00,0x00,0xfa]
 
+s_load_dwordx16 s[20:35], s[2:3], s0 offset:0x12345
+// GFX10: encoding: [0x01,0x05,0x10,0xf4,0x45,0x23,0x01,0x00]
+
 s_load_dwordx16 s[20:35], s[2:3], s0 glc
 // GFX10: encoding: [0x01,0x05,0x11,0xf4,0x00,0x00,0x00,0x00]
 
 s_load_dwordx16 s[20:35], s[2:3], s0 dlc
 // GFX10: encoding: [0x01,0x45,0x10,0xf4,0x00,0x00,0x00,0x00]
 
 s_load_dwordx16 s[20:35], s[2:3], s0 glc dlc
 // GFX10: encoding: [0x01,0x45,0x11,0xf4,0x00,0x00,0x00,0x00]
 
 s_load_dwordx16 s[20:35], s[2:3], 0x1234 glc dlc
 // GFX10: encoding: [0x01,0x45,0x11,0xf4,0x34,0x12,0x00,0xfa]
 
+s_load_dwordx16 s[20:35], s[2:3], s0 offset:0x12345 glc dlc
+// GFX10: encoding: [0x01,0x45,0x11,0xf4,0x45,0x23,0x01,0x00]
+
 s_buffer_load_dword s5, s[4:7], s0
 // GFX10: encoding: [0x42,0x01,0x20,0xf4,0x00,0x00,0x00,0x00]
 
 s_buffer_load_dword s101, s[4:7], s0
 // GFX10: encoding: [0x42,0x19,0x20,0xf4,0x00,0x00,0x00,0x00]
 
 s_buffer_load_dword vcc_lo, s[4:7], s0
 // GFX10: encoding: [0x82,0x1a,0x20,0xf4,0x00,0x00,0x00,0x00]

 // GFX10: encoding: [0x42,0x01,0x20,0xf4,0x00,0x00,0x00,0xd4]
 
 s_buffer_load_dword s5, s[4:7], vcc_hi
 // GFX10: encoding: [0x42,0x01,0x20,0xf4,0x00,0x00,0x00,0xd6]
 
 s_buffer_load_dword s5, s[4:7], m0
 // GFX10: encoding: [0x42,0x01,0x20,0xf4,0x00,0x00,0x00,0xf8]
 
+s_buffer_load_dword s5, s[4:7], null
+// GFX10: encoding: [0x42,0x01,0x20,0xf4,0x00,0x00,0x00,0xfa]
+
 s_buffer_load_dword s5, s[4:7], 0x0
 // GFX10: encoding: [0x42,0x01,0x20,0xf4,0x00,0x00,0x00,0xfa]
 
+s_buffer_load_dword s5, s[4:7], s0 offset:0x12345
+// GFX10: encoding: [0x42,0x01,0x20,0xf4,0x45,0x23,0x01,0x00]
+
 s_buffer_load_dword s5, s[4:7], s0 glc
 // GFX10: encoding: [0x42,0x01,0x21,0xf4,0x00,0x00,0x00,0x00]
 
 s_buffer_load_dword s5, s[4:7], s0 dlc
 // GFX10: encoding: [0x42,0x41,0x20,0xf4,0x00,0x00,0x00,0x00]
 
 s_buffer_load_dword s5, s[4:7], s0 glc dlc
 // GFX10: encoding: [0x42,0x41,0x21,0xf4,0x00,0x00,0x00,0x00]
 
 s_buffer_load_dword s5, s[4:7], 0x1234 glc dlc
 // GFX10: encoding: [0x42,0x41,0x21,0xf4,0x34,0x12,0x00,0xfa]
 
+s_buffer_load_dword s5, s[4:7], s0 offset:0x12345 glc dlc
+// GFX10: encoding: [0x42,0x41,0x21,0xf4,0x45,0x23,0x01,0x00]
+
 s_buffer_load_dwordx2 s[10:11], s[4:7], s0
 // GFX10: encoding: [0x82,0x02,0x24,0xf4,0x00,0x00,0x00,0x00]
 
 s_buffer_load_dwordx2 s[12:13], s[4:7], s0
 // GFX10: encoding: [0x02,0x03,0x24,0xf4,0x00,0x00,0x00,0x00]
 
 s_buffer_load_dwordx2 s[100:101], s[4:7], s0
 // GFX10: encoding: [0x02,0x19,0x24,0xf4,0x00,0x00,0x00,0x00]

 // GFX10: encoding: [0x82,0x02,0x24,0xf4,0x00,0x00,0x00,0xd4]
 
 s_buffer_load_dwordx2 s[10:11], s[4:7], vcc_hi
 // GFX10: encoding: [0x82,0x02,0x24,0xf4,0x00,0x00,0x00,0xd6]
 
 s_buffer_load_dwordx2 s[10:11], s[4:7], m0
 // GFX10: encoding: [0x82,0x02,0x24,0xf4,0x00,0x00,0x00,0xf8]
 
+s_buffer_load_dwordx2 s[10:11], s[4:7], null
+// GFX10: encoding: [0x82,0x02,0x24,0xf4,0x00,0x00,0x00,0xfa]
+
 s_buffer_load_dwordx2 s[10:11], s[4:7], 0x0
 // GFX10: encoding: [0x82,0x02,0x24,0xf4,0x00,0x00,0x00,0xfa]
 
+s_buffer_load_dwordx2 s[10:11], s[4:7], s0 offset:0x12345
+// GFX10: encoding: [0x82,0x02,0x24,0xf4,0x45,0x23,0x01,0x00]
+
 s_buffer_load_dwordx2 s[10:11], s[4:7], s0 glc
 // GFX10: encoding: [0x82,0x02,0x25,0xf4,0x00,0x00,0x00,0x00]
 
 s_buffer_load_dwordx2 s[10:11], s[4:7], s0 dlc
 // GFX10: encoding: [0x82,0x42,0x24,0xf4,0x00,0x00,0x00,0x00]
 
 s_buffer_load_dwordx2 s[10:11], s[4:7], s0 glc dlc
 // GFX10: encoding: [0x82,0x42,0x25,0xf4,0x00,0x00,0x00,0x00]
 
 s_buffer_load_dwordx2 s[10:11], s[4:7], 0x1234 glc dlc
 // GFX10: encoding: [0x82,0x42,0x25,0xf4,0x34,0x12,0x00,0xfa]
 
+s_buffer_load_dwordx2 s[10:11], s[4:7], s0 offset:0x12345 glc dlc
+// GFX10: encoding: [0x82,0x42,0x25,0xf4,0x45,0x23,0x01,0x00]
+
 s_buffer_load_dwordx4 s[20:23], s[4:7], s0
 // GFX10: encoding: [0x02,0x05,0x28,0xf4,0x00,0x00,0x00,0x00]
 
 s_buffer_load_dwordx4 s[24:27], s[4:7], s0
 // GFX10: encoding: [0x02,0x06,0x28,0xf4,0x00,0x00,0x00,0x00]
 
 s_buffer_load_dwordx4 s[96:99], s[4:7], s0
 // GFX10: encoding: [0x02,0x18,0x28,0xf4,0x00,0x00,0x00,0x00]

 // GFX10: encoding: [0x02,0x05,0x28,0xf4,0x00,0x00,0x00,0xd4]
 
 s_buffer_load_dwordx4 s[20:23], s[4:7], vcc_hi
 // GFX10: encoding: [0x02,0x05,0x28,0xf4,0x00,0x00,0x00,0xd6]
 
 s_buffer_load_dwordx4 s[20:23], s[4:7], m0
 // GFX10: encoding: [0x02,0x05,0x28,0xf4,0x00,0x00,0x00,0xf8]
 
+s_buffer_load_dwordx4 s[20:23], s[4:7], null
+// GFX10: encoding: [0x02,0x05,0x28,0xf4,0x00,0x00,0x00,0xfa]
+
 s_buffer_load_dwordx4 s[20:23], s[4:7], 0x0
 // GFX10: encoding: [0x02,0x05,0x28,0xf4,0x00,0x00,0x00,0xfa]
 
+s_buffer_load_dwordx4 s[20:23], s[4:7], s0 offset:0x12345
+// GFX10: encoding: [0x02,0x05,0x28,0xf4,0x45,0x23,0x01,0x00]
+
 s_buffer_load_dwordx4 s[20:23], s[4:7], s0 glc
 // GFX10: encoding: [0x02,0x05,0x29,0xf4,0x00,0x00,0x00,0x00]
 
 s_buffer_load_dwordx4 s[20:23], s[4:7], s0 dlc
 // GFX10: encoding: [0x02,0x45,0x28,0xf4,0x00,0x00,0x00,0x00]
 
 s_buffer_load_dwordx4 s[20:23], s[4:7], s0 glc dlc
 // GFX10: encoding: [0x02,0x45,0x29,0xf4,0x00,0x00,0x00,0x00]
 
 s_buffer_load_dwordx4 s[20:23], s[4:7], 0x1234 glc dlc
 // GFX10: encoding: [0x02,0x45,0x29,0xf4,0x34,0x12,0x00,0xfa]
 
+s_buffer_load_dwordx4 s[20:23], s[4:7], s0 offset:0x12345 glc dlc
+// GFX10: encoding: [0x02,0x45,0x29,0xf4,0x45,0x23,0x01,0x00]
+
 s_buffer_load_dwordx8 s[20:27], s[4:7], s0
 // GFX10: encoding: [0x02,0x05,0x2c,0xf4,0x00,0x00,0x00,0x00]
 
 s_buffer_load_dwordx8 s[24:31], s[4:7], s0
 // GFX10: encoding: [0x02,0x06,0x2c,0xf4,0x00,0x00,0x00,0x00]
 
 s_buffer_load_dwordx8 s[92:99], s[4:7], s0
 // GFX10: encoding: [0x02,0x17,0x2c,0xf4,0x00,0x00,0x00,0x00]

 // GFX10: encoding: [0x02,0x05,0x2c,0xf4,0x00,0x00,0x00,0xd4]
 
 s_buffer_load_dwordx8 s[20:27], s[4:7], vcc_hi
 // GFX10: encoding: [0x02,0x05,0x2c,0xf4,0x00,0x00,0x00,0xd6]
 
 s_buffer_load_dwordx8 s[20:27], s[4:7], m0
 // GFX10: encoding: [0x02,0x05,0x2c,0xf4,0x00,0x00,0x00,0xf8]
 
+s_buffer_load_dwordx8 s[20:27], s[4:7], null
+// GFX10: encoding: [0x02,0x05,0x2c,0xf4,0x00,0x00,0x00,0xfa]
+
 s_buffer_load_dwordx8 s[20:27], s[4:7], 0x0
 // GFX10: encoding: [0x02,0x05,0x2c,0xf4,0x00,0x00,0x00,0xfa]
 
+s_buffer_load_dwordx8 s[20:27], s[4:7], s0 offset:0x12345
+// GFX10: encoding: [0x02,0x05,0x2c,0xf4,0x45,0x23,0x01,0x00]
+
 s_buffer_load_dwordx8 s[20:27], s[4:7], s0 glc
 // GFX10: encoding: [0x02,0x05,0x2d,0xf4,0x00,0x00,0x00,0x00]
 
 s_buffer_load_dwordx8 s[20:27], s[4:7], s0 dlc
 // GFX10: encoding: [0x02,0x45,0x2c,0xf4,0x00,0x00,0x00,0x00]
 
 s_buffer_load_dwordx8 s[20:27], s[4:7], s0 glc dlc
 // GFX10: encoding: [0x02,0x45,0x2d,0xf4,0x00,0x00,0x00,0x00]
 
 s_buffer_load_dwordx8 s[20:27], s[4:7], 0x1234 glc dlc
 // GFX10: encoding: [0x02,0x45,0x2d,0xf4,0x34,0x12,0x00,0xfa]
 
+s_buffer_load_dwordx8 s[20:27], s[4:7], s0 offset:0x12345 glc dlc
+// GFX10: encoding: [0x02,0x45,0x2d,0xf4,0x45,0x23,0x01,0x00]
+
 s_buffer_load_dwordx16 s[20:35], s[4:7], s0
 // GFX10: encoding: [0x02,0x05,0x30,0xf4,0x00,0x00,0x00,0x00]
 
 s_buffer_load_dwordx16 s[24:39], s[4:7], s0
 // GFX10: encoding: [0x02,0x06,0x30,0xf4,0x00,0x00,0x00,0x00]
 
 s_buffer_load_dwordx16 s[84:99], s[4:7], s0
 // GFX10: encoding: [0x02,0x15,0x30,0xf4,0x00,0x00,0x00,0x00]

 // GFX10: encoding: [0x02,0x05,0x30,0xf4,0x00,0x00,0x00,0xd4]
 
 s_buffer_load_dwordx16 s[20:35], s[4:7], vcc_hi
 // GFX10: encoding: [0x02,0x05,0x30,0xf4,0x00,0x00,0x00,0xd6]
 
 s_buffer_load_dwordx16 s[20:35], s[4:7], m0
 // GFX10: encoding: [0x02,0x05,0x30,0xf4,0x00,0x00,0x00,0xf8]
 
+s_buffer_load_dwordx16 s[20:35], s[4:7], null
+// GFX10: encoding: [0x02,0x05,0x30,0xf4,0x00,0x00,0x00,0xfa]
+
 s_buffer_load_dwordx16 s[20:35], s[4:7], 0x0
 // GFX10: encoding: [0x02,0x05,0x30,0xf4,0x00,0x00,0x00,0xfa]
 
+s_buffer_load_dwordx16 s[20:35], s[4:7], s0 offset:0x12345
+// GFX10: encoding: [0x02,0x05,0x30,0xf4,0x45,0x23,0x01,0x00]
+
 s_buffer_load_dwordx16 s[20:35], s[4:7], s0 glc
 // GFX10: encoding: [0x02,0x05,0x31,0xf4,0x00,0x00,0x00,0x00]
 
 s_buffer_load_dwordx16 s[20:35], s[4:7], s0 dlc
 // GFX10: encoding: [0x02,0x45,0x30,0xf4,0x00,0x00,0x00,0x00]
 
 s_buffer_load_dwordx16 s[20:35], s[4:7], s0 glc dlc
 // GFX10: encoding: [0x02,0x45,0x31,0xf4,0x00,0x00,0x00,0x00]
 
 s_buffer_load_dwordx16 s[20:35], s[4:7], 0x1234 glc dlc
 // GFX10: encoding: [0x02,0x45,0x31,0xf4,0x34,0x12,0x00,0xfa]
 
+s_buffer_load_dwordx16 s[20:35], s[4:7], s0 offset:0x12345 glc dlc
+// GFX10: encoding: [0x02,0x45,0x31,0xf4,0x45,0x23,0x01,0x00]
+
 s_store_dword s1, s[4:5], s0
 // GFX10: encoding: [0x42,0x00,0x40,0xf4,0x00,0x00,0x00,0x00]
 
 s_store_dword s101, s[4:5], s0
 // GFX10: encoding: [0x42,0x19,0x40,0xf4,0x00,0x00,0x00,0x00]
 
 s_store_dword vcc_lo, s[4:5], s0
 // GFX10: encoding: [0x82,0x1a,0x40,0xf4,0x00,0x00,0x00,0x00]

 // GFX10: encoding: [0x42,0x00,0x40,0xf4,0x00,0x00,0x00,0xd4]
 
 s_store_dword s1, s[4:5], vcc_hi
 // GFX10: encoding: [0x42,0x00,0x40,0xf4,0x00,0x00,0x00,0xd6]
 
 s_store_dword s1, s[4:5], m0
 // GFX10: encoding: [0x42,0x00,0x40,0xf4,0x00,0x00,0x00,0xf8]
 
+s_store_dword s1, s[4:5], null
+// GFX10: encoding: [0x42,0x00,0x40,0xf4,0x00,0x00,0x00,0xfa]
+
 s_store_dword s1, s[4:5], 0x0
 // GFX10: encoding: [0x42,0x00,0x40,0xf4,0x00,0x00,0x00,0xfa]
 
 s_store_dword s1, s[4:5], s0 glc
 // GFX10: encoding: [0x42,0x00,0x41,0xf4,0x00,0x00,0x00,0x00]
 
 s_store_dword s1, s[4:5], s0 dlc
 // GFX10: encoding: [0x42,0x40,0x40,0xf4,0x00,0x00,0x00,0x00]

 // GFX10: encoding: [0x82,0x00,0x44,0xf4,0x00,0x00,0x00,0xd4]
 
 s_store_dwordx2 s[2:3], s[4:5], vcc_hi
 // GFX10: encoding: [0x82,0x00,0x44,0xf4,0x00,0x00,0x00,0xd6]
 
 s_store_dwordx2 s[2:3], s[4:5], m0
 // GFX10: encoding: [0x82,0x00,0x44,0xf4,0x00,0x00,0x00,0xf8]
 
+s_store_dwordx2 s[2:3], s[4:5], null
+// GFX10: encoding: [0x82,0x00,0x44,0xf4,0x00,0x00,0x00,0xfa]
+
 s_store_dwordx2 s[2:3], s[4:5], 0x0
 // GFX10: encoding: [0x82,0x00,0x44,0xf4,0x00,0x00,0x00,0xfa]
 
 s_store_dwordx2 s[2:3], s[4:5], s0 glc
 // GFX10: encoding: [0x82,0x00,0x45,0xf4,0x00,0x00,0x00,0x00]
 
 s_store_dwordx2 s[2:3], s[4:5], s0 dlc
 // GFX10: encoding: [0x82,0x40,0x44,0xf4,0x00,0x00,0x00,0x00]

 // GFX10: encoding: [0x02,0x01,0x48,0xf4,0x00,0x00,0x00,0xd4]
 
 s_store_dwordx4 s[4:7], s[4:5], vcc_hi
 // GFX10: encoding: [0x02,0x01,0x48,0xf4,0x00,0x00,0x00,0xd6]
 
 s_store_dwordx4 s[4:7], s[4:5], m0
 // GFX10: encoding: [0x02,0x01,0x48,0xf4,0x00,0x00,0x00,0xf8]
 
+s_store_dwordx4 s[4:7], s[4:5], null
+// GFX10: encoding: [0x02,0x01,0x48,0xf4,0x00,0x00,0x00,0xfa]
+
 s_store_dwordx4 s[4:7], s[4:5], 0x0
 // GFX10: encoding: [0x02,0x01,0x48,0xf4,0x00,0x00,0x00,0xfa]
 
 s_store_dwordx4 s[4:7], s[4:5], s0 glc
 // GFX10: encoding: [0x02,0x01,0x49,0xf4,0x00,0x00,0x00,0x00]
 
 s_store_dwordx4 s[4:7], s[4:5], s0 dlc
 // GFX10: encoding: [0x02,0x41,0x48,0xf4,0x00,0x00,0x00,0x00]

 // GFX10: encoding: [0x44,0x00,0x60,0xf4,0x00,0x00,0x00,0xd4]
 
 s_buffer_store_dword s1, s[8:11], vcc_hi
 // GFX10: encoding: [0x44,0x00,0x60,0xf4,0x00,0x00,0x00,0xd6]
 
 s_buffer_store_dword s1, s[8:11], m0
 // GFX10: encoding: [0x44,0x00,0x60,0xf4,0x00,0x00,0x00,0xf8]
 
+s_buffer_store_dword s1, s[8:11], null
+// GFX10: encoding: [0x44,0x00,0x60,0xf4,0x00,0x00,0x00,0xfa]
+
 s_buffer_store_dword s1, s[8:11], 0x0
 // GFX10: encoding: [0x44,0x00,0x60,0xf4,0x00,0x00,0x00,0xfa]
 
 s_buffer_store_dword s1, s[8:11], s0 glc
 // GFX10: encoding: [0x44,0x00,0x61,0xf4,0x00,0x00,0x00,0x00]
 
 s_buffer_store_dword s1, s[8:11], s0 dlc
 // GFX10: encoding: [0x44,0x40,0x60,0xf4,0x00,0x00,0x00,0x00]

 // GFX10: encoding: [0x84,0x00,0x64,0xf4,0x00,0x00,0x00,0xd4]
 
 s_buffer_store_dwordx2 s[2:3], s[8:11], vcc_hi
 // GFX10: encoding: [0x84,0x00,0x64,0xf4,0x00,0x00,0x00,0xd6]
 
 s_buffer_store_dwordx2 s[2:3], s[8:11], m0
 // GFX10: encoding: [0x84,0x00,0x64,0xf4,0x00,0x00,0x00,0xf8]
 
+s_buffer_store_dwordx2 s[2:3], s[8:11], null
+// GFX10: encoding: [0x84,0x00,0x64,0xf4,0x00,0x00,0x00,0xfa]
+
 s_buffer_store_dwordx2 s[2:3], s[8:11], 0x0
 // GFX10: encoding: [0x84,0x00,0x64,0xf4,0x00,0x00,0x00,0xfa]
 
 s_buffer_store_dwordx2 s[2:3], s[8:11], s0 glc
 // GFX10: encoding: [0x84,0x00,0x65,0xf4,0x00,0x00,0x00,0x00]
 
 s_buffer_store_dwordx2 s[2:3], s[8:11], s0 dlc
 // GFX10: encoding: [0x84,0x40,0x64,0xf4,0x00,0x00,0x00,0x00]

 // GFX10: encoding: [0x04,0x01,0x68,0xf4,0x00,0x00,0x00,0xd4]
 
 s_buffer_store_dwordx4 s[4:7], s[8:11], vcc_hi
 // GFX10: encoding: [0x04,0x01,0x68,0xf4,0x00,0x00,0x00,0xd6]
 
 s_buffer_store_dwordx4 s[4:7], s[8:11], m0
 // GFX10: encoding: [0x04,0x01,0x68,0xf4,0x00,0x00,0x00,0xf8]
 
+s_buffer_store_dwordx4 s[4:7], s[8:11], null
+// GFX10: encoding: [0x04,0x01,0x68,0xf4,0x00,0x00,0x00,0xfa]
+
 s_buffer_store_dwordx4 s[4:7], s[8:11], 0x0
 // GFX10: encoding: [0x04,0x01,0x68,0xf4,0x00,0x00,0x00,0xfa]
 
 s_buffer_store_dwordx4 s[4:7], s[8:11], s0 glc
 // GFX10: encoding: [0x04,0x01,0x69,0xf4,0x00,0x00,0x00,0x00]
 
 s_buffer_store_dwordx4 s[4:7], s[8:11], s0 dlc
 // GFX10: encoding: [0x04,0x41,0x68,0xf4,0x00,0x00,0x00,0x00]

llvm/test/MC/AMDGPU/smem.s

 // RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti -show-encoding %s | FileCheck -check-prefix=SICI %s
 // RUN: not llvm-mc -arch=amdgcn -mcpu=bonaire -show-encoding %s | FileCheck -check-prefix=SICI %s
 // RUN: not llvm-mc -arch=amdgcn -mcpu=kaveri -show-encoding %s | FileCheck -check-prefix=SICI %s
 // RUN: not llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s | FileCheck --check-prefixes=VI,GFX89 %s
 // RUN: not llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck --check-prefixes=GFX89,GFX9 %s
 // RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1012 -show-encoding %s | FileCheck --check-prefixes=GFX10,GFX1012 %s
 // RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1030 -show-encoding %s | FileCheck -check-prefix=GFX10 %s
 // RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti %s 2>&1 | FileCheck --check-prefixes=NOSICI,NOSICIGFX10,NOSICIGFX1030,NOSICIVIGFX1030 --implicit-check-not=error: %s
 // RUN: not llvm-mc -arch=amdgcn -mcpu=bonaire %s 2>&1 | FileCheck --check-prefixes=NOSICI,NOSICIGFX10,NOSICIGFX1030,NOSICIVIGFX1030 --implicit-check-not=error: %s
 // RUN: not llvm-mc -arch=amdgcn -mcpu=kaveri %s 2>&1 | FileCheck --check-prefixes=NOSICI,NOSICIGFX10,NOSICIGFX1030,NOSICIVIGFX1030 --implicit-check-not=error: %s
 // RUN: not llvm-mc -arch=amdgcn -mcpu=tonga %s 2>&1 | FileCheck --check-prefixes=NOVI,NOSICIVIGFX1030 --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx900 %s 2>&1 | FileCheck --check-prefixes=NOGFX9,NOGFX9GFX1012 --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1012 %s 2>&1 | FileCheck --check-prefixes=NOSICIGFX10,NOGFX9,NOGFX9GFX1012 --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1030 %s 2>&1 | FileCheck --check-prefixes=NOSICIGFX1030,NOSICIVIGFX1030,NOSICIGFX10,NOGFX9,NOGFX1030 --implicit-check-not=error: %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx900 %s 2>&1 | FileCheck --check-prefixes=NOGFX9GFX10,NOGFX9GFX1012,NOGFX9 --implicit-check-not=error: %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1012 %s 2>&1 | FileCheck --check-prefixes=NOSICIGFX10,NOGFX9GFX10,NOGFX9GFX1012,NOGFX10 --implicit-check-not=error: %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1030 %s 2>&1 | FileCheck --check-prefixes=NOSICIGFX1030,NOSICIVIGFX1030,NOSICIGFX10,NOGFX9GFX10,NOGFX1030,NOGFX10 --implicit-check-not=error: %s
 
 s_dcache_wb
 // GFX89: s_dcache_wb  ; encoding: [0x00,0x00,0x84,0xc0,0x00,0x00,0x00,0x00]
 // GFX1012: s_dcache_wb  ; encoding: [0x00,0x00,0x84,0xf4,0x00,0x00,0x00,0x00]
 // NOSICIGFX1030: error: instruction not supported on this GPU
 
 s_dcache_wb_vol
 // GFX89: s_dcache_wb_vol ; encoding: [0x00,0x00,0x8c,0xc0,0x00,0x00,0x00,0x00]

 s_memrealtime s[4:5]
 // GFX89: s_memrealtime s[4:5] ; encoding: [0x00,0x01,0x94,0xc0,0x00,0x00,0x00,0x00]
 // GFX10: s_memrealtime s[4:5] ; encoding: [0x00,0x01,0x94,0xf4,0x00,0x00,0x00,0x00]
 // NOSICI: error: instruction not supported on this GPU
 
 s_memrealtime tba
 // VI: s_memrealtime tba ; encoding: [0x00,0x1b,0x94,0xc0,0x00,0x00,0x00,0x00]
 // NOSICI: error: instruction not supported on this GPU
-// NOGFX9: error: register not available on this GPU
+// NOGFX9GFX10: error: register not available on this GPU
 
 s_memrealtime tma
 // VI: s_memrealtime tma ; encoding: [0x80,0x1b,0x94,0xc0,0x00,0x00,0x00,0x00]
 // NOSICI: error: instruction not supported on this GPU
-// NOGFX9: error: register not available on this GPU
+// NOGFX9GFX10: error: register not available on this GPU
 
 s_memrealtime ttmp[0:1]
 // VI:    s_memrealtime ttmp[0:1] ; encoding: [0x00,0x1c,0x94,0xc0,0x00,0x00,0x00,0x00]
 // GFX9:  s_memrealtime ttmp[0:1] ; encoding: [0x00,0x1b,0x94,0xc0,0x00,0x00,0x00,0x00]
 // GFX10: s_memrealtime ttmp[0:1] ; encoding: [0x00,0x1b,0x94,0xf4,0x00,0x00,0x00,0x00]
 // NOSICI: error: instruction not supported on this GPU
 
 s_store_dword s1, s[2:3], 0xfc

 s_buffer_load_dword s10, s[92:95], m0
 // GFX89: s_buffer_load_dword s10, s[92:95], m0 ; encoding: [0xae,0x02,0x20,0xc0,0x7c,0x00,0x00,0x00]
 // SICI: s_buffer_load_dword s10, s[92:95], m0 ; encoding: [0x7c,0x5c,0x05,0xc2]
 // GFX10: s_buffer_load_dword s10, s[92:95], m0 ; encoding: [0xae,0x02,0x20,0xf4,0x00,0x00,0x00,0xf8]
 
 s_buffer_load_dword tba_lo, s[92:95], m0
 // VI: s_buffer_load_dword tba_lo, s[92:95], m0 ; encoding: [0x2e,0x1b,0x20,0xc0,0x7c,0x00,0x00,0x00]
 // SICI: s_buffer_load_dword tba_lo, s[92:95], m0 ; encoding: [0x7c,0x5c,0x36,0xc2]
-// NOGFX9: error: register not available on this GPU
+// NOGFX9GFX10: error: register not available on this GPU
 
 s_buffer_load_dword tba_hi, s[92:95], m0
 // VI: s_buffer_load_dword tba_hi, s[92:95], m0 ; encoding: [0x6e,0x1b,0x20,0xc0,0x7c,0x00,0x00,0x00]
 // SICI: s_buffer_load_dword tba_hi, s[92:95], m0 ; encoding: [0x7c,0xdc,0x36,0xc2]
-// NOGFX9: error: register not available on this GPU
+// NOGFX9GFX10: error: register not available on this GPU
 
 s_buffer_load_dword tma_lo, s[92:95], m0
 // VI: s_buffer_load_dword tma_lo, s[92:95], m0 ; encoding: [0xae,0x1b,0x20,0xc0,0x7c,0x00,0x00,0x00]
 // SICI: s_buffer_load_dword tma_lo, s[92:95], m0 ; encoding: [0x7c,0x5c,0x37,0xc2]
-// NOGFX9: error: register not available on this GPU
+// NOGFX9GFX10: error: register not available on this GPU
 
 s_buffer_load_dword tma_hi, s[92:95], m0
 // VI: s_buffer_load_dword tma_hi, s[92:95], m0 ; encoding: [0xee,0x1b,0x20,0xc0,0x7c,0x00,0x00,0x00]
 // SICI: s_buffer_load_dword tma_hi, s[92:95], m0 ; encoding: [0x7c,0xdc,0x37,0xc2]
-// NOGFX9: error: register not available on this GPU
+// NOGFX9GFX10: error: register not available on this GPU
 
 s_buffer_load_dword ttmp0, s[92:95], m0
 // VI:    s_buffer_load_dword ttmp0, s[92:95], m0 ; encoding: [0x2e,0x1c,0x20,0xc0,0x7c,0x00,0x00,0x00]
 // GFX9:  s_buffer_load_dword ttmp0, s[92:95], m0 ; encoding: [0x2e,0x1b,0x20,0xc0,0x7c,0x00,0x00,0x00]
 // SICI:  s_buffer_load_dword ttmp0, s[92:95], m0 ; encoding: [0x7c,0x5c,0x38,0xc2]
 // GFX10: s_buffer_load_dword ttmp0, s[92:95], m0 ; encoding: [0x2e,0x1b,0x20,0xf4,0x00,0x00,0x00,0xf8]
 
 s_buffer_load_dwordx2 s[10:11], s[92:95], m0
 // GFX89: s_buffer_load_dwordx2 s[10:11], s[92:95], m0 ; encoding: [0xae,0x02,0x24,0xc0,0x7c,0x00,0x00,0x00]
 // SICI:  s_buffer_load_dwordx2 s[10:11], s[92:95], m0 ; encoding: [0x7c,0x5c,0x45,0xc2]
 // GFX10: s_buffer_load_dwordx2 s[10:11], s[92:95], m0 ; encoding: [0xae,0x02,0x24,0xf4,0x00,0x00,0x00,0xf8]
 
 s_buffer_load_dwordx2 tba, s[92:95], m0
 // VI:   s_buffer_load_dwordx2 tba, s[92:95], m0 ; encoding: [0x2e,0x1b,0x24,0xc0,0x7c,0x00,0x00,0x00]
 // SICI: s_buffer_load_dwordx2 tba, s[92:95], m0 ; encoding: [0x7c,0x5c,0x76,0xc2]
-// NOGFX9: error: register not available on this GPU
+// NOGFX9GFX10: error: register not available on this GPU
 
 s_buffer_load_dwordx2 tma, s[92:95], m0
 // VI: s_buffer_load_dwordx2 tma, s[92:95], m0 ; encoding: [0xae,0x1b,0x24,0xc0,0x7c,0x00,0x00,0x00]
 // SICI: s_buffer_load_dwordx2 tma, s[92:95], m0 ; encoding: [0x7c,0x5c,0x77,0xc2]
-// NOGFX9: error: register not available on this GPU
+// NOGFX9GFX10: error: register not available on this GPU
 
 s_buffer_load_dwordx2 ttmp[0:1], s[92:95], m0
 // VI:    s_buffer_load_dwordx2 ttmp[0:1], s[92:95], m0 ; encoding: [0x2e,0x1c,0x24,0xc0,0x7c,0x00,0x00,0x00]
 // GFX9:  s_buffer_load_dwordx2 ttmp[0:1], s[92:95], m0 ; encoding: [0x2e,0x1b,0x24,0xc0,0x7c,0x00,0x00,0x00]
 // SICI:  s_buffer_load_dwordx2 ttmp[0:1], s[92:95], m0 ; encoding: [0x7c,0x5c,0x78,0xc2]
 // GFX10: s_buffer_load_dwordx2 ttmp[0:1], s[92:95], m0 ; encoding: [0x2e,0x1b,0x24,0xf4,0x00,0x00,0x00,0xf8]
 
 // FIXME: Should error on SI instead of silently ignoring glc

 
 s_buffer_atomic_swap s5, s[4:7], 0xFFFFF
 // NOSICIVIGFX1030: error: instruction not supported on this GPU
 // GFX1012: s_buffer_atomic_swap s5, s[4:7], 0xfffff ; encoding: [0x42,0x01,0x00,0xf5,0xff,0xff,0x0f,0xfa]
 // GFX9: s_buffer_atomic_swap s5, s[4:7], 0xfffff ; encoding: [0x42,0x01,0x02,0xc1,0xff,0xff,0x0f,0x00]
 
 s_atc_probe 0x7, s[4:5], 0x1FFFFF
 // NOSICI: error: instruction not supported on this GPU
-// NOGFX9: error: expected a 21-bit signed offset
+// NOGFX9GFX10: error: expected a 21-bit signed offset
 // NOVI: error: expected a 20-bit unsigned offset
 
 s_atc_probe_buffer 0x1, s[8:11], 0x1FFFFF
 // NOSICI: error: instruction not supported on this GPU
-// NOGFX9: error: expected a 20-bit unsigned offset
+// NOGFX9GFX10: error: expected a 20-bit unsigned offset
 // NOVI: error: expected a 20-bit unsigned offset
 
+s_load_dword s1, s[2:3], s0 offset:0x1FFFFF
+// NOSICI: error: operands are not valid for this GPU or mode
+// NOVI: error: operands are not valid for this GPU or mode
+// NOGFX9: error: operands are not valid for this GPU or mode
+// NOGFX10: error: expected a 21-bit signed offset
+
 s_store_dword s1, s[2:3], 0x1FFFFF
 // NOSICIGFX1030: error: instruction not supported on this GPU
 // NOGFX9GFX1012: error: expected a 21-bit signed offset
 // NOVI: error: expected a 20-bit unsigned offset
 
+s_buffer_load_dword s10, s[92:95], s0 offset:-1
+// NOSICI: error: operands are not valid for this GPU or mode
+// NOVI: error: operands are not valid for this GPU or mode
+// NOGFX9: error: operands are not valid for this GPU or mode
+// NOGFX10: error: expected a 20-bit unsigned offset
+
 s_buffer_store_dword s10, s[92:95], 0x1FFFFF
 // NOSICIGFX1030: error: instruction not supported on this GPU
 // NOGFX9GFX1012: error: expected a 20-bit unsigned offset
 // NOVI: error: expected a 20-bit unsigned offset
 
 s_atomic_swap s5, s[2:3], 0x1FFFFF
 // NOSICIVIGFX1030: error: instruction not supported on this GPU
 // NOGFX9GFX1012: error: expected a 21-bit signed offset

 // NOVI: error: expected a 20-bit unsigned offset
 // GFX9: s_atc_probe 7, s[4:5], -0x1 ; encoding: [0xc2,0x01,0x9a,0xc0,0xff,0xff,0x1f,0x00]
 // GFX10: s_atc_probe 7, s[4:5], -0x1 ; encoding: [0xc2,0x01,0x98,0xf4,0xff,0xff,0x1f,0xfa]
 // NOSICI: error: instruction not supported on this GPU
 
 s_atc_probe_buffer 0x1, s[8:11], -1
 // NOVI: error: expected a 20-bit unsigned offset
 // NOSICI: error: instruction not supported on this GPU
-// NOGFX9: error: expected a 20-bit unsigned offset
+// NOGFX9GFX10: error: expected a 20-bit unsigned offset
 
 s_store_dword s1, s[2:3], -1
 // NOVI: error: expected a 20-bit unsigned offset
 // GFX9: s_store_dword s1, s[2:3], -0x1 ; encoding: [0x41,0x00,0x42,0xc0,0xff,0xff,0x1f,0x00]
 // GFX1012: s_store_dword s1, s[2:3], -0x1 ; encoding: [0x41,0x00,0x40,0xf4,0xff,0xff,0x1f,0xfa]
 // NOSICIGFX1030: error: instruction not supported on this GPU
 
 s_buffer_store_dword s10, s[92:95], -1
 // NOVI: error: expected a 20-bit unsigned offset
 // NOSICIGFX1030: error: instruction not supported on this GPU
 // NOGFX9GFX1012: error: expected a 20-bit unsigned offset
 
 s_load_dword s1, s[2:3], -1
 // NOVI: error: expected a 20-bit unsigned offset
 // GFX9: s_load_dword s1, s[2:3], -0x1 ; encoding: [0x41,0x00,0x02,0xc0,0xff,0xff,0x1f,0x00]
 // GFX10: s_load_dword s1, s[2:3], -0x1 ; encoding: [0x41,0x00,0x00,0xf4,0xff,0xff,0x1f,0xfa]
 // NOSICI: error: operands are not valid for this GPU or mode
 
 s_buffer_load_dword s10, s[92:95], -1
 // NOVI: error: expected a 20-bit unsigned offset
 // NOSICI: error: operands are not valid for this GPU or mode
-// NOGFX9: error: expected a 20-bit unsigned offset
+// NOGFX9GFX10: error: expected a 20-bit unsigned offset
 
 s_atomic_swap s5, s[2:3], -1
 // NOVI: error: instruction not supported on this GPU
 // GFX9: s_atomic_swap s5, s[2:3], -0x1 ; encoding: [0x41,0x01,0x02,0xc2,0xff,0xff,0x1f,0x00]
 // GFX1012: s_atomic_swap s5, s[2:3], -0x1 ; encoding: [0x41,0x01,0x00,0xf6,0xff,0xff,0x1f,0xfa]
 // NOSICIGFX1030: error: instruction not supported on this GPU
 
 s_buffer_atomic_swap s5, s[4:7], -1
 // NOVI: error: instruction not supported on this GPU
 // NOSICIGFX1030: error: instruction not supported on this GPU
 // NOGFX9GFX1012: error: expected a 20-bit unsigned offset
 
 s_atc_probe 0x7, s[4:5], 0xFFFFFFFFFFF00000
 // NOSICI: error: instruction not supported on this GPU
 // GFX10: s_atc_probe 7, s[4:5], -0x100000 ; encoding: [0xc2,0x01,0x98,0xf4,0x00,0x00,0x10,0xfa]
 // GFX9: s_atc_probe 7, s[4:5], -0x100000 ; encoding: [0xc2,0x01,0x9a,0xc0,0x00,0x00,0x10,0x00]
 // NOVI: error: expected a 20-bit unsigned offset
 
 s_atc_probe_buffer 0x1, s[8:11], 0xFFFFFFFFFFF00000
 // NOSICI: error: instruction not supported on this GPU
-// NOGFX9: error: expected a 20-bit unsigned offset
+// NOGFX9GFX10: error: expected a 20-bit unsigned offset
 // NOVI: error: expected a 20-bit unsigned offset
 
 s_store_dword s1, s[2:3], 0xFFFFFFFFFFF00000
 // NOSICIGFX1030: error: instruction not supported on this GPU
 // GFX1012: s_store_dword s1, s[2:3], -0x100000 ; encoding: [0x41,0x00,0x40,0xf4,0x00,0x00,0x10,0xfa]
 // GFX9: s_store_dword s1, s[2:3], -0x100000 ; encoding: [0x41,0x00,0x42,0xc0,0x00,0x00,0x10,0x00]
 // NOVI: error: expected a 20-bit unsigned offset
 
 s_buffer_store_dword s10, s[92:95], 0xFFFFFFFFFFF00000
 // NOSICIGFX1030: error: instruction not supported on this GPU
 // NOGFX9GFX1012: error: expected a 20-bit unsigned offset
 // NOVI: error: expected a 20-bit unsigned offset
 
 s_load_dword s1, s[2:3], 0xFFFFFFFFFFF00000
 // NOSICI: error: operands are not valid for this GPU or mode
 // GFX10: s_load_dword s1, s[2:3], -0x100000 ; encoding: [0x41,0x00,0x00,0xf4,0x00,0x00,0x10,0xfa]
 // GFX9: s_load_dword s1, s[2:3], -0x100000 ; encoding: [0x41,0x00,0x02,0xc0,0x00,0x00,0x10,0x00]
 // NOVI: error: expected a 20-bit unsigned offset
 
 s_buffer_load_dword s10, s[92:95], 0xFFFFFFFFFFF00000
 // NOSICI: error: operands are not valid for this GPU or mode
-// NOGFX9: error: expected a 20-bit unsigned offset
+// NOGFX9GFX10: error: expected a 20-bit unsigned offset
 // NOVI: error: expected a 20-bit unsigned offset
 
 s_atomic_swap s5, s[2:3], 0xFFFFFFFFFFF00000
 // NOSICIVIGFX1030: error: instruction not supported on this GPU
 // GFX1012: s_atomic_swap s5, s[2:3], -0x100000 ; encoding: [0x41,0x01,0x00,0xf6,0x00,0x00,0x10,0xfa]
 // GFX9: s_atomic_swap s5, s[2:3], -0x100000 ; encoding: [0x41,0x01,0x02,0xc2,0x00,0x00,0x10,0x00]
 
 s_buffer_atomic_swap s5, s[4:7], 0xFFFFFFFFFFF00000
 // NOSICIVIGFX1030: error: instruction not supported on this GPU
 // NOGFX9GFX1012: error: expected a 20-bit unsigned offset

llvm/test/MC/Disassembler/AMDGPU/gfx10_dasm_all.txt

 0x02,0x0c,0xe8,0xbe
 
 # GFX10: s_brev_b64 vcc, s[2:3]                  ; encoding: [0x02,0x0c,0xea,0xbe]
 0x02,0x0c,0xea,0xbe
 
 # GFX10: s_buffer_load_dword s101, s[4:7], s0    ; encoding: [0x42,0x19,0x20,0xf4,0x00,0x00,0x00,0x00]
 0x42,0x19,0x20,0xf4,0x00,0x00,0x00,0x00
 
-# GFX10: s_buffer_load_dword s5, s[4:7], 0x0     ; encoding: [0x42,0x01,0x20,0xf4,0x00,0x00,0x00,0xfa]
+# GFX10: s_buffer_load_dword s5, s[4:7], null    ; encoding: [0x42,0x01,0x20,0xf4,0x00,0x00,0x00,0xfa]
 0x42,0x01,0x20,0xf4,0x00,0x00,0x00,0xfa
 
 # GFX10: s_buffer_load_dword s5, s[4:7], 0x1234 glc dlc ; encoding: [0x42,0x41,0x21,0xf4,0x34,0x12,0x00,0xfa]
 0x42,0x41,0x21,0xf4,0x34,0x12,0x00,0xfa
 
+# GFX10: s_buffer_load_dword s5, s[4:7], s0 offset:0x12345 glc dlc ; encoding: [0x42,0x41,0x21,0xf4,0x45,0x23,0x01,0x00]
+0x42,0x41,0x21,0xf4,0x45,0x23,0x01,0x00
+
 # GFX10: s_buffer_load_dword s5, s[4:7], m0      ; encoding: [0x42,0x01,0x20,0xf4,0x00,0x00,0x00,0xf8]
 0x42,0x01,0x20,0xf4,0x00,0x00,0x00,0xf8
 
 # GFX10: s_buffer_load_dword s5, s[4:7], s0      ; encoding: [0x42,0x01,0x20,0xf4,0x00,0x00,0x00,0x00]
 0x42,0x01,0x20,0xf4,0x00,0x00,0x00,0x00
 
 # GFX10: s_buffer_load_dword s5, s[4:7], s0 dlc  ; encoding: [0x42,0x41,0x20,0xf4,0x00,0x00,0x00,0x00]
 0x42,0x41,0x20,0xf4,0x00,0x00,0x00,0x00

 0x70,0x01,0x20,0xf4,0x00,0x00,0x00,0x00
 
 # GFX10: s_buffer_load_dword vcc_hi, s[4:7], s0  ; encoding: [0xc2,0x1a,0x20,0xf4,0x00,0x00,0x00,0x00]
 0xc2,0x1a,0x20,0xf4,0x00,0x00,0x00,0x00
 
 # GFX10: s_buffer_load_dword vcc_lo, s[4:7], s0  ; encoding: [0x82,0x1a,0x20,0xf4,0x00,0x00,0x00,0x00]
 0x82,0x1a,0x20,0xf4,0x00,0x00,0x00,0x00
 
-# GFX10: s_buffer_load_dwordx16 s[20:35], s[4:7], 0x0 ; encoding: [0x02,0x05,0x30,0xf4,0x00,0x00,0x00,0xfa]
+# GFX10: s_buffer_load_dwordx16 s[20:35], s[4:7], null ; encoding: [0x02,0x05,0x30,0xf4,0x00,0x00,0x00,0xfa]
 0x02,0x05,0x30,0xf4,0x00,0x00,0x00,0xfa
 
 # GFX10: s_buffer_load_dwordx16 s[20:35], s[4:7], 0x1234 glc dlc ; encoding: [0x02,0x45,0x31,0xf4,0x34,0x12,0x00,0xfa]
 0x02,0x45,0x31,0xf4,0x34,0x12,0x00,0xfa
 
+# GFX10: s_buffer_load_dwordx16 s[20:35], s[4:7], s0 offset:0x12345 glc dlc ; encoding: [0x02,0x45,0x31,0xf4,0x45,0x23,0x01,0x00]
+0x02,0x45,0x31,0xf4,0x45,0x23,0x01,0x00
+
 # GFX10: s_buffer_load_dwordx16 s[20:35], s[4:7], m0 ; encoding: [0x02,0x05,0x30,0xf4,0x00,0x00,0x00,0xf8]
 0x02,0x05,0x30,0xf4,0x00,0x00,0x00,0xf8
 
 # GFX10: s_buffer_load_dwordx16 s[20:35], s[4:7], s0 ; encoding: [0x02,0x05,0x30,0xf4,0x00,0x00,0x00,0x00]
 0x02,0x05,0x30,0xf4,0x00,0x00,0x00,0x00
 
 # GFX10: s_buffer_load_dwordx16 s[20:35], s[4:7], s0 dlc ; encoding: [0x02,0x45,0x30,0xf4,0x00,0x00,0x00,0x00]
 0x02,0x45,0x30,0xf4,0x00,0x00,0x00,0x00

 0x02,0x06,0x30,0xf4,0x00,0x00,0x00,0x00
 
 # GFX10: s_buffer_load_dwordx16 s[84:99], s[4:7], s0 ; encoding: [0x02,0x15,0x30,0xf4,0x00,0x00,0x00,0x00]
 0x02,0x15,0x30,0xf4,0x00,0x00,0x00,0x00
 
 # GFX10: s_buffer_load_dwordx2 s[100:101], s[4:7], s0 ; encoding: [0x02,0x19,0x24,0xf4,0x00,0x00,0x00,0x00]
 0x02,0x19,0x24,0xf4,0x00,0x00,0x00,0x00
 
-# GFX10: s_buffer_load_dwordx2 s[10:11], s[4:7], 0x0 ; encoding: [0x82,0x02,0x24,0xf4,0x00,0x00,0x00,0xfa]
+# GFX10: s_buffer_load_dwordx2 s[10:11], s[4:7], null ; encoding: [0x82,0x02,0x24,0xf4,0x00,0x00,0x00,0xfa]
 0x82,0x02,0x24,0xf4,0x00,0x00,0x00,0xfa
 
 # GFX10: s_buffer_load_dwordx2 s[10:11], s[4:7], 0x1234 glc dlc ; encoding: [0x82,0x42,0x25,0xf4,0x34,0x12,0x00,0xfa]
 0x82,0x42,0x25,0xf4,0x34,0x12,0x00,0xfa
 
+# GFX10: s_buffer_load_dwordx2 s[10:11], s[4:7], s0 offset:0x12345 glc dlc ; encoding: [0x82,0x42,0x25,0xf4,0x45,0x23,0x01,0x00]
+0x82,0x42,0x25,0xf4,0x45,0x23,0x01,0x00
+
 # GFX10: s_buffer_load_dwordx2 s[10:11], s[4:7], m0 ; encoding: [0x82,0x02,0x24,0xf4,0x00,0x00,0x00,0xf8]
 0x82,0x02,0x24,0xf4,0x00,0x00,0x00,0xf8
 
 # GFX10: s_buffer_load_dwordx2 s[10:11], s[4:7], s0 ; encoding: [0x82,0x02,0x24,0xf4,0x00,0x00,0x00,0x00]
 0x82,0x02,0x24,0xf4,0x00,0x00,0x00,0x00
 
 # GFX10: s_buffer_load_dwordx2 s[10:11], s[4:7], s0 dlc ; encoding: [0x82,0x42,0x24,0xf4,0x00,0x00,0x00,0x00]
 0x82,0x42,0x24,0xf4,0x00,0x00,0x00,0x00

 0xb0,0x02,0x24,0xf4,0x00,0x00,0x00,0x00
 
 # GFX10: s_buffer_load_dwordx2 s[12:13], s[4:7], s0 ; encoding: [0x02,0x03,0x24,0xf4,0x00,0x00,0x00,0x00]
 0x02,0x03,0x24,0xf4,0x00,0x00,0x00,0x00
 
 # GFX10: s_buffer_load_dwordx2 vcc, s[4:7], s0   ; encoding: [0x82,0x1a,0x24,0xf4,0x00,0x00,0x00,0x00]
 0x82,0x1a,0x24,0xf4,0x00,0x00,0x00,0x00
 
-# GFX10: s_buffer_load_dwordx4 s[20:23], s[4:7], 0x0 ; encoding: [0x02,0x05,0x28,0xf4,0x00,0x00,0x00,0xfa]
+# GFX10: s_buffer_load_dwordx4 s[20:23], s[4:7], null ; encoding: [0x02,0x05,0x28,0xf4,0x00,0x00,0x00,0xfa]
 0x02,0x05,0x28,0xf4,0x00,0x00,0x00,0xfa
 
 # GFX10: s_buffer_load_dwordx4 s[20:23], s[4:7], 0x1234 glc dlc ; encoding: [0x02,0x45,0x29,0xf4,0x34,0x12,0x00,0xfa]
 0x02,0x45,0x29,0xf4,0x34,0x12,0x00,0xfa
 
+# GFX10: s_buffer_load_dwordx4 s[20:23], s[4:7], s0 offset:0x12345 glc dlc ; encoding: [0x02,0x45,0x29,0xf4,0x45,0x23,0x01,0x00]
+0x02,0x45,0x29,0xf4,0x45,0x23,0x01,0x00
+
 # GFX10: s_buffer_load_dwordx4 s[20:23], s[4:7], m0 ; encoding: [0x02,0x05,0x28,0xf4,0x00,0x00,0x00,0xf8]
 0x02,0x05,0x28,0xf4,0x00,0x00,0x00,0xf8
 
 # GFX10: s_buffer_load_dwordx4 s[20:23], s[4:7], s0 ; encoding: [0x02,0x05,0x28,0xf4,0x00,0x00,0x00,0x00]
 0x02,0x05,0x28,0xf4,0x00,0x00,0x00,0x00
 
 # GFX10: s_buffer_load_dwordx4 s[20:23], s[4:7], s0 dlc ; encoding: [0x02,0x45,0x28,0xf4,0x00,0x00,0x00,0x00]
 0x02,0x45,0x28,0xf4,0x00,0x00,0x00,0x00

 0x30,0x05,0x28,0xf4,0x00,0x00,0x00,0x00
 
 # GFX10: s_buffer_load_dwordx4 s[24:27], s[4:7], s0 ; encoding: [0x02,0x06,0x28,0xf4,0x00,0x00,0x00,0x00]
 0x02,0x06,0x28,0xf4,0x00,0x00,0x00,0x00
 
 # GFX10: s_buffer_load_dwordx4 s[96:99], s[4:7], s0 ; encoding: [0x02,0x18,0x28,0xf4,0x00,0x00,0x00,0x00]
 0x02,0x18,0x28,0xf4,0x00,0x00,0x00,0x00
 
-# GFX10: s_buffer_load_dwordx8 s[20:27], s[4:7], 0x0 ; encoding: [0x02,0x05,0x2c,0xf4,0x00,0x00,0x00,0xfa]
+# GFX10: s_buffer_load_dwordx8 s[20:27], s[4:7], null ; encoding: [0x02,0x05,0x2c,0xf4,0x00,0x00,0x00,0xfa]
 0x02,0x05,0x2c,0xf4,0x00,0x00,0x00,0xfa
 
 # GFX10: s_buffer_load_dwordx8 s[20:27], s[4:7], 0x1234 glc dlc ; encoding: [0x02,0x45,0x2d,0xf4,0x34,0x12,0x00,0xfa]
 0x02,0x45,0x2d,0xf4,0x34,0x12,0x00,0xfa
 
+# GFX10: s_buffer_load_dwordx8 s[20:27], s[4:7], s0 offset:0x12345 glc dlc ; encoding: [0x02,0x45,0x2d,0xf4,0x45,0x23,0x01,0x00]
+0x02,0x45,0x2d,0xf4,0x45,0x23,0x01,0x00
+
 # GFX10: s_buffer_load_dwordx8 s[20:27], s[4:7], m0 ; encoding: [0x02,0x05,0x2c,0xf4,0x00,0x00,0x00,0xf8]
 0x02,0x05,0x2c,0xf4,0x00,0x00,0x00,0xf8
 
 # GFX10: s_buffer_load_dwordx8 s[20:27], s[4:7], s0 ; encoding: [0x02,0x05,0x2c,0xf4,0x00,0x00,0x00,0x00]
 0x02,0x05,0x2c,0xf4,0x00,0x00,0x00,0x00
 
 # GFX10: s_buffer_load_dwordx8 s[20:27], s[4:7], s0 dlc ; encoding: [0x02,0x45,0x2c,0xf4,0x00,0x00,0x00,0x00]
 0x02,0x45,0x2c,0xf4,0x00,0x00,0x00,0x00

 0x02,0x06,0x2c,0xf4,0x00,0x00,0x00,0x00
 
 # GFX10: s_buffer_load_dwordx8 s[92:99], s[4:7], s0 ; encoding: [0x02,0x17,0x2c,0xf4,0x00,0x00,0x00,0x00]
 0x02,0x17,0x2c,0xf4,0x00,0x00,0x00,0x00
 
 # GFX10: s_buffer_store_dword s1, s[12:15], s0   ; encoding: [0x46,0x00,0x60,0xf4,0x00,0x00,0x00,0x00]
 0x46,0x00,0x60,0xf4,0x00,0x00,0x00,0x00
 
-# GFX10: s_buffer_store_dword s1, s[8:11], 0x0   ; encoding: [0x44,0x00,0x60,0xf4,0x00,0x00,0x00,0xfa]
+# GFX10: s_buffer_store_dword s1, s[8:11], null  ; encoding: [0x44,0x00,0x60,0xf4,0x00,0x00,0x00,0xfa]
 0x44,0x00,0x60,0xf4,0x00,0x00,0x00,0xfa
 
 # GFX10: s_buffer_store_dword s1, s[8:11], 0x1234 glc dlc ; encoding: [0x44,0x40,0x61,0xf4,0x34,0x12,0x00,0xfa]
 0x44,0x40,0x61,0xf4,0x34,0x12,0x00,0xfa
 
 # GFX10: s_buffer_store_dword s1, s[8:11], m0    ; encoding: [0x44,0x00,0x60,0xf4,0x00,0x00,0x00,0xf8]
 0x44,0x00,0x60,0xf4,0x00,0x00,0x00,0xf8
 

 0x84,0x1a,0x60,0xf4,0x00,0x00,0x00,0x00
 
 # GFX10: s_buffer_store_dwordx2 s[100:101], s[8:11], s0 ; encoding: [0x04,0x19,0x64,0xf4,0x00,0x00,0x00,0x00]
 0x04,0x19,0x64,0xf4,0x00,0x00,0x00,0x00
 
 # GFX10: s_buffer_store_dwordx2 s[2:3], s[12:15], s0 ; encoding: [0x86,0x00,0x64,0xf4,0x00,0x00,0x00,0x00]
 0x86,0x00,0x64,0xf4,0x00,0x00,0x00,0x00
 
-# GFX10: s_buffer_store_dwordx2 s[2:3], s[8:11], 0x0 ; encoding: [0x84,0x00,0x64,0xf4,0x00,0x00,0x00,0xfa]
+# GFX10: s_buffer_store_dwordx2 s[2:3], s[8:11], null ; encoding: [0x84,0x00,0x64,0xf4,0x00,0x00,0x00,0xfa]
 0x84,0x00,0x64,0xf4,0x00,0x00,0x00,0xfa
 
 # GFX10: s_buffer_store_dwordx2 s[2:3], s[8:11], 0x1234 glc dlc ; encoding: [0x84,0x40,0x65,0xf4,0x34,0x12,0x00,0xfa]
 0x84,0x40,0x65,0xf4,0x34,0x12,0x00,0xfa
 
 # GFX10: s_buffer_store_dwordx2 s[2:3], s[8:11], m0 ; encoding: [0x84,0x00,0x64,0xf4,0x00,0x00,0x00,0xf8]
 0x84,0x00,0x64,0xf4,0x00,0x00,0x00,0xf8
 

 0x04,0x01,0x64,0xf4,0x00,0x00,0x00,0x00
 
 # GFX10: s_buffer_store_dwordx2 vcc, s[8:11], s0 ; encoding: [0x84,0x1a,0x64,0xf4,0x00,0x00,0x00,0x00]
 0x84,0x1a,0x64,0xf4,0x00,0x00,0x00,0x00
 
 # GFX10: s_buffer_store_dwordx4 s[4:7], s[12:15], s0 ; encoding: [0x06,0x01,0x68,0xf4,0x00,0x00,0x00,0x00]
 0x06,0x01,0x68,0xf4,0x00,0x00,0x00,0x00
 
-# GFX10: s_buffer_store_dwordx4 s[4:7], s[8:11], 0x0 ; encoding: [0x04,0x01,0x68,0xf4,0x00,0x00,0x00,0xfa]
+# GFX10: s_buffer_store_dwordx4 s[4:7], s[8:11], null ; encoding: [0x04,0x01,0x68,0xf4,0x00,0x00,0x00,0xfa]
 0x04,0x01,0x68,0xf4,0x00,0x00,0x00,0xfa
 
 # GFX10: s_buffer_store_dwordx4 s[4:7], s[8:11], 0x1234 glc dlc ; encoding: [0x04,0x41,0x69,0xf4,0x34,0x12,0x00,0xfa]
 0x04,0x41,0x69,0xf4,0x34,0x12,0x00,0xfa
 
 # GFX10: s_buffer_store_dwordx4 s[4:7], s[8:11], m0 ; encoding: [0x04,0x01,0x68,0xf4,0x00,0x00,0x00,0xf8]
 0x04,0x01,0x68,0xf4,0x00,0x00,0x00,0xf8
 

 0xd1,0xc1,0xa0,0xbf
 
 # GFX10: s_load_dword s101, s[2:3], s0           ; encoding: [0x41,0x19,0x00,0xf4,0x00,0x00,0x00,0x00]
 0x41,0x19,0x00,0xf4,0x00,0x00,0x00,0x00
 
 # GFX10: s_load_dword s5, s[100:101], s0         ; encoding: [0x72,0x01,0x00,0xf4,0x00,0x00,0x00,0x00]
 0x72,0x01,0x00,0xf4,0x00,0x00,0x00,0x00
 
-# GFX10: s_load_dword s5, s[2:3], 0x0            ; encoding: [0x41,0x01,0x00,0xf4,0x00,0x00,0x00,0xfa]
+# GFX10: s_load_dword s5, s[2:3], null           ; encoding: [0x41,0x01,0x00,0xf4,0x00,0x00,0x00,0xfa]
 0x41,0x01,0x00,0xf4,0x00,0x00,0x00,0xfa
 
 # GFX10: s_load_dword s5, s[2:3], 0x1234 glc dlc ; encoding: [0x41,0x41,0x01,0xf4,0x34,0x12,0x00,0xfa]
 0x41,0x41,0x01,0xf4,0x34,0x12,0x00,0xfa
 
+# GFX10: s_load_dword s5, s[2:3], s0 offset:0x12345 glc dlc ; encoding: [0x41,0x41,0x01,0xf4,0x45,0x23,0x01,0x00]
+0x41,0x41,0x01,0xf4,0x45,0x23,0x01,0x00
+
 # GFX10: s_load_dword s5, s[2:3], m0             ; encoding: [0x41,0x01,0x00,0xf4,0x00,0x00,0x00,0xf8]
 0x41,0x01,0x00,0xf4,0x00,0x00,0x00,0xf8
 
 # GFX10: s_load_dword s5, s[2:3], s0             ; encoding: [0x41,0x01,0x00,0xf4,0x00,0x00,0x00,0x00]
 0x41,0x01,0x00,0xf4,0x00,0x00,0x00,0x00
 
 # GFX10: s_load_dword s5, s[2:3], s0 dlc         ; encoding: [0x41,0x41,0x00,0xf4,0x00,0x00,0x00,0x00]
 0x41,0x41,0x00,0xf4,0x00,0x00,0x00,0x00

 0xc1,0x1a,0x00,0xf4,0x00,0x00,0x00,0x00
 
 # GFX10: s_load_dword vcc_lo, s[2:3], s0         ; encoding: [0x81,0x1a,0x00,0xf4,0x00,0x00,0x00,0x00]
 0x81,0x1a,0x00,0xf4,0x00,0x00,0x00,0x00
 
 # GFX10: s_load_dwordx16 s[20:35], s[100:101], s0 ; encoding: [0x32,0x05,0x10,0xf4,0x00,0x00,0x00,0x00]
 0x32,0x05,0x10,0xf4,0x00,0x00,0x00,0x00
 
-# GFX10: s_load_dwordx16 s[20:35], s[2:3], 0x0   ; encoding: [0x01,0x05,0x10,0xf4,0x00,0x00,0x00,0xfa]
+# GFX10: s_load_dwordx16 s[20:35], s[2:3], null  ; encoding: [0x01,0x05,0x10,0xf4,0x00,0x00,0x00,0xfa]
 0x01,0x05,0x10,0xf4,0x00,0x00,0x00,0xfa
 
 # GFX10: s_load_dwordx16 s[20:35], s[2:3], 0x1234 glc dlc ; encoding: [0x01,0x45,0x11,0xf4,0x34,0x12,0x00,0xfa]
 0x01,0x45,0x11,0xf4,0x34,0x12,0x00,0xfa
 
+# GFX10: s_load_dwordx16 s[20:35], s[2:3], s0 offset:0x12345 glc dlc ; encoding: [0x01,0x45,0x11,0xf4,0x45,0x23,0x01,0x00]
+0x01,0x45,0x11,0xf4,0x45,0x23,0x01,0x00
+
 # GFX10: s_load_dwordx16 s[20:35], s[2:3], m0    ; encoding: [0x01,0x05,0x10,0xf4,0x00,0x00,0x00,0xf8]
 0x01,0x05,0x10,0xf4,0x00,0x00,0x00,0xf8
 
 # GFX10: s_load_dwordx16 s[20:35], s[2:3], s0    ; encoding: [0x01,0x05,0x10,0xf4,0x00,0x00,0x00,0x00]
 0x01,0x05,0x10,0xf4,0x00,0x00,0x00,0x00
 
 # GFX10: s_load_dwordx16 s[20:35], s[2:3], s0 dlc ; encoding: [0x01,0x45,0x10,0xf4,0x00,0x00,0x00,0x00]
 0x01,0x45,0x10,0xf4,0x00,0x00,0x00,0x00

 0x01,0x15,0x10,0xf4,0x00,0x00,0x00,0x00
 
 # GFX10: s_load_dwordx2 s[100:101], s[2:3], s0   ; encoding: [0x01,0x19,0x04,0xf4,0x00,0x00,0x00,0x00]
 0x01,0x19,0x04,0xf4,0x00,0x00,0x00,0x00
 
 # GFX10: s_load_dwordx2 s[10:11], s[100:101], s0 ; encoding: [0xb2,0x02,0x04,0xf4,0x00,0x00,0x00,0x00]
 0xb2,0x02,0x04,0xf4,0x00,0x00,0x00,0x00
 
-# GFX10: s_load_dwordx2 s[10:11], s[2:3], 0x0    ; encoding: [0x81,0x02,0x04,0xf4,0x00,0x00,0x00,0xfa]
+# GFX10: s_load_dwordx2 s[10:11], s[2:3], null   ; encoding: [0x81,0x02,0x04,0xf4,0x00,0x00,0x00,0xfa]
 0x81,0x02,0x04,0xf4,0x00,0x00,0x00,0xfa
 
 # GFX10: s_load_dwordx2 s[10:11], s[2:3], 0x1234 glc dlc ; encoding: [0x81,0x42,0x05,0xf4,0x34,0x12,0x00,0xfa]
 0x81,0x42,0x05,0xf4,0x34,0x12,0x00,0xfa
 
+# GFX10: s_load_dwordx2 s[10:11], s[2:3], s0 offset:0x12345 glc dlc ; encoding: [0x81,0x42,0x05,0xf4,0x45,0x23,0x01,0x00]
+0x81,0x42,0x05,0xf4,0x45,0x23,0x01,0x00
+
 # GFX10: s_load_dwordx2 s[10:11], s[2:3], m0     ; encoding: [0x81,0x02,0x04,0xf4,0x00,0x00,0x00,0xf8]
 0x81,0x02,0x04,0xf4,0x00,0x00,0x00,0xf8
 
 # GFX10: s_load_dwordx2 s[10:11], s[2:3], s0     ; encoding: [0x81,0x02,0x04,0xf4,0x00,0x00,0x00,0x00]
 0x81,0x02,0x04,0xf4,0x00,0x00,0x00,0x00
 
 # GFX10: s_load_dwordx2 s[10:11], s[2:3], s0 dlc ; encoding: [0x81,0x42,0x04,0xf4,0x00,0x00,0x00,0x00]
 0x81,0x42,0x04,0xf4,0x00,0x00,0x00,0x00

 0x01,0x03,0x04,0xf4,0x00,0x00,0x00,0x00
 
 # GFX10: s_load_dwordx2 vcc, s[2:3], s0          ; encoding: [0x81,0x1a,0x04,0xf4,0x00,0x00,0x00,0x00]
 0x81,0x1a,0x04,0xf4,0x00,0x00,0x00,0x00
 
 # GFX10: s_load_dwordx4 s[20:23], s[100:101], s0 ; encoding: [0x32,0x05,0x08,0xf4,0x00,0x00,0x00,0x00]
 0x32,0x05,0x08,0xf4,0x00,0x00,0x00,0x00
 
-# GFX10: s_load_dwordx4 s[20:23], s[2:3], 0x0    ; encoding: [0x01,0x05,0x08,0xf4,0x00,0x00,0x00,0xfa]
+# GFX10: s_load_dwordx4 s[20:23], s[2:3], null   ; encoding: [0x01,0x05,0x08,0xf4,0x00,0x00,0x00,0xfa]
 0x01,0x05,0x08,0xf4,0x00,0x00,0x00,0xfa
 
 # GFX10: s_load_dwordx4 s[20:23], s[2:3], 0x1234 glc dlc ; encoding: [0x01,0x45,0x09,0xf4,0x34,0x12,0x00,0xfa]
 0x01,0x45,0x09,0xf4,0x34,0x12,0x00,0xfa
 
+# GFX10: s_load_dwordx4 s[20:23], s[2:3], s0 offset:0x12345 glc dlc ; encoding: [0x01,0x45,0x09,0xf4,0x45,0x23,0x01,0x00]
+0x01,0x45,0x09,0xf4,0x45,0x23,0x01,0x00
+
 # GFX10: s_load_dwordx4 s[20:23], s[2:3], m0     ; encoding: [0x01,0x05,0x08,0xf4,0x00,0x00,0x00,0xf8]
 0x01,0x05,0x08,0xf4,0x00,0x00,0x00,0xf8
 
 # GFX10: s_load_dwordx4 s[20:23], s[2:3], s0     ; encoding: [0x01,0x05,0x08,0xf4,0x00,0x00,0x00,0x00]
 0x01,0x05,0x08,0xf4,0x00,0x00,0x00,0x00
 
 # GFX10: s_load_dwordx4 s[20:23], s[2:3], s0 dlc ; encoding: [0x01,0x45,0x08,0xf4,0x00,0x00,0x00,0x00]
 0x01,0x45,0x08,0xf4,0x00,0x00,0x00,0x00

 0x01,0x06,0x08,0xf4,0x00,0x00,0x00,0x00
 
 # GFX10: s_load_dwordx4 s[96:99], s[2:3], s0     ; encoding: [0x01,0x18,0x08,0xf4,0x00,0x00,0x00,0x00]
 0x01,0x18,0x08,0xf4,0x00,0x00,0x00,0x00
 
 # GFX10: s_load_dwordx8 s[20:27], s[100:101], s0 ; encoding: [0x32,0x05,0x0c,0xf4,0x00,0x00,0x00,0x00]
 0x32,0x05,0x0c,0xf4,0x00,0x00,0x00,0x00
 
-# GFX10: s_load_dwordx8 s[20:27], s[2:3], 0x0    ; encoding: [0x01,0x05,0x0c,0xf4,0x00,0x00,0x00,0xfa]
+# GFX10: s_load_dwordx8 s[20:27], s[2:3], null   ; encoding: [0x01,0x05,0x0c,0xf4,0x00,0x00,0x00,0xfa]
 0x01,0x05,0x0c,0xf4,0x00,0x00,0x00,0xfa
 
 # GFX10: s_load_dwordx8 s[20:27], s[2:3], 0x1234 glc dlc ; encoding: [0x01,0x45,0x0d,0xf4,0x34,0x12,0x00,0xfa]
 0x01,0x45,0x0d,0xf4,0x34,0x12,0x00,0xfa
 
+# GFX10: s_load_dwordx8 s[20:27], s[2:3], s0 offset:0x12345 glc dlc ; encoding: [0x01,0x45,0x0d,0xf4,0x45,0x23,0x01,0x00]
+0x01,0x45,0x0d,0xf4,0x45,0x23,0x01,0x00
+
 # GFX10: s_load_dwordx8 s[20:27], s[2:3], m0     ; encoding: [0x01,0x05,0x0c,0xf4,0x00,0x00,0x00,0xf8]
 0x01,0x05,0x0c,0xf4,0x00,0x00,0x00,0xf8
 
 # GFX10: s_load_dwordx8 s[20:27], s[2:3], s0     ; encoding: [0x01,0x05,0x0c,0xf4,0x00,0x00,0x00,0x00]
 0x01,0x05,0x0c,0xf4,0x00,0x00,0x00,0x00
 
 # GFX10: s_load_dwordx8 s[20:27], s[2:3], s0 dlc ; encoding: [0x01,0x45,0x0c,0xf4,0x00,0x00,0x00,0x00]
 0x01,0x45,0x0c,0xf4,0x00,0x00,0x00,0x00

 0x34,0x12,0x8e,0xbf
 
 # GFX10: s_sleep 0xc1d1                          ; encoding: [0xd1,0xc1,0x8e,0xbf]
 0xd1,0xc1,0x8e,0xbf
 
 # GFX10: s_store_dword s1, s[100:101], s0        ; encoding: [0x72,0x00,0x40,0xf4,0x00,0x00,0x00,0x00]
 0x72,0x00,0x40,0xf4,0x00,0x00,0x00,0x00
 
-# GFX10: s_store_dword s1, s[4:5], 0x0           ; encoding: [0x42,0x00,0x40,0xf4,0x00,0x00,0x00,0xfa]
+# GFX10: s_store_dword s1, s[4:5], null          ; encoding: [0x42,0x00,0x40,0xf4,0x00,0x00,0x00,0xfa]
 0x42,0x00,0x40,0xf4,0x00,0x00,0x00,0xfa
 
 # GFX10: s_store_dword s1, s[4:5], 0x1234 glc dlc ; encoding: [0x42,0x40,0x41,0xf4,0x34,0x12,0x00,0xfa]
 0x42,0x40,0x41,0xf4,0x34,0x12,0x00,0xfa
 
 # GFX10: s_store_dword s1, s[4:5], m0            ; encoding: [0x42,0x00,0x40,0xf4,0x00,0x00,0x00,0xf8]
 0x42,0x00,0x40,0xf4,0x00,0x00,0x00,0xf8
 

 0x82,0x1a,0x40,0xf4,0x00,0x00,0x00,0x00
 
 # GFX10: s_store_dwordx2 s[100:101], s[4:5], s0  ; encoding: [0x02,0x19,0x44,0xf4,0x00,0x00,0x00,0x00]
 0x02,0x19,0x44,0xf4,0x00,0x00,0x00,0x00
 
 # GFX10: s_store_dwordx2 s[2:3], s[100:101], s0  ; encoding: [0xb2,0x00,0x44,0xf4,0x00,0x00,0x00,0x00]
 0xb2,0x00,0x44,0xf4,0x00,0x00,0x00,0x00
 
-# GFX10: s_store_dwordx2 s[2:3], s[4:5], 0x0     ; encoding: [0x82,0x00,0x44,0xf4,0x00,0x00,0x00,0xfa]
+# GFX10: s_store_dwordx2 s[2:3], s[4:5], null    ; encoding: [0x82,0x00,0x44,0xf4,0x00,0x00,0x00,0xfa]
 0x82,0x00,0x44,0xf4,0x00,0x00,0x00,0xfa
 
 # GFX10: s_store_dwordx2 s[2:3], s[4:5], 0x1234 glc dlc ; encoding: [0x82,0x40,0x45,0xf4,0x34,0x12,0x00,0xfa]
 0x82,0x40,0x45,0xf4,0x34,0x12,0x00,0xfa
 
 # GFX10: s_store_dwordx2 s[2:3], s[4:5], m0      ; encoding: [0x82,0x00,0x44,0xf4,0x00,0x00,0x00,0xf8]
 0x82,0x00,0x44,0xf4,0x00,0x00,0x00,0xf8
 

 0x02,0x01,0x44,0xf4,0x00,0x00,0x00,0x00
 
 # GFX10: s_store_dwordx2 vcc, s[4:5], s0         ; encoding: [0x82,0x1a,0x44,0xf4,0x00,0x00,0x00,0x00]
 0x82,0x1a,0x44,0xf4,0x00,0x00,0x00,0x00
 
 # GFX10: s_store_dwordx4 s[4:7], s[100:101], s0  ; encoding: [0x32,0x01,0x48,0xf4,0x00,0x00,0x00,0x00]
 0x32,0x01,0x48,0xf4,0x00,0x00,0x00,0x00
 
-# GFX10: s_store_dwordx4 s[4:7], s[4:5], 0x0     ; encoding: [0x02,0x01,0x48,0xf4,0x00,0x00,0x00,0xfa]
+# GFX10: s_store_dwordx4 s[4:7], s[4:5], null    ; encoding: [0x02,0x01,0x48,0xf4,0x00,0x00,0x00,0xfa]
 0x02,0x01,0x48,0xf4,0x00,0x00,0x00,0xfa
 
 # GFX10: s_store_dwordx4 s[4:7], s[4:5], 0x1234 glc dlc ; encoding: [0x02,0x41,0x49,0xf4,0x34,0x12,0x00,0xfa]
 0x02,0x41,0x49,0xf4,0x34,0x12,0x00,0xfa
 
 # GFX10: s_store_dwordx4 s[4:7], s[4:5], m0      ; encoding: [0x02,0x01,0x48,0xf4,0x00,0x00,0x00,0xf8]
 0x02,0x01,0x48,0xf4,0x00,0x00,0x00,0xf8