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Differential D124134

[libc] Use correct mnemonic for arm64_32 architecture
ClosedPublic

Authored by ddcc on Apr 20 2022, 5:32 PM.

Details

Reviewers
sivachandra
lntue
gchatelet
avieira
michaelrj
Commits
rGe8572aca0c42: [libc] Use correct mnemonic for arm64_32 architecture
Summary

arm64_32 is an ILP32 platform

Diff Detail

Event Timeline

ddcc created this revision.Apr 20 2022, 5:32 PM
Herald added projects: Restricted Project, Restricted Project. · View Herald TranscriptApr 20 2022, 5:32 PM
Herald added subscribers: ecnelises, tschuett, kristof.beyls. · View Herald Transcript
ddcc requested review of this revision.Apr 20 2022, 5:32 PM
sivachandra added a reviewer: gchatelet.Apr 20 2022, 5:35 PM
Harbormaster completed remote builds in B160559: Diff 424062.Apr 20 2022, 5:40 PM
gchatelet added a reviewer: avieira.Apr 21 2022, 1:03 AM

@avieira can you approve this change?

michaelrj accepted this revision.Apr 21 2022, 11:17 AM
michaelrj added a subscriber: michaelrj.

LGTM

This revision is now accepted and ready to land.Apr 21 2022, 11:17 AM
Closed by commit rGe8572aca0c42: [libc] Use correct mnemonic for arm64_32 architecture (authored by ddcc). · Explain WhyApr 21 2022, 3:13 PM
This revision was automatically updated to reflect the committed changes.
ddcc added a commit: rGe8572aca0c42: [libc] Use correct mnemonic for arm64_32 architecture.

Revision Contents

PathSize
libc/
src/
string/
memory_utils/
4 lines

Diff 424307

libc/src/string/memory_utils/elements_aarch64.h

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using _3 = __llvm_libc::scalar::_3; using _3 = __llvm_libc::scalar::_3;
using _4 = __llvm_libc::scalar::_4; using _4 = __llvm_libc::scalar::_4;
using _32 = Chained<_16, _16>; using _32 = Chained<_16, _16>;
using _64 = Chained<_32, _32>; using _64 = Chained<_32, _32>;
struct ZVA { struct ZVA {
static constexpr size_t SIZE = 64; static constexpr size_t SIZE = 64;
static void splat_set(char *dst, const unsigned char value) { static void splat_set(char *dst, const unsigned char value) {
#if __SIZEOF_POINTER__ == 4
asm("dc zva, %w[dst]" : : [dst] "r"(dst) : "memory");
#else
asm("dc zva, %[dst]" : : [dst] "r"(dst) : "memory"); asm("dc zva, %[dst]" : : [dst] "r"(dst) : "memory");
#endif
} }
}; };
inline static bool AArch64ZVA(char *dst, size_t count) { inline static bool AArch64ZVA(char *dst, size_t count) {
uint64_t zva_val; uint64_t zva_val;
asm("mrs %[zva_val], dczid_el0" : [zva_val] "=r"(zva_val)); asm("mrs %[zva_val], dczid_el0" : [zva_val] "=r"(zva_val));
if ((zva_val & 31) != 4) if ((zva_val & 31) != 4)
return false; return false;
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