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Differential D124087

[AMDGPU][GFX90A+] Disabled ds_ordered_count and exp
ClosedPublic

Authored by dp on Apr 20 2022, 4:58 AM.

Details

Reviewers
foad
rampitec
Commits
rGb4231ac4bef6: [AMDGPU][GFX90A+] Disabled ds_ordered_count and exp
Summary

GFX9 SPG explicitly states that these instructions are not supported:

MI200 cannot execute:

  • GDS ops – MI200 supports only GWS (not ordered count)
  • Exports

These opcodes are not supported by SP3 either.

Diff Detail

Event Timeline

dp created this revision.Apr 20 2022, 4:58 AM
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dp requested review of this revision.Apr 20 2022, 4:58 AM
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Harbormaster completed remote builds in B160432: Diff 423871.Apr 20 2022, 6:23 AM
rampitec accepted this revision.Apr 20 2022, 12:03 PM
This revision is now accepted and ready to land.Apr 20 2022, 12:03 PM
This revision was landed with ongoing or failed builds.Apr 21 2022, 3:17 AM
Closed by commit rGb4231ac4bef6: [AMDGPU][GFX90A+] Disabled ds_ordered_count and exp (authored by dp). · Explain Why
This revision was automatically updated to reflect the committed changes.
dp added a commit: rGb4231ac4bef6: [AMDGPU][GFX90A+] Disabled ds_ordered_count and exp.

Revision Contents

PathSize
llvm/
lib/
Target/
AMDGPU/
2 lines
3 lines
test/
MC/
AMDGPU/
6 lines
24 lines
6 lines
Disassembler/
AMDGPU/
18 lines

Diff 424137

llvm/lib/Target/AMDGPU/DSInstructions.td

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let SubtargetPredicate = HasDSAddTid in { let SubtargetPredicate = HasDSAddTid in {
def DS_READ_ADDTID_B32 : DS_0A_RET<"ds_read_addtid_b32">; def DS_READ_ADDTID_B32 : DS_0A_RET<"ds_read_addtid_b32">;
} }
} // End mayStore = 0 } // End mayStore = 0
def DS_CONSUME : DS_0A_RET<"ds_consume">; def DS_CONSUME : DS_0A_RET<"ds_consume">;
def DS_APPEND : DS_0A_RET<"ds_append">; def DS_APPEND : DS_0A_RET<"ds_append">;
let SubtargetPredicate = isNotGFX90APlus in
def DS_ORDERED_COUNT : DS_1A_RET_GDS<"ds_ordered_count">; def DS_ORDERED_COUNT : DS_1A_RET_GDS<"ds_ordered_count">;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Instruction definitions for CI and newer. // Instruction definitions for CI and newer.
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
let SubtargetPredicate = isGFX7Plus in { let SubtargetPredicate = isGFX7Plus in {
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llvm/lib/Target/AMDGPU/EXPInstructions.td

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} }
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// EXP Instructions // EXP Instructions
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Split EXP instruction into EXP and EXP_DONE so we can set // Split EXP instruction into EXP and EXP_DONE so we can set
// mayLoad for done=1. // mayLoad for done=1.
let SubtargetPredicate = isNotGFX90APlus in {
def EXP : EXP_Pseudo<0>; def EXP : EXP_Pseudo<0>;
def EXP_DONE : EXP_Pseudo<1>; def EXP_DONE : EXP_Pseudo<1>;
} // let SubtargetPredicate = isNotGFX90APlus
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// SI // SI
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
class EXP_Real_si<bit _done, string pseudo> class EXP_Real_si<bit _done, string pseudo>
: EXP_Real<_done, pseudo, SIEncodingFamily.SI>, EXPe { : EXP_Real<_done, pseudo, SIEncodingFamily.SI>, EXPe {
let AssemblerPredicate = isGFX6GFX7; let AssemblerPredicate = isGFX6GFX7;
let DecoderNamespace = "GFX6GFX7"; let DecoderNamespace = "GFX6GFX7";
let done = _done; let done = _done;
} }
def EXP_si : EXP_Real_si<0, "EXP">; def EXP_si : EXP_Real_si<0, "EXP">;
def EXP_DONE_si : EXP_Real_si<1, "EXP_DONE">; def EXP_DONE_si : EXP_Real_si<1, "EXP_DONE">;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// VI // VI
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
class EXP_Real_vi<bit _done, string pseudo> class EXP_Real_vi<bit _done, string pseudo>
: EXP_Real<_done, pseudo, SIEncodingFamily.VI>, EXPe_vi { : EXP_Real<_done, pseudo, SIEncodingFamily.VI>, EXPe_vi {
let AssemblerPredicate = isGFX8GFX9; let AssemblerPredicate = isGFX8GFX9;
let SubtargetPredicate = isNotGFX90APlus;
let DecoderNamespace = "GFX8"; let DecoderNamespace = "GFX8";
let done = _done; let done = _done;
} }
def EXP_vi : EXP_Real_vi<0, "EXP">; def EXP_vi : EXP_Real_vi<0, "EXP">;
def EXP_DONE_vi : EXP_Real_vi<1, "EXP_DONE">; def EXP_DONE_vi : EXP_Real_vi<1, "EXP_DONE">;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
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llvm/test/MC/AMDGPU/gfx90a_err.s

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ds_gws_sema_br v255 offset:65535 gds ds_gws_sema_br v255 offset:65535 gds
// GFX90A: error: vgpr must be even aligned // GFX90A: error: vgpr must be even aligned
ds_gws_barrier a3 offset:4 gds ds_gws_barrier a3 offset:4 gds
// GFX90A: error: vgpr must be even aligned // GFX90A: error: vgpr must be even aligned
ds_gws_barrier a255 offset:4 gds ds_gws_barrier a255 offset:4 gds
// GFX90A: error: vgpr must be even aligned // GFX90A: error: vgpr must be even aligned
ds_ordered_count v5, v1 offset:65535 gds
// GFX90A: error: instruction not supported on this GPU
exp pos0 v3, v2, v1, v0
// GFX90A: error: instruction not supported on this GPU

llvm/test/MC/AMDGPU/gfx90a_ldst_acc.s

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
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// GFX90A: ds_append a5 offset:4 ; encoding: [0x04,0x00,0x7c,0xdb,0x00,0x00,0x00,0x05] // GFX90A: ds_append a5 offset:4 ; encoding: [0x04,0x00,0x7c,0xdb,0x00,0x00,0x00,0x05]
// NOT-GFX90A: error: invalid register class: agpr loads and stores not supported on this GPU // NOT-GFX90A: error: invalid register class: agpr loads and stores not supported on this GPU
ds_append a5 offset:4 ds_append a5 offset:4
// GFX90A: ds_append a5 offset:65535 gds ; encoding: [0xff,0xff,0x7d,0xdb,0x00,0x00,0x00,0x05] // GFX90A: ds_append a5 offset:65535 gds ; encoding: [0xff,0xff,0x7d,0xdb,0x00,0x00,0x00,0x05]
// NOT-GFX90A: error: invalid register class: agpr loads and stores not supported on this GPU // NOT-GFX90A: error: invalid register class: agpr loads and stores not supported on this GPU
ds_append a5 offset:65535 gds ds_append a5 offset:65535 gds
// GFX90A: ds_ordered_count a5, v1 offset:65535 gds ; encoding: [0xff,0xff,0x7f,0xdb,0x01,0x00,0x00,0x05]
// NOT-GFX90A: error: invalid register class: agpr loads and stores not supported on this GPU
ds_ordered_count a5, v1 offset:65535 gds
// GFX90A: ds_ordered_count a255, v1 offset:65535 gds ; encoding: [0xff,0xff,0x7f,0xdb,0x01,0x00,0x00,0xff]
// NOT-GFX90A: error: invalid register class: agpr loads and stores not supported on this GPU
ds_ordered_count a255, v1 offset:65535 gds
// GFX90A: ds_ordered_count a5, v255 offset:65535 gds ; encoding: [0xff,0xff,0x7f,0xdb,0xff,0x00,0x00,0x05]
// NOT-GFX90A: error: invalid register class: agpr loads and stores not supported on this GPU
ds_ordered_count a5, v255 offset:65535 gds
// GFX90A: ds_ordered_count a5, v1 gds ; encoding: [0x00,0x00,0x7f,0xdb,0x01,0x00,0x00,0x05]
// NOT-GFX90A: error: invalid register class: agpr loads and stores not supported on this GPU
ds_ordered_count a5, v1 gds
// GFX90A: ds_ordered_count a5, v1 gds ; encoding: [0x00,0x00,0x7f,0xdb,0x01,0x00,0x00,0x05]
// NOT-GFX90A: error: invalid register class: agpr loads and stores not supported on this GPU
ds_ordered_count a5, v1 gds
// GFX90A: ds_ordered_count a5, v1 offset:4 gds ; encoding: [0x04,0x00,0x7f,0xdb,0x01,0x00,0x00,0x05]
// NOT-GFX90A: error: invalid register class: agpr loads and stores not supported on this GPU
ds_ordered_count a5, v1 offset:4 gds
// GFX90A: ds_write_b96 v1, a[2:4] offset:65535 ; encoding: [0xff,0xff,0xbc,0xdb,0x01,0x02,0x00,0x00] // GFX90A: ds_write_b96 v1, a[2:4] offset:65535 ; encoding: [0xff,0xff,0xbc,0xdb,0x01,0x02,0x00,0x00]
// NOT-GFX90A: error: invalid register class: agpr loads and stores not supported on this GPU // NOT-GFX90A: error: invalid register class: agpr loads and stores not supported on this GPU
ds_write_b96 v1, a[2:4] offset:65535 ds_write_b96 v1, a[2:4] offset:65535
// GFX90A: ds_write_b96 v255, a[2:4] offset:65535 ; encoding: [0xff,0xff,0xbc,0xdb,0xff,0x02,0x00,0x00] // GFX90A: ds_write_b96 v255, a[2:4] offset:65535 ; encoding: [0xff,0xff,0xbc,0xdb,0xff,0x02,0x00,0x00]
// NOT-GFX90A: error: invalid register class: agpr loads and stores not supported on this GPU // NOT-GFX90A: error: invalid register class: agpr loads and stores not supported on this GPU
ds_write_b96 v255, a[2:4] offset:65535 ds_write_b96 v255, a[2:4] offset:65535
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llvm/test/MC/AMDGPU/gfx940_err.s

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s_getreg_b32 s1, hwreg(HW_REG_HW_ID1) s_getreg_b32 s1, hwreg(HW_REG_HW_ID1)
// GFX940: error: specified hardware register is not supported on this GPU // GFX940: error: specified hardware register is not supported on this GPU
s_getreg_b32 s1, hwreg(HW_REG_HW_ID2) s_getreg_b32 s1, hwreg(HW_REG_HW_ID2)
// GFX940: error: specified hardware register is not supported on this GPU // GFX940: error: specified hardware register is not supported on this GPU
s_getreg_b32 s1, hwreg(HW_REG_POPS_PACKER) s_getreg_b32 s1, hwreg(HW_REG_POPS_PACKER)
// GFX940: error: specified hardware register is not supported on this GPU // GFX940: error: specified hardware register is not supported on this GPU
ds_ordered_count v5, v1 offset:65535 gds
// GFX940: error: instruction not supported on this GPU
exp pos0 v3, v2, v1, v0
// GFX940: error: instruction not supported on this GPU

llvm/test/MC/Disassembler/AMDGPU/gfx90a_ldst_acc.txt

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0x00,0x00,0x7c,0xdb,0x00,0x00,0x00,0x05 0x00,0x00,0x7c,0xdb,0x00,0x00,0x00,0x05
# GFX90A: ds_append a5 offset:4 ; encoding: [0x04,0x00,0x7c,0xdb,0x00,0x00,0x00,0x05] # GFX90A: ds_append a5 offset:4 ; encoding: [0x04,0x00,0x7c,0xdb,0x00,0x00,0x00,0x05]
0x04,0x00,0x7c,0xdb,0x00,0x00,0x00,0x05 0x04,0x00,0x7c,0xdb,0x00,0x00,0x00,0x05
# GFX90A: ds_append a5 offset:65535 gds ; encoding: [0xff,0xff,0x7d,0xdb,0x00,0x00,0x00,0x05] # GFX90A: ds_append a5 offset:65535 gds ; encoding: [0xff,0xff,0x7d,0xdb,0x00,0x00,0x00,0x05]
0xff,0xff,0x7d,0xdb,0x00,0x00,0x00,0x05 0xff,0xff,0x7d,0xdb,0x00,0x00,0x00,0x05
# GFX90A: ds_ordered_count a5, v1 offset:65535 gds ; encoding: [0xff,0xff,0x7f,0xdb,0x01,0x00,0x00,0x05]
0xff,0xff,0x7f,0xdb,0x01,0x00,0x00,0x05
# GFX90A: ds_ordered_count a255, v1 offset:65535 gds ; encoding: [0xff,0xff,0x7f,0xdb,0x01,0x00,0x00,0xff]
0xff,0xff,0x7f,0xdb,0x01,0x00,0x00,0xff
# GFX90A: ds_ordered_count a5, v255 offset:65535 gds ; encoding: [0xff,0xff,0x7f,0xdb,0xff,0x00,0x00,0x05]
0xff,0xff,0x7f,0xdb,0xff,0x00,0x00,0x05
# GFX90A: ds_ordered_count a5, v1 gds ; encoding: [0x00,0x00,0x7f,0xdb,0x01,0x00,0x00,0x05]
0x00,0x00,0x7f,0xdb,0x01,0x00,0x00,0x05
# GFX90A: ds_ordered_count a5, v1 gds ; encoding: [0x00,0x00,0x7f,0xdb,0x01,0x00,0x00,0x05]
0x00,0x00,0x7f,0xdb,0x01,0x00,0x00,0x05
# GFX90A: ds_ordered_count a5, v1 offset:4 gds ; encoding: [0x04,0x00,0x7f,0xdb,0x01,0x00,0x00,0x05]
0x04,0x00,0x7f,0xdb,0x01,0x00,0x00,0x05
# GFX90A: ds_write_b96 v1, a[2:4] offset:65535 ; encoding: [0xff,0xff,0xbc,0xdb,0x01,0x02,0x00,0x00] # GFX90A: ds_write_b96 v1, a[2:4] offset:65535 ; encoding: [0xff,0xff,0xbc,0xdb,0x01,0x02,0x00,0x00]
0xff,0xff,0xbc,0xdb,0x01,0x02,0x00,0x00 0xff,0xff,0xbc,0xdb,0x01,0x02,0x00,0x00
# GFX90A: ds_write_b96 v255, a[2:4] offset:65535 ; encoding: [0xff,0xff,0xbc,0xdb,0xff,0x02,0x00,0x00] # GFX90A: ds_write_b96 v255, a[2:4] offset:65535 ; encoding: [0xff,0xff,0xbc,0xdb,0xff,0x02,0x00,0x00]
0xff,0xff,0xbc,0xdb,0xff,0x02,0x00,0x00 0xff,0xff,0xbc,0xdb,0xff,0x02,0x00,0x00
# GFX90A: ds_write_b96 v1, a[252:254] offset:65535 ; encoding: [0xff,0xff,0xbc,0xdb,0x01,0xfc,0x00,0x00] # GFX90A: ds_write_b96 v1, a[252:254] offset:65535 ; encoding: [0xff,0xff,0xbc,0xdb,0x01,0xfc,0x00,0x00]
0xff,0xff,0xbc,0xdb,0x01,0xfc,0x00,0x00 0xff,0xff,0xbc,0xdb,0x01,0xfc,0x00,0x00
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