[mlir][LLVMIR] Add vector predication type cast intrinsic ops.

[jacquesguan]

Summary

This patch adds vector predication type cast intrinsic ops.

mlir/include/mlir/Dialect/LLVMIR/LLVMIntrinsicOps.td

 
 class LLVM_VPReductionF<string mnem> : LLVM_VPReductionBase<mnem, AnyFloat>;
 
 class LLVM_VPSelectBase<string mnem>
     : LLVM_OneResultIntrOp<"vp." # mnem, [], [1], [NoSideEffect]>,
       Arguments<(ins LLVM_VectorOf<I1>:$cond, LLVM_AnyVector:$true_val,
                      LLVM_AnyVector:$false_val, I32:$evl)>;
 
+class LLVM_VPCastBase<string mnem, Type element>
+    : LLVM_OneResultIntrOp<"vp." # mnem, [0], [0], [NoSideEffect]>,
+      Arguments<(ins LLVM_VectorOf<element>:$src,
+                     LLVM_VectorOf<I1>:$mask, I32:$evl)>;
+
+class LLVM_VPCastI<string mnem>   : LLVM_VPCastBase<mnem, AnyInteger>;
+
+class LLVM_VPCastF<string mnem>   : LLVM_VPCastBase<mnem, AnyFloat>;
+
+class LLVM_VPCastPtr<string mnem> : LLVM_VPCastBase<mnem, LLVM_AnyPointer>;
+
 // Integer Binary
 def LLVM_VPAddOp  : LLVM_VPBinaryI<"add">;
 def LLVM_VPSubOp  : LLVM_VPBinaryI<"sub">;
 def LLVM_VPMulOp  : LLVM_VPBinaryI<"mul">;
 def LLVM_VPSDivOp : LLVM_VPBinaryI<"sdiv">;
 def LLVM_VPUDivOp : LLVM_VPBinaryI<"udiv">;
 def LLVM_VPSRemOp : LLVM_VPBinaryI<"srem">;
 def LLVM_VPURemOp : LLVM_VPBinaryI<"urem">;
: LLVM_OneResultIntrOp<"experimental.vp.strided.load", [0], [0, 1], []>,
       Arguments<(ins LLVM_AnyPointer:$ptr, AnyInteger:$stride,
                      LLVM_VectorOf<I1>:$mask, I32:$evl)>;
 
 def LLVM_VPStridedStoreOp
     : LLVM_ZeroResultIntrOp<"experimental.vp.strided.store",[0, 1, 2], []>,
       Arguments<(ins LLVM_AnyVector:$val, LLVM_AnyPointer:$ptr,
                      AnyInteger:$stride, LLVM_VectorOf<I1>:$mask, I32:$evl)>;
 
+def LLVM_VPTruncOp : LLVM_VPCastI<"trunc">;
+def LLVM_VPZExtOp  : LLVM_VPCastI<"zext">;
+def LLVM_VPSExtOp  : LLVM_VPCastI<"sext">;
+
+def LLVM_VPFPTruncOp : LLVM_VPCastF<"fptrunc">;
+def LLVM_VPFPExtOp   : LLVM_VPCastF<"fpext">;
+
+def LLVM_VPFPToUIOp : LLVM_VPCastF<"fptoui">;
+def LLVM_VPFPToSIOp : LLVM_VPCastF<"fptosi">;
+
+def LLVM_VPUIToFPOp : LLVM_VPCastI<"uitofp">;
+def LLVM_VPSIToFPOp : LLVM_VPCastI<"sitofp">;
+
+def LLVM_VPPtrToIntOp : LLVM_VPCastPtr<"ptrtoint">;
+def LLVM_VPIntToPtrOp : LLVM_VPCastI<"inttoptr">;
+
 #endif // LLVM_INTRINSIC_OPS
 No newline at end of file

mlir/test/Target/LLVMIR/llvmir-intrinsics.mlir

llvm.func @stack_restore(%arg0: !llvm.ptr<i8>) {
   // CHECK: call void @llvm.stackrestore
   llvm.intr.stackrestore %arg0
   llvm.return
 }
 
 // CHECK-LABEL: @vector_predication_intrinsics
 llvm.func @vector_predication_intrinsics(%A: vector<8xi32>, %B: vector<8xi32>,
                                          %C: vector<8xf32>, %D: vector<8xf32>,
+                                         %E: vector<8xi64>, %F: vector<8xf64>,
+                                         %G: !llvm.vec<8 x !llvm.ptr<i32>>,
                                          %i: i32, %f: f32,
                                          %iptr : !llvm.ptr<i32>,
                                          %fptr : !llvm.ptr<f32>,
                                          %mask: vector<8xi1>, %evl: i32) {
   // CHECK: call <8 x i32> @llvm.vp.add.v8i32
   "llvm.intr.vp.add" (%A, %B, %mask, %evl) :
          (vector<8xi32>, vector<8xi32>, vector<8xi1>, i32) -> vector<8xi32>
   // CHECK: call <8 x i32> @llvm.vp.sub.v8i32
"llvm.intr.vp.load" (%iptr, %mask, %evl) :
          (!llvm.ptr<i32>, vector<8xi1>, i32) -> vector<8xi32>
   // CHECK: call void @llvm.experimental.vp.strided.store.v8i32.p0i32.i32
   "llvm.intr.experimental.vp.strided.store" (%A, %iptr, %i, %mask, %evl) : 
          (vector<8xi32>, !llvm.ptr<i32>, i32, vector<8xi1>, i32) -> ()
   // CHECK: call <8 x i32> @llvm.experimental.vp.strided.load.v8i32.p0i32.i32
   "llvm.intr.experimental.vp.strided.load" (%iptr, %i, %mask, %evl) :
          (!llvm.ptr<i32>, i32, vector<8xi1>, i32) -> vector<8xi32>
 
+  // CHECK: call <8 x i32> @llvm.vp.trunc.v8i32.v8i64
+  "llvm.intr.vp.trunc" (%E, %mask, %evl) :
+         (vector<8xi64>, vector<8xi1>, i32) -> vector<8xi32>
+  // CHECK: call <8 x i64> @llvm.vp.zext.v8i64.v8i32
+  "llvm.intr.vp.zext" (%A, %mask, %evl) :
+         (vector<8xi32>, vector<8xi1>, i32) -> vector<8xi64>
+  // CHECK: call <8 x i64> @llvm.vp.sext.v8i64.v8i32
+  "llvm.intr.vp.sext" (%A, %mask, %evl) :
+         (vector<8xi32>, vector<8xi1>, i32) -> vector<8xi64>
+
+  // CHECK: call <8 x float> @llvm.vp.fptrunc.v8f32.v8f64
+  "llvm.intr.vp.fptrunc" (%F, %mask, %evl) :
+         (vector<8xf64>, vector<8xi1>, i32) -> vector<8xf32>
+  // CHECK: call <8 x double> @llvm.vp.fpext.v8f64.v8f32
+  "llvm.intr.vp.fpext" (%C, %mask, %evl) :
+         (vector<8xf32>, vector<8xi1>, i32) -> vector<8xf64>
+
+  // CHECK: call <8 x i64> @llvm.vp.fptoui.v8i64.v8f64
+  "llvm.intr.vp.fptoui" (%F, %mask, %evl) :
+         (vector<8xf64>, vector<8xi1>, i32) -> vector<8xi64>
+  // CHECK: call <8 x i64> @llvm.vp.fptosi.v8i64.v8f64
+  "llvm.intr.vp.fptosi" (%F, %mask, %evl) :
+         (vector<8xf64>, vector<8xi1>, i32) -> vector<8xi64>
+
+  // CHECK: call <8 x i64> @llvm.vp.ptrtoint.v8i64.v8p0i32
+  "llvm.intr.vp.ptrtoint" (%G, %mask, %evl) :
+         (!llvm.vec<8 x !llvm.ptr<i32>>, vector<8xi1>, i32) -> vector<8xi64>
+  // CHECK: call <8 x i32*> @llvm.vp.inttoptr.v8p0i32.v8i64
+  "llvm.intr.vp.inttoptr" (%E, %mask, %evl) :
+         (vector<8xi64>, vector<8xi1>, i32) -> !llvm.vec<8 x !llvm.ptr<i32>>
   llvm.return
 }
 
 // Check that intrinsics are declared with appropriate types.
 // CHECK-DAG: declare float @llvm.fma.f32(float, float, float)
 // CHECK-DAG: declare <8 x float> @llvm.fma.v8f32(<8 x float>, <8 x float>, <8 x float>) #0
 // CHECK-DAG: declare float @llvm.fmuladd.f32(float, float, float)
 // CHECK-DAG: declare <8 x float> @llvm.fmuladd.v8f32(<8 x float>, <8 x float>, <8 x float>) #0

 // CHECK-DAG: declare float @llvm.vp.reduce.fadd.v8f32(float, <8 x float>, <8 x i1>, i32) #0
 // CHECK-DAG: declare float @llvm.vp.reduce.fmul.v8f32(float, <8 x float>, <8 x i1>, i32) #0
 // CHECK-DAG: declare float @llvm.vp.reduce.fmax.v8f32(float, <8 x float>, <8 x i1>, i32) #0
 // CHECK-DAG: declare float @llvm.vp.reduce.fmin.v8f32(float, <8 x float>, <8 x i1>, i32) #0
 // CHECK-DAG: declare <8 x i32> @llvm.vp.select.v8i32(<8 x i1>, <8 x i32>, <8 x i32>, i32) #12
 // CHECK-DAG: declare <8 x i32> @llvm.vp.merge.v8i32(<8 x i1>, <8 x i32>, <8 x i32>, i32) #12
 // CHECK-DAG: declare void @llvm.experimental.vp.strided.store.v8i32.p0i32.i32(<8 x i32>, i32* nocapture, i32, <8 x i1>, i32) #4
 // CHECK-DAG: declare <8 x i32> @llvm.experimental.vp.strided.load.v8i32.p0i32.i32(i32* nocapture, i32, <8 x i1>, i32) #3
+// CHECK-DAG: declare <8 x i32> @llvm.vp.trunc.v8i32.v8i64(<8 x i64>, <8 x i1>, i32) #12
+// CHECK-DAG: declare <8 x i64> @llvm.vp.zext.v8i64.v8i32(<8 x i32>, <8 x i1>, i32) #12
+// CHECK-DAG: declare <8 x i64> @llvm.vp.sext.v8i64.v8i32(<8 x i32>, <8 x i1>, i32) #12
+// CHECK-DAG: declare <8 x float> @llvm.vp.fptrunc.v8f32.v8f64(<8 x double>, <8 x i1>, i32) #12
+// CHECK-DAG: declare <8 x double> @llvm.vp.fpext.v8f64.v8f32(<8 x float>, <8 x i1>, i32) #12
+// CHECK-DAG: declare <8 x i64> @llvm.vp.fptoui.v8i64.v8f64(<8 x double>, <8 x i1>, i32) #12
+// CHECK-DAG: declare <8 x i64> @llvm.vp.fptosi.v8i64.v8f64(<8 x double>, <8 x i1>, i32) #12
+// CHECK-DAG: declare <8 x i64> @llvm.vp.ptrtoint.v8i64.v8p0i32(<8 x i32*>, <8 x i1>, i32) #12
+// CHECK-DAG: declare <8 x i32*> @llvm.vp.inttoptr.v8p0i32.v8i64(<8 x i64>, <8 x i1>, i32) #12