AArch64/GlobalISel: Stop using legal s1 values

[arsenm]

Summary

As far as I can tell treating s1 values as legal makes no sense. There
are no allocatable 1-bit registers. SelectionDAG legalizes the usual
set of boolean operations to 32-bits, and this should do the
same. This avoids some special case handling in the selector of s1
values, and some extra code to look through truncates.

This makes some code worse at -O0, since nothing cleans up the and 1
the artifact combiner inserts. We could probably add some
non-essential combines or teach the artifact combiner to elide
intermediates betweeen boolean uses and defs.

[paquette]

I think this is a good cleanup. Even if we get some slightly worse codegen at -O0, it simplifies the selector + legalizer. LGTM

[arsenm]

Remove special case copy handling for s1 in selector too

[arsenm]

02769f2b3fdebb5066d7a973b171d2873a804560

llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp

getRegClassesForCopy(MachineInstr &I, const TargetInstrInfo &TII,
                      const RegisterBankInfo &RBI) {
   Register DstReg = I.getOperand(0).getReg();
   Register SrcReg = I.getOperand(1).getReg();
   const RegisterBank &DstRegBank = *RBI.getRegBank(DstReg, MRI, TRI);
   const RegisterBank &SrcRegBank = *RBI.getRegBank(SrcReg, MRI, TRI);
   unsigned DstSize = RBI.getSizeInBits(DstReg, MRI, TRI);
   unsigned SrcSize = RBI.getSizeInBits(SrcReg, MRI, TRI);
 
-  // Special casing for cross-bank copies of s1s. We can technically represent
-  // a 1-bit value with any size of register. The minimum size for a GPR is 32
-  // bits. So, we need to put the FPR on 32 bits as well.
-  //
-  // FIXME: I'm not sure if this case holds true outside of copies. If it does,
-  // then we can pull it into the helpers that get the appropriate class for a
-  // register bank. Or make a new helper that carries along some constraint
-  // information.
-  if (SrcRegBank != DstRegBank && (DstSize == 1 && SrcSize == 1))
-    SrcSize = DstSize = 32;
-
   return {getMinClassForRegBank(SrcRegBank, SrcSize, true),
           getMinClassForRegBank(DstRegBank, DstSize, true)};
 }
 
 static bool selectCopy(MachineInstr &I, const TargetInstrInfo &TII,
                        MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI,
                        const RegisterBankInfo &RBI) {
   Register DstReg = I.getOperand(0).getReg();
bool AArch64InstructionSelector::selectCompareBranchFedByICmp(
   I.eraseFromParent();
   return true;
 }
 
 bool AArch64InstructionSelector::selectCompareBranch(
     MachineInstr &I, MachineFunction &MF, MachineRegisterInfo &MRI) {
   Register CondReg = I.getOperand(0).getReg();
   MachineInstr *CCMI = MRI.getVRegDef(CondReg);
-  if (CCMI->getOpcode() == TargetOpcode::G_TRUNC) {
-    CondReg = CCMI->getOperand(1).getReg();
-    CCMI = MRI.getVRegDef(CondReg);
-  }
-
   // Try to select the G_BRCOND using whatever is feeding the condition if
   // possible.
   unsigned CCMIOpc = CCMI->getOpcode();
   if (CCMIOpc == TargetOpcode::G_FCMP)
     return selectCompareBranchFedByFCmp(I, *CCMI, MIB);
   if (CCMIOpc == TargetOpcode::G_ICMP)
     return selectCompareBranchFedByICmp(I, *CCMI, MIB);
 
case TargetOpcode::G_BITCAST:
     // bitcast from a type to the same type. Ideally, these shouldn't occur
     // but we might not run an optimizer that deletes them. The other exception
     // is bitcasts involving pointer types, as SelectionDAG has no knowledge
     // of them.
     return selectCopy(I, TII, MRI, TRI, RBI);
 
   case TargetOpcode::G_SELECT: {
     auto &Sel = cast<GSelect>(I);
-    if (MRI.getType(Sel.getCondReg()) != LLT::scalar(1)) {
-      LLVM_DEBUG(dbgs() << "G_SELECT cond has type: " << Ty
-                        << ", expected: " << LLT::scalar(1) << '\n');
-      return false;
-    }
-
     const Register CondReg = Sel.getCondReg();
     const Register TReg = Sel.getTrueReg();
     const Register FReg = Sel.getFalseReg();
 
     if (tryOptSelect(Sel))
       return true;
 
     // Make sure to use an unused vreg instead of wzr, so that the peephole

 ///                     can be implemented for free.
 static bool canEmitConjunction(Register Val, bool &CanNegate, bool &MustBeFirst,
                                bool WillNegate, MachineRegisterInfo &MRI,
                                unsigned Depth = 0) {
   if (!MRI.hasOneNonDBGUse(Val))
     return false;
   MachineInstr *ValDef = MRI.getVRegDef(Val);
   unsigned Opcode = ValDef->getOpcode();
-  if (Opcode == TargetOpcode::G_TRUNC) {
-    // Look through a trunc.
-    Val = ValDef->getOperand(1).getReg();
-    ValDef = MRI.getVRegDef(Val);
-    Opcode = ValDef->getOpcode();
-  }
   if (isa<GAnyCmp>(ValDef)) {
     CanNegate = true;
     MustBeFirst = false;
     return true;
   }
   // Protect against exponential runtime and stack overflow.
   if (Depth > 6)
     return false;

 
 MachineInstr *AArch64InstructionSelector::emitConjunctionRec(
     Register Val, AArch64CC::CondCode &OutCC, bool Negate, Register CCOp,
     AArch64CC::CondCode Predicate, MachineIRBuilder &MIB) const {
   // We're at a tree leaf, produce a conditional comparison operation.
   auto &MRI = *MIB.getMRI();
   MachineInstr *ValDef = MRI.getVRegDef(Val);
   unsigned Opcode = ValDef->getOpcode();
-  if (Opcode == TargetOpcode::G_TRUNC) {
-    // Look through a trunc.
-    Val = ValDef->getOperand(1).getReg();
-    ValDef = MRI.getVRegDef(Val);
-    Opcode = ValDef->getOpcode();
-  }
   if (auto *Cmp = dyn_cast<GAnyCmp>(ValDef)) {
     Register LHS = Cmp->getLHSReg();
     Register RHS = Cmp->getRHSReg();
     CmpInst::Predicate CC = Cmp->getCond();
     if (Negate)
       CC = CmpInst::getInversePredicate(CC);
     if (isa<GICmp>(Cmp)) {
       OutCC = changeICMPPredToAArch64CC(CC);
bool AArch64InstructionSelector::tryOptSelect(GSelect &I) {
   // fcmp $x, $y
   // fcsel $w, $a, $b, pred
   //
   // Rather than emitting both of the rather long sequences in the standard
   // G_FCMP/G_SELECT select methods.
 
   // First, check if the condition is defined by a compare.
   MachineInstr *CondDef = MRI.getVRegDef(I.getOperand(1).getReg());
-  while (CondDef) {
-    // We can only fold if all of the defs have one use.
-    Register CondDefReg = CondDef->getOperand(0).getReg();
-    if (!MRI.hasOneNonDBGUse(CondDefReg)) {
-      // Unless it's another select.
-      for (const MachineInstr &UI : MRI.use_nodbg_instructions(CondDefReg)) {
-        if (CondDef == &UI)
-          continue;
-        if (UI.getOpcode() != TargetOpcode::G_SELECT)
-          return false;
-      }
-    }
+
 
-    // We can skip over G_TRUNC since the condition is 1-bit.
-    // Truncating/extending can have no impact on the value.
-    unsigned Opc = CondDef->getOpcode();
-    if (Opc != TargetOpcode::COPY && Opc != TargetOpcode::G_TRUNC)
-      break;
-
-    // Can't see past copies from physregs.
-    if (Opc == TargetOpcode::COPY &&
-        Register::isPhysicalRegister(CondDef->getOperand(1).getReg()))
-      return false;
-
-    CondDef = MRI.getVRegDef(CondDef->getOperand(1).getReg());
-  }
-
   // Is the condition defined by a compare?
   unsigned CondOpc = CondDef->getOpcode();
   if (CondOpc != TargetOpcode::G_ICMP && CondOpc != TargetOpcode::G_FCMP) {
     if (tryOptSelectConjunction(I, *CondDef))
       return true;
     return false;
   }
 

llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp

 using namespace LegalizeMutations;
 using namespace LegalityPredicates;
 using namespace MIPatternMatch;
 
 AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
     : ST(&ST) {
   using namespace TargetOpcode;
   const LLT p0 = LLT::pointer(0, 64);
-  const LLT s1 = LLT::scalar(1);
   const LLT s8 = LLT::scalar(8);
   const LLT s16 = LLT::scalar(16);
   const LLT s32 = LLT::scalar(32);
   const LLT s64 = LLT::scalar(64);
   const LLT s128 = LLT::scalar(128);
   const LLT v16s8 = LLT::fixed_vector(16, 8);
   const LLT v8s8 = LLT::fixed_vector(8, 8);
   const LLT v4s8 = LLT::fixed_vector(4, 8);
AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
   }
 
   // Some instructions only support s16 if the subtarget has full 16-bit FP
   // support.
   const bool HasFP16 = ST.hasFullFP16();
   const LLT &MinFPScalar = HasFP16 ? s16 : s32;
 
   getActionDefinitionsBuilder({G_IMPLICIT_DEF, G_FREEZE})
-      .legalFor({p0, s1, s8, s16, s32, s64})
+      .legalFor({p0, s8, s16, s32, s64})
       .legalFor(PackedVectorAllTypeList)
       .widenScalarToNextPow2(0)
       .clampScalar(0, s8, s64)
       .fewerElementsIf(
           [=](const LegalityQuery &Query) {
             return Query.Types[0].isVector() &&
                    (Query.Types[0].getElementType() != s64 ||
                     Query.Types[0].getNumElements() != 2);
getActionDefinitionsBuilder({G_SMIN, G_SMAX, G_UMIN, G_UMAX})
       .clampNumElements(0, v2s32, v4s32)
       // FIXME: This sholdn't be needed as v2s64 types are going to
       // be expanded anyway, but G_ICMP doesn't support splitting vectors yet
       .clampNumElements(0, v2s64, v2s64)
       .lower();
 
   getActionDefinitionsBuilder(
       {G_SADDE, G_SSUBE, G_UADDE, G_USUBE, G_SADDO, G_SSUBO, G_UADDO, G_USUBO})
-      .legalFor({{s32, s1}, {s64, s1}})
+      .legalFor({{s32, s32}, {s64, s32}})
       .clampScalar(0, s32, s64)
+       .clampScalar(1, s32, s64)
       .widenScalarToNextPow2(0);
 
   getActionDefinitionsBuilder({G_FADD, G_FSUB, G_FMUL, G_FDIV, G_FNEG})
       .legalFor({MinFPScalar, s32, s64, v2s64, v4s32, v2s32})
       .clampScalar(0, MinFPScalar, s64)
       .clampNumElements(0, v2s32, v4s32)
       .clampNumElements(0, v2s64, v2s64);
 
getActionDefinitionsBuilder(
       // We need a call for these, so we always need to scalarize.
       .scalarize(0)
       // Regardless of FP16 support, widen 16-bit elements to 32-bits.
       .minScalar(0, s32)
       .libcallFor({s32, s64, v2s32, v4s32, v2s64});
 
   getActionDefinitionsBuilder(G_INSERT)
       .legalIf(all(typeInSet(0, {s32, s64, p0}),
-                   typeInSet(1, {s1, s8, s16, s32}), smallerThan(1, 0)))
+                   typeInSet(1, {s8, s16, s32}), smallerThan(1, 0)))
       .widenScalarToNextPow2(0)
       .clampScalar(0, s32, s64)
       .widenScalarToNextPow2(1)
       .minScalar(1, s8)
       .maxScalarIf(typeInSet(0, {s32}), 1, s16)
       .maxScalarIf(typeInSet(0, {s64, p0}), 1, s32);
 
   getActionDefinitionsBuilder(G_EXTRACT)
auto ExtLegalFunc = [=](const LegalityQuery &Query) {
 
     // Make sure that we have something that will fit in a register, and
     // make sure it's a power of 2.
     if (DstSize < 8 || DstSize > 128 || !isPowerOf2_32(DstSize))
       return false;
 
     const LLT &SrcTy = Query.Types[1];
 
-    // Special case for s1.
-    if (SrcTy == s1)
-      return true;
-
     // Make sure we fit in a register otherwise. Don't bother checking that
     // the source type is below 128 bits. We shouldn't be allowing anything
     // through which is wider than the destination in the first place.
     unsigned SrcSize = SrcTy.getSizeInBits();
     if (SrcSize < 8 || !isPowerOf2_32(SrcSize))
       return false;
 
     return true;
AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
   getActionDefinitionsBuilder({G_SITOFP, G_UITOFP})
       .legalForCartesianProduct({s32, s64, v2s64, v4s32, v2s32})
       .clampScalar(1, s32, s64)
       .minScalarSameAs(1, 0)
       .clampScalar(0, s32, s64)
       .widenScalarToNextPow2(0);
 
   // Control-flow
-  getActionDefinitionsBuilder(G_BRCOND).legalFor({s1, s8, s16, s32});
+  getActionDefinitionsBuilder(G_BRCOND)
+    .legalFor({s32})
+    .clampScalar(0, s32, s32);
   getActionDefinitionsBuilder(G_BRINDIRECT).legalFor({p0});
 
   getActionDefinitionsBuilder(G_SELECT)
-      .legalFor({{s32, s1}, {s64, s1}, {p0, s1}})
+      .legalFor({{s32, s32}, {s64, s32}, {p0, s32}})
       .widenScalarToNextPow2(0)
       .clampScalar(0, s32, s64)
+      .clampScalar(1, s32, s32)
       .minScalarEltSameAsIf(all(isVector(0), isVector(1)), 1, 0)
       .lowerIf(isVector(0));
 
   // Pointer-handling
   getActionDefinitionsBuilder(G_FRAME_INDEX).legalFor({p0});
 
   if (TM.getCodeModel() == CodeModel::Small)
     getActionDefinitionsBuilder(G_GLOBAL_VALUE).custom();
   else
     getActionDefinitionsBuilder(G_GLOBAL_VALUE).legalFor({p0});
 
   getActionDefinitionsBuilder(G_PTRTOINT)
-      .legalForCartesianProduct({s1, s8, s16, s32, s64}, {p0})
+      .legalForCartesianProduct({s8, s16, s32, s64}, {p0})
       .legalFor({{v2s64, v2p0}})
       .maxScalar(0, s64)
       .widenScalarToNextPow2(0, /*Min*/ 8);
 
   getActionDefinitionsBuilder(G_INTTOPTR)
       .unsupportedIf([&](const LegalityQuery &Query) {
         return Query.Types[0].getSizeInBits() != Query.Types[1].getSizeInBits();
       })
       .legalFor({{p0, s64}, {v2p0, v2s64}});
 
   // Casts for 32 and 64-bit width type are just copies.
   // Same for 128-bit width type, except they are on the FPR bank.
   getActionDefinitionsBuilder(G_BITCAST)
       // FIXME: This is wrong since G_BITCAST is not allowed to change the
       // number of bits but it's what the previous code described and fixing
       // it breaks tests.
-      .legalForCartesianProduct({s1, s8, s16, s32, s64, s128, v16s8, v8s8, v4s8,
+      .legalForCartesianProduct({s8, s16, s32, s64, s128, v16s8, v8s8, v4s8,
                                  v8s16, v4s16, v2s16, v4s32, v2s32, v2s64,
                                  v2p0});
 
   getActionDefinitionsBuilder(G_VASTART).legalFor({p0});
 
   // va_list must be a pointer, but most sized types are pretty easy to handle
   // as the destination.
   getActionDefinitionsBuilder(G_VAARG)

llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic.ll

 ; CHECK-NOLSE-O0-NEXT:  LBB33_1: ; %atomicrmw.start
 ; CHECK-NOLSE-O0-NEXT:    ; =>This Loop Header: Depth=1
 ; CHECK-NOLSE-O0-NEXT:    ; Child Loop BB33_2 Depth 2
 ; CHECK-NOLSE-O0-NEXT:    ldr w10, [sp, #28] ; 4-byte Folded Reload
 ; CHECK-NOLSE-O0-NEXT:    ldr x11, [sp, #16] ; 8-byte Folded Reload
 ; CHECK-NOLSE-O0-NEXT:    ldr w8, [sp, #24] ; 4-byte Folded Reload
 ; CHECK-NOLSE-O0-NEXT:    sxtb w9, w10
 ; CHECK-NOLSE-O0-NEXT:    subs w9, w9, w8, sxtb
-; CHECK-NOLSE-O0-NEXT:    csel w12, w10, w8, le
+; CHECK-NOLSE-O0-NEXT:    cset w9, le
+; CHECK-NOLSE-O0-NEXT:    and w9, w9, #0x1
+; CHECK-NOLSE-O0-NEXT:    ands w9, w9, #0x1
+; CHECK-NOLSE-O0-NEXT:    csel w12, w10, w8, ne
 ; CHECK-NOLSE-O0-NEXT:  LBB33_2: ; %atomicrmw.start
 ; CHECK-NOLSE-O0-NEXT:    ; Parent Loop BB33_1 Depth=1
 ; CHECK-NOLSE-O0-NEXT:    ; => This Inner Loop Header: Depth=2
 ; CHECK-NOLSE-O0-NEXT:    ldaxrb w9, [x11]
 ; CHECK-NOLSE-O0-NEXT:    cmp w9, w10, uxtb
 ; CHECK-NOLSE-O0-NEXT:    b.ne LBB33_4
 ; CHECK-NOLSE-O0-NEXT:  ; %bb.3: ; %atomicrmw.start
 ; CHECK-NOLSE-O0-NEXT:    ; in Loop: Header=BB33_2 Depth=2

 ; CHECK-NOLSE-O0-NEXT:  LBB34_1: ; %atomicrmw.start
 ; CHECK-NOLSE-O0-NEXT:    ; =>This Loop Header: Depth=1
 ; CHECK-NOLSE-O0-NEXT:    ; Child Loop BB34_2 Depth 2
 ; CHECK-NOLSE-O0-NEXT:    ldr w10, [sp, #28] ; 4-byte Folded Reload
 ; CHECK-NOLSE-O0-NEXT:    ldr x11, [sp, #16] ; 8-byte Folded Reload
 ; CHECK-NOLSE-O0-NEXT:    ldr w8, [sp, #24] ; 4-byte Folded Reload
 ; CHECK-NOLSE-O0-NEXT:    sxtb w9, w10
 ; CHECK-NOLSE-O0-NEXT:    subs w9, w9, w8, sxtb
-; CHECK-NOLSE-O0-NEXT:    csel w12, w10, w8, gt
+; CHECK-NOLSE-O0-NEXT:    cset w9, gt
+; CHECK-NOLSE-O0-NEXT:    and w9, w9, #0x1
+; CHECK-NOLSE-O0-NEXT:    ands w9, w9, #0x1
+; CHECK-NOLSE-O0-NEXT:    csel w12, w10, w8, ne
 ; CHECK-NOLSE-O0-NEXT:  LBB34_2: ; %atomicrmw.start
 ; CHECK-NOLSE-O0-NEXT:    ; Parent Loop BB34_1 Depth=1
 ; CHECK-NOLSE-O0-NEXT:    ; => This Inner Loop Header: Depth=2
 ; CHECK-NOLSE-O0-NEXT:    ldaxrb w9, [x11]
 ; CHECK-NOLSE-O0-NEXT:    cmp w9, w10, uxtb
 ; CHECK-NOLSE-O0-NEXT:    b.ne LBB34_4
 ; CHECK-NOLSE-O0-NEXT:  ; %bb.3: ; %atomicrmw.start
 ; CHECK-NOLSE-O0-NEXT:    ; in Loop: Header=BB34_2 Depth=2

 ; CHECK-NOLSE-O0-NEXT:  LBB35_1: ; %atomicrmw.start
 ; CHECK-NOLSE-O0-NEXT:    ; =>This Loop Header: Depth=1
 ; CHECK-NOLSE-O0-NEXT:    ; Child Loop BB35_2 Depth 2
 ; CHECK-NOLSE-O0-NEXT:    ldr w10, [sp, #28] ; 4-byte Folded Reload
 ; CHECK-NOLSE-O0-NEXT:    ldr x11, [sp, #16] ; 8-byte Folded Reload
 ; CHECK-NOLSE-O0-NEXT:    ldr w8, [sp, #24] ; 4-byte Folded Reload
 ; CHECK-NOLSE-O0-NEXT:    and w9, w10, #0xff
 ; CHECK-NOLSE-O0-NEXT:    subs w9, w9, w8, uxtb
-; CHECK-NOLSE-O0-NEXT:    csel w12, w10, w8, ls
+; CHECK-NOLSE-O0-NEXT:    cset w9, ls
+; CHECK-NOLSE-O0-NEXT:    and w9, w9, #0x1
+; CHECK-NOLSE-O0-NEXT:    ands w9, w9, #0x1
+; CHECK-NOLSE-O0-NEXT:    csel w12, w10, w8, ne
 ; CHECK-NOLSE-O0-NEXT:  LBB35_2: ; %atomicrmw.start
 ; CHECK-NOLSE-O0-NEXT:    ; Parent Loop BB35_1 Depth=1
 ; CHECK-NOLSE-O0-NEXT:    ; => This Inner Loop Header: Depth=2
 ; CHECK-NOLSE-O0-NEXT:    ldaxrb w9, [x11]
 ; CHECK-NOLSE-O0-NEXT:    cmp w9, w10, uxtb
 ; CHECK-NOLSE-O0-NEXT:    b.ne LBB35_4
 ; CHECK-NOLSE-O0-NEXT:  ; %bb.3: ; %atomicrmw.start
 ; CHECK-NOLSE-O0-NEXT:    ; in Loop: Header=BB35_2 Depth=2

 ; CHECK-NOLSE-O0-NEXT:  LBB36_1: ; %atomicrmw.start
 ; CHECK-NOLSE-O0-NEXT:    ; =>This Loop Header: Depth=1
 ; CHECK-NOLSE-O0-NEXT:    ; Child Loop BB36_2 Depth 2
 ; CHECK-NOLSE-O0-NEXT:    ldr w10, [sp, #28] ; 4-byte Folded Reload
 ; CHECK-NOLSE-O0-NEXT:    ldr x11, [sp, #16] ; 8-byte Folded Reload
 ; CHECK-NOLSE-O0-NEXT:    ldr w8, [sp, #24] ; 4-byte Folded Reload
 ; CHECK-NOLSE-O0-NEXT:    and w9, w10, #0xff
 ; CHECK-NOLSE-O0-NEXT:    subs w9, w9, w8, uxtb
-; CHECK-NOLSE-O0-NEXT:    csel w12, w10, w8, hi
+; CHECK-NOLSE-O0-NEXT:    cset w9, hi
+; CHECK-NOLSE-O0-NEXT:    and w9, w9, #0x1
+; CHECK-NOLSE-O0-NEXT:    ands w9, w9, #0x1
+; CHECK-NOLSE-O0-NEXT:    csel w12, w10, w8, ne
 ; CHECK-NOLSE-O0-NEXT:  LBB36_2: ; %atomicrmw.start
 ; CHECK-NOLSE-O0-NEXT:    ; Parent Loop BB36_1 Depth=1
 ; CHECK-NOLSE-O0-NEXT:    ; => This Inner Loop Header: Depth=2
 ; CHECK-NOLSE-O0-NEXT:    ldaxrb w9, [x11]
 ; CHECK-NOLSE-O0-NEXT:    cmp w9, w10, uxtb
 ; CHECK-NOLSE-O0-NEXT:    b.ne LBB36_4
 ; CHECK-NOLSE-O0-NEXT:  ; %bb.3: ; %atomicrmw.start
 ; CHECK-NOLSE-O0-NEXT:    ; in Loop: Header=BB36_2 Depth=2

 ; CHECK-NOLSE-O0-NEXT:  LBB43_1: ; %atomicrmw.start
 ; CHECK-NOLSE-O0-NEXT:    ; =>This Loop Header: Depth=1
 ; CHECK-NOLSE-O0-NEXT:    ; Child Loop BB43_2 Depth 2
 ; CHECK-NOLSE-O0-NEXT:    ldr w8, [sp, #28] ; 4-byte Folded Reload
 ; CHECK-NOLSE-O0-NEXT:    ldr x11, [sp, #16] ; 8-byte Folded Reload
 ; CHECK-NOLSE-O0-NEXT:    ldr w9, [sp, #24] ; 4-byte Folded Reload
 ; CHECK-NOLSE-O0-NEXT:    sxth w10, w8
 ; CHECK-NOLSE-O0-NEXT:    subs w10, w10, w9, sxth
-; CHECK-NOLSE-O0-NEXT:    csel w12, w8, w9, le
+; CHECK-NOLSE-O0-NEXT:    cset w10, le
+; CHECK-NOLSE-O0-NEXT:    and w10, w10, #0x1
+; CHECK-NOLSE-O0-NEXT:    ands w10, w10, #0x1
+; CHECK-NOLSE-O0-NEXT:    csel w12, w8, w9, ne
 ; CHECK-NOLSE-O0-NEXT:  LBB43_2: ; %atomicrmw.start
 ; CHECK-NOLSE-O0-NEXT:    ; Parent Loop BB43_1 Depth=1
 ; CHECK-NOLSE-O0-NEXT:    ; => This Inner Loop Header: Depth=2
 ; CHECK-NOLSE-O0-NEXT:    ldaxrh w9, [x11]
 ; CHECK-NOLSE-O0-NEXT:    cmp w9, w8, uxth
 ; CHECK-NOLSE-O0-NEXT:    b.ne LBB43_4
 ; CHECK-NOLSE-O0-NEXT:  ; %bb.3: ; %atomicrmw.start
 ; CHECK-NOLSE-O0-NEXT:    ; in Loop: Header=BB43_2 Depth=2

 ; CHECK-NOLSE-O0-NEXT:  LBB44_1: ; %atomicrmw.start
 ; CHECK-NOLSE-O0-NEXT:    ; =>This Loop Header: Depth=1
 ; CHECK-NOLSE-O0-NEXT:    ; Child Loop BB44_2 Depth 2
 ; CHECK-NOLSE-O0-NEXT:    ldr w8, [sp, #28] ; 4-byte Folded Reload
 ; CHECK-NOLSE-O0-NEXT:    ldr x11, [sp, #16] ; 8-byte Folded Reload
 ; CHECK-NOLSE-O0-NEXT:    ldr w9, [sp, #24] ; 4-byte Folded Reload
 ; CHECK-NOLSE-O0-NEXT:    sxth w10, w8
 ; CHECK-NOLSE-O0-NEXT:    subs w10, w10, w9, sxth
-; CHECK-NOLSE-O0-NEXT:    csel w12, w8, w9, gt
+; CHECK-NOLSE-O0-NEXT:    cset w10, gt
+; CHECK-NOLSE-O0-NEXT:    and w10, w10, #0x1
+; CHECK-NOLSE-O0-NEXT:    ands w10, w10, #0x1
+; CHECK-NOLSE-O0-NEXT:    csel w12, w8, w9, ne
 ; CHECK-NOLSE-O0-NEXT:  LBB44_2: ; %atomicrmw.start
 ; CHECK-NOLSE-O0-NEXT:    ; Parent Loop BB44_1 Depth=1
 ; CHECK-NOLSE-O0-NEXT:    ; => This Inner Loop Header: Depth=2
 ; CHECK-NOLSE-O0-NEXT:    ldaxrh w9, [x11]
 ; CHECK-NOLSE-O0-NEXT:    cmp w9, w8, uxth
 ; CHECK-NOLSE-O0-NEXT:    b.ne LBB44_4
 ; CHECK-NOLSE-O0-NEXT:  ; %bb.3: ; %atomicrmw.start
 ; CHECK-NOLSE-O0-NEXT:    ; in Loop: Header=BB44_2 Depth=2

 ; CHECK-NOLSE-O0-NEXT:  LBB45_1: ; %atomicrmw.start
 ; CHECK-NOLSE-O0-NEXT:    ; =>This Loop Header: Depth=1
 ; CHECK-NOLSE-O0-NEXT:    ; Child Loop BB45_2 Depth 2
 ; CHECK-NOLSE-O0-NEXT:    ldr w8, [sp, #28] ; 4-byte Folded Reload
 ; CHECK-NOLSE-O0-NEXT:    ldr x11, [sp, #16] ; 8-byte Folded Reload
 ; CHECK-NOLSE-O0-NEXT:    ldr w9, [sp, #24] ; 4-byte Folded Reload
 ; CHECK-NOLSE-O0-NEXT:    uxth w10, w8
 ; CHECK-NOLSE-O0-NEXT:    subs w10, w10, w9, uxth
-; CHECK-NOLSE-O0-NEXT:    csel w12, w8, w9, ls
+; CHECK-NOLSE-O0-NEXT:    cset w10, ls
+; CHECK-NOLSE-O0-NEXT:    and w10, w10, #0x1
+; CHECK-NOLSE-O0-NEXT:    ands w10, w10, #0x1
+; CHECK-NOLSE-O0-NEXT:    csel w12, w8, w9, ne
 ; CHECK-NOLSE-O0-NEXT:  LBB45_2: ; %atomicrmw.start
 ; CHECK-NOLSE-O0-NEXT:    ; Parent Loop BB45_1 Depth=1
 ; CHECK-NOLSE-O0-NEXT:    ; => This Inner Loop Header: Depth=2
 ; CHECK-NOLSE-O0-NEXT:    ldaxrh w9, [x11]
 ; CHECK-NOLSE-O0-NEXT:    cmp w9, w8, uxth
 ; CHECK-NOLSE-O0-NEXT:    b.ne LBB45_4
 ; CHECK-NOLSE-O0-NEXT:  ; %bb.3: ; %atomicrmw.start
 ; CHECK-NOLSE-O0-NEXT:    ; in Loop: Header=BB45_2 Depth=2

 ; CHECK-NOLSE-O0-NEXT:  LBB46_1: ; %atomicrmw.start
 ; CHECK-NOLSE-O0-NEXT:    ; =>This Loop Header: Depth=1
 ; CHECK-NOLSE-O0-NEXT:    ; Child Loop BB46_2 Depth 2
 ; CHECK-NOLSE-O0-NEXT:    ldr w8, [sp, #28] ; 4-byte Folded Reload
 ; CHECK-NOLSE-O0-NEXT:    ldr x11, [sp, #16] ; 8-byte Folded Reload
 ; CHECK-NOLSE-O0-NEXT:    ldr w9, [sp, #24] ; 4-byte Folded Reload
 ; CHECK-NOLSE-O0-NEXT:    uxth w10, w8
 ; CHECK-NOLSE-O0-NEXT:    subs w10, w10, w9, uxth
-; CHECK-NOLSE-O0-NEXT:    csel w12, w8, w9, hi
+; CHECK-NOLSE-O0-NEXT:    cset w10, hi
+; CHECK-NOLSE-O0-NEXT:    and w10, w10, #0x1
+; CHECK-NOLSE-O0-NEXT:    ands w10, w10, #0x1
+; CHECK-NOLSE-O0-NEXT:    csel w12, w8, w9, ne
 ; CHECK-NOLSE-O0-NEXT:  LBB46_2: ; %atomicrmw.start
 ; CHECK-NOLSE-O0-NEXT:    ; Parent Loop BB46_1 Depth=1
 ; CHECK-NOLSE-O0-NEXT:    ; => This Inner Loop Header: Depth=2
 ; CHECK-NOLSE-O0-NEXT:    ldaxrh w9, [x11]
 ; CHECK-NOLSE-O0-NEXT:    cmp w9, w8, uxth
 ; CHECK-NOLSE-O0-NEXT:    b.ne LBB46_4
 ; CHECK-NOLSE-O0-NEXT:  ; %bb.3: ; %atomicrmw.start
 ; CHECK-NOLSE-O0-NEXT:    ; in Loop: Header=BB46_2 Depth=2

llvm/test/CodeGen/AArch64/GlobalISel/fold-brcond-fcmp.mir

body:             |
   ; CHECK-NEXT:   RET_ReallyLR implicit $s1
   bb.0:
     successors: %bb.1(0x50000000), %bb.2(0x30000000)
     liveins: $s0, $s1, $w0, $w1
 
     %cmp_lhs:fpr(s32) = COPY $s0
     %cmp_rhs:fpr(s32) = COPY $s1
     %fcmp:gpr(s32) = G_FCMP floatpred(oeq), %cmp_lhs(s32), %cmp_rhs
-    %trunc:gpr(s1) = G_TRUNC %fcmp(s32)
-    G_BRCOND %trunc(s1), %bb.2
+    G_BRCOND %fcmp, %bb.2
     G_BR %bb.1
   bb.1:
     $s0 = COPY %cmp_lhs
     RET_ReallyLR implicit $s0
   bb.2:
     $s1 = COPY %cmp_rhs
     RET_ReallyLR implicit $s1
 
body:             |
   ; CHECK-NEXT:   RET_ReallyLR implicit $s1
   bb.0:
     successors: %bb.1(0x50000000), %bb.2(0x30000000)
     liveins: $s0, $s1, $w0, $w1
 
     %cmp_lhs:fpr(s32) = COPY $s0
     %cmp_rhs:fpr(s32) = COPY $s1
     %fcmp:gpr(s32) = G_FCMP floatpred(ogt), %cmp_lhs(s32), %cmp_rhs
-    %trunc:gpr(s1) = G_TRUNC %fcmp(s32)
-    G_BRCOND %trunc(s1), %bb.2
+    G_BRCOND %fcmp, %bb.2
     G_BR %bb.1
   bb.1:
     $s0 = COPY %cmp_lhs
     RET_ReallyLR implicit $s0
   bb.2:
     $s1 = COPY %cmp_rhs
     RET_ReallyLR implicit $s1
 
body:             |
   ; CHECK-NEXT:   RET_ReallyLR implicit $s1
   bb.0:
     successors: %bb.1(0x50000000), %bb.2(0x30000000)
     liveins: $s0, $s1, $w0, $w1
 
     %cmp_lhs:fpr(s32) = COPY $s0
     %cmp_rhs:fpr(s32) = COPY $s1
     %fcmp:gpr(s32) = G_FCMP floatpred(oge), %cmp_lhs(s32), %cmp_rhs
-    %trunc:gpr(s1) = G_TRUNC %fcmp(s32)
-    G_BRCOND %trunc(s1), %bb.2
+    G_BRCOND %fcmp, %bb.2
     G_BR %bb.1
   bb.1:
     $s0 = COPY %cmp_lhs
     RET_ReallyLR implicit $s0
   bb.2:
     $s1 = COPY %cmp_rhs
     RET_ReallyLR implicit $s1
 
body:             |
   ; CHECK-NEXT:   RET_ReallyLR implicit $s1
   bb.0:
     successors: %bb.1(0x50000000), %bb.2(0x30000000)
     liveins: $s0, $s1, $w0, $w1
 
     %cmp_lhs:fpr(s32) = COPY $s0
     %cmp_rhs:fpr(s32) = COPY $s1
     %fcmp:gpr(s32) = G_FCMP floatpred(olt), %cmp_lhs(s32), %cmp_rhs
-    %trunc:gpr(s1) = G_TRUNC %fcmp(s32)
-    G_BRCOND %trunc(s1), %bb.2
+    G_BRCOND %fcmp, %bb.2
     G_BR %bb.1
   bb.1:
     $s0 = COPY %cmp_lhs
     RET_ReallyLR implicit $s0
   bb.2:
     $s1 = COPY %cmp_rhs
     RET_ReallyLR implicit $s1
 
body:             |
   ; CHECK-NEXT:   RET_ReallyLR implicit $s1
   bb.0:
     successors: %bb.1(0x50000000), %bb.2(0x30000000)
     liveins: $s0, $s1, $w0, $w1
 
     %cmp_lhs:fpr(s32) = COPY $s0
     %cmp_rhs:fpr(s32) = COPY $s1
     %fcmp:gpr(s32) = G_FCMP floatpred(ole), %cmp_lhs(s32), %cmp_rhs
-    %trunc:gpr(s1) = G_TRUNC %fcmp(s32)
-    G_BRCOND %trunc(s1), %bb.2
+    G_BRCOND %fcmp, %bb.2
     G_BR %bb.1
   bb.1:
     $s0 = COPY %cmp_lhs
     RET_ReallyLR implicit $s0
   bb.2:
     $s1 = COPY %cmp_rhs
     RET_ReallyLR implicit $s1
 
body:             |
   ; CHECK-NEXT:   RET_ReallyLR implicit $s1
   bb.0:
     successors: %bb.1(0x50000000), %bb.2(0x30000000)
     liveins: $s0, $s1, $w0, $w1
 
     %cmp_lhs:fpr(s32) = COPY $s0
     %cmp_rhs:fpr(s32) = COPY $s1
     %fcmp:gpr(s32) = G_FCMP floatpred(one), %cmp_lhs(s32), %cmp_rhs
-    %trunc:gpr(s1) = G_TRUNC %fcmp(s32)
-    G_BRCOND %trunc(s1), %bb.2
+    G_BRCOND %fcmp, %bb.2
     G_BR %bb.1
   bb.1:
     $s0 = COPY %cmp_lhs
     RET_ReallyLR implicit $s0
   bb.2:
     $s1 = COPY %cmp_rhs
     RET_ReallyLR implicit $s1
 
body:             |
   ; CHECK-NEXT:   RET_ReallyLR implicit $s1
   bb.0:
     successors: %bb.1(0x50000000), %bb.2(0x30000000)
     liveins: $s0, $s1, $w0, $w1
 
     %cmp_lhs:fpr(s32) = COPY $s0
     %cmp_rhs:fpr(s32) = COPY $s1
     %fcmp:gpr(s32) = G_FCMP floatpred(ord), %cmp_lhs(s32), %cmp_rhs
-    %trunc:gpr(s1) = G_TRUNC %fcmp(s32)
-    G_BRCOND %trunc(s1), %bb.2
+    G_BRCOND %fcmp, %bb.2
     G_BR %bb.1
   bb.1:
     $s0 = COPY %cmp_lhs
     RET_ReallyLR implicit $s0
   bb.2:
     $s1 = COPY %cmp_rhs
     RET_ReallyLR implicit $s1
 
body:             |
   ; CHECK-NEXT:   RET_ReallyLR implicit $s1
   bb.0:
     successors: %bb.1(0x50000000), %bb.2(0x30000000)
     liveins: $s0, $s1, $w0, $w1
 
     %cmp_lhs:fpr(s32) = COPY $s0
     %cmp_rhs:fpr(s32) = COPY $s1
     %fcmp:gpr(s32) = G_FCMP floatpred(uno), %cmp_lhs(s32), %cmp_rhs
-    %trunc:gpr(s1) = G_TRUNC %fcmp(s32)
-    G_BRCOND %trunc(s1), %bb.2
+    G_BRCOND %fcmp, %bb.2
     G_BR %bb.1
   bb.1:
     $s0 = COPY %cmp_lhs
     RET_ReallyLR implicit $s0
   bb.2:
     $s1 = COPY %cmp_rhs
     RET_ReallyLR implicit $s1
 
body:             |
   ; CHECK-NEXT:   RET_ReallyLR implicit $s1
   bb.0:
     successors: %bb.1(0x50000000), %bb.2(0x30000000)
     liveins: $s0, $s1, $w0, $w1
 
     %cmp_lhs:fpr(s32) = COPY $s0
     %cmp_rhs:fpr(s32) = COPY $s1
     %fcmp:gpr(s32) = G_FCMP floatpred(ueq), %cmp_lhs(s32), %cmp_rhs
-    %trunc:gpr(s1) = G_TRUNC %fcmp(s32)
-    G_BRCOND %trunc(s1), %bb.2
+    G_BRCOND %fcmp, %bb.2
     G_BR %bb.1
   bb.1:
     $s0 = COPY %cmp_lhs
     RET_ReallyLR implicit $s0
   bb.2:
     $s1 = COPY %cmp_rhs
     RET_ReallyLR implicit $s1
 
body:             |
   ; CHECK-NEXT:   RET_ReallyLR implicit $s1
   bb.0:
     successors: %bb.1(0x50000000), %bb.2(0x30000000)
     liveins: $s0, $s1, $w0, $w1
 
     %cmp_lhs:fpr(s32) = COPY $s0
     %cmp_rhs:fpr(s32) = COPY $s1
     %fcmp:gpr(s32) = G_FCMP floatpred(ugt), %cmp_lhs(s32), %cmp_rhs
-    %trunc:gpr(s1) = G_TRUNC %fcmp(s32)
-    G_BRCOND %trunc(s1), %bb.2
+    G_BRCOND %fcmp, %bb.2
     G_BR %bb.1
   bb.1:
     $s0 = COPY %cmp_lhs
     RET_ReallyLR implicit $s0
   bb.2:
     $s1 = COPY %cmp_rhs
     RET_ReallyLR implicit $s1
 
body:             |
   ; CHECK-NEXT:   RET_ReallyLR implicit $s1
   bb.0:
     successors: %bb.1(0x50000000), %bb.2(0x30000000)
     liveins: $s0, $s1, $w0, $w1
 
     %cmp_lhs:fpr(s32) = COPY $s0
     %cmp_rhs:fpr(s32) = COPY $s1
     %fcmp:gpr(s32) = G_FCMP floatpred(uge), %cmp_lhs(s32), %cmp_rhs
-    %trunc:gpr(s1) = G_TRUNC %fcmp(s32)
-    G_BRCOND %trunc(s1), %bb.2
+    G_BRCOND %fcmp, %bb.2
     G_BR %bb.1
   bb.1:
     $s0 = COPY %cmp_lhs
     RET_ReallyLR implicit $s0
   bb.2:
     $s1 = COPY %cmp_rhs
     RET_ReallyLR implicit $s1
 
body:             |
   ; CHECK-NEXT:   RET_ReallyLR implicit $s1
   bb.0:
     successors: %bb.1(0x50000000), %bb.2(0x30000000)
     liveins: $s0, $s1, $w0, $w1
 
     %cmp_lhs:fpr(s32) = COPY $s0
     %cmp_rhs:fpr(s32) = COPY $s1
     %fcmp:gpr(s32) = G_FCMP floatpred(ult), %cmp_lhs(s32), %cmp_rhs
-    %trunc:gpr(s1) = G_TRUNC %fcmp(s32)
-    G_BRCOND %trunc(s1), %bb.2
+    G_BRCOND %fcmp, %bb.2
     G_BR %bb.1
   bb.1:
     $s0 = COPY %cmp_lhs
     RET_ReallyLR implicit $s0
   bb.2:
     $s1 = COPY %cmp_rhs
     RET_ReallyLR implicit $s1
 
body:             |
   ; CHECK-NEXT:   RET_ReallyLR implicit $s1
   bb.0:
     successors: %bb.1(0x50000000), %bb.2(0x30000000)
     liveins: $s0, $s1, $w0, $w1
 
     %cmp_lhs:fpr(s32) = COPY $s0
     %cmp_rhs:fpr(s32) = COPY $s1
     %fcmp:gpr(s32) = G_FCMP floatpred(ule), %cmp_lhs(s32), %cmp_rhs
-    %trunc:gpr(s1) = G_TRUNC %fcmp(s32)
-    G_BRCOND %trunc(s1), %bb.2
+    G_BRCOND %fcmp, %bb.2
     G_BR %bb.1
   bb.1:
     $s0 = COPY %cmp_lhs
     RET_ReallyLR implicit $s0
   bb.2:
     $s1 = COPY %cmp_rhs
     RET_ReallyLR implicit $s1
 
body:             |
   ; CHECK-NEXT:   RET_ReallyLR implicit $s1
   bb.0:
     successors: %bb.1(0x50000000), %bb.2(0x30000000)
     liveins: $s0, $s1, $w0, $w1
 
     %cmp_lhs:fpr(s32) = COPY $s0
     %cmp_rhs:fpr(s32) = COPY $s1
     %fcmp:gpr(s32) = G_FCMP floatpred(une), %cmp_lhs(s32), %cmp_rhs
-    %trunc:gpr(s1) = G_TRUNC %fcmp(s32)
-    G_BRCOND %trunc(s1), %bb.2
+    G_BRCOND %fcmp, %bb.2
     G_BR %bb.1
   bb.1:
     $s0 = COPY %cmp_lhs
     RET_ReallyLR implicit $s0
   bb.2:
     $s1 = COPY %cmp_rhs
     RET_ReallyLR implicit $s1

llvm/test/CodeGen/AArch64/GlobalISel/fold-fp-select.mir

bb.0:
     ; CHECK-LABEL: name: fcmp_more_than_one_user_no_fold
     ; CHECK: liveins: $s0, $s1, $w1
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
     ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1
     ; CHECK-NEXT: [[FMOVS0_:%[0-9]+]]:fpr32 = FMOVS0
     ; CHECK-NEXT: FCMPSri [[COPY]], implicit-def $nzcv
     ; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv
-    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr32 = COPY [[CSINCWr]]
-    ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr32 = COPY [[COPY2]]
-    ; CHECK-NEXT: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri [[COPY3]], 0, implicit-def $nzcv
+    ; CHECK-NEXT: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri [[CSINCWr]], 0, implicit-def $nzcv
     ; CHECK-NEXT: [[FCSELSrrr:%[0-9]+]]:fpr32 = FCSELSrrr [[FMOVS0_]], [[COPY1]], 1, implicit $nzcv
     ; CHECK-NEXT: $w1 = COPY [[CSINCWr]]
     ; CHECK-NEXT: $s0 = COPY [[FCSELSrrr]]
     ; CHECK-NEXT: RET_ReallyLR implicit $s0
     %0:fpr(s32) = COPY $s0
     %1:fpr(s32) = COPY $s1
     %2:fpr(s32) = G_FCONSTANT float 0.000000e+00
     %5:gpr(s32) = G_FCMP floatpred(oeq), %0(s32), %2
-    %3:gpr(s1) = G_TRUNC %5(s32)
-    %6:fpr(s1) = COPY %3(s1)
-    %4:fpr(s32) = G_SELECT %6(s1), %2, %1
+    %4:fpr(s32) = G_SELECT %5, %2, %1
     $w1 = COPY %5(s32)
     $s0 = COPY %4(s32)
     RET_ReallyLR implicit $s0
 
 ...
 ---
 name:            fcmp_more_than_one_select
 alignment:       4
bb.0:
     ; CHECK-NEXT: [[FCSELSrrr1:%[0-9]+]]:fpr32 = FCSELSrrr [[COPY1]], [[FMOVS0_]], 0, implicit $nzcv
     ; CHECK-NEXT: $s0 = COPY [[FCSELSrrr]]
     ; CHECK-NEXT: $s1 = COPY [[FCSELSrrr1]]
     ; CHECK-NEXT: RET_ReallyLR implicit $s0
     %0:fpr(s32) = COPY $s0
     %1:fpr(s32) = COPY $s1
     %2:fpr(s32) = G_FCONSTANT float 0.000000e+00
     %5:gpr(s32) = G_FCMP floatpred(oeq), %0(s32), %2
-    %3:gpr(s1) = G_TRUNC %5(s32)
-    %6:fpr(s1) = COPY %3(s1)
-    %4:fpr(s32) = G_SELECT %6(s1), %2, %1
-    %7:fpr(s32) = G_SELECT %6(s1), %1, %2
+    %4:fpr(s32) = G_SELECT %5, %2, %1
+    %7:fpr(s32) = G_SELECT %5, %1, %2
     $s0 = COPY %4(s32)
     $s1 = COPY %7(s32)
     RET_ReallyLR implicit $s0
 
 ...
 ---
 name:            using_icmp
 alignment:       4
bb.0:
     ; CHECK-NEXT: [[FCSELSrrr:%[0-9]+]]:fpr32 = FCSELSrrr [[COPY1]], [[FMOVS0_]], 0, implicit $nzcv
     ; CHECK-NEXT: $s0 = COPY [[FCSELSrrr]]
     ; CHECK-NEXT: RET_ReallyLR implicit $s0
     %0:gpr(s32) = COPY $w0
     %1:fpr(s32) = COPY $s0
     %2:gpr(s32) = G_CONSTANT i32 0
     %5:fpr(s32) = G_FCONSTANT float 0.000000e+00
     %6:gpr(s32) = G_ICMP intpred(eq), %0(s32), %2
-    %3:gpr(s1) = G_TRUNC %6(s32)
-    %7:fpr(s1) = COPY %3(s1)
-    %4:fpr(s32) = G_SELECT %7(s1), %1, %5
+    %4:fpr(s32) = G_SELECT %6, %1, %5
     $s0 = COPY %4(s32)
     RET_ReallyLR implicit $s0
 
 ...
 ---
 name:            foeq
 alignment:       4
 legalized:       true
bb.0:
     ; CHECK-NEXT: FCMPSri [[COPY]], implicit-def $nzcv
     ; CHECK-NEXT: [[FCSELSrrr:%[0-9]+]]:fpr32 = FCSELSrrr [[FMOVS0_]], [[COPY1]], 0, implicit $nzcv
     ; CHECK-NEXT: $s0 = COPY [[FCSELSrrr]]
     ; CHECK-NEXT: RET_ReallyLR implicit $s0
     %0:fpr(s32) = COPY $s0
     %1:fpr(s32) = COPY $s1
     %2:fpr(s32) = G_FCONSTANT float 0.000000e+00
     %5:gpr(s32) = G_FCMP floatpred(oeq), %0(s32), %2
-    %3:gpr(s1) = G_TRUNC %5(s32)
-    %6:fpr(s1) = COPY %3(s1)
-    %4:fpr(s32) = G_SELECT %6(s1), %2, %1
+    %4:fpr(s32) = G_SELECT %5, %2, %1
     $s0 = COPY %4(s32)
     RET_ReallyLR implicit $s0
 
 ...
 ---
 name:            fueq
 alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 body:             |
   bb.0:
     liveins: $s0, $s1
 
     ; CHECK-LABEL: name: fueq
     ; CHECK: liveins: $s0, $s1
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
     ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1
     ; CHECK-NEXT: [[FMOVS0_:%[0-9]+]]:fpr32 = FMOVS0
     ; CHECK-NEXT: FCMPSri [[COPY]], implicit-def $nzcv
     ; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv
     ; CHECK-NEXT: [[CSINCWr1:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 7, implicit $nzcv
     ; CHECK-NEXT: [[ORRWrr:%[0-9]+]]:gpr32 = ORRWrr [[CSINCWr]], [[CSINCWr1]]
-    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr32 = COPY [[ORRWrr]]
-    ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr32 = COPY [[COPY2]]
-    ; CHECK-NEXT: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri [[COPY3]], 0, implicit-def $nzcv
+    ; CHECK-NEXT: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri [[ORRWrr]], 0, implicit-def $nzcv
     ; CHECK-NEXT: [[FCSELSrrr:%[0-9]+]]:fpr32 = FCSELSrrr [[FMOVS0_]], [[COPY1]], 1, implicit $nzcv
     ; CHECK-NEXT: $s0 = COPY [[FCSELSrrr]]
     ; CHECK-NEXT: RET_ReallyLR implicit $s0
     %0:fpr(s32) = COPY $s0
     %1:fpr(s32) = COPY $s1
     %2:fpr(s32) = G_FCONSTANT float 0.000000e+00
     %5:gpr(s32) = G_FCMP floatpred(ueq), %0(s32), %2
-    %3:gpr(s1) = G_TRUNC %5(s32)
-    %6:fpr(s1) = COPY %3(s1)
-    %4:fpr(s32) = G_SELECT %6(s1), %2, %1
+    %4:fpr(s32) = G_SELECT %5, %2, %1
     $s0 = COPY %4(s32)
     RET_ReallyLR implicit $s0
 
 ...
 ---
 name:            fone
 alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 body:             |
   bb.0:
     liveins: $s0, $s1
 
     ; CHECK-LABEL: name: fone
     ; CHECK: liveins: $s0, $s1
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
     ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1
     ; CHECK-NEXT: [[FMOVS0_:%[0-9]+]]:fpr32 = FMOVS0
     ; CHECK-NEXT: FCMPSri [[COPY]], implicit-def $nzcv
     ; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 5, implicit $nzcv
     ; CHECK-NEXT: [[CSINCWr1:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 13, implicit $nzcv
     ; CHECK-NEXT: [[ORRWrr:%[0-9]+]]:gpr32 = ORRWrr [[CSINCWr]], [[CSINCWr1]]
-    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr32 = COPY [[ORRWrr]]
-    ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr32 = COPY [[COPY2]]
-    ; CHECK-NEXT: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri [[COPY3]], 0, implicit-def $nzcv
+    ; CHECK-NEXT: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri [[ORRWrr]], 0, implicit-def $nzcv
     ; CHECK-NEXT: [[FCSELSrrr:%[0-9]+]]:fpr32 = FCSELSrrr [[COPY1]], [[FMOVS0_]], 1, implicit $nzcv
     ; CHECK-NEXT: $s0 = COPY [[FCSELSrrr]]
     ; CHECK-NEXT: RET_ReallyLR implicit $s0
     %0:fpr(s32) = COPY $s0
     %1:fpr(s32) = COPY $s1
     %2:fpr(s32) = G_FCONSTANT float 0.000000e+00
     %5:gpr(s32) = G_FCMP floatpred(one), %0(s32), %2
-    %3:gpr(s1) = G_TRUNC %5(s32)
-    %6:fpr(s1) = COPY %3(s1)
-    %4:fpr(s32) = G_SELECT %6(s1), %1, %2
+    %4:fpr(s32) = G_SELECT %5, %1, %2
     $s0 = COPY %4(s32)
     RET_ReallyLR implicit $s0
 
 ...
 ---
 name:            fune
 alignment:       4
 legalized:       true
bb.0:
     ; CHECK-NEXT: FCMPSri [[COPY]], implicit-def $nzcv
     ; CHECK-NEXT: [[FCSELSrrr:%[0-9]+]]:fpr32 = FCSELSrrr [[COPY1]], [[FMOVS0_]], 1, implicit $nzcv
     ; CHECK-NEXT: $s0 = COPY [[FCSELSrrr]]
     ; CHECK-NEXT: RET_ReallyLR implicit $s0
     %0:fpr(s32) = COPY $s0
     %1:fpr(s32) = COPY $s1
     %2:fpr(s32) = G_FCONSTANT float 0.000000e+00
     %5:gpr(s32) = G_FCMP floatpred(une), %0(s32), %2
-    %3:gpr(s1) = G_TRUNC %5(s32)
-    %6:fpr(s1) = COPY %3(s1)
-    %4:fpr(s32) = G_SELECT %6(s1), %1, %2
+    %4:fpr(s32) = G_SELECT %5, %1, %2
     $s0 = COPY %4(s32)
     RET_ReallyLR implicit $s0
 
 ...
 ---
 name:            doeq
 alignment:       4
 legalized:       true
bb.0:
     ; CHECK-NEXT: FCMPDri [[COPY]], implicit-def $nzcv
     ; CHECK-NEXT: [[FCSELDrrr:%[0-9]+]]:fpr64 = FCSELDrrr [[FMOVD0_]], [[COPY1]], 0, implicit $nzcv
     ; CHECK-NEXT: $d0 = COPY [[FCSELDrrr]]
     ; CHECK-NEXT: RET_ReallyLR implicit $d0
     %0:fpr(s64) = COPY $d0
     %1:fpr(s64) = COPY $d1
     %2:fpr(s64) = G_FCONSTANT double 0.000000e+00
     %5:gpr(s32) = G_FCMP floatpred(oeq), %0(s64), %2
-    %3:gpr(s1) = G_TRUNC %5(s32)
-    %6:fpr(s1) = COPY %3(s1)
-    %4:fpr(s64) = G_SELECT %6(s1), %2, %1
+    %4:fpr(s64) = G_SELECT %5, %2, %1
     $d0 = COPY %4(s64)
     RET_ReallyLR implicit $d0
 
 ...
 ---
 name:            dueq
 alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 body:             |
   bb.0:
     liveins: $d0, $d1
 
     ; CHECK-LABEL: name: dueq
     ; CHECK: liveins: $d0, $d1
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
     ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
     ; CHECK-NEXT: [[FMOVD0_:%[0-9]+]]:fpr64 = FMOVD0
     ; CHECK-NEXT: FCMPDri [[COPY]], implicit-def $nzcv
     ; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv
     ; CHECK-NEXT: [[CSINCWr1:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 7, implicit $nzcv
     ; CHECK-NEXT: [[ORRWrr:%[0-9]+]]:gpr32 = ORRWrr [[CSINCWr]], [[CSINCWr1]]
-    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr32 = COPY [[ORRWrr]]
-    ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr32 = COPY [[COPY2]]
-    ; CHECK-NEXT: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri [[COPY3]], 0, implicit-def $nzcv
+    ; CHECK-NEXT: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri [[ORRWrr]], 0, implicit-def $nzcv
     ; CHECK-NEXT: [[FCSELDrrr:%[0-9]+]]:fpr64 = FCSELDrrr [[FMOVD0_]], [[COPY1]], 1, implicit $nzcv
     ; CHECK-NEXT: $d0 = COPY [[FCSELDrrr]]
     ; CHECK-NEXT: RET_ReallyLR implicit $d0
     %0:fpr(s64) = COPY $d0
     %1:fpr(s64) = COPY $d1
     %2:fpr(s64) = G_FCONSTANT double 0.000000e+00
     %5:gpr(s32) = G_FCMP floatpred(ueq), %0(s64), %2
-    %3:gpr(s1) = G_TRUNC %5(s32)
-    %6:fpr(s1) = COPY %3(s1)
-    %4:fpr(s64) = G_SELECT %6(s1), %2, %1
+    %4:fpr(s64) = G_SELECT %5, %2, %1
     $d0 = COPY %4(s64)
     RET_ReallyLR implicit $d0
 
 ...
 ---
 name:            done
 alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 body:             |
   bb.0:
     liveins: $d0, $d1
 
     ; CHECK-LABEL: name: done
     ; CHECK: liveins: $d0, $d1
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
     ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
     ; CHECK-NEXT: [[FMOVD0_:%[0-9]+]]:fpr64 = FMOVD0
     ; CHECK-NEXT: FCMPDri [[COPY]], implicit-def $nzcv
     ; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 5, implicit $nzcv
     ; CHECK-NEXT: [[CSINCWr1:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 13, implicit $nzcv
     ; CHECK-NEXT: [[ORRWrr:%[0-9]+]]:gpr32 = ORRWrr [[CSINCWr]], [[CSINCWr1]]
-    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr32 = COPY [[ORRWrr]]
-    ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr32 = COPY [[COPY2]]
-    ; CHECK-NEXT: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri [[COPY3]], 0, implicit-def $nzcv
+    ; CHECK-NEXT: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri [[ORRWrr]], 0, implicit-def $nzcv
     ; CHECK-NEXT: [[FCSELDrrr:%[0-9]+]]:fpr64 = FCSELDrrr [[COPY1]], [[FMOVD0_]], 1, implicit $nzcv
     ; CHECK-NEXT: $d0 = COPY [[FCSELDrrr]]
     ; CHECK-NEXT: RET_ReallyLR implicit $d0
     %0:fpr(s64) = COPY $d0
     %1:fpr(s64) = COPY $d1
     %2:fpr(s64) = G_FCONSTANT double 0.000000e+00
     %5:gpr(s32) = G_FCMP floatpred(one), %0(s64), %2
-    %3:gpr(s1) = G_TRUNC %5(s32)
-    %6:fpr(s1) = COPY %3(s1)
-    %4:fpr(s64) = G_SELECT %6(s1), %1, %2
+    %4:fpr(s64) = G_SELECT %5, %1, %2
     $d0 = COPY %4(s64)
     RET_ReallyLR implicit $d0
 
 ...
 ---
 name:            dune
 alignment:       4
 legalized:       true
bb.0:
     ; CHECK-NEXT: FCMPDri [[COPY]], implicit-def $nzcv
     ; CHECK-NEXT: [[FCSELDrrr:%[0-9]+]]:fpr64 = FCSELDrrr [[COPY1]], [[FMOVD0_]], 1, implicit $nzcv
     ; CHECK-NEXT: $d0 = COPY [[FCSELDrrr]]
     ; CHECK-NEXT: RET_ReallyLR implicit $d0
     %0:fpr(s64) = COPY $d0
     %1:fpr(s64) = COPY $d1
     %2:fpr(s64) = G_FCONSTANT double 0.000000e+00
     %5:gpr(s32) = G_FCMP floatpred(une), %0(s64), %2
-    %3:gpr(s1) = G_TRUNC %5(s32)
-    %6:fpr(s1) = COPY %3(s1)
-    %4:fpr(s64) = G_SELECT %6(s1), %1, %2
+    %4:fpr(s64) = G_SELECT %5, %1, %2
     $d0 = COPY %4(s64)
     RET_ReallyLR implicit $d0
 
 ...
 ---
 name:            copy_from_physreg
 alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 body:             |
   bb.0:
     liveins: $s0, $w0, $w1
 
     ; CHECK-LABEL: name: copy_from_physreg
     ; CHECK: liveins: $s0, $w0, $w1
     ; CHECK-NEXT: {{  $}}
-    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
-    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $s0
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
     ; CHECK-NEXT: [[FMOVS0_:%[0-9]+]]:fpr32 = FMOVS0
     ; CHECK-NEXT: BL @copy_from_physreg, implicit-def $w0
-    ; CHECK-NEXT: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri [[COPY]], 0, implicit-def $nzcv
-    ; CHECK-NEXT: [[FCSELSrrr:%[0-9]+]]:fpr32 = FCSELSrrr [[COPY1]], [[FMOVS0_]], 1, implicit $nzcv
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY [[FMOVS0_]]
+    ; CHECK-NEXT: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri [[COPY1]], 0, implicit-def $nzcv
+    ; CHECK-NEXT: [[FCSELSrrr:%[0-9]+]]:fpr32 = FCSELSrrr [[COPY]], [[FMOVS0_]], 1, implicit $nzcv
     ; CHECK-NEXT: BL @copy_from_physreg, implicit-def $w0
     ; CHECK-NEXT: $s0 = COPY [[FCSELSrrr]]
     ; CHECK-NEXT: RET_ReallyLR implicit $s0
     %0:gpr(s32) = COPY $w0
     %1:fpr(s32) = COPY $s0
     %5:fpr(s32) = G_FCONSTANT float 0.000000e+00
     BL @copy_from_physreg, implicit-def $w0
-    %3:gpr(s1) = G_TRUNC %0(s32)
-    %4:fpr(s32) = G_SELECT %3(s1), %1, %5
+    %4:fpr(s32) = G_SELECT %5, %1, %5
     BL @copy_from_physreg, implicit-def $w0
     $s0 = COPY %4(s32)
     RET_ReallyLR implicit $s0
 
 ...

llvm/test/CodeGen/AArch64/GlobalISel/fold-select.mir

bb.0:
     ; CHECK-NEXT: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[COPY]], 0, 0, implicit-def $nzcv
     ; CHECK-NEXT: [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[COPY2]], [[COPY1]], 0, implicit $nzcv
     ; CHECK-NEXT: $w0 = COPY [[CSELWr]]
     ; CHECK-NEXT: RET_ReallyLR implicit $w0
     %0:gpr(s32) = COPY $w0
     %1:gpr(s32) = COPY $w1
     %2:gpr(s32) = G_CONSTANT i32 0
     %5:gpr(s32) = G_ICMP intpred(eq), %0(s32), %2
-    %3:gpr(s1) = G_TRUNC %5(s32)
-    %4:gpr(s32) = G_SELECT %3(s1), %2, %1
+    %4:gpr(s32) = G_SELECT %5, %2, %1
     $w0 = COPY %4(s32)
     RET_ReallyLR implicit $w0
 
 ...
 ---
 name:            using_fcmp
 alignment:       4
 legalized:       true
bb.0:
     ; CHECK-NEXT: [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[COPY2]], [[COPY]], 0, implicit $nzcv
     ; CHECK-NEXT: $w0 = COPY [[CSELWr]]
     ; CHECK-NEXT: RET_ReallyLR implicit $w0
     %1:gpr(s32) = COPY $w1
     %2:fpr(s32) = COPY $s0
     %3:fpr(s32) = G_FCONSTANT float 0.000000e+00
     %6:gpr(s32) = G_CONSTANT i32 0
     %7:gpr(s32) = G_FCMP floatpred(oeq), %2(s32), %3
-    %4:gpr(s1) = G_TRUNC %7(s32)
-    %5:gpr(s32) = G_SELECT %4(s1), %6, %1
+    %5:gpr(s32) = G_SELECT %7, %6, %1
     $w0 = COPY %5(s32)
     RET_ReallyLR implicit $w0
 
 ...
 ---
 name:            csinc
 alignment:       4
 legalized:       true
bb.0:
     ; CHECK-NEXT: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[COPY]], 1, 0, implicit-def $nzcv
     ; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr [[COPY]], $wzr, 0, implicit $nzcv
     ; CHECK-NEXT: $w0 = COPY [[CSINCWr]]
     ; CHECK-NEXT: RET_ReallyLR implicit $w0
     %0:gpr(s32) = COPY $w0
     %1:gpr(s32) = COPY $w1
     %2:gpr(s32) = G_CONSTANT i32 1
     %5:gpr(s32) = G_ICMP intpred(eq), %0(s32), %2
-    %3:gpr(s1) = G_TRUNC %5(s32)
-    %4:gpr(s32) = G_SELECT %3(s1), %0, %2
+    %4:gpr(s32) = G_SELECT %5, %0, %2
     $w0 = COPY %4(s32)
     RET_ReallyLR implicit $w0
 ...

llvm/test/CodeGen/AArch64/GlobalISel/huge-switch.ll

 ; RUN: llc -mtriple=arm64-apple-ios %s -o - -O0 -global-isel=1 | FileCheck %s
 define void @foo(i512 %in) {
 ; CHECK-LABEL: foo:
-; CHECK: cbz
+; CHECK: subs
+; CHECK-NEXT: cset
+; CHECK-NEXT: tbnz
   switch i512 %in, label %default [
     i512 3923188584616675477397368389504791510063972152790021570560, label %l1
     i512 3923188584616675477397368389504791510063972152790021570561, label %l2
     i512 3923188584616675477397368389504791510063972152790021570562, label %l3
   ]
 
 default:
   ret void

llvm/test/CodeGen/AArch64/GlobalISel/legalize-add.mir

 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -march=aarch64 -run-pass=legalizer %s -o - | FileCheck %s
 ---
 name:            test_scalar_add_big
 body:             |
   bb.0.entry:
     ; CHECK-LABEL: name: test_scalar_add_big
     ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
     ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
     ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
     ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
-    ; CHECK-NEXT: [[UADDO:%[0-9]+]]:_(s64), [[UADDO1:%[0-9]+]]:_(s1) = G_UADDO [[COPY]], [[COPY2]]
-    ; CHECK-NEXT: [[UADDE:%[0-9]+]]:_(s64), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[COPY1]], [[COPY3]], [[UADDO1]]
+    ; CHECK-NEXT: [[UADDO:%[0-9]+]]:_(s64), [[UADDO1:%[0-9]+]]:_(s32) = G_UADDO [[COPY]], [[COPY2]]
+    ; CHECK-NEXT: [[UADDE:%[0-9]+]]:_(s64), [[UADDE1:%[0-9]+]]:_(s32) = G_UADDE [[COPY1]], [[COPY3]], %18
+    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[UADDO1]], [[C]]
     ; CHECK-NEXT: $x0 = COPY [[UADDO]](s64)
     ; CHECK-NEXT: $x1 = COPY [[UADDE]](s64)
     %0:_(s64) = COPY $x0
     %1:_(s64) = COPY $x1
     %2:_(s64) = COPY $x2
     %3:_(s64) = COPY $x3
     %4:_(s128) = G_MERGE_VALUES %0(s64), %1(s64)
     %5:_(s128) = G_MERGE_VALUES %2(s64), %3(s64)
     %6:_(s128) = G_ADD %4, %5
     %7:_(s64), %8:_(s64) = G_UNMERGE_VALUES %6(s128)
     $x0 = COPY %7(s64)
     $x1 = COPY %8(s64)
 
 ...
 ---
 name:            test_scalar_add_big_nonpow2
 body:             |
   bb.0.entry:
     ; CHECK-LABEL: name: test_scalar_add_big_nonpow2
     ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
     ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
     ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
     ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
-    ; CHECK-NEXT: [[UADDO:%[0-9]+]]:_(s64), [[UADDO1:%[0-9]+]]:_(s1) = G_UADDO [[COPY]], [[COPY1]]
-    ; CHECK-NEXT: [[UADDE:%[0-9]+]]:_(s64), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[COPY1]], [[COPY2]], [[UADDO1]]
-    ; CHECK-NEXT: [[UADDE2:%[0-9]+]]:_(s64), [[UADDE3:%[0-9]+]]:_(s1) = G_UADDE [[COPY2]], [[COPY3]], [[UADDE1]]
+    ; CHECK-NEXT: [[UADDO:%[0-9]+]]:_(s64), [[UADDO1:%[0-9]+]]:_(s32) = G_UADDO [[COPY]], [[COPY1]]
+    ; CHECK-NEXT: [[UADDE:%[0-9]+]]:_(s64), [[UADDE1:%[0-9]+]]:_(s32) = G_UADDE [[COPY1]], [[COPY2]], %34
+    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[UADDO1]], [[C]]
+    ; CHECK-NEXT: [[UADDE2:%[0-9]+]]:_(s64), [[UADDE3:%[0-9]+]]:_(s32) = G_UADDE [[COPY2]], [[COPY3]], %32
+    ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[UADDE1]], [[C]]
     ; CHECK-NEXT: $x0 = COPY [[UADDO]](s64)
     ; CHECK-NEXT: $x1 = COPY [[UADDE]](s64)
     ; CHECK-NEXT: $x2 = COPY [[UADDE2]](s64)
     %0:_(s64) = COPY $x0
     %1:_(s64) = COPY $x1
     %2:_(s64) = COPY $x2
     %3:_(s64) = COPY $x3
     %4:_(s192) = G_MERGE_VALUES %0(s64), %1(s64), %2(s64)

 name:            test_scalar_add_narrowing
 body:             |
   bb.0.entry:
     ; CHECK-LABEL: name: test_scalar_add_narrowing
     ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
     ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
     ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
     ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
-    ; CHECK-NEXT: [[UADDO:%[0-9]+]]:_(s64), [[UADDO1:%[0-9]+]]:_(s1) = G_UADDO [[COPY]], [[COPY2]]
-    ; CHECK-NEXT: [[UADDE:%[0-9]+]]:_(s64), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[COPY1]], [[COPY3]], [[UADDO1]]
+    ; CHECK-NEXT: [[UADDO:%[0-9]+]]:_(s64), [[UADDO1:%[0-9]+]]:_(s32) = G_UADDO [[COPY]], [[COPY2]]
+    ; CHECK-NEXT: [[UADDE:%[0-9]+]]:_(s64), [[UADDE1:%[0-9]+]]:_(s32) = G_UADDE [[COPY1]], [[COPY3]], %24
+    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[UADDO1]], [[C]]
     ; CHECK-NEXT: $x0 = COPY [[UADDO]](s64)
     ; CHECK-NEXT: $x1 = COPY [[UADDE]](s64)
     %0:_(s64) = COPY $x0
     %1:_(s64) = COPY $x1
     %2:_(s64) = COPY $x2
     %3:_(s64) = COPY $x3
     %4:_(s128) = G_MERGE_VALUES %0(s64), %1(s64)
     %5:_(s128) = G_MERGE_VALUES %2(s64), %3(s64)

 name:            test_scalar_add_narrowing_s65
 body:             |
   bb.0.entry:
     ; CHECK-LABEL: name: test_scalar_add_narrowing_s65
     ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
     ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
     ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
     ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
-    ; CHECK-NEXT: [[UADDO:%[0-9]+]]:_(s64), [[UADDO1:%[0-9]+]]:_(s1) = G_UADDO [[COPY]], [[COPY2]]
-    ; CHECK-NEXT: [[UADDE:%[0-9]+]]:_(s64), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[COPY1]], [[COPY3]], [[UADDO1]]
+    ; CHECK-NEXT: [[UADDO:%[0-9]+]]:_(s64), [[UADDO1:%[0-9]+]]:_(s32) = G_UADDO [[COPY]], [[COPY2]]
+    ; CHECK-NEXT: [[UADDE:%[0-9]+]]:_(s64), [[UADDE1:%[0-9]+]]:_(s32) = G_UADDE [[COPY1]], [[COPY3]], %24
+    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[UADDO1]], [[C]]
     ; CHECK-NEXT: $x0 = COPY [[UADDO]](s64)
     ; CHECK-NEXT: $x1 = COPY [[UADDE]](s64)
     %0:_(s64) = COPY $x0
     %1:_(s64) = COPY $x1
     %2:_(s64) = COPY $x2
     %3:_(s64) = COPY $x3
     %4:_(s128) = G_MERGE_VALUES %0(s64), %1(s64)
     %5:_(s128) = G_MERGE_VALUES %2(s64), %3(s64)

llvm/test/CodeGen/AArch64/GlobalISel/legalize-build-vector.mir

bb.0:
     RET_ReallyLR
 ...
 ---
 name:            widen_v16s1
 body: |
   bb.0:
     ; CHECK-LABEL: name: widen_v16s1
     ; CHECK: [[DEF:%[0-9]+]]:_(s8) = G_IMPLICIT_DEF
-    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s8) = COPY [[DEF]](s8)
-    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s8) = COPY [[DEF]](s8)
-    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s8) = COPY [[DEF]](s8)
-    ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s8) = COPY [[DEF]](s8)
-    ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(s8) = COPY [[DEF]](s8)
-    ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(s8) = COPY [[DEF]](s8)
-    ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(s8) = COPY [[DEF]](s8)
-    ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(s8) = COPY [[DEF]](s8)
-    ; CHECK-NEXT: [[COPY8:%[0-9]+]]:_(s8) = COPY [[DEF]](s8)
-    ; CHECK-NEXT: [[COPY9:%[0-9]+]]:_(s8) = COPY [[DEF]](s8)
-    ; CHECK-NEXT: [[COPY10:%[0-9]+]]:_(s8) = COPY [[DEF]](s8)
-    ; CHECK-NEXT: [[COPY11:%[0-9]+]]:_(s8) = COPY [[DEF]](s8)
-    ; CHECK-NEXT: [[COPY12:%[0-9]+]]:_(s8) = COPY [[DEF]](s8)
-    ; CHECK-NEXT: [[COPY13:%[0-9]+]]:_(s8) = COPY [[DEF]](s8)
-    ; CHECK-NEXT: [[COPY14:%[0-9]+]]:_(s8) = COPY [[DEF]](s8)
-    ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<16 x s8>) = G_BUILD_VECTOR [[COPY]](s8), [[COPY1]](s8), [[COPY2]](s8), [[COPY3]](s8), [[COPY4]](s8), [[COPY5]](s8), [[COPY6]](s8), [[COPY7]](s8), [[COPY8]](s8), [[COPY9]](s8), [[COPY10]](s8), [[COPY11]](s8), [[COPY12]](s8), [[COPY13]](s8), [[COPY14]](s8), [[DEF]](s8)
+    ; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(s8) = G_IMPLICIT_DEF
+    ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<16 x s8>) = G_BUILD_VECTOR [[DEF]](s8), [[DEF1]](s8), [[DEF]](s8), [[DEF1]](s8), [[DEF]](s8), [[DEF1]](s8), [[DEF]](s8), [[DEF1]](s8), [[DEF]](s8), [[DEF1]](s8), [[DEF]](s8), [[DEF1]](s8), [[DEF]](s8), [[DEF1]](s8), [[DEF]](s8), [[DEF1]](s8)
     ; CHECK-NEXT: $q0 = COPY [[BUILD_VECTOR]](<16 x s8>)
     ; CHECK-NEXT: RET_ReallyLR
     %0:_(s1) = G_IMPLICIT_DEF
     %1:_(s1) = G_IMPLICIT_DEF
     %2:_(<16 x s1>) = G_BUILD_VECTOR %0(s1), %1(s1), %0(s1), %1(s1), %0(s1), %1(s1), %0(s1), %1(s1), %0(s1), %1(s1), %0(s1), %1(s1), %0(s1), %1(s1), %0(s1), %1(s1)
     %w:_(<16 x s8>) = G_ANYEXT %2
     $q0 = COPY %w(<16 x s8>)
     RET_ReallyLR
 ...

llvm/test/CodeGen/AArch64/GlobalISel/legalize-cmp.mir

body:             |
   ; CHECK: bb.0:
   ; CHECK-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT:   [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
   ; CHECK-NEXT:   [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
   ; CHECK-NEXT:   [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967296
   ; CHECK-NEXT:   [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[DEF]](s64), [[C1]]
   ; CHECK-NEXT:   [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[DEF]](s64), [[C1]]
-  ; CHECK-NEXT:   [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP1]](s32)
   ; CHECK-NEXT:   [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[DEF]](s64), [[C]]
-  ; CHECK-NEXT:   [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[TRUNC]](s1), [[ICMP2]], [[ICMP]]
-  ; CHECK-NEXT:   [[TRUNC1:%[0-9]+]]:_(s1) = G_TRUNC [[SELECT]](s32)
-  ; CHECK-NEXT:   G_BRCOND [[TRUNC1]](s1), %bb.1
+  ; CHECK-NEXT:   [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+  ; CHECK-NEXT:   [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP1]], [[C2]]
+  ; CHECK-NEXT:   [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[ICMP2]], [[ICMP]]
+  ; CHECK-NEXT:   [[AND1:%[0-9]+]]:_(s32) = G_AND [[SELECT]], [[C2]]
+  ; CHECK-NEXT:   G_BRCOND [[AND1]](s32), %bb.1
   ; CHECK-NEXT:   G_BR %bb.2
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT: bb.1:
   ; CHECK-NEXT:   successors:
   ; CHECK: bb.2:
   ; CHECK-NEXT:   RET_ReallyLR
   bb.1:
     %0:_(s128) = G_IMPLICIT_DEF
body:             |
   ; CHECK-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT:   [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
   ; CHECK-NEXT:   [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
   ; CHECK-NEXT:   [[XOR:%[0-9]+]]:_(s64) = G_XOR [[DEF]], [[DEF]]
   ; CHECK-NEXT:   [[XOR1:%[0-9]+]]:_(s64) = G_XOR [[DEF]], [[DEF]]
   ; CHECK-NEXT:   [[OR:%[0-9]+]]:_(s64) = G_OR [[XOR]], [[XOR1]]
   ; CHECK-NEXT:   [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[OR]](s64), [[C]]
-  ; CHECK-NEXT:   %cmp:_(s1) = G_TRUNC [[ICMP]](s32)
-  ; CHECK-NEXT:   G_BRCOND %cmp(s1), %bb.1
+  ; CHECK-NEXT:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+  ; CHECK-NEXT:   [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C1]]
+  ; CHECK-NEXT:   G_BRCOND [[AND]](s32), %bb.1
   ; CHECK-NEXT:   G_BR %bb.2
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT: bb.1:
   ; CHECK-NEXT:   successors:
   ; CHECK: bb.2:
   ; CHECK-NEXT:   RET_ReallyLR
   bb.1:
     %lhs:_(s128) = G_IMPLICIT_DEF
body:             |
   ; CHECK-NEXT:   [[AND1:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C1]]
   ; CHECK-NEXT:   [[AND2:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C]]
   ; CHECK-NEXT:   [[AND3:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C1]]
   ; CHECK-NEXT:   [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
   ; CHECK-NEXT:   [[XOR:%[0-9]+]]:_(s64) = G_XOR [[AND]], [[AND2]]
   ; CHECK-NEXT:   [[XOR1:%[0-9]+]]:_(s64) = G_XOR [[AND1]], [[AND3]]
   ; CHECK-NEXT:   [[OR:%[0-9]+]]:_(s64) = G_OR [[XOR]], [[XOR1]]
   ; CHECK-NEXT:   [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[OR]](s64), [[C2]]
-  ; CHECK-NEXT:   %cmp:_(s1) = G_TRUNC [[ICMP]](s32)
-  ; CHECK-NEXT:   G_BRCOND %cmp(s1), %bb.1
+  ; CHECK-NEXT:   [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+  ; CHECK-NEXT:   [[AND4:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C3]]
+  ; CHECK-NEXT:   G_BRCOND [[AND4]](s32), %bb.1
   ; CHECK-NEXT:   G_BR %bb.2
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT: bb.1:
   ; CHECK-NEXT:   successors:
   ; CHECK: bb.2:
   ; CHECK-NEXT:   RET_ReallyLR
   bb.1:
     %lhs:_(s88) = G_IMPLICIT_DEF
body:             |
   ; CHECK-NEXT:   [[AND1:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C1]]
   ; CHECK-NEXT:   [[AND2:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C]]
   ; CHECK-NEXT:   [[AND3:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C1]]
   ; CHECK-NEXT:   [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
   ; CHECK-NEXT:   [[XOR:%[0-9]+]]:_(s64) = G_XOR [[AND]], [[AND2]]
   ; CHECK-NEXT:   [[XOR1:%[0-9]+]]:_(s64) = G_XOR [[AND1]], [[AND3]]
   ; CHECK-NEXT:   [[OR:%[0-9]+]]:_(s64) = G_OR [[XOR]], [[XOR1]]
   ; CHECK-NEXT:   [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[OR]](s64), [[C2]]
-  ; CHECK-NEXT:   %cmp:_(s1) = G_TRUNC [[ICMP]](s32)
-  ; CHECK-NEXT:   G_BRCOND %cmp(s1), %bb.1
+  ; CHECK-NEXT:   [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+  ; CHECK-NEXT:   [[AND4:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C3]]
+  ; CHECK-NEXT:   G_BRCOND [[AND4]](s32), %bb.1
   ; CHECK-NEXT:   G_BR %bb.2
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT: bb.1:
   ; CHECK-NEXT:   successors:
   ; CHECK: bb.2:
   ; CHECK-NEXT:   RET_ReallyLR
   bb.1:
     %lhs:_(s88) = G_IMPLICIT_DEF
body:             |
   ; CHECK-NEXT:   [[AND1:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C1]]
   ; CHECK-NEXT:   [[AND2:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C]]
   ; CHECK-NEXT:   [[AND3:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C1]]
   ; CHECK-NEXT:   [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
   ; CHECK-NEXT:   [[XOR:%[0-9]+]]:_(s64) = G_XOR [[AND]], [[AND2]]
   ; CHECK-NEXT:   [[XOR1:%[0-9]+]]:_(s64) = G_XOR [[AND1]], [[AND3]]
   ; CHECK-NEXT:   [[OR:%[0-9]+]]:_(s64) = G_OR [[XOR]], [[XOR1]]
   ; CHECK-NEXT:   [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[OR]](s64), [[C2]]
-  ; CHECK-NEXT:   %cmp:_(s1) = G_TRUNC [[ICMP]](s32)
-  ; CHECK-NEXT:   G_BRCOND %cmp(s1), %bb.1
+  ; CHECK-NEXT:   [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+  ; CHECK-NEXT:   [[AND4:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C3]]
+  ; CHECK-NEXT:   G_BRCOND [[AND4]](s32), %bb.1
   ; CHECK-NEXT:   G_BR %bb.2
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT: bb.1:
   ; CHECK-NEXT:   successors:
   ; CHECK: bb.2:
   ; CHECK-NEXT:   RET_ReallyLR
   bb.1:
     %lhs:_(s96) = G_IMPLICIT_DEF
body:             |
   ; CHECK-NEXT:   [[OR:%[0-9]+]]:_(s64) = G_OR [[XOR]], [[XOR1]]
   ; CHECK-NEXT:   [[OR1:%[0-9]+]]:_(s64) = G_OR [[OR]], [[XOR2]]
   ; CHECK-NEXT:   [[OR2:%[0-9]+]]:_(s64) = G_OR [[OR1]], [[XOR3]]
   ; CHECK-NEXT:   [[OR3:%[0-9]+]]:_(s64) = G_OR [[OR2]], [[XOR4]]
   ; CHECK-NEXT:   [[OR4:%[0-9]+]]:_(s64) = G_OR [[OR3]], [[XOR5]]
   ; CHECK-NEXT:   [[OR5:%[0-9]+]]:_(s64) = G_OR [[OR4]], [[XOR6]]
   ; CHECK-NEXT:   [[OR6:%[0-9]+]]:_(s64) = G_OR [[OR5]], [[XOR7]]
   ; CHECK-NEXT:   [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[OR6]](s64), [[C2]]
-  ; CHECK-NEXT:   %cmp:_(s1) = G_TRUNC [[ICMP]](s32)
-  ; CHECK-NEXT:   G_BRCOND %cmp(s1), %bb.1
+  ; CHECK-NEXT:   [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+  ; CHECK-NEXT:   [[AND16:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C3]]
+  ; CHECK-NEXT:   G_BRCOND [[AND16]](s32), %bb.1
   ; CHECK-NEXT:   G_BR %bb.2
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT: bb.1:
   ; CHECK-NEXT:   successors:
   ; CHECK: bb.2:
   ; CHECK-NEXT:   RET_ReallyLR
   bb.1:
     %lhs:_(s318) = G_IMPLICIT_DEF
body:             |
   ; CHECK-NEXT:   [[XOR:%[0-9]+]]:_(s64) = G_XOR [[AND]], [[AND4]]
   ; CHECK-NEXT:   [[XOR1:%[0-9]+]]:_(s64) = G_XOR [[AND1]], [[AND5]]
   ; CHECK-NEXT:   [[XOR2:%[0-9]+]]:_(s64) = G_XOR [[AND2]], [[AND6]]
   ; CHECK-NEXT:   [[XOR3:%[0-9]+]]:_(s64) = G_XOR [[AND3]], [[AND7]]
   ; CHECK-NEXT:   [[OR:%[0-9]+]]:_(s64) = G_OR [[XOR]], [[XOR1]]
   ; CHECK-NEXT:   [[OR1:%[0-9]+]]:_(s64) = G_OR [[OR]], [[XOR2]]
   ; CHECK-NEXT:   [[OR2:%[0-9]+]]:_(s64) = G_OR [[OR1]], [[XOR3]]
   ; CHECK-NEXT:   [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[OR2]](s64), [[C2]]
-  ; CHECK-NEXT:   %cmp:_(s1) = G_TRUNC [[ICMP]](s32)
-  ; CHECK-NEXT:   G_BRCOND %cmp(s1), %bb.1
+  ; CHECK-NEXT:   [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+  ; CHECK-NEXT:   [[AND8:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C3]]
+  ; CHECK-NEXT:   G_BRCOND [[AND8]](s32), %bb.1
   ; CHECK-NEXT:   G_BR %bb.2
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT: bb.1:
   ; CHECK-NEXT:   successors:
   ; CHECK: bb.2:
   ; CHECK-NEXT:   RET_ReallyLR
   bb.1:
     %lhs:_(s158) = G_IMPLICIT_DEF
     %rhs:_(s158) = G_IMPLICIT_DEF
     %cmp:_(s1) = G_ICMP intpred(eq), %lhs(s158), %rhs
     G_BRCOND %cmp(s1), %bb.2
     G_BR %bb.3
   bb.2:
     successors:
   bb.3:
     RET_ReallyLR

llvm/test/CodeGen/AArch64/GlobalISel/legalize-freeze.mir

bb.0:
     $w1 = COPY %2
 ...
 ---
 name:            test_freeze_s1
 body: |
   bb.0.entry:
     liveins: $x0
     ; CHECK-LABEL: name: test_freeze_s1
-    ; CHECK: %x:_(s1) = G_IMPLICIT_DEF
-    ; CHECK-NEXT: %freeze:_(s1) = G_FREEZE %x
-    ; CHECK-NEXT: %ext:_(s64) = G_ZEXT %freeze(s1)
+    ; CHECK: [[DEF:%[0-9]+]]:_(s8) = G_IMPLICIT_DEF
+    ; CHECK-NEXT: [[FREEZE:%[0-9]+]]:_(s8) = G_FREEZE [[DEF]]
+    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+    ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[FREEZE]](s8)
+    ; CHECK-NEXT: %ext:_(s64) = G_AND [[ANYEXT]], [[C]]
     ; CHECK-NEXT: $x0 = COPY %ext(s64)
     %x:_(s1) = G_IMPLICIT_DEF
     %freeze:_(s1) = G_FREEZE %x
     %ext:_(s64) = G_ZEXT %freeze
     $x0 = COPY %ext(s64)
 ...
 ---
 name:            test_freeze_s2

llvm/test/CodeGen/AArch64/GlobalISel/legalize-inserts.mir

bb.0:
     ; CHECK-NEXT: [[AND62:%[0-9]+]]:_(s32) = G_AND [[LSHR54]], [[C7]]
     ; CHECK-NEXT: [[SHL54:%[0-9]+]]:_(s32) = G_SHL [[AND62]], [[C5]](s64)
     ; CHECK-NEXT: [[OR54:%[0-9]+]]:_(s32) = G_OR [[OR53]], [[SHL54]]
     ; CHECK-NEXT: [[AND63:%[0-9]+]]:_(s32) = G_AND [[LSHR55]], [[C7]]
     ; CHECK-NEXT: [[SHL55:%[0-9]+]]:_(s32) = G_SHL [[AND63]], [[C6]](s64)
     ; CHECK-NEXT: [[OR55:%[0-9]+]]:_(s32) = G_OR [[OR54]], [[SHL55]]
     ; CHECK-NEXT: [[TRUNC7:%[0-9]+]]:_(s8) = G_TRUNC [[OR55]](s32)
     ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[TRUNC]](s8), [[TRUNC1]](s8), [[TRUNC2]](s8), [[TRUNC3]](s8), [[TRUNC4]](s8), [[TRUNC5]](s8), [[TRUNC6]](s8), [[TRUNC7]](s8)
-    ; CHECK-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
-    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
-    ; CHECK-NEXT: [[SHL56:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s64)
+    ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
+    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
+    ; CHECK-NEXT: [[AND64:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C7]]
+    ; CHECK-NEXT: [[SHL56:%[0-9]+]]:_(s32) = G_SHL [[AND64]], [[C]](s64)
     ; CHECK-NEXT: [[TRUNC8:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
-    ; CHECK-NEXT: [[AND64:%[0-9]+]]:_(s32) = G_AND [[TRUNC8]], [[C7]]
-    ; CHECK-NEXT: [[OR56:%[0-9]+]]:_(s32) = G_OR [[AND64]], [[SHL56]]
-    ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
-    ; CHECK-NEXT: [[SHL57:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C1]](s64)
+    ; CHECK-NEXT: [[AND65:%[0-9]+]]:_(s32) = G_AND [[TRUNC8]], [[C7]]
+    ; CHECK-NEXT: [[OR56:%[0-9]+]]:_(s32) = G_OR [[AND65]], [[SHL56]]
+    ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
+    ; CHECK-NEXT: [[AND66:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C7]]
+    ; CHECK-NEXT: [[SHL57:%[0-9]+]]:_(s32) = G_SHL [[AND66]], [[C1]](s64)
     ; CHECK-NEXT: [[OR57:%[0-9]+]]:_(s32) = G_OR [[OR56]], [[SHL57]]
-    ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
-    ; CHECK-NEXT: [[SHL58:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C2]](s64)
+    ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
+    ; CHECK-NEXT: [[AND67:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C7]]
+    ; CHECK-NEXT: [[SHL58:%[0-9]+]]:_(s32) = G_SHL [[AND67]], [[C2]](s64)
     ; CHECK-NEXT: [[OR58:%[0-9]+]]:_(s32) = G_OR [[OR57]], [[SHL58]]
-    ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
-    ; CHECK-NEXT: [[SHL59:%[0-9]+]]:_(s32) = G_SHL [[COPY5]], [[C3]](s64)
+    ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
+    ; CHECK-NEXT: [[AND68:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C7]]
+    ; CHECK-NEXT: [[SHL59:%[0-9]+]]:_(s32) = G_SHL [[AND68]], [[C3]](s64)
     ; CHECK-NEXT: [[OR59:%[0-9]+]]:_(s32) = G_OR [[OR58]], [[SHL59]]
-    ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
-    ; CHECK-NEXT: [[SHL60:%[0-9]+]]:_(s32) = G_SHL [[COPY6]], [[C4]](s64)
+    ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
+    ; CHECK-NEXT: [[AND69:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C7]]
+    ; CHECK-NEXT: [[SHL60:%[0-9]+]]:_(s32) = G_SHL [[AND69]], [[C4]](s64)
     ; CHECK-NEXT: [[OR60:%[0-9]+]]:_(s32) = G_OR [[OR59]], [[SHL60]]
-    ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
-    ; CHECK-NEXT: [[SHL61:%[0-9]+]]:_(s32) = G_SHL [[COPY7]], [[C5]](s64)
+    ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
+    ; CHECK-NEXT: [[AND70:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C7]]
+    ; CHECK-NEXT: [[SHL61:%[0-9]+]]:_(s32) = G_SHL [[AND70]], [[C5]](s64)
     ; CHECK-NEXT: [[OR61:%[0-9]+]]:_(s32) = G_OR [[OR60]], [[SHL61]]
-    ; CHECK-NEXT: [[COPY8:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
-    ; CHECK-NEXT: [[SHL62:%[0-9]+]]:_(s32) = G_SHL [[COPY8]], [[C6]](s64)
+    ; CHECK-NEXT: [[COPY8:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
+    ; CHECK-NEXT: [[AND71:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C7]]
+    ; CHECK-NEXT: [[SHL62:%[0-9]+]]:_(s32) = G_SHL [[AND71]], [[C6]](s64)
     ; CHECK-NEXT: [[OR62:%[0-9]+]]:_(s32) = G_OR [[OR61]], [[SHL62]]
     ; CHECK-NEXT: [[TRUNC9:%[0-9]+]]:_(s8) = G_TRUNC [[OR62]](s32)
-    ; CHECK-NEXT: [[COPY9:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
-    ; CHECK-NEXT: [[SHL63:%[0-9]+]]:_(s32) = G_SHL [[COPY9]], [[C]](s64)
-    ; CHECK-NEXT: [[COPY10:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
-    ; CHECK-NEXT: [[OR63:%[0-9]+]]:_(s32) = G_OR [[COPY10]], [[SHL63]]
-    ; CHECK-NEXT: [[COPY11:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
-    ; CHECK-NEXT: [[SHL64:%[0-9]+]]:_(s32) = G_SHL [[COPY11]], [[C1]](s64)
+    ; CHECK-NEXT: [[COPY9:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
+    ; CHECK-NEXT: [[AND72:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C7]]
+    ; CHECK-NEXT: [[SHL63:%[0-9]+]]:_(s32) = G_SHL [[AND72]], [[C]](s64)
+    ; CHECK-NEXT: [[COPY10:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
+    ; CHECK-NEXT: [[AND73:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C7]]
+    ; CHECK-NEXT: [[OR63:%[0-9]+]]:_(s32) = G_OR [[AND73]], [[SHL63]]
+    ; CHECK-NEXT: [[COPY11:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
+    ; CHECK-NEXT: [[AND74:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C7]]
+    ; CHECK-NEXT: [[SHL64:%[0-9]+]]:_(s32) = G_SHL [[AND74]], [[C1]](s64)
     ; CHECK-NEXT: [[OR64:%[0-9]+]]:_(s32) = G_OR [[OR63]], [[SHL64]]
-    ; CHECK-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
-    ; CHECK-NEXT: [[SHL65:%[0-9]+]]:_(s32) = G_SHL [[COPY12]], [[C2]](s64)
+    ; CHECK-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
+    ; CHECK-NEXT: [[AND75:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C7]]
+    ; CHECK-NEXT: [[SHL65:%[0-9]+]]:_(s32) = G_SHL [[AND75]], [[C2]](s64)
     ; CHECK-NEXT: [[OR65:%[0-9]+]]:_(s32) = G_OR [[OR64]], [[SHL65]]
-    ; CHECK-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
-    ; CHECK-NEXT: [[SHL66:%[0-9]+]]:_(s32) = G_SHL [[COPY13]], [[C3]](s64)
+    ; CHECK-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
+    ; CHECK-NEXT: [[AND76:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C7]]
+    ; CHECK-NEXT: [[SHL66:%[0-9]+]]:_(s32) = G_SHL [[AND76]], [[C3]](s64)
     ; CHECK-NEXT: [[OR66:%[0-9]+]]:_(s32) = G_OR [[OR65]], [[SHL66]]
-    ; CHECK-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
-    ; CHECK-NEXT: [[SHL67:%[0-9]+]]:_(s32) = G_SHL [[COPY14]], [[C4]](s64)
+    ; CHECK-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
+    ; CHECK-NEXT: [[AND77:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C7]]
+    ; CHECK-NEXT: [[SHL67:%[0-9]+]]:_(s32) = G_SHL [[AND77]], [[C4]](s64)
     ; CHECK-NEXT: [[OR67:%[0-9]+]]:_(s32) = G_OR [[OR66]], [[SHL67]]
-    ; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
-    ; CHECK-NEXT: [[SHL68:%[0-9]+]]:_(s32) = G_SHL [[COPY15]], [[C5]](s64)
+    ; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
+    ; CHECK-NEXT: [[AND78:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C7]]
+    ; CHECK-NEXT: [[SHL68:%[0-9]+]]:_(s32) = G_SHL [[AND78]], [[C5]](s64)
     ; CHECK-NEXT: [[OR68:%[0-9]+]]:_(s32) = G_OR [[OR67]], [[SHL68]]
-    ; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
-    ; CHECK-NEXT: [[SHL69:%[0-9]+]]:_(s32) = G_SHL [[COPY16]], [[C6]](s64)
+    ; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
+    ; CHECK-NEXT: [[AND79:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C7]]
+    ; CHECK-NEXT: [[SHL69:%[0-9]+]]:_(s32) = G_SHL [[AND79]], [[C6]](s64)
     ; CHECK-NEXT: [[OR69:%[0-9]+]]:_(s32) = G_OR [[OR68]], [[SHL69]]
     ; CHECK-NEXT: [[TRUNC10:%[0-9]+]]:_(s8) = G_TRUNC [[OR69]](s32)
-    ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
-    ; CHECK-NEXT: [[SHL70:%[0-9]+]]:_(s32) = G_SHL [[COPY17]], [[C]](s64)
-    ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
-    ; CHECK-NEXT: [[OR70:%[0-9]+]]:_(s32) = G_OR [[COPY18]], [[SHL70]]
-    ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
-    ; CHECK-NEXT: [[SHL71:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C1]](s64)
+    ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
+    ; CHECK-NEXT: [[AND80:%[0-9]+]]:_(s32) = G_AND [[COPY17]], [[C7]]
+    ; CHECK-NEXT: [[SHL70:%[0-9]+]]:_(s32) = G_SHL [[AND80]], [[C]](s64)
+    ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
+    ; CHECK-NEXT: [[AND81:%[0-9]+]]:_(s32) = G_AND [[COPY18]], [[C7]]
+    ; CHECK-NEXT: [[OR70:%[0-9]+]]:_(s32) = G_OR [[AND81]], [[SHL70]]
+    ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
+    ; CHECK-NEXT: [[AND82:%[0-9]+]]:_(s32) = G_AND [[COPY19]], [[C7]]
+    ; CHECK-NEXT: [[SHL71:%[0-9]+]]:_(s32) = G_SHL [[AND82]], [[C1]](s64)
     ; CHECK-NEXT: [[OR71:%[0-9]+]]:_(s32) = G_OR [[OR70]], [[SHL71]]
-    ; CHECK-NEXT: [[COPY20:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
-    ; CHECK-NEXT: [[SHL72:%[0-9]+]]:_(s32) = G_SHL [[COPY20]], [[C2]](s64)
+    ; CHECK-NEXT: [[COPY20:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
+    ; CHECK-NEXT: [[AND83:%[0-9]+]]:_(s32) = G_AND [[COPY20]], [[C7]]
+    ; CHECK-NEXT: [[SHL72:%[0-9]+]]:_(s32) = G_SHL [[AND83]], [[C2]](s64)
     ; CHECK-NEXT: [[OR72:%[0-9]+]]:_(s32) = G_OR [[OR71]], [[SHL72]]
-    ; CHECK-NEXT: [[COPY21:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
-    ; CHECK-NEXT: [[SHL73:%[0-9]+]]:_(s32) = G_SHL [[COPY21]], [[C3]](s64)
+    ; CHECK-NEXT: [[COPY21:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
+    ; CHECK-NEXT: [[AND84:%[0-9]+]]:_(s32) = G_AND [[COPY21]], [[C7]]
+    ; CHECK-NEXT: [[SHL73:%[0-9]+]]:_(s32) = G_SHL [[AND84]], [[C3]](s64)
     ; CHECK-NEXT: [[OR73:%[0-9]+]]:_(s32) = G_OR [[OR72]], [[SHL73]]
-    ; CHECK-NEXT: [[COPY22:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
-    ; CHECK-NEXT: [[SHL74:%[0-9]+]]:_(s32) = G_SHL [[COPY22]], [[C4]](s64)
+    ; CHECK-NEXT: [[COPY22:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
+    ; CHECK-NEXT: [[AND85:%[0-9]+]]:_(s32) = G_AND [[COPY22]], [[C7]]
+    ; CHECK-NEXT: [[SHL74:%[0-9]+]]:_(s32) = G_SHL [[AND85]], [[C4]](s64)
     ; CHECK-NEXT: [[OR74:%[0-9]+]]:_(s32) = G_OR [[OR73]], [[SHL74]]
-    ; CHECK-NEXT: [[COPY23:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
-    ; CHECK-NEXT: [[SHL75:%[0-9]+]]:_(s32) = G_SHL [[COPY23]], [[C5]](s64)
+    ; CHECK-NEXT: [[COPY23:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
+    ; CHECK-NEXT: [[AND86:%[0-9]+]]:_(s32) = G_AND [[COPY23]], [[C7]]
+    ; CHECK-NEXT: [[SHL75:%[0-9]+]]:_(s32) = G_SHL [[AND86]], [[C5]](s64)
     ; CHECK-NEXT: [[OR75:%[0-9]+]]:_(s32) = G_OR [[OR74]], [[SHL75]]
-    ; CHECK-NEXT: [[COPY24:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
-    ; CHECK-NEXT: [[SHL76:%[0-9]+]]:_(s32) = G_SHL [[COPY24]], [[C6]](s64)
+    ; CHECK-NEXT: [[COPY24:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
+    ; CHECK-NEXT: [[AND87:%[0-9]+]]:_(s32) = G_AND [[COPY24]], [[C7]]
+    ; CHECK-NEXT: [[SHL76:%[0-9]+]]:_(s32) = G_SHL [[AND87]], [[C6]](s64)
     ; CHECK-NEXT: [[OR76:%[0-9]+]]:_(s32) = G_OR [[OR75]], [[SHL76]]
     ; CHECK-NEXT: [[TRUNC11:%[0-9]+]]:_(s8) = G_TRUNC [[OR76]](s32)
-    ; CHECK-NEXT: [[COPY25:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
-    ; CHECK-NEXT: [[SHL77:%[0-9]+]]:_(s32) = G_SHL [[COPY25]], [[C]](s64)
-    ; CHECK-NEXT: [[COPY26:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
-    ; CHECK-NEXT: [[OR77:%[0-9]+]]:_(s32) = G_OR [[COPY26]], [[SHL77]]
-    ; CHECK-NEXT: [[COPY27:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
-    ; CHECK-NEXT: [[SHL78:%[0-9]+]]:_(s32) = G_SHL [[COPY27]], [[C1]](s64)
+    ; CHECK-NEXT: [[COPY25:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
+    ; CHECK-NEXT: [[AND88:%[0-9]+]]:_(s32) = G_AND [[COPY25]], [[C7]]
+    ; CHECK-NEXT: [[SHL77:%[0-9]+]]:_(s32) = G_SHL [[AND88]], [[C]](s64)
+    ; CHECK-NEXT: [[COPY26:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
+    ; CHECK-NEXT: [[AND89:%[0-9]+]]:_(s32) = G_AND [[COPY26]], [[C7]]
+    ; CHECK-NEXT: [[OR77:%[0-9]+]]:_(s32) = G_OR [[AND89]], [[SHL77]]
+    ; CHECK-NEXT: [[COPY27:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
+    ; CHECK-NEXT: [[AND90:%[0-9]+]]:_(s32) = G_AND [[COPY27]], [[C7]]
+    ; CHECK-NEXT: [[SHL78:%[0-9]+]]:_(s32) = G_SHL [[AND90]], [[C1]](s64)
     ; CHECK-NEXT: [[OR78:%[0-9]+]]:_(s32) = G_OR [[OR77]], [[SHL78]]
-    ; CHECK-NEXT: [[COPY28:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
-    ; CHECK-NEXT: [[SHL79:%[0-9]+]]:_(s32) = G_SHL [[COPY28]], [[C2]](s64)
+    ; CHECK-NEXT: [[COPY28:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
+    ; CHECK-NEXT: [[AND91:%[0-9]+]]:_(s32) = G_AND [[COPY28]], [[C7]]
+    ; CHECK-NEXT: [[SHL79:%[0-9]+]]:_(s32) = G_SHL [[AND91]], [[C2]](s64)
     ; CHECK-NEXT: [[OR79:%[0-9]+]]:_(s32) = G_OR [[OR78]], [[SHL79]]
-    ; CHECK-NEXT: [[COPY29:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
-    ; CHECK-NEXT: [[SHL80:%[0-9]+]]:_(s32) = G_SHL [[COPY29]], [[C3]](s64)
+    ; CHECK-NEXT: [[COPY29:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
+    ; CHECK-NEXT: [[AND92:%[0-9]+]]:_(s32) = G_AND [[COPY29]], [[C7]]
+    ; CHECK-NEXT: [[SHL80:%[0-9]+]]:_(s32) = G_SHL [[AND92]], [[C3]](s64)
     ; CHECK-NEXT: [[OR80:%[0-9]+]]:_(s32) = G_OR [[OR79]], [[SHL80]]
-    ; CHECK-NEXT: [[COPY30:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
-    ; CHECK-NEXT: [[SHL81:%[0-9]+]]:_(s32) = G_SHL [[COPY30]], [[C4]](s64)
+    ; CHECK-NEXT: [[COPY30:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
+    ; CHECK-NEXT: [[AND93:%[0-9]+]]:_(s32) = G_AND [[COPY30]], [[C7]]
+    ; CHECK-NEXT: [[SHL81:%[0-9]+]]:_(s32) = G_SHL [[AND93]], [[C4]](s64)
     ; CHECK-NEXT: [[OR81:%[0-9]+]]:_(s32) = G_OR [[OR80]], [[SHL81]]
-    ; CHECK-NEXT: [[COPY31:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
-    ; CHECK-NEXT: [[SHL82:%[0-9]+]]:_(s32) = G_SHL [[COPY31]], [[C5]](s64)
+    ; CHECK-NEXT: [[COPY31:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
+    ; CHECK-NEXT: [[AND94:%[0-9]+]]:_(s32) = G_AND [[COPY31]], [[C7]]
+    ; CHECK-NEXT: [[SHL82:%[0-9]+]]:_(s32) = G_SHL [[AND94]], [[C5]](s64)
     ; CHECK-NEXT: [[OR82:%[0-9]+]]:_(s32) = G_OR [[OR81]], [[SHL82]]
-    ; CHECK-NEXT: [[COPY32:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
-    ; CHECK-NEXT: [[SHL83:%[0-9]+]]:_(s32) = G_SHL [[COPY32]], [[C6]](s64)
+    ; CHECK-NEXT: [[COPY32:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
+    ; CHECK-NEXT: [[AND95:%[0-9]+]]:_(s32) = G_AND [[COPY32]], [[C7]]
+    ; CHECK-NEXT: [[SHL83:%[0-9]+]]:_(s32) = G_SHL [[AND95]], [[C6]](s64)
     ; CHECK-NEXT: [[OR83:%[0-9]+]]:_(s32) = G_OR [[OR82]], [[SHL83]]
     ; CHECK-NEXT: [[TRUNC12:%[0-9]+]]:_(s8) = G_TRUNC [[OR83]](s32)
-    ; CHECK-NEXT: [[COPY33:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
-    ; CHECK-NEXT: [[SHL84:%[0-9]+]]:_(s32) = G_SHL [[COPY33]], [[C]](s64)
-    ; CHECK-NEXT: [[COPY34:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
-    ; CHECK-NEXT: [[OR84:%[0-9]+]]:_(s32) = G_OR [[COPY34]], [[SHL84]]
-    ; CHECK-NEXT: [[COPY35:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
-    ; CHECK-NEXT: [[SHL85:%[0-9]+]]:_(s32) = G_SHL [[COPY35]], [[C1]](s64)
+    ; CHECK-NEXT: [[COPY33:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
+    ; CHECK-NEXT: [[AND96:%[0-9]+]]:_(s32) = G_AND [[COPY33]], [[C7]]
+    ; CHECK-NEXT: [[SHL84:%[0-9]+]]:_(s32) = G_SHL [[AND96]], [[C]](s64)
+    ; CHECK-NEXT: [[COPY34:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
+    ; CHECK-NEXT: [[AND97:%[0-9]+]]:_(s32) = G_AND [[COPY34]], [[C7]]
+    ; CHECK-NEXT: [[OR84:%[0-9]+]]:_(s32) = G_OR [[AND97]], [[SHL84]]
+    ; CHECK-NEXT: [[COPY35:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
+    ; CHECK-NEXT: [[AND98:%[0-9]+]]:_(s32) = G_AND [[COPY35]], [[C7]]
+    ; CHECK-NEXT: [[SHL85:%[0-9]+]]:_(s32) = G_SHL [[AND98]], [[C1]](s64)
     ; CHECK-NEXT: [[OR85:%[0-9]+]]:_(s32) = G_OR [[OR84]], [[SHL85]]
-    ; CHECK-NEXT: [[COPY36:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
-    ; CHECK-NEXT: [[SHL86:%[0-9]+]]:_(s32) = G_SHL [[COPY36]], [[C2]](s64)
+    ; CHECK-NEXT: [[COPY36:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
+    ; CHECK-NEXT: [[AND99:%[0-9]+]]:_(s32) = G_AND [[COPY36]], [[C7]]
+    ; CHECK-NEXT: [[SHL86:%[0-9]+]]:_(s32) = G_SHL [[AND99]], [[C2]](s64)
     ; CHECK-NEXT: [[OR86:%[0-9]+]]:_(s32) = G_OR [[OR85]], [[SHL86]]
-    ; CHECK-NEXT: [[COPY37:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
-    ; CHECK-NEXT: [[SHL87:%[0-9]+]]:_(s32) = G_SHL [[COPY37]], [[C3]](s64)
+    ; CHECK-NEXT: [[COPY37:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
+    ; CHECK-NEXT: [[AND100:%[0-9]+]]:_(s32) = G_AND [[COPY37]], [[C7]]
+    ; CHECK-NEXT: [[SHL87:%[0-9]+]]:_(s32) = G_SHL [[AND100]], [[C3]](s64)
     ; CHECK-NEXT: [[OR87:%[0-9]+]]:_(s32) = G_OR [[OR86]], [[SHL87]]
-    ; CHECK-NEXT: [[COPY38:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
-    ; CHECK-NEXT: [[SHL88:%[0-9]+]]:_(s32) = G_SHL [[COPY38]], [[C4]](s64)
+    ; CHECK-NEXT: [[COPY38:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
+    ; CHECK-NEXT: [[AND101:%[0-9]+]]:_(s32) = G_AND [[COPY38]], [[C7]]
+    ; CHECK-NEXT: [[SHL88:%[0-9]+]]:_(s32) = G_SHL [[AND101]], [[C4]](s64)
     ; CHECK-NEXT: [[OR88:%[0-9]+]]:_(s32) = G_OR [[OR87]], [[SHL88]]
-    ; CHECK-NEXT: [[COPY39:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
-    ; CHECK-NEXT: [[SHL89:%[0-9]+]]:_(s32) = G_SHL [[COPY39]], [[C5]](s64)
+    ; CHECK-NEXT: [[COPY39:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
+    ; CHECK-NEXT: [[AND102:%[0-9]+]]:_(s32) = G_AND [[COPY39]], [[C7]]
+    ; CHECK-NEXT: [[SHL89:%[0-9]+]]:_(s32) = G_SHL [[AND102]], [[C5]](s64)
     ; CHECK-NEXT: [[OR89:%[0-9]+]]:_(s32) = G_OR [[OR88]], [[SHL89]]
-    ; CHECK-NEXT: [[COPY40:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
-    ; CHECK-NEXT: [[SHL90:%[0-9]+]]:_(s32) = G_SHL [[COPY40]], [[C6]](s64)
+    ; CHECK-NEXT: [[COPY40:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
+    ; CHECK-NEXT: [[AND103:%[0-9]+]]:_(s32) = G_AND [[COPY40]], [[C7]]
+    ; CHECK-NEXT: [[SHL90:%[0-9]+]]:_(s32) = G_SHL [[AND103]], [[C6]](s64)
     ; CHECK-NEXT: [[OR90:%[0-9]+]]:_(s32) = G_OR [[OR89]], [[SHL90]]
     ; CHECK-NEXT: [[TRUNC13:%[0-9]+]]:_(s8) = G_TRUNC [[OR90]](s32)
-    ; CHECK-NEXT: [[COPY41:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
-    ; CHECK-NEXT: [[SHL91:%[0-9]+]]:_(s32) = G_SHL [[COPY41]], [[C]](s64)
-    ; CHECK-NEXT: [[COPY42:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
-    ; CHECK-NEXT: [[OR91:%[0-9]+]]:_(s32) = G_OR [[COPY42]], [[SHL91]]
-    ; CHECK-NEXT: [[COPY43:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
-    ; CHECK-NEXT: [[SHL92:%[0-9]+]]:_(s32) = G_SHL [[COPY43]], [[C1]](s64)
+    ; CHECK-NEXT: [[COPY41:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
+    ; CHECK-NEXT: [[AND104:%[0-9]+]]:_(s32) = G_AND [[COPY41]], [[C7]]
+    ; CHECK-NEXT: [[SHL91:%[0-9]+]]:_(s32) = G_SHL [[AND104]], [[C]](s64)
+    ; CHECK-NEXT: [[COPY42:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
+    ; CHECK-NEXT: [[AND105:%[0-9]+]]:_(s32) = G_AND [[COPY42]], [[C7]]
+    ; CHECK-NEXT: [[OR91:%[0-9]+]]:_(s32) = G_OR [[AND105]], [[SHL91]]
+    ; CHECK-NEXT: [[COPY43:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
+    ; CHECK-NEXT: [[AND106:%[0-9]+]]:_(s32) = G_AND [[COPY43]], [[C7]]
+    ; CHECK-NEXT: [[SHL92:%[0-9]+]]:_(s32) = G_SHL [[AND106]], [[C1]](s64)
     ; CHECK-NEXT: [[OR92:%[0-9]+]]:_(s32) = G_OR [[OR91]], [[SHL92]]
-    ; CHECK-NEXT: [[COPY44:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
-    ; CHECK-NEXT: [[SHL93:%[0-9]+]]:_(s32) = G_SHL [[COPY44]], [[C2]](s64)
+    ; CHECK-NEXT: [[COPY44:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
+    ; CHECK-NEXT: [[AND107:%[0-9]+]]:_(s32) = G_AND [[COPY44]], [[C7]]
+    ; CHECK-NEXT: [[SHL93:%[0-9]+]]:_(s32) = G_SHL [[AND107]], [[C2]](s64)
     ; CHECK-NEXT: [[OR93:%[0-9]+]]:_(s32) = G_OR [[OR92]], [[SHL93]]
-    ; CHECK-NEXT: [[COPY45:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
-    ; CHECK-NEXT: [[SHL94:%[0-9]+]]:_(s32) = G_SHL [[COPY45]], [[C3]](s64)
+    ; CHECK-NEXT: [[COPY45:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
+    ; CHECK-NEXT: [[AND108:%[0-9]+]]:_(s32) = G_AND [[COPY45]], [[C7]]
+    ; CHECK-NEXT: [[SHL94:%[0-9]+]]:_(s32) = G_SHL [[AND108]], [[C3]](s64)
     ; CHECK-NEXT: [[OR94:%[0-9]+]]:_(s32) = G_OR [[OR93]], [[SHL94]]
-    ; CHECK-NEXT: [[COPY46:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
-    ; CHECK-NEXT: [[SHL95:%[0-9]+]]:_(s32) = G_SHL [[COPY46]], [[C4]](s64)
+    ; CHECK-NEXT: [[COPY46:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
+    ; CHECK-NEXT: [[AND109:%[0-9]+]]:_(s32) = G_AND [[COPY46]], [[C7]]
+    ; CHECK-NEXT: [[SHL95:%[0-9]+]]:_(s32) = G_SHL [[AND109]], [[C4]](s64)
     ; CHECK-NEXT: [[OR95:%[0-9]+]]:_(s32) = G_OR [[OR94]], [[SHL95]]
-    ; CHECK-NEXT: [[COPY47:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
-    ; CHECK-NEXT: [[SHL96:%[0-9]+]]:_(s32) = G_SHL [[COPY47]], [[C5]](s64)
+    ; CHECK-NEXT: [[COPY47:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
+    ; CHECK-NEXT: [[AND110:%[0-9]+]]:_(s32) = G_AND [[COPY47]], [[C7]]
+    ; CHECK-NEXT: [[SHL96:%[0-9]+]]:_(s32) = G_SHL [[AND110]], [[C5]](s64)
     ; CHECK-NEXT: [[OR96:%[0-9]+]]:_(s32) = G_OR [[OR95]], [[SHL96]]
-    ; CHECK-NEXT: [[COPY48:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
-    ; CHECK-NEXT: [[SHL97:%[0-9]+]]:_(s32) = G_SHL [[COPY48]], [[C6]](s64)
+    ; CHECK-NEXT: [[COPY48:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
+    ; CHECK-NEXT: [[AND111:%[0-9]+]]:_(s32) = G_AND [[COPY48]], [[C7]]
+    ; CHECK-NEXT: [[SHL97:%[0-9]+]]:_(s32) = G_SHL [[AND111]], [[C6]](s64)
     ; CHECK-NEXT: [[OR97:%[0-9]+]]:_(s32) = G_OR [[OR96]], [[SHL97]]
     ; CHECK-NEXT: [[TRUNC14:%[0-9]+]]:_(s8) = G_TRUNC [[OR97]](s32)
-    ; CHECK-NEXT: [[COPY49:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
-    ; CHECK-NEXT: [[SHL98:%[0-9]+]]:_(s32) = G_SHL [[COPY49]], [[C]](s64)
-    ; CHECK-NEXT: [[COPY50:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
-    ; CHECK-NEXT: [[OR98:%[0-9]+]]:_(s32) = G_OR [[COPY50]], [[SHL98]]
-    ; CHECK-NEXT: [[COPY51:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
-    ; CHECK-NEXT: [[SHL99:%[0-9]+]]:_(s32) = G_SHL [[COPY51]], [[C1]](s64)
+    ; CHECK-NEXT: [[COPY49:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
+    ; CHECK-NEXT: [[AND112:%[0-9]+]]:_(s32) = G_AND [[COPY49]], [[C7]]
+    ; CHECK-NEXT: [[SHL98:%[0-9]+]]:_(s32) = G_SHL [[AND112]], [[C]](s64)
+    ; CHECK-NEXT: [[COPY50:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
+    ; CHECK-NEXT: [[AND113:%[0-9]+]]:_(s32) = G_AND [[COPY50]], [[C7]]
+    ; CHECK-NEXT: [[OR98:%[0-9]+]]:_(s32) = G_OR [[AND113]], [[SHL98]]
+    ; CHECK-NEXT: [[COPY51:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
+    ; CHECK-NEXT: [[AND114:%[0-9]+]]:_(s32) = G_AND [[COPY51]], [[C7]]
+    ; CHECK-NEXT: [[SHL99:%[0-9]+]]:_(s32) = G_SHL [[AND114]], [[C1]](s64)
     ; CHECK-NEXT: [[OR99:%[0-9]+]]:_(s32) = G_OR [[OR98]], [[SHL99]]
-    ; CHECK-NEXT: [[COPY52:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
-    ; CHECK-NEXT: [[SHL100:%[0-9]+]]:_(s32) = G_SHL [[COPY52]], [[C2]](s64)
+    ; CHECK-NEXT: [[COPY52:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
+    ; CHECK-NEXT: [[AND115:%[0-9]+]]:_(s32) = G_AND [[COPY52]], [[C7]]
+    ; CHECK-NEXT: [[SHL100:%[0-9]+]]:_(s32) = G_SHL [[AND115]], [[C2]](s64)
     ; CHECK-NEXT: [[OR100:%[0-9]+]]:_(s32) = G_OR [[OR99]], [[SHL100]]
-    ; CHECK-NEXT: [[COPY53:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
-    ; CHECK-NEXT: [[SHL101:%[0-9]+]]:_(s32) = G_SHL [[COPY53]], [[C3]](s64)
+    ; CHECK-NEXT: [[COPY53:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
+    ; CHECK-NEXT: [[AND116:%[0-9]+]]:_(s32) = G_AND [[COPY53]], [[C7]]
+    ; CHECK-NEXT: [[SHL101:%[0-9]+]]:_(s32) = G_SHL [[AND116]], [[C3]](s64)
     ; CHECK-NEXT: [[OR101:%[0-9]+]]:_(s32) = G_OR [[OR100]], [[SHL101]]
-    ; CHECK-NEXT: [[COPY54:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
-    ; CHECK-NEXT: [[SHL102:%[0-9]+]]:_(s32) = G_SHL [[COPY54]], [[C4]](s64)
+    ; CHECK-NEXT: [[COPY54:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
+    ; CHECK-NEXT: [[AND117:%[0-9]+]]:_(s32) = G_AND [[COPY54]], [[C7]]
+    ; CHECK-NEXT: [[SHL102:%[0-9]+]]:_(s32) = G_SHL [[AND117]], [[C4]](s64)
     ; CHECK-NEXT: [[OR102:%[0-9]+]]:_(s32) = G_OR [[OR101]], [[SHL102]]
-    ; CHECK-NEXT: [[COPY55:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
-    ; CHECK-NEXT: [[SHL103:%[0-9]+]]:_(s32) = G_SHL [[COPY55]], [[C5]](s64)
+    ; CHECK-NEXT: [[COPY55:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
+    ; CHECK-NEXT: [[AND118:%[0-9]+]]:_(s32) = G_AND [[COPY55]], [[C7]]
+    ; CHECK-NEXT: [[SHL103:%[0-9]+]]:_(s32) = G_SHL [[AND118]], [[C5]](s64)
     ; CHECK-NEXT: [[OR103:%[0-9]+]]:_(s32) = G_OR [[OR102]], [[SHL103]]
-    ; CHECK-NEXT: [[COPY56:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
-    ; CHECK-NEXT: [[SHL104:%[0-9]+]]:_(s32) = G_SHL [[COPY56]], [[C6]](s64)
+    ; CHECK-NEXT: [[COPY56:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
+    ; CHECK-NEXT: [[AND119:%[0-9]+]]:_(s32) = G_AND [[COPY56]], [[C7]]
+    ; CHECK-NEXT: [[SHL104:%[0-9]+]]:_(s32) = G_SHL [[AND119]], [[C6]](s64)
     ; CHECK-NEXT: [[OR104:%[0-9]+]]:_(s32) = G_OR [[OR103]], [[SHL104]]
     ; CHECK-NEXT: [[TRUNC15:%[0-9]+]]:_(s8) = G_TRUNC [[OR104]](s32)
-    ; CHECK-NEXT: [[SHL105:%[0-9]+]]:_(s32) = G_SHL [[C8]], [[C]](s64)
-    ; CHECK-NEXT: [[COPY57:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
-    ; CHECK-NEXT: [[OR105:%[0-9]+]]:_(s32) = G_OR [[COPY57]], [[SHL105]]
-    ; CHECK-NEXT: [[COPY58:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
-    ; CHECK-NEXT: [[SHL106:%[0-9]+]]:_(s32) = G_SHL [[COPY58]], [[C1]](s64)
+    ; CHECK-NEXT: [[AND120:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C7]]
+    ; CHECK-NEXT: [[SHL105:%[0-9]+]]:_(s32) = G_SHL [[AND120]], [[C]](s64)
+    ; CHECK-NEXT: [[COPY57:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
+    ; CHECK-NEXT: [[AND121:%[0-9]+]]:_(s32) = G_AND [[COPY57]], [[C7]]
+    ; CHECK-NEXT: [[OR105:%[0-9]+]]:_(s32) = G_OR [[AND121]], [[SHL105]]
+    ; CHECK-NEXT: [[COPY58:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
+    ; CHECK-NEXT: [[AND122:%[0-9]+]]:_(s32) = G_AND [[COPY58]], [[C7]]
+    ; CHECK-NEXT: [[SHL106:%[0-9]+]]:_(s32) = G_SHL [[AND122]], [[C1]](s64)
     ; CHECK-NEXT: [[OR106:%[0-9]+]]:_(s32) = G_OR [[OR105]], [[SHL106]]
-    ; CHECK-NEXT: [[COPY59:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
-    ; CHECK-NEXT: [[SHL107:%[0-9]+]]:_(s32) = G_SHL [[COPY59]], [[C2]](s64)
+    ; CHECK-NEXT: [[COPY59:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
+    ; CHECK-NEXT: [[AND123:%[0-9]+]]:_(s32) = G_AND [[COPY59]], [[C7]]
+    ; CHECK-NEXT: [[SHL107:%[0-9]+]]:_(s32) = G_SHL [[AND123]], [[C2]](s64)
     ; CHECK-NEXT: [[OR107:%[0-9]+]]:_(s32) = G_OR [[OR106]], [[SHL107]]
-    ; CHECK-NEXT: [[COPY60:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
-    ; CHECK-NEXT: [[SHL108:%[0-9]+]]:_(s32) = G_SHL [[COPY60]], [[C3]](s64)
+    ; CHECK-NEXT: [[COPY60:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
+    ; CHECK-NEXT: [[AND124:%[0-9]+]]:_(s32) = G_AND [[COPY60]], [[C7]]
+    ; CHECK-NEXT: [[SHL108:%[0-9]+]]:_(s32) = G_SHL [[AND124]], [[C3]](s64)
     ; CHECK-NEXT: [[OR108:%[0-9]+]]:_(s32) = G_OR [[OR107]], [[SHL108]]
-    ; CHECK-NEXT: [[COPY61:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
-    ; CHECK-NEXT: [[SHL109:%[0-9]+]]:_(s32) = G_SHL [[COPY61]], [[C4]](s64)
+    ; CHECK-NEXT: [[COPY61:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
+    ; CHECK-NEXT: [[AND125:%[0-9]+]]:_(s32) = G_AND [[COPY61]], [[C7]]
+    ; CHECK-NEXT: [[SHL109:%[0-9]+]]:_(s32) = G_SHL [[AND125]], [[C4]](s64)
     ; CHECK-NEXT: [[OR109:%[0-9]+]]:_(s32) = G_OR [[OR108]], [[SHL109]]
-    ; CHECK-NEXT: [[COPY62:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
-    ; CHECK-NEXT: [[SHL110:%[0-9]+]]:_(s32) = G_SHL [[COPY62]], [[C5]](s64)
+    ; CHECK-NEXT: [[COPY62:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
+    ; CHECK-NEXT: [[AND126:%[0-9]+]]:_(s32) = G_AND [[COPY62]], [[C7]]
+    ; CHECK-NEXT: [[SHL110:%[0-9]+]]:_(s32) = G_SHL [[AND126]], [[C5]](s64)
     ; CHECK-NEXT: [[OR110:%[0-9]+]]:_(s32) = G_OR [[OR109]], [[SHL110]]
-    ; CHECK-NEXT: [[COPY63:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
-    ; CHECK-NEXT: [[SHL111:%[0-9]+]]:_(s32) = G_SHL [[COPY63]], [[C6]](s64)
+    ; CHECK-NEXT: [[COPY63:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
+    ; CHECK-NEXT: [[AND127:%[0-9]+]]:_(s32) = G_AND [[COPY63]], [[C7]]
+    ; CHECK-NEXT: [[SHL111:%[0-9]+]]:_(s32) = G_SHL [[AND127]], [[C6]](s64)
     ; CHECK-NEXT: [[OR111:%[0-9]+]]:_(s32) = G_OR [[OR110]], [[SHL111]]
     ; CHECK-NEXT: [[TRUNC16:%[0-9]+]]:_(s8) = G_TRUNC [[OR111]](s32)
     ; CHECK-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[TRUNC9]](s8), [[TRUNC10]](s8), [[TRUNC11]](s8), [[TRUNC12]](s8), [[TRUNC13]](s8), [[TRUNC14]](s8), [[TRUNC15]](s8), [[TRUNC16]](s8)
     ; CHECK-NEXT: $x0 = COPY [[MV]](s64)
     ; CHECK-NEXT: $x1 = COPY [[MV1]](s64)
     %0:_(s64) = COPY $x0
     %1:_(s64) = COPY $x1
     %2:_(s64) = COPY $x2

llvm/test/CodeGen/AArch64/GlobalISel/legalize-intrinsic-min-max.mir

bb.1:
     liveins: $w0, $w1
 
     ; CHECK-LABEL: name: smin_s32
     ; CHECK: liveins: $w0, $w1
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
     ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
     ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(slt), [[COPY]](s32), [[COPY1]]
-    ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32)
-    ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[TRUNC]](s1), [[COPY]], [[COPY1]]
+    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C]]
+    ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[COPY]], [[COPY1]]
     ; CHECK-NEXT: $w0 = COPY [[SELECT]](s32)
     ; CHECK-NEXT: RET_ReallyLR implicit $w0
     %0:_(s32) = COPY $w0
     %1:_(s32) = COPY $w1
     %2:_(s32) = G_SMIN %0, %1
     $w0 = COPY %2(s32)
     RET_ReallyLR implicit $w0
 
bb.1:
     liveins: $x0, $x1
 
     ; CHECK-LABEL: name: smin_s64
     ; CHECK: liveins: $x0, $x1
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
     ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
     ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(slt), [[COPY]](s64), [[COPY1]]
-    ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32)
-    ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[TRUNC]](s1), [[COPY]], [[COPY1]]
+    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C]]
+    ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[AND]](s32), [[COPY]], [[COPY1]]
     ; CHECK-NEXT: $x0 = COPY [[SELECT]](s64)
     ; CHECK-NEXT: RET_ReallyLR implicit $x0
     %0:_(s64) = COPY $x0
     %1:_(s64) = COPY $x1
     %2:_(s64) = G_SMIN %0, %1
     $x0 = COPY %2(s64)
     RET_ReallyLR implicit $x0
 
bb.1:
     liveins: $w0, $w1
 
     ; CHECK-LABEL: name: smax_s32
     ; CHECK: liveins: $w0, $w1
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
     ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
     ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(sgt), [[COPY]](s32), [[COPY1]]
-    ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32)
-    ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[TRUNC]](s1), [[COPY]], [[COPY1]]
+    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C]]
+    ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[COPY]], [[COPY1]]
     ; CHECK-NEXT: $w0 = COPY [[SELECT]](s32)
     ; CHECK-NEXT: RET_ReallyLR implicit $w0
     %0:_(s32) = COPY $w0
     %1:_(s32) = COPY $w1
     %2:_(s32) = G_SMAX %0, %1
     $w0 = COPY %2(s32)
     RET_ReallyLR implicit $w0
 
bb.1:
     liveins: $x0, $x1
 
     ; CHECK-LABEL: name: smax_s64
     ; CHECK: liveins: $x0, $x1
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
     ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
     ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(sgt), [[COPY]](s64), [[COPY1]]
-    ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32)
-    ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[TRUNC]](s1), [[COPY]], [[COPY1]]
+    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C]]
+    ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[AND]](s32), [[COPY]], [[COPY1]]
     ; CHECK-NEXT: $x0 = COPY [[SELECT]](s64)
     ; CHECK-NEXT: RET_ReallyLR implicit $x0
     %0:_(s64) = COPY $x0
     %1:_(s64) = COPY $x1
     %2:_(s64) = G_SMAX %0, %1
     $x0 = COPY %2(s64)
     RET_ReallyLR implicit $x0
 
bb.1:
     liveins: $w0, $w1
 
     ; CHECK-LABEL: name: umin_s32
     ; CHECK: liveins: $w0, $w1
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
     ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
     ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY]](s32), [[COPY1]]
-    ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32)
-    ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[TRUNC]](s1), [[COPY]], [[COPY1]]
+    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C]]
+    ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[COPY]], [[COPY1]]
     ; CHECK-NEXT: $w0 = COPY [[SELECT]](s32)
     ; CHECK-NEXT: RET_ReallyLR implicit $w0
     %0:_(s32) = COPY $w0
     %1:_(s32) = COPY $w1
     %2:_(s32) = G_UMIN %0, %1
     $w0 = COPY %2(s32)
     RET_ReallyLR implicit $w0
 
bb.1:
     liveins: $x0, $x1
 
     ; CHECK-LABEL: name: umin_s64
     ; CHECK: liveins: $x0, $x1
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
     ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
     ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY]](s64), [[COPY1]]
-    ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32)
-    ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[TRUNC]](s1), [[COPY]], [[COPY1]]
+    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C]]
+    ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[AND]](s32), [[COPY]], [[COPY1]]
     ; CHECK-NEXT: $x0 = COPY [[SELECT]](s64)
     ; CHECK-NEXT: RET_ReallyLR implicit $x0
     %0:_(s64) = COPY $x0
     %1:_(s64) = COPY $x1
     %2:_(s64) = G_UMIN %0, %1
     $x0 = COPY %2(s64)
     RET_ReallyLR implicit $x0
 
bb.1:
     liveins: $w0, $w1
 
     ; CHECK-LABEL: name: umax_s32
     ; CHECK: liveins: $w0, $w1
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
     ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
     ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[COPY]](s32), [[COPY1]]
-    ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32)
-    ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[TRUNC]](s1), [[COPY]], [[COPY1]]
+    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C]]
+    ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[COPY]], [[COPY1]]
     ; CHECK-NEXT: $w0 = COPY [[SELECT]](s32)
     ; CHECK-NEXT: RET_ReallyLR implicit $w0
     %0:_(s32) = COPY $w0
     %1:_(s32) = COPY $w1
     %2:_(s32) = G_UMAX %0, %1
     $w0 = COPY %2(s32)
     RET_ReallyLR implicit $w0
 
bb.1:
     liveins: $x0, $x1
 
     ; CHECK-LABEL: name: umax_s64
     ; CHECK: liveins: $x0, $x1
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
     ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
     ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[COPY]](s64), [[COPY1]]
-    ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32)
-    ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[TRUNC]](s1), [[COPY]], [[COPY1]]
+    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C]]
+    ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[AND]](s32), [[COPY]], [[COPY1]]
     ; CHECK-NEXT: $x0 = COPY [[SELECT]](s64)
     ; CHECK-NEXT: RET_ReallyLR implicit $x0
     %0:_(s64) = COPY $x0
     %1:_(s64) = COPY $x1
     %2:_(s64) = G_UMAX %0, %1
     $x0 = COPY %2(s64)
     RET_ReallyLR implicit $x0
 
 ...

llvm/test/CodeGen/AArch64/GlobalISel/legalize-itofp.mir

 
 ---
 name:            test_uitofp_v2s64_v2i1
 body: |
   bb.0:
     liveins: $q0
     ; CHECK-LABEL: name: test_uitofp_v2s64_v2i1
     ; CHECK: [[DEF:%[0-9]+]]:_(s8) = G_IMPLICIT_DEF
-    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s8) = COPY [[DEF]](s8)
-    ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s8>) = G_BUILD_VECTOR [[COPY]](s8), [[DEF]](s8)
+    ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s8>) = G_BUILD_VECTOR [[DEF]](s8), [[DEF]](s8)
     ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
     ; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)
     ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(<2 x s64>) = G_ANYEXT [[BUILD_VECTOR]](<2 x s8>)
     ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<2 x s64>) = G_AND [[ANYEXT]], [[BUILD_VECTOR1]]
     ; CHECK-NEXT: [[UITOFP:%[0-9]+]]:_(<2 x s64>) = G_UITOFP [[AND]](<2 x s64>)
     ; CHECK-NEXT: $q0 = COPY [[UITOFP]](<2 x s64>)
     %0:_(<2 x s1>) = G_IMPLICIT_DEF
     %1:_(<2 x s64>) = G_UITOFP %0
     $q0 = COPY %1
 ...
 
 ---
 name:            test_sitofp_v2s64_v2i1
 body: |
   bb.0:
     liveins: $q0
     ; CHECK-LABEL: name: test_sitofp_v2s64_v2i1
     ; CHECK: [[DEF:%[0-9]+]]:_(s8) = G_IMPLICIT_DEF
-    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s8) = COPY [[DEF]](s8)
-    ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s8>) = G_BUILD_VECTOR [[COPY]](s8), [[DEF]](s8)
+    ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s8>) = G_BUILD_VECTOR [[DEF]](s8), [[DEF]](s8)
     ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(<2 x s64>) = G_ANYEXT [[BUILD_VECTOR]](<2 x s8>)
     ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 63
     ; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)
     ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(<2 x s64>) = G_SHL [[ANYEXT]], [[BUILD_VECTOR1]](<2 x s64>)
     ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(<2 x s64>) = G_ASHR [[SHL]], [[BUILD_VECTOR1]](<2 x s64>)
     ; CHECK-NEXT: [[SITOFP:%[0-9]+]]:_(<2 x s64>) = G_SITOFP [[ASHR]](<2 x s64>)
     ; CHECK-NEXT: $q0 = COPY [[SITOFP]](<2 x s64>)
     %0:_(<2 x s1>) = G_IMPLICIT_DEF

llvm/test/CodeGen/AArch64/GlobalISel/legalize-phi-insertpt-decrement.mir

body:             |
   ; CHECK-NEXT:   [[INTTOPTR:%[0-9]+]]:_(p0) = G_INTTOPTR [[C]](s64)
   ; CHECK-NEXT:   [[DEF:%[0-9]+]]:_(p0) = G_IMPLICIT_DEF
   ; CHECK-NEXT:   [[DEF1:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT: bb.1.bb1:
   ; CHECK-NEXT:   successors: %bb.3(0x40000000), %bb.2(0x40000000)
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT:   [[PHI:%[0-9]+]]:_(p0) = G_PHI %6(p0), %bb.2, [[DEF]](p0), %bb.0
-  ; CHECK-NEXT:   [[PHI1:%[0-9]+]]:_(s16) = G_PHI %20(s16), %bb.2, [[DEF1]](s16), %bb.0
-  ; CHECK-NEXT:   [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[PHI1]](s16)
-  ; CHECK-NEXT:   G_BRCOND [[TRUNC]](s1), %bb.3
+  ; CHECK-NEXT:   [[PHI1:%[0-9]+]]:_(s16) = G_PHI %22(s16), %bb.2, [[DEF1]](s16), %bb.0
+  ; CHECK-NEXT:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+  ; CHECK-NEXT:   [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[PHI1]](s16)
+  ; CHECK-NEXT:   [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C1]]
+  ; CHECK-NEXT:   G_BRCOND [[AND]](s32), %bb.3
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT: bb.2.bb3:
   ; CHECK-NEXT:   successors: %bb.3(0x40000000), %bb.1(0x40000000)
   ; CHECK-NEXT: {{  $}}
-  ; CHECK-NEXT:   [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
-  ; CHECK-NEXT:   [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[INTTOPTR]], [[C1]](s64)
+  ; CHECK-NEXT:   [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
+  ; CHECK-NEXT:   [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[INTTOPTR]], [[C2]](s64)
   ; CHECK-NEXT:   [[LOAD:%[0-9]+]]:_(s16) = G_LOAD [[PHI]](p0) :: (load (s16) from %ir.lsr.iv)
   ; CHECK-NEXT:   [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[LOAD]](s16)
-  ; CHECK-NEXT:   [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
-  ; CHECK-NEXT:   [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[ZEXT]](s32), [[C2]]
-  ; CHECK-NEXT:   [[TRUNC1:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32)
+  ; CHECK-NEXT:   [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
+  ; CHECK-NEXT:   [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[ZEXT]](s32), [[C3]]
   ; CHECK-NEXT:   [[LOAD1:%[0-9]+]]:_(s16) = G_LOAD [[PTR_ADD]](p0) :: (load (s16) from %ir.tmp5)
   ; CHECK-NEXT:   [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[LOAD1]](s16)
-  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
   ; CHECK-NEXT:   [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[ZEXT1]](s32), [[COPY]]
-  ; CHECK-NEXT:   [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[PHI]], [[C1]](s64)
-  ; CHECK-NEXT:   [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[ICMP1]](s32)
-  ; CHECK-NEXT:   G_BRCOND [[TRUNC1]](s1), %bb.3
+  ; CHECK-NEXT:   [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[PHI]], [[C2]](s64)
+  ; CHECK-NEXT:   [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+  ; CHECK-NEXT:   [[AND1:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C4]]
+  ; CHECK-NEXT:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[ICMP1]](s32)
+  ; CHECK-NEXT:   G_BRCOND [[AND1]](s32), %bb.3
   ; CHECK-NEXT:   G_BR %bb.1
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT: bb.3.bb10:
   ; CHECK-NEXT:   RET_ReallyLR
   bb.1.bb:
     %3:_(s64) = G_CONSTANT i64 0
     %2:_(p0) = G_INTTOPTR %3(s64)
     %7:_(s16) = G_CONSTANT i16 -1

llvm/test/CodeGen/AArch64/GlobalISel/legalize-phi.mir

body:             |
   ; CHECK-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
   ; CHECK-NEXT:   liveins: $w0
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT:   [[COPY:%[0-9]+]]:_(s32) = COPY $w0
   ; CHECK-NEXT:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
   ; CHECK-NEXT:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
   ; CHECK-NEXT:   [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
   ; CHECK-NEXT:   [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[COPY]](s32), [[C]]
-  ; CHECK-NEXT:   [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32)
-  ; CHECK-NEXT:   G_BRCOND [[TRUNC]](s1), %bb.1
+  ; CHECK-NEXT:   [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C1]]
+  ; CHECK-NEXT:   G_BRCOND [[AND]](s32), %bb.1
   ; CHECK-NEXT:   G_BR %bb.2
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT: bb.1:
   ; CHECK-NEXT:   successors: %bb.3(0x80000000)
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT:   [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[C1]]
-  ; CHECK-NEXT:   [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[ADD]](s32)
+  ; CHECK-NEXT:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[ADD]](s32)
   ; CHECK-NEXT:   G_BR %bb.3
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT: bb.2:
   ; CHECK-NEXT:   successors: %bb.3(0x80000000)
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT:   [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[C2]]
-  ; CHECK-NEXT:   [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[ADD1]](s32)
+  ; CHECK-NEXT:   [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[ADD1]](s32)
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT: bb.3:
-  ; CHECK-NEXT:   [[PHI:%[0-9]+]]:_(s16) = G_PHI [[TRUNC1]](s16), %bb.1, [[TRUNC2]](s16), %bb.2
+  ; CHECK-NEXT:   [[PHI:%[0-9]+]]:_(s16) = G_PHI [[TRUNC]](s16), %bb.1, [[TRUNC1]](s16), %bb.2
   ; CHECK-NEXT:   [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
   ; CHECK-NEXT:   [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[PHI]](s16)
-  ; CHECK-NEXT:   [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C3]]
-  ; CHECK-NEXT:   $w0 = COPY [[AND]](s32)
+  ; CHECK-NEXT:   [[AND1:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C3]]
+  ; CHECK-NEXT:   $w0 = COPY [[AND1]](s32)
   ; CHECK-NEXT:   RET_ReallyLR implicit $w0
   bb.0:
    ; Test that we insert legalization artifacts(Truncs here) into the correct BBs
    ; while legalizing the G_PHI to s16.
 
 
     successors: %bb.1(0x40000000), %bb.2(0x40000000)
     liveins: $w0
body:             |
   ; CHECK-LABEL: name: legalize_phi_ptr
   ; CHECK: bb.0:
   ; CHECK-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
   ; CHECK-NEXT:   liveins: $w2, $x0, $x1
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT:   [[COPY:%[0-9]+]]:_(p0) = COPY $x0
   ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
   ; CHECK-NEXT:   [[COPY2:%[0-9]+]]:_(s32) = COPY $w2
-  ; CHECK-NEXT:   [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY2]](s32)
-  ; CHECK-NEXT:   G_BRCOND [[TRUNC]](s1), %bb.1
+  ; CHECK-NEXT:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+  ; CHECK-NEXT:   [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
+  ; CHECK-NEXT:   G_BRCOND [[AND]](s32), %bb.1
   ; CHECK-NEXT:   G_BR %bb.2
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT: bb.1:
   ; CHECK-NEXT:   successors: %bb.2(0x80000000)
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT: bb.2:
   ; CHECK-NEXT:   [[PHI:%[0-9]+]]:_(p0) = G_PHI [[COPY]](p0), %bb.0, [[COPY1]](p0), %bb.1
body:             |
   ; CHECK-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
   ; CHECK-NEXT:   liveins: $w0
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT:   [[COPY:%[0-9]+]]:_(s32) = COPY $w0
   ; CHECK-NEXT:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
   ; CHECK-NEXT:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
   ; CHECK-NEXT:   [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
   ; CHECK-NEXT:   [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[COPY]](s32), [[C]]
-  ; CHECK-NEXT:   [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32)
   ; CHECK-NEXT:   [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[C1]]
-  ; CHECK-NEXT:   G_BRCOND [[TRUNC]](s1), %bb.1
+  ; CHECK-NEXT:   [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C2]]
+  ; CHECK-NEXT:   G_BRCOND [[AND]](s32), %bb.1
   ; CHECK-NEXT:   G_BR %bb.2
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT: bb.1:
   ; CHECK-NEXT:   successors: %bb.3(0x80000000)
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT:   [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[C2]]
-  ; CHECK-NEXT:   [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[ADD1]](s32)
+  ; CHECK-NEXT:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[ADD1]](s32)
   ; CHECK-NEXT:   G_BR %bb.3
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT: bb.2:
   ; CHECK-NEXT:   successors: %bb.3(0x80000000)
   ; CHECK-NEXT: {{  $}}
-  ; CHECK-NEXT:   [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[ADD]](s32)
+  ; CHECK-NEXT:   [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[ADD]](s32)
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT: bb.3:
-  ; CHECK-NEXT:   [[PHI:%[0-9]+]]:_(s16) = G_PHI [[TRUNC1]](s16), %bb.1, [[TRUNC2]](s16), %bb.2
+  ; CHECK-NEXT:   [[PHI:%[0-9]+]]:_(s16) = G_PHI [[TRUNC]](s16), %bb.1, [[TRUNC1]](s16), %bb.2
   ; CHECK-NEXT:   [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
   ; CHECK-NEXT:   [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[PHI]](s16)
-  ; CHECK-NEXT:   [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C3]]
-  ; CHECK-NEXT:   $w0 = COPY [[AND]](s32)
+  ; CHECK-NEXT:   [[AND1:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C3]]
+  ; CHECK-NEXT:   $w0 = COPY [[AND1]](s32)
   ; CHECK-NEXT:   RET_ReallyLR implicit $w0
   bb.0:
     successors: %bb.1(0x40000000), %bb.2(0x40000000)
     liveins: $w0
    ; Test that we properly legalize a phi with a predecessor that's empty
 
 
 
body:             |
   ; CHECK-NEXT:   liveins: $w0
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT:   [[COPY:%[0-9]+]]:_(s32) = COPY $w0
   ; CHECK-NEXT:   [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 0
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT: bb.1:
   ; CHECK-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
   ; CHECK-NEXT: {{  $}}
-  ; CHECK-NEXT:   [[PHI:%[0-9]+]]:_(s16) = G_PHI [[C]](s16), %bb.0, %13(s16), %bb.1
+  ; CHECK-NEXT:   [[PHI:%[0-9]+]]:_(s16) = G_PHI [[C]](s16), %bb.0, %14(s16), %bb.1
   ; CHECK-NEXT:   [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[PHI]](s16)
   ; CHECK-NEXT:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
   ; CHECK-NEXT:   [[ADD:%[0-9]+]]:_(s32) = G_ADD [[ANYEXT]], [[C1]]
   ; CHECK-NEXT:   [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
   ; CHECK-NEXT:   [[AND:%[0-9]+]]:_(s32) = G_AND [[ADD]], [[C2]]
   ; CHECK-NEXT:   [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[AND]](s32), [[COPY]]
-  ; CHECK-NEXT:   [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32)
-  ; CHECK-NEXT:   [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[ADD]](s32)
-  ; CHECK-NEXT:   G_BRCOND [[TRUNC]](s1), %bb.1
+  ; CHECK-NEXT:   [[AND1:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C1]]
+  ; CHECK-NEXT:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[ADD]](s32)
+  ; CHECK-NEXT:   G_BRCOND [[AND1]](s32), %bb.1
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT: bb.2:
   ; CHECK-NEXT:   [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
-  ; CHECK-NEXT:   [[AND1:%[0-9]+]]:_(s32) = G_AND [[ADD]], [[C3]]
-  ; CHECK-NEXT:   $w0 = COPY [[AND1]](s32)
+  ; CHECK-NEXT:   [[AND2:%[0-9]+]]:_(s32) = G_AND [[ADD]], [[C3]]
+  ; CHECK-NEXT:   $w0 = COPY [[AND2]](s32)
   ; CHECK-NEXT:   RET_ReallyLR implicit $w0
   bb.0:
     successors: %bb.1(0x80000000)
     liveins: $w0
    ; Test that we properly legalize a phi that uses a value from the same BB
 
     %0(s32) = COPY $w0
     %2(s8) = G_CONSTANT i8 1
body:             |
   ; CHECK-NEXT: bb.1:
   ; CHECK-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT:   [[PHI:%[0-9]+]]:_(s16) = G_PHI [[C]](s16), %bb.0, [[PHI]](s16), %bb.1
   ; CHECK-NEXT:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
   ; CHECK-NEXT:   [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[PHI]](s16)
   ; CHECK-NEXT:   [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C1]]
   ; CHECK-NEXT:   [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[AND]](s32), [[COPY]]
-  ; CHECK-NEXT:   [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32)
-  ; CHECK-NEXT:   G_BRCOND [[TRUNC]](s1), %bb.1
+  ; CHECK-NEXT:   [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+  ; CHECK-NEXT:   [[AND1:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C2]]
+  ; CHECK-NEXT:   G_BRCOND [[AND1]](s32), %bb.1
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT: bb.2:
   ; CHECK-NEXT:   $w0 = COPY [[AND]](s32)
   ; CHECK-NEXT:   RET_ReallyLR implicit $w0
   bb.0:
     successors: %bb.1(0x80000000)
     liveins: $w0
    ; Test that we properly legalize a phi that uses itself
body:             |
   ; CHECK-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
   ; CHECK-NEXT:   liveins: $w0
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT:   [[COPY:%[0-9]+]]:_(s32) = COPY $w0
   ; CHECK-NEXT:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
   ; CHECK-NEXT:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
   ; CHECK-NEXT:   [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
   ; CHECK-NEXT:   [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[COPY]](s32), [[C]]
-  ; CHECK-NEXT:   [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32)
   ; CHECK-NEXT:   [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[C1]]
-  ; CHECK-NEXT:   G_BRCOND [[TRUNC]](s1), %bb.1
+  ; CHECK-NEXT:   [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C2]]
+  ; CHECK-NEXT:   G_BRCOND [[AND]](s32), %bb.1
   ; CHECK-NEXT:   G_BR %bb.2
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT: bb.1:
   ; CHECK-NEXT:   successors: %bb.3(0x80000000)
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT:   [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[C2]]
+  ; CHECK-NEXT:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[ADD1]](s32)
   ; CHECK-NEXT:   [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[ADD1]](s32)
-  ; CHECK-NEXT:   [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[ADD1]](s32)
   ; CHECK-NEXT:   G_BR %bb.3
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT: bb.2:
   ; CHECK-NEXT:   successors: %bb.3(0x80000000)
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT:   [[C3:%[0-9]+]]:_(s16) = G_CONSTANT i16 42
-  ; CHECK-NEXT:   [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[ADD]](s32)
+  ; CHECK-NEXT:   [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[ADD]](s32)
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT: bb.3:
-  ; CHECK-NEXT:   [[PHI:%[0-9]+]]:_(s16) = G_PHI [[TRUNC2]](s16), %bb.1, [[TRUNC3]](s16), %bb.2
-  ; CHECK-NEXT:   [[PHI1:%[0-9]+]]:_(s16) = G_PHI [[TRUNC1]](s16), %bb.1, [[C3]](s16), %bb.2
+  ; CHECK-NEXT:   [[PHI:%[0-9]+]]:_(s16) = G_PHI [[TRUNC1]](s16), %bb.1, [[TRUNC2]](s16), %bb.2
+  ; CHECK-NEXT:   [[PHI1:%[0-9]+]]:_(s16) = G_PHI [[TRUNC]](s16), %bb.1, [[C3]](s16), %bb.2
   ; CHECK-NEXT:   [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
   ; CHECK-NEXT:   [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[PHI]](s16)
-  ; CHECK-NEXT:   [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C4]]
+  ; CHECK-NEXT:   [[AND1:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C4]]
   ; CHECK-NEXT:   [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[PHI1]](s16)
-  ; CHECK-NEXT:   [[AND1:%[0-9]+]]:_(s32) = G_AND [[ANYEXT1]], [[C4]]
-  ; CHECK-NEXT:   [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[AND]], [[AND1]]
+  ; CHECK-NEXT:   [[AND2:%[0-9]+]]:_(s32) = G_AND [[ANYEXT1]], [[C4]]
+  ; CHECK-NEXT:   [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[AND1]], [[AND2]]
   ; CHECK-NEXT:   $w0 = COPY [[ADD2]](s32)
   ; CHECK-NEXT:   RET_ReallyLR implicit $w0
   bb.0:
     successors: %bb.1(0x40000000), %bb.2(0x40000000)
     liveins: $w0
    ; Make sure that we correctly insert the new legalized G_PHI at the
    ; correct location (ie make sure G_PHIs are the first insts in the BB).
 
body:             |
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT:   [[COPY:%[0-9]+]]:_(s32) = COPY $w0
   ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
   ; CHECK-NEXT:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
   ; CHECK-NEXT:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
   ; CHECK-NEXT:   [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
   ; CHECK-NEXT:   [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 44
   ; CHECK-NEXT:   [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[COPY]](s32), [[C]]
-  ; CHECK-NEXT:   [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32)
   ; CHECK-NEXT:   [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[C1]]
+  ; CHECK-NEXT:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[ADD]](s32)
   ; CHECK-NEXT:   [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[ADD]](s32)
-  ; CHECK-NEXT:   [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[ADD]](s32)
-  ; CHECK-NEXT:   G_BRCOND [[TRUNC]](s1), %bb.1
+  ; CHECK-NEXT:   [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C2]]
+  ; CHECK-NEXT:   G_BRCOND [[AND]](s32), %bb.1
   ; CHECK-NEXT:   G_BR %bb.2
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT: bb.1:
   ; CHECK-NEXT:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
   ; CHECK-NEXT: {{  $}}
-  ; CHECK-NEXT:   [[PHI:%[0-9]+]]:_(s16) = G_PHI [[TRUNC2]](s16), %bb.0, %21(s16), %bb.1
+  ; CHECK-NEXT:   [[PHI:%[0-9]+]]:_(s16) = G_PHI [[TRUNC1]](s16), %bb.0, %22(s16), %bb.1
   ; CHECK-NEXT:   [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
   ; CHECK-NEXT:   [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[PHI]](s16)
-  ; CHECK-NEXT:   [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C4]]
-  ; CHECK-NEXT:   [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[AND]], [[C2]]
+  ; CHECK-NEXT:   [[AND1:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C4]]
+  ; CHECK-NEXT:   [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[AND1]], [[C2]]
   ; CHECK-NEXT:   [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[ADD1]](s32), [[C3]]
-  ; CHECK-NEXT:   [[TRUNC3:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP1]](s32)
-  ; CHECK-NEXT:   [[C5:%[0-9]+]]:_(s16) = G_CONSTANT i16 43
-  ; CHECK-NEXT:   G_BRCOND [[TRUNC3]](s1), %bb.2
+  ; CHECK-NEXT:   [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+  ; CHECK-NEXT:   [[AND2:%[0-9]+]]:_(s32) = G_AND [[ICMP1]], [[C5]]
+  ; CHECK-NEXT:   [[C6:%[0-9]+]]:_(s16) = G_CONSTANT i16 43
+  ; CHECK-NEXT:   G_BRCOND [[AND2]](s32), %bb.2
   ; CHECK-NEXT:   G_BR %bb.1
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT: bb.2:
-  ; CHECK-NEXT:   [[PHI1:%[0-9]+]]:_(s16) = G_PHI [[PHI]](s16), %bb.1, [[TRUNC1]](s16), %bb.0
-  ; CHECK-NEXT:   [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+  ; CHECK-NEXT:   [[PHI1:%[0-9]+]]:_(s16) = G_PHI [[PHI]](s16), %bb.1, [[TRUNC]](s16), %bb.0
+  ; CHECK-NEXT:   [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
   ; CHECK-NEXT:   [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[PHI1]](s16)
-  ; CHECK-NEXT:   [[AND1:%[0-9]+]]:_(s32) = G_AND [[ANYEXT1]], [[C6]]
-  ; CHECK-NEXT:   $w0 = COPY [[AND1]](s32)
+  ; CHECK-NEXT:   [[AND3:%[0-9]+]]:_(s32) = G_AND [[ANYEXT1]], [[C7]]
+  ; CHECK-NEXT:   $w0 = COPY [[AND3]](s32)
   ; CHECK-NEXT:   RET_ReallyLR implicit $w0
   bb.0:
     successors: %bb.1(0x40000000), %bb.3(0x40000000)
     liveins: $w0, $w1
    ; Make sure that we correctly legalize PHIs sharing common defs
    ; in different BBs.
 
 

 tracksRegLiveness: true
 liveins:
 body:             |
   ; CHECK-LABEL: name: s88
   ; CHECK: bb.0:
   ; CHECK-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
   ; CHECK-NEXT:   liveins: $x0
   ; CHECK-NEXT: {{  $}}
-  ; CHECK-NEXT:   %cond:_(s1) = G_IMPLICIT_DEF
-  ; CHECK-NEXT:   G_BRCOND %cond(s1), %bb.1
+  ; CHECK-NEXT:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+  ; CHECK-NEXT:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
+  ; CHECK-NEXT:   [[AND:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C]]
+  ; CHECK-NEXT:   G_BRCOND [[AND]](s32), %bb.1
   ; CHECK-NEXT:   G_BR %bb.2
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT: bb.1:
   ; CHECK-NEXT:   successors: %bb.3(0x80000000)
   ; CHECK-NEXT: {{  $}}
-  ; CHECK-NEXT:   [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
+  ; CHECK-NEXT:   [[DEF1:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
   ; CHECK-NEXT:   G_BR %bb.3
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT: bb.2:
   ; CHECK-NEXT:   successors: %bb.3(0x80000000)
   ; CHECK-NEXT: {{  $}}
-  ; CHECK-NEXT:   [[DEF1:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
+  ; CHECK-NEXT:   [[DEF2:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT: bb.3:
-  ; CHECK-NEXT:   [[PHI:%[0-9]+]]:_(s64) = G_PHI [[DEF]](s64), %bb.1, [[DEF1]](s64), %bb.2
+  ; CHECK-NEXT:   [[PHI:%[0-9]+]]:_(s64) = G_PHI [[DEF1]](s64), %bb.1, [[DEF2]](s64), %bb.2
   ; CHECK-NEXT:   $x0 = COPY [[PHI]](s64)
   ; CHECK-NEXT:   RET_ReallyLR implicit $x0
   bb.0:
     successors: %bb.1(0x40000000), %bb.2(0x40000000)
     liveins: $x0
     %cond:_(s1) = G_IMPLICIT_DEF
     G_BRCOND %cond(s1), %bb.1
     G_BR %bb.2

 body:             |
   ; CHECK-LABEL: name: v4s64
   ; CHECK: bb.0:
   ; CHECK-NEXT:   successors: %bb.1(0x50000000), %bb.2(0x30000000)
   ; CHECK-NEXT:   liveins: $x0, $x1
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT:   %ptr1:_(p0) = COPY $x1
   ; CHECK-NEXT:   %ptr2:_(p0) = COPY $x0
-  ; CHECK-NEXT:   %cond:_(s1) = G_IMPLICIT_DEF
   ; CHECK-NEXT:   [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD %ptr1(p0) :: (load (<2 x s64>), align 32)
   ; CHECK-NEXT:   [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
   ; CHECK-NEXT:   [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD %ptr1, [[C]](s64)
   ; CHECK-NEXT:   [[LOAD1:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[PTR_ADD]](p0) :: (load (<2 x s64>) from unknown-address + 16)
-  ; CHECK-NEXT:   G_BRCOND %cond(s1), %bb.2
+  ; CHECK-NEXT:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+  ; CHECK-NEXT:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
+  ; CHECK-NEXT:   [[AND:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C1]]
+  ; CHECK-NEXT:   G_BRCOND [[AND]](s32), %bb.2
   ; CHECK-NEXT:   G_BR %bb.1
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT: bb.1:
   ; CHECK-NEXT:   successors: %bb.2(0x80000000)
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT:   [[LOAD2:%[0-9]+]]:_(<2 x s64>) = G_LOAD %ptr2(p0) :: (load (<2 x s64>), align 32)
-  ; CHECK-NEXT:   [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
-  ; CHECK-NEXT:   [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD %ptr2, [[C1]](s64)
+  ; CHECK-NEXT:   [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
+  ; CHECK-NEXT:   [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD %ptr2, [[C2]](s64)
   ; CHECK-NEXT:   [[LOAD3:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[PTR_ADD1]](p0) :: (load (<2 x s64>) from unknown-address + 16)
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT: bb.2:
   ; CHECK-NEXT:   [[PHI:%[0-9]+]]:_(<2 x s64>) = G_PHI [[LOAD2]](<2 x s64>), %bb.1, [[LOAD]](<2 x s64>), %bb.0
   ; CHECK-NEXT:   [[PHI1:%[0-9]+]]:_(<2 x s64>) = G_PHI [[LOAD3]](<2 x s64>), %bb.1, [[LOAD1]](<2 x s64>), %bb.0
   ; CHECK-NEXT:   $q0 = COPY [[PHI]](<2 x s64>)
   ; CHECK-NEXT:   $q1 = COPY [[PHI1]](<2 x s64>)
   ; CHECK-NEXT:   RET_ReallyLR implicit $q0, implicit $q1

 alignment:       4
 tracksRegLiveness: true
 body:             |
   ; CHECK-LABEL: name: v8s32
   ; CHECK: bb.0:
   ; CHECK-NEXT:   successors: %bb.1(0x50000000), %bb.2(0x30000000)
   ; CHECK-NEXT:   liveins: $x0, $x1
   ; CHECK-NEXT: {{  $}}
-  ; CHECK-NEXT:   %cond:_(s1) = G_IMPLICIT_DEF
   ; CHECK-NEXT:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
   ; CHECK-NEXT:   [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[DEF]](s32), [[DEF]](s32), [[DEF]](s32), [[DEF]](s32)
-  ; CHECK-NEXT:   G_BRCOND %cond(s1), %bb.2
+  ; CHECK-NEXT:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
+  ; CHECK-NEXT:   [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
+  ; CHECK-NEXT:   G_BRCOND [[AND]](s32), %bb.2
   ; CHECK-NEXT:   G_BR %bb.1
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT: bb.1:
   ; CHECK-NEXT:   successors: %bb.2(0x80000000)
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT:   [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
   ; CHECK-NEXT:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[DEF1]](s32), [[DEF1]](s32), [[DEF1]](s32), [[DEF1]](s32)
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT: bb.2:
   ; CHECK-NEXT:   [[PHI:%[0-9]+]]:_(<4 x s32>) = G_PHI [[BUILD_VECTOR1]](<4 x s32>), %bb.1, [[BUILD_VECTOR]](<4 x s32>), %bb.0
-  ; CHECK-NEXT:   [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
-  ; CHECK-NEXT:   %extract:_(s32) = G_EXTRACT_VECTOR_ELT [[PHI]](<4 x s32>), [[C]](s64)
+  ; CHECK-NEXT:   [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+  ; CHECK-NEXT:   %extract:_(s32) = G_EXTRACT_VECTOR_ELT [[PHI]](<4 x s32>), [[C1]](s64)
   ; CHECK-NEXT:   $w0 = COPY %extract(s32)
   ; CHECK-NEXT:   RET_ReallyLR implicit $w0
   bb.0:
     successors: %bb.1(0x50000000), %bb.2(0x30000000)
     liveins: $x0, $x1
     %cond:_(s1) = G_IMPLICIT_DEF
     %val_1:_(<8 x s32>) = G_IMPLICIT_DEF
     G_BRCOND %cond(s1), %bb.2

 alignment:       4
 tracksRegLiveness: true
 body:             |
   ; CHECK-LABEL: name: v16s16
   ; CHECK: bb.0:
   ; CHECK-NEXT:   successors: %bb.1(0x50000000), %bb.2(0x30000000)
   ; CHECK-NEXT:   liveins: $x0, $x1
   ; CHECK-NEXT: {{  $}}
-  ; CHECK-NEXT:   %cond:_(s1) = G_IMPLICIT_DEF
   ; CHECK-NEXT:   [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
   ; CHECK-NEXT:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s16>) = G_BUILD_VECTOR [[DEF]](s16), [[DEF]](s16), [[DEF]](s16), [[DEF]](s16), [[DEF]](s16), [[DEF]](s16), [[DEF]](s16), [[DEF]](s16)
-  ; CHECK-NEXT:   G_BRCOND %cond(s1), %bb.2
+  ; CHECK-NEXT:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+  ; CHECK-NEXT:   [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
+  ; CHECK-NEXT:   [[AND:%[0-9]+]]:_(s32) = G_AND [[DEF1]], [[C]]
+  ; CHECK-NEXT:   G_BRCOND [[AND]](s32), %bb.2
   ; CHECK-NEXT:   G_BR %bb.1
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT: bb.1:
   ; CHECK-NEXT:   successors: %bb.2(0x80000000)
   ; CHECK-NEXT: {{  $}}
-  ; CHECK-NEXT:   [[DEF1:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
-  ; CHECK-NEXT:   [[BUILD_VECTOR1:%[0-9]+]]:_(<8 x s16>) = G_BUILD_VECTOR [[DEF1]](s16), [[DEF1]](s16), [[DEF1]](s16), [[DEF1]](s16), [[DEF1]](s16), [[DEF1]](s16), [[DEF1]](s16), [[DEF1]](s16)
+  ; CHECK-NEXT:   [[DEF2:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
+  ; CHECK-NEXT:   [[BUILD_VECTOR1:%[0-9]+]]:_(<8 x s16>) = G_BUILD_VECTOR [[DEF2]](s16), [[DEF2]](s16), [[DEF2]](s16), [[DEF2]](s16), [[DEF2]](s16), [[DEF2]](s16), [[DEF2]](s16), [[DEF2]](s16)
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT: bb.2:
   ; CHECK-NEXT:   [[PHI:%[0-9]+]]:_(<8 x s16>) = G_PHI [[BUILD_VECTOR1]](<8 x s16>), %bb.1, [[BUILD_VECTOR]](<8 x s16>), %bb.0
-  ; CHECK-NEXT:   [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
-  ; CHECK-NEXT:   %extract:_(s16) = G_EXTRACT_VECTOR_ELT [[PHI]](<8 x s16>), [[C]](s64)
+  ; CHECK-NEXT:   [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+  ; CHECK-NEXT:   %extract:_(s16) = G_EXTRACT_VECTOR_ELT [[PHI]](<8 x s16>), [[C1]](s64)
   ; CHECK-NEXT:   $h0 = COPY %extract(s16)
   ; CHECK-NEXT:   RET_ReallyLR implicit $h0
   bb.0:
     successors: %bb.1(0x50000000), %bb.2(0x30000000)
     liveins: $x0, $x1
     %cond:_(s1) = G_IMPLICIT_DEF
     %val_1:_(<16 x s16>) = G_IMPLICIT_DEF
     G_BRCOND %cond(s1), %bb.2

 body:             |
   ; CHECK-LABEL: name: v4p0
   ; CHECK: bb.0:
   ; CHECK-NEXT:   successors: %bb.1(0x50000000), %bb.2(0x30000000)
   ; CHECK-NEXT:   liveins: $x0, $x1
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT:   %ptr1:_(p0) = COPY $x1
   ; CHECK-NEXT:   %ptr2:_(p0) = COPY $x0
-  ; CHECK-NEXT:   %cond:_(s1) = G_IMPLICIT_DEF
   ; CHECK-NEXT:   [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD %ptr1(p0) :: (load (<2 x s64>), align 32)
   ; CHECK-NEXT:   [[BITCAST:%[0-9]+]]:_(<2 x p0>) = G_BITCAST [[LOAD]](<2 x s64>)
   ; CHECK-NEXT:   [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
   ; CHECK-NEXT:   [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD %ptr1, [[C]](s64)
   ; CHECK-NEXT:   [[LOAD1:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[PTR_ADD]](p0) :: (load (<2 x s64>) from unknown-address + 16)
   ; CHECK-NEXT:   [[BITCAST1:%[0-9]+]]:_(<2 x p0>) = G_BITCAST [[LOAD1]](<2 x s64>)
-  ; CHECK-NEXT:   G_BRCOND %cond(s1), %bb.2
+  ; CHECK-NEXT:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+  ; CHECK-NEXT:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
+  ; CHECK-NEXT:   [[AND:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C1]]
+  ; CHECK-NEXT:   G_BRCOND [[AND]](s32), %bb.2
   ; CHECK-NEXT:   G_BR %bb.1
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT: bb.1:
   ; CHECK-NEXT:   successors: %bb.2(0x80000000)
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT:   [[LOAD2:%[0-9]+]]:_(<2 x s64>) = G_LOAD %ptr2(p0) :: (load (<2 x s64>), align 32)
   ; CHECK-NEXT:   [[BITCAST2:%[0-9]+]]:_(<2 x p0>) = G_BITCAST [[LOAD2]](<2 x s64>)
-  ; CHECK-NEXT:   [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
-  ; CHECK-NEXT:   [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD %ptr2, [[C1]](s64)
+  ; CHECK-NEXT:   [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
+  ; CHECK-NEXT:   [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD %ptr2, [[C2]](s64)
   ; CHECK-NEXT:   [[LOAD3:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[PTR_ADD1]](p0) :: (load (<2 x s64>) from unknown-address + 16)
   ; CHECK-NEXT:   [[BITCAST3:%[0-9]+]]:_(<2 x p0>) = G_BITCAST [[LOAD3]](<2 x s64>)
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT: bb.2:
   ; CHECK-NEXT:   [[PHI:%[0-9]+]]:_(<2 x p0>) = G_PHI [[BITCAST2]](<2 x p0>), %bb.1, [[BITCAST]](<2 x p0>), %bb.0
   ; CHECK-NEXT:   [[PHI1:%[0-9]+]]:_(<2 x p0>) = G_PHI [[BITCAST3]](<2 x p0>), %bb.1, [[BITCAST1]](<2 x p0>), %bb.0
   ; CHECK-NEXT:   $q0 = COPY [[PHI]](<2 x p0>)
   ; CHECK-NEXT:   $q1 = COPY [[PHI1]](<2 x p0>)

llvm/test/CodeGen/AArch64/GlobalISel/legalize-sadde.mir

 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple aarch64 -verify-machineinstrs -run-pass=legalizer -debugify-and-strip-all-safe %s -o - | FileCheck %s
 
 ---
 name:            narrow_scalar_sadde_s128
 body:             |
   bb.0.entry:
     ; CHECK-LABEL: name: narrow_scalar_sadde_s128
     ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
     ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
     ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
     ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
     ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(s64) = COPY $x4
-    ; CHECK-NEXT: %carry_in:_(s1) = G_TRUNC [[COPY4]](s64)
-    ; CHECK-NEXT: [[UADDE:%[0-9]+]]:_(s64), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[COPY]], [[COPY2]], %carry_in
-    ; CHECK-NEXT: %19:_(s64), %carry_out:_(s1) = G_SADDE [[COPY1]], [[COPY3]], [[UADDE1]]
-    ; CHECK-NEXT: %carry_out_ext:_(s64) = G_ANYEXT %carry_out(s1)
+    ; CHECK-NEXT: [[UADDE:%[0-9]+]]:_(s64), [[UADDE1:%[0-9]+]]:_(s32) = G_UADDE [[COPY]], [[COPY2]], %24
+    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+    ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY4]](s64)
+    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[C]]
+    ; CHECK-NEXT: [[SADDE:%[0-9]+]]:_(s64), [[SADDE1:%[0-9]+]]:_(s32) = G_SADDE [[COPY1]], [[COPY3]], %22
+    ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[UADDE1]], [[C]]
+    ; CHECK-NEXT: %carry_out_ext:_(s64) = G_ANYEXT [[SADDE1]](s32)
     ; CHECK-NEXT: $x0 = COPY [[UADDE]](s64)
-    ; CHECK-NEXT: $x1 = COPY %19(s64)
+    ; CHECK-NEXT: $x1 = COPY [[SADDE]](s64)
     ; CHECK-NEXT: $x2 = COPY %carry_out_ext(s64)
     %0:_(s64) = COPY $x0
     %1:_(s64) = COPY $x1
     %2:_(s64) = COPY $x2
     %3:_(s64) = COPY $x3
     %4:_(s64) = COPY $x4
     %lhs:_(s128) = G_MERGE_VALUES %0, %1
     %rhs:_(s128) = G_MERGE_VALUES %2, %3

 body:             |
   bb.0.entry:
     ; CHECK-LABEL: name: narrow_scalar_sadde_big_nonpow2
     ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
     ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
     ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
     ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
     ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(s64) = COPY $x4
-    ; CHECK-NEXT: %carry_in:_(s1) = G_TRUNC [[COPY4]](s64)
-    ; CHECK-NEXT: [[UADDE:%[0-9]+]]:_(s64), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[COPY]], [[COPY1]], %carry_in
-    ; CHECK-NEXT: [[UADDE2:%[0-9]+]]:_(s64), [[UADDE3:%[0-9]+]]:_(s1) = G_UADDE [[COPY1]], [[COPY2]], [[UADDE1]]
-    ; CHECK-NEXT: %24:_(s64), %carry_out:_(s1) = G_SADDE [[COPY2]], [[COPY3]], [[UADDE3]]
-    ; CHECK-NEXT: %carry_out_ext:_(s64) = G_ANYEXT %carry_out(s1)
+    ; CHECK-NEXT: [[UADDE:%[0-9]+]]:_(s64), [[UADDE1:%[0-9]+]]:_(s32) = G_UADDE [[COPY]], [[COPY1]], %31
+    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+    ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY4]](s64)
+    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[C]]
+    ; CHECK-NEXT: [[UADDE2:%[0-9]+]]:_(s64), [[UADDE3:%[0-9]+]]:_(s32) = G_UADDE [[COPY1]], [[COPY2]], %29
+    ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[UADDE1]], [[C]]
+    ; CHECK-NEXT: [[SADDE:%[0-9]+]]:_(s64), [[SADDE1:%[0-9]+]]:_(s32) = G_SADDE [[COPY2]], [[COPY3]], %27
+    ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[UADDE3]], [[C]]
+    ; CHECK-NEXT: %carry_out_ext:_(s64) = G_ANYEXT [[SADDE1]](s32)
     ; CHECK-NEXT: $x0 = COPY [[UADDE]](s64)
     ; CHECK-NEXT: $x1 = COPY [[UADDE2]](s64)
-    ; CHECK-NEXT: $x2 = COPY %24(s64)
+    ; CHECK-NEXT: $x2 = COPY [[SADDE]](s64)
     ; CHECK-NEXT: $x3 = COPY %carry_out_ext(s64)
     %0:_(s64) = COPY $x0
     %1:_(s64) = COPY $x1
     %2:_(s64) = COPY $x2
     %3:_(s64) = COPY $x3
     %4:_(s64) = COPY $x4
     %lhs:_(s192) = G_MERGE_VALUES %0, %1, %2
     %rhs:_(s192) = G_MERGE_VALUES %1, %2, %3

 ---
 name:            widen_scalar_sadde_s8
 body:             |
   bb.0.entry:
     ; CHECK-LABEL: name: widen_scalar_sadde_s8
     ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
     ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
     ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
-    ; CHECK-NEXT: %carry_in:_(s1) = G_TRUNC [[COPY2]](s64)
     ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
     ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[TRUNC]], 8
     ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
     ; CHECK-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[TRUNC1]], 8
-    ; CHECK-NEXT: [[UADDE:%[0-9]+]]:_(s32), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[SEXT_INREG]], [[SEXT_INREG1]], %carry_in
+    ; CHECK-NEXT: [[UADDE:%[0-9]+]]:_(s32), [[UADDE1:%[0-9]+]]:_(s32) = G_UADDE [[SEXT_INREG]], [[SEXT_INREG1]], %18
+    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+    ; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(s32) = G_TRUNC [[COPY2]](s64)
+    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC2]], [[C]]
     ; CHECK-NEXT: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UADDE]], 8
     ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[UADDE]](s32), [[SEXT_INREG2]]
     ; CHECK-NEXT: %add_ext:_(s64) = G_ANYEXT [[UADDE]](s32)
     ; CHECK-NEXT: %carry_out_ext:_(s64) = G_ANYEXT [[ICMP]](s32)
     ; CHECK-NEXT: $x0 = COPY %add_ext(s64)
     ; CHECK-NEXT: $x1 = COPY %carry_out_ext(s64)
     %0:_(s64) = COPY $x0
     %1:_(s64) = COPY $x1

 ---
 name:            test_scalar_sadde_32
 body:             |
   bb.0.entry:
     ; CHECK-LABEL: name: test_scalar_sadde_32
     ; CHECK: %lhs:_(s32) = COPY $w0
     ; CHECK-NEXT: %rhs:_(s32) = COPY $w1
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w2
-    ; CHECK-NEXT: %carry_in:_(s1) = G_TRUNC [[COPY]](s32)
-    ; CHECK-NEXT: %add:_(s32), %carry_out:_(s1) = G_SADDE %lhs, %rhs, %carry_in
-    ; CHECK-NEXT: %carry_out_ext:_(s32) = G_ANYEXT %carry_out(s1)
+    ; CHECK-NEXT: %add:_(s32), %7:_(s32) = G_SADDE %lhs, %rhs, %8
+    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
     ; CHECK-NEXT: $w0 = COPY %add(s32)
-    ; CHECK-NEXT: $w1 = COPY %carry_out_ext(s32)
+    ; CHECK-NEXT: $w1 = COPY %7(s32)
     %lhs:_(s32) = COPY $w0
     %rhs:_(s32) = COPY $w1
     %2:_(s32) = COPY $w2
     %carry_in:_(s1) = G_TRUNC %2
     %add:_(s32), %carry_out:_(s1) = G_SADDE %lhs, %rhs, %carry_in
     %carry_out_ext:_(s32) = G_ANYEXT %carry_out
     $w0 = COPY %add
     $w1 = COPY %carry_out_ext
 
 ...

llvm/test/CodeGen/AArch64/GlobalISel/legalize-saddo.mir

 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple aarch64 -verify-machineinstrs -run-pass=legalizer -debugify-and-strip-all-safe %s -o - | FileCheck %s
 
 ---
 name:            narrow_scalar_saddo_s128
 body:             |
   bb.0.entry:
     ; CHECK-LABEL: name: narrow_scalar_saddo_s128
     ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
     ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
     ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
     ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
-    ; CHECK-NEXT: [[UADDO:%[0-9]+]]:_(s64), [[UADDO1:%[0-9]+]]:_(s1) = G_UADDO [[COPY]], [[COPY2]]
-    ; CHECK-NEXT: %17:_(s64), %carry_out:_(s1) = G_SADDE [[COPY1]], [[COPY3]], [[UADDO1]]
-    ; CHECK-NEXT: %carry_out_ext:_(s64) = G_ANYEXT %carry_out(s1)
+    ; CHECK-NEXT: [[UADDO:%[0-9]+]]:_(s64), [[UADDO1:%[0-9]+]]:_(s32) = G_UADDO [[COPY]], [[COPY2]]
+    ; CHECK-NEXT: [[SADDE:%[0-9]+]]:_(s64), [[SADDE1:%[0-9]+]]:_(s32) = G_SADDE [[COPY1]], [[COPY3]], %20
+    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[UADDO1]], [[C]]
+    ; CHECK-NEXT: %carry_out_ext:_(s64) = G_ANYEXT [[SADDE1]](s32)
     ; CHECK-NEXT: $x0 = COPY [[UADDO]](s64)
-    ; CHECK-NEXT: $x1 = COPY %17(s64)
+    ; CHECK-NEXT: $x1 = COPY [[SADDE]](s64)
     ; CHECK-NEXT: $x2 = COPY %carry_out_ext(s64)
     %0:_(s64) = COPY $x0
     %1:_(s64) = COPY $x1
     %2:_(s64) = COPY $x2
     %3:_(s64) = COPY $x3
     %lhs:_(s128) = G_MERGE_VALUES %0, %1
     %rhs:_(s128) = G_MERGE_VALUES %2, %3
     %add:_(s128), %carry_out:_(s1) = G_SADDO %lhs, %rhs
     %add0:_(s64), %add1:_(s64) = G_UNMERGE_VALUES %add
     %carry_out_ext:_(s64) = G_ANYEXT %carry_out
     $x0 = COPY %add0
     $x1 = COPY %add1
     $x2 = COPY %carry_out_ext
 
 ...
 ---
 name:            narrow_scalar_saddo_big_nonpow2
 body:             |
   bb.0.entry:
     ; CHECK-LABEL: name: narrow_scalar_saddo_big_nonpow2
     ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
     ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
     ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
     ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
-    ; CHECK-NEXT: [[UADDO:%[0-9]+]]:_(s64), [[UADDO1:%[0-9]+]]:_(s1) = G_UADDO [[COPY]], [[COPY1]]
-    ; CHECK-NEXT: [[UADDE:%[0-9]+]]:_(s64), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[COPY1]], [[COPY2]], [[UADDO1]]
-    ; CHECK-NEXT: %22:_(s64), %carry_out:_(s1) = G_SADDE [[COPY2]], [[COPY3]], [[UADDE1]]
-    ; CHECK-NEXT: %carry_out_ext:_(s64) = G_ANYEXT %carry_out(s1)
+    ; CHECK-NEXT: [[UADDO:%[0-9]+]]:_(s64), [[UADDO1:%[0-9]+]]:_(s32) = G_UADDO [[COPY]], [[COPY1]]
+    ; CHECK-NEXT: [[UADDE:%[0-9]+]]:_(s64), [[UADDE1:%[0-9]+]]:_(s32) = G_UADDE [[COPY1]], [[COPY2]], %27
+    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[UADDO1]], [[C]]
+    ; CHECK-NEXT: [[SADDE:%[0-9]+]]:_(s64), [[SADDE1:%[0-9]+]]:_(s32) = G_SADDE [[COPY2]], [[COPY3]], %25
+    ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[UADDE1]], [[C]]
+    ; CHECK-NEXT: %carry_out_ext:_(s64) = G_ANYEXT [[SADDE1]](s32)
     ; CHECK-NEXT: $x0 = COPY [[UADDO]](s64)
     ; CHECK-NEXT: $x1 = COPY [[UADDE]](s64)
-    ; CHECK-NEXT: $x2 = COPY %22(s64)
+    ; CHECK-NEXT: $x2 = COPY [[SADDE]](s64)
     ; CHECK-NEXT: $x3 = COPY %carry_out_ext(s64)
     %0:_(s64) = COPY $x0
     %1:_(s64) = COPY $x1
     %2:_(s64) = COPY $x2
     %3:_(s64) = COPY $x3
     %lhs:_(s192) = G_MERGE_VALUES %0, %1, %2
     %rhs:_(s192) = G_MERGE_VALUES %1, %2, %3
     %add:_(s192), %carry_out:_(s1) = G_SADDO %lhs, %rhs

 ...
 ---
 name:            test_scalar_saddo_32
 body:             |
   bb.0.entry:
     ; CHECK-LABEL: name: test_scalar_saddo_32
     ; CHECK: %lhs:_(s32) = COPY $w0
     ; CHECK-NEXT: %rhs:_(s32) = COPY $w1
-    ; CHECK-NEXT: %add:_(s32), %carry_out:_(s1) = G_SADDO %lhs, %rhs
-    ; CHECK-NEXT: %carry_out_ext:_(s32) = G_ANYEXT %carry_out(s1)
+    ; CHECK-NEXT: %add:_(s32), %5:_(s32) = G_SADDO %lhs, %rhs
     ; CHECK-NEXT: $w0 = COPY %add(s32)
-    ; CHECK-NEXT: $w1 = COPY %carry_out_ext(s32)
+    ; CHECK-NEXT: $w1 = COPY %5(s32)
     %lhs:_(s32) = COPY $w0
     %rhs:_(s32) = COPY $w1
     %add:_(s32), %carry_out:_(s1) = G_SADDO %lhs, %rhs
     %carry_out_ext:_(s32) = G_ANYEXT %carry_out
     $w0 = COPY %add
     $w1 = COPY %carry_out_ext
 
 ...

llvm/test/CodeGen/AArch64/GlobalISel/legalize-saddsat.mir

 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=aarch64 -run-pass=legalizer -verify-machineinstrs -global-isel-abort=0 %s -o - | FileCheck %s
 
 ...
 ---
 name:            s32
 tracksRegLiveness: true
 body:             |
   bb.0:
     liveins: $w0, $w1
     ; CHECK-LABEL: name: s32
     ; CHECK: liveins: $w0, $w1
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: %x:_(s32) = COPY $w0
     ; CHECK-NEXT: %y:_(s32) = COPY $w1
-    ; CHECK-NEXT: [[SADDO:%[0-9]+]]:_(s32), [[SADDO1:%[0-9]+]]:_(s1) = G_SADDO %x, %y
+    ; CHECK-NEXT: [[SADDO:%[0-9]+]]:_(s32), [[SADDO1:%[0-9]+]]:_(s32) = G_SADDO %x, %y
     ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 31
     ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SADDO]], [[C]](s64)
     ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648
     ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[ASHR]], [[C1]]
-    ; CHECK-NEXT: %saddsat:_(s32) = G_SELECT [[SADDO1]](s1), [[ADD]], [[SADDO]]
+    ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[SADDO1]], [[C2]]
+    ; CHECK-NEXT: %saddsat:_(s32) = G_SELECT [[AND]](s32), [[ADD]], [[SADDO]]
     ; CHECK-NEXT: $w0 = COPY %saddsat(s32)
     ; CHECK-NEXT: RET_ReallyLR implicit $w0
     %x:_(s32) = COPY $w0
     %y:_(s32) = COPY $w1
     %saddsat:_(s32) = G_SADDSAT %x, %y
     $w0 = COPY %saddsat(s32)
     RET_ReallyLR implicit $w0
 
 ...
 ---
 name:            s64
 tracksRegLiveness: true
 body:             |
   bb.0:
     liveins: $x0, $x1
     ; CHECK-LABEL: name: s64
     ; CHECK: liveins: $x0, $x1
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: %x:_(s64) = COPY $x0
     ; CHECK-NEXT: %y:_(s64) = COPY $x1
-    ; CHECK-NEXT: [[SADDO:%[0-9]+]]:_(s64), [[SADDO1:%[0-9]+]]:_(s1) = G_SADDO %x, %y
+    ; CHECK-NEXT: [[SADDO:%[0-9]+]]:_(s64), [[SADDO1:%[0-9]+]]:_(s32) = G_SADDO %x, %y
     ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 63
     ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SADDO]], [[C]](s64)
     ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -9223372036854775808
     ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[ASHR]], [[C1]]
-    ; CHECK-NEXT: %saddsat:_(s64) = G_SELECT [[SADDO1]](s1), [[ADD]], [[SADDO]]
+    ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[SADDO1]], [[C2]]
+    ; CHECK-NEXT: %saddsat:_(s64) = G_SELECT [[AND]](s32), [[ADD]], [[SADDO]]
     ; CHECK-NEXT: $x0 = COPY %saddsat(s64)
     ; CHECK-NEXT: RET_ReallyLR implicit $x0
     %x:_(s64) = COPY $x0
     %y:_(s64) = COPY $x1
     %saddsat:_(s64) = G_SADDSAT %x, %y
     $x0 = COPY %saddsat(s64)
     RET_ReallyLR implicit $x0
 
bb.0:
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: %copy_1:_(s32) = COPY $w0
     ; CHECK-NEXT: %copy_2:_(s32) = COPY $w1
     ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG %copy_1, 16
     ; CHECK-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG %copy_2, 16
     ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[SEXT_INREG]], [[SEXT_INREG1]]
     ; CHECK-NEXT: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ADD]], 16
     ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[ADD]](s32), [[SEXT_INREG2]]
-    ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32)
     ; CHECK-NEXT: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ADD]], 16
     ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 15
     ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG3]], [[C]](s64)
     ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -32768
     ; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[ASHR]], [[C1]]
-    ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[TRUNC]](s1), [[ADD1]], [[ADD]]
+    ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C2]]
+    ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[ADD1]], [[ADD]]
     ; CHECK-NEXT: $w0 = COPY [[SELECT]](s32)
     ; CHECK-NEXT: RET_ReallyLR implicit $w0
     %copy_1:_(s32) = COPY $w0
     %x:_(s16) = G_TRUNC %copy_1(s32)
     %copy_2:_(s32) = COPY $w1
     %y:_(s16) = G_TRUNC %copy_2(s32)
     %saddsat:_(s16) = G_SADDSAT %x, %y
     %ext:_(s32) = G_ANYEXT %saddsat(s16)
bb.0:
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: %copy_1:_(s32) = COPY $w0
     ; CHECK-NEXT: %copy_2:_(s32) = COPY $w1
     ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG %copy_1, 1
     ; CHECK-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG %copy_2, 1
     ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[SEXT_INREG]], [[SEXT_INREG1]]
     ; CHECK-NEXT: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ADD]], 1
     ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[ADD]](s32), [[SEXT_INREG2]]
-    ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32)
     ; CHECK-NEXT: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ADD]], 1
     ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
     ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG3]], [[C]](s64)
     ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
     ; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[ASHR]], [[C1]]
-    ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[TRUNC]](s1), [[ADD1]], [[ADD]]
+    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C1]]
+    ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[ADD1]], [[ADD]]
     ; CHECK-NEXT: $w0 = COPY [[SELECT]](s32)
     ; CHECK-NEXT: RET_ReallyLR implicit $w0
     %copy_1:_(s32) = COPY $w0
     %x:_(s1) = G_TRUNC %copy_1(s32)
     %copy_2:_(s32) = COPY $w1
     %y:_(s1) = G_TRUNC %copy_2(s32)
     %saddsat:_(s1) = G_SADDSAT %x, %y
     %ext:_(s32) = G_ANYEXT %saddsat(s1)
bb.0:
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: %copy_1:_(s32) = COPY $w0
     ; CHECK-NEXT: %copy_2:_(s32) = COPY $w1
     ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG %copy_1, 3
     ; CHECK-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG %copy_2, 3
     ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[SEXT_INREG]], [[SEXT_INREG1]]
     ; CHECK-NEXT: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ADD]], 3
     ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[ADD]](s32), [[SEXT_INREG2]]
-    ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32)
     ; CHECK-NEXT: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ADD]], 3
     ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
     ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG3]], [[C]](s64)
     ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
     ; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[ASHR]], [[C1]]
-    ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[TRUNC]](s1), [[ADD1]], [[ADD]]
+    ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C2]]
+    ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[ADD1]], [[ADD]]
     ; CHECK-NEXT: $w0 = COPY [[SELECT]](s32)
     ; CHECK-NEXT: RET_ReallyLR implicit $w0
     %copy_1:_(s32) = COPY $w0
     %x:_(s3) = G_TRUNC %copy_1(s32)
     %copy_2:_(s32) = COPY $w1
     %y:_(s3) = G_TRUNC %copy_2(s32)
     %saddsat:_(s3) = G_SADDSAT %x, %y
     %ext:_(s32) = G_ANYEXT %saddsat(s3)
bb.0:
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: %copy_1:_(s64) = COPY $x0
     ; CHECK-NEXT: %copy_2:_(s64) = COPY $x1
     ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG %copy_1, 36
     ; CHECK-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG %copy_2, 36
     ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[SEXT_INREG]], [[SEXT_INREG1]]
     ; CHECK-NEXT: [[SEXT_INREG2:%[0-9]+]]:_(s64) = G_SEXT_INREG [[ADD]], 36
     ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[ADD]](s64), [[SEXT_INREG2]]
-    ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32)
     ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 35
     ; CHECK-NEXT: [[SEXT_INREG3:%[0-9]+]]:_(s64) = G_SEXT_INREG [[ADD]], 36
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY [[C]](s64)
     ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SEXT_INREG3]], [[COPY]](s64)
     ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 34359738368
     ; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(s64) = G_ADD [[ASHR]], [[C1]]
-    ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[TRUNC]](s1), [[ADD1]], [[ADD]]
+    ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C2]]
+    ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[AND]](s32), [[ADD1]], [[ADD]]
     ; CHECK-NEXT: $x0 = COPY [[SELECT]](s64)
     ; CHECK-NEXT: RET_ReallyLR implicit $x0
     %copy_1:_(s64) = COPY $x0
     %x:_(s36) = G_TRUNC %copy_1(s64)
     %copy_2:_(s64) = COPY $x1
     %y:_(s36) = G_TRUNC %copy_2(s64)
     %saddsat:_(s36) = G_SADDSAT %x, %y
     %ext:_(s64) = G_ANYEXT %saddsat(s36)
bb.0:
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: %copy_1:_(s128) = COPY $q0
     ; CHECK-NEXT: %copy_2:_(s128) = COPY $q1
     ; CHECK-NEXT: [[EXTRACT:%[0-9]+]]:_(s64) = G_EXTRACT %copy_1(s128), 0
     ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
     ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES %copy_1(s128)
     ; CHECK-NEXT: [[EXTRACT1:%[0-9]+]]:_(s64) = G_EXTRACT %copy_2(s128), 0
     ; CHECK-NEXT: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES %copy_2(s128)
-    ; CHECK-NEXT: [[UADDO:%[0-9]+]]:_(s64), [[UADDO1:%[0-9]+]]:_(s1) = G_UADDO [[EXTRACT]], [[EXTRACT1]]
+    ; CHECK-NEXT: [[UADDO:%[0-9]+]]:_(s64), [[UADDO1:%[0-9]+]]:_(s32) = G_UADDO [[EXTRACT]], [[EXTRACT1]]
     ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[UV1]](s64)
     ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[TRUNC]], 24
     ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[UV3]](s64)
     ; CHECK-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[TRUNC1]], 24
-    ; CHECK-NEXT: [[UADDE:%[0-9]+]]:_(s32), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[SEXT_INREG]], [[SEXT_INREG1]], [[UADDO1]]
+    ; CHECK-NEXT: [[UADDE:%[0-9]+]]:_(s32), [[UADDE1:%[0-9]+]]:_(s32) = G_UADDE [[SEXT_INREG]], [[SEXT_INREG1]], %85
+    ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[UADDO1]], [[C1]]
     ; CHECK-NEXT: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UADDE]], 24
     ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[UADDE]](s32), [[SEXT_INREG2]]
-    ; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32)
     ; CHECK-NEXT: [[UV4:%[0-9]+]]:_(s8), [[UV5:%[0-9]+]]:_(s8), [[UV6:%[0-9]+]]:_(s8), [[UV7:%[0-9]+]]:_(s8), [[UV8:%[0-9]+]]:_(s8), [[UV9:%[0-9]+]]:_(s8), [[UV10:%[0-9]+]]:_(s8), [[UV11:%[0-9]+]]:_(s8) = G_UNMERGE_VALUES [[UADDO]](s64)
     ; CHECK-NEXT: [[UV12:%[0-9]+]]:_(s8), [[UV13:%[0-9]+]]:_(s8), [[UV14:%[0-9]+]]:_(s8), [[UV15:%[0-9]+]]:_(s8) = G_UNMERGE_VALUES [[UADDE]](s32)
     ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s8) = G_IMPLICIT_DEF
     ; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
     ; CHECK-NEXT: [[UV16:%[0-9]+]]:_(s8), [[UV17:%[0-9]+]]:_(s8), [[UV18:%[0-9]+]]:_(s8), [[UV19:%[0-9]+]]:_(s8) = G_UNMERGE_VALUES [[DEF1]](s32)
     ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s32) = G_MERGE_VALUES [[UV4]](s8), [[UV5]](s8), [[UV6]](s8), [[UV7]](s8)
     ; CHECK-NEXT: [[MV1:%[0-9]+]]:_(s32) = G_MERGE_VALUES [[UV8]](s8), [[UV9]](s8), [[UV10]](s8), [[UV11]](s8)
     ; CHECK-NEXT: [[MV2:%[0-9]+]]:_(s32) = G_MERGE_VALUES [[UV12]](s8), [[UV13]](s8), [[UV14]](s8), [[DEF]](s8)
     ; CHECK-NEXT: [[MV3:%[0-9]+]]:_(s32) = G_MERGE_VALUES [[UV16]](s8), [[UV17]](s8), [[UV18]](s8), [[UV16]](s8)
-    ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 40
+    ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 40
     ; CHECK-NEXT: [[MV4:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[MV]](s32), [[MV1]](s32)
     ; CHECK-NEXT: [[MV5:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[MV2]](s32), [[MV3]](s32)
-    ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[MV5]], [[C1]](s64)
-    ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 24
-    ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[MV4]], [[C2]](s64)
+    ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[MV5]], [[C2]](s64)
+    ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 24
+    ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[MV4]], [[C3]](s64)
     ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[SHL]], [[LSHR]]
-    ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[OR]], [[C1]](s64)
-    ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 23
-    ; CHECK-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[ASHR]], [[C3]](s64)
-    ; CHECK-NEXT: [[UADDO2:%[0-9]+]]:_(s64), [[UADDO3:%[0-9]+]]:_(s1) = G_UADDO [[ASHR1]], [[C]]
+    ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[OR]], [[C2]](s64)
+    ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 23
+    ; CHECK-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[ASHR]], [[C4]](s64)
+    ; CHECK-NEXT: [[UADDO2:%[0-9]+]]:_(s64), [[UADDO3:%[0-9]+]]:_(s32) = G_UADDO [[ASHR1]], [[C]]
     ; CHECK-NEXT: [[MV6:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[MV]](s32), [[MV1]](s32)
-    ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[TRUNC2]](s1), [[UADDO2]], [[MV6]]
+    ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C1]]
+    ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[AND1]](s32), [[UADDO2]], [[MV6]]
     ; CHECK-NEXT: $x0 = COPY [[SELECT]](s64)
     ; CHECK-NEXT: RET_ReallyLR implicit $x0
     %copy_1:_(s128) = COPY $q0
     %x:_(s88) = G_TRUNC %copy_1(s128)
     %copy_2:_(s128) = COPY $q1
     %y:_(s88) = G_TRUNC %copy_2(s128)
     %saddsat:_(s88) = G_SADDSAT %x, %y
     %trunc:_(s64) = G_TRUNC %saddsat(s88)
     $x0 = COPY %trunc(s64)
     RET_ReallyLR implicit $x0

llvm/test/CodeGen/AArch64/GlobalISel/legalize-select.mir

bb.1:
     ; CHECK: liveins: $q0, $w0
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
     ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $q0
     ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4100
     ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
     ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[C1]](s32), [[C1]](s32), [[C1]](s32), [[C1]](s32)
     ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY]](s32), [[C]]
-    ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ICMP]], 1
+    ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C2]]
+    ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[AND]], 1
+    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[SEXT_INREG]](s32)
     ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<4 x s32>) = G_IMPLICIT_DEF
-    ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
-    ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<4 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], [[SEXT_INREG]](s32), [[C2]](s64)
+    ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
+    ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<4 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], [[COPY2]](s32), [[C3]](s64)
     ; CHECK-NEXT: [[SHUF:%[0-9]+]]:_(<4 x s32>) = G_SHUFFLE_VECTOR [[IVEC]](<4 x s32>), [[DEF]], shufflemask(0, 0, 0, 0)
-    ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
-    ; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[C3]](s32), [[C3]](s32), [[C3]](s32), [[C3]](s32)
+    ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
+    ; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[C4]](s32), [[C4]](s32), [[C4]](s32), [[C4]](s32)
     ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<4 x s32>) = G_XOR [[SHUF]], [[BUILD_VECTOR1]]
-    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<4 x s32>) = G_AND [[COPY1]], [[SHUF]]
-    ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<4 x s32>) = G_AND [[BUILD_VECTOR]], [[XOR]]
-    ; CHECK-NEXT: [[OR:%[0-9]+]]:_(<4 x s32>) = G_OR [[AND]], [[AND1]]
+    ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<4 x s32>) = G_AND [[COPY1]], [[SHUF]]
+    ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(<4 x s32>) = G_AND [[BUILD_VECTOR]], [[XOR]]
+    ; CHECK-NEXT: [[OR:%[0-9]+]]:_(<4 x s32>) = G_OR [[AND1]], [[AND2]]
     ; CHECK-NEXT: $q0 = COPY [[OR]](<4 x s32>)
     ; CHECK-NEXT: RET_ReallyLR implicit $q0
     %0:_(s32) = COPY $w0
     %1:_(<4 x s32>) = COPY $q0
     %2:_(s32) = G_CONSTANT i32 4100
     %6:_(s32) = G_FCONSTANT float 0.000000e+00
     %5:_(<4 x s32>) = G_BUILD_VECTOR %6(s32), %6(s32), %6(s32), %6(s32)
     %3:_(s1) = G_ICMP intpred(eq), %0(s32), %2
bb.0:
     liveins: $w0, $w1, $x0
 
     ; CHECK-LABEL: name: s88
     ; CHECK: liveins: $w0, $w1, $x0
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: %a:_(s32) = COPY $w0
     ; CHECK-NEXT: %b:_(s32) = COPY $w1
     ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(sgt), %a(s32), %b
-    ; CHECK-NEXT: %cmp:_(s1) = G_TRUNC [[ICMP]](s32)
     ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
-    ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT %cmp(s1), [[DEF]], [[DEF]]
+    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C]]
+    ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[AND]](s32), [[DEF]], [[DEF]]
     ; CHECK-NEXT: $x0 = COPY [[SELECT]](s64)
     ; CHECK-NEXT: RET_ReallyLR implicit $x0
     %a:_(s32) = COPY $w0
     %b:_(s32) = COPY $w1
     %cmp:_(s1) = G_ICMP intpred(sgt), %a(s32), %b
     %sel_a:_(s88) = G_IMPLICIT_DEF
     %sel_b:_(s88) = G_IMPLICIT_DEF
     %select:_(s88) = G_SELECT %cmp(s1), %sel_a, %sel_b
bb.0:
     ; CHECK-NEXT: %q1:_(<4 x s32>) = COPY $q1
     ; CHECK-NEXT: %q2:_(<4 x s32>) = COPY $q2
     ; CHECK-NEXT: %vec_cond0:_(<4 x s1>) = G_ICMP intpred(eq), %q0(<4 x s32>), %q1
     ; CHECK-NEXT: %vec_cond1:_(<4 x s1>) = G_ICMP intpred(eq), %q0(<4 x s32>), %q2
     ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4100
     ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
     ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[C1]](s32), [[C1]](s32), [[C1]](s32), [[C1]](s32)
     ; CHECK-NEXT: %cmp:_(s1) = G_ICMP intpred(eq), %w0(s32), [[C]]
-    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s1) = COPY %cmp(s1)
+    ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT %cmp(s1)
+    ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ZEXT]](s32)
     ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<4 x s1>) = G_IMPLICIT_DEF
     ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
-    ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<4 x s1>) = G_INSERT_VECTOR_ELT [[DEF]], [[COPY]](s1), [[C2]](s64)
+    ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<4 x s1>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s1), [[C2]](s64)
     ; CHECK-NEXT: [[SHUF:%[0-9]+]]:_(<4 x s1>) = G_SHUFFLE_VECTOR [[IVEC]](<4 x s1>), [[DEF]], shufflemask(0, 0, 0, 0)
     ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s1) = G_CONSTANT i1 true
     ; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s1>) = G_BUILD_VECTOR [[C3]](s1), [[C3]](s1), [[C3]](s1), [[C3]](s1)
     ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<4 x s1>) = G_XOR [[SHUF]], [[BUILD_VECTOR1]]
     ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<4 x s1>) = G_AND %vec_cond0, [[SHUF]]
     ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<4 x s1>) = G_AND %vec_cond1, [[XOR]]
     ; CHECK-NEXT: %select:_(<4 x s1>) = G_OR [[AND]], [[AND1]]
     ; CHECK-NEXT: %zext_select:_(<4 x s32>) = G_ZEXT %select(<4 x s1>)

llvm/test/CodeGen/AArch64/GlobalISel/legalize-shift.mir

bb.0:
     ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s128) = COPY $q1
     ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s64) = G_TRUNC [[COPY1]](s128)
     ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 64
     ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
     ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[TRUNC]], [[C]]
     ; CHECK-NEXT: [[SUB1:%[0-9]+]]:_(s64) = G_SUB [[C]], [[TRUNC]]
     ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
     ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[TRUNC]](s64), [[C]]
-    ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32)
     ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[TRUNC]](s64), [[C1]]
-    ; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP1]](s32)
     ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[UV]], [[TRUNC]](s64)
     ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[UV]], [[SUB1]](s64)
     ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[UV1]], [[TRUNC]](s64)
     ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR]], [[SHL1]]
     ; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s64) = G_SHL [[UV]], [[SUB]](s64)
-    ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[TRUNC1]](s1), [[SHL]], [[C1]]
-    ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[TRUNC1]](s1), [[OR]], [[SHL2]]
-    ; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[TRUNC2]](s1), [[UV1]], [[SELECT1]]
+    ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C2]]
+    ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[AND]](s32), [[SHL]], [[C1]]
+    ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C2]]
+    ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[AND1]](s32), [[OR]], [[SHL2]]
+    ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ICMP1]], [[C2]]
+    ; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[AND2]](s32), [[UV1]], [[SELECT1]]
     ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SELECT]](s64), [[SELECT2]](s64)
     ; CHECK-NEXT: $q0 = COPY [[MV]](s128)
     %0:_(s128) = COPY $q0
     %1:_(s128) = COPY $q1
     %2:_(s128) = G_SHL %0, %1
     $q0 = COPY %2
 
 ...
 
 ---
 name: test_lshr_s128_s128
 body:             |
   bb.0:
     ; CHECK-LABEL: name: test_lshr_s128_s128
     ; CHECK: [[COPY:%[0-9]+]]:_(s128) = COPY $q0
     ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s128) = COPY $q1
     ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s64) = G_TRUNC [[COPY1]](s128)
     ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 64
     ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
     ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[TRUNC]], [[C]]
     ; CHECK-NEXT: [[SUB1:%[0-9]+]]:_(s64) = G_SUB [[C]], [[TRUNC]]
     ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
     ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[TRUNC]](s64), [[C]]
-    ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32)
     ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[TRUNC]](s64), [[C1]]
-    ; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP1]](s32)
     ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[UV1]], [[TRUNC]](s64)
     ; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[UV]], [[TRUNC]](s64)
     ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[UV1]], [[SUB1]](s64)
     ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR1]], [[SHL]]
     ; CHECK-NEXT: [[LSHR2:%[0-9]+]]:_(s64) = G_LSHR [[UV1]], [[SUB]](s64)
-    ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[TRUNC1]](s1), [[OR]], [[LSHR2]]
-    ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[TRUNC2]](s1), [[UV]], [[SELECT]]
-    ; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[TRUNC1]](s1), [[LSHR]], [[C1]]
+    ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C2]]
+    ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[AND]](s32), [[OR]], [[LSHR2]]
+    ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ICMP1]], [[C2]]
+    ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[AND1]](s32), [[UV]], [[SELECT]]
+    ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C2]]
+    ; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[AND2]](s32), [[LSHR]], [[C1]]
     ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SELECT1]](s64), [[SELECT2]](s64)
     ; CHECK-NEXT: $q0 = COPY [[MV]](s128)
     %0:_(s128) = COPY $q0
     %1:_(s128) = COPY $q1
     %2:_(s128) = G_LSHR %0, %1
     $q0 = COPY %2
 
 ...
 
 ---
 name: test_ashr_s128_s128
 body:             |
   bb.0:
     ; CHECK-LABEL: name: test_ashr_s128_s128
     ; CHECK: [[COPY:%[0-9]+]]:_(s128) = COPY $q0
     ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s128) = COPY $q1
     ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s64) = G_TRUNC [[COPY1]](s128)
     ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 64
     ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
     ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[TRUNC]], [[C]]
     ; CHECK-NEXT: [[SUB1:%[0-9]+]]:_(s64) = G_SUB [[C]], [[TRUNC]]
     ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
     ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[TRUNC]](s64), [[C]]
-    ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32)
     ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[TRUNC]](s64), [[C1]]
-    ; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP1]](s32)
     ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[UV1]], [[TRUNC]](s64)
     ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[UV]], [[TRUNC]](s64)
     ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[UV1]], [[SUB1]](s64)
     ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR]], [[SHL]]
     ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 63
     ; CHECK-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[UV1]], [[C2]](s64)
     ; CHECK-NEXT: [[ASHR2:%[0-9]+]]:_(s64) = G_ASHR [[UV1]], [[SUB]](s64)
-    ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[TRUNC1]](s1), [[OR]], [[ASHR2]]
-    ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[TRUNC2]](s1), [[UV]], [[SELECT]]
-    ; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[TRUNC1]](s1), [[ASHR]], [[ASHR1]]
+    ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C3]]
+    ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[AND]](s32), [[OR]], [[ASHR2]]
+    ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ICMP1]], [[C3]]
+    ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[AND1]](s32), [[UV]], [[SELECT]]
+    ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C3]]
+    ; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[AND2]](s32), [[ASHR]], [[ASHR1]]
     ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SELECT1]](s64), [[SELECT2]](s64)
     ; CHECK-NEXT: $q0 = COPY [[MV]](s128)
     %0:_(s128) = COPY $q0
     %1:_(s128) = COPY $q1
     %2:_(s128) = G_ASHR %0, %1
     $q0 = COPY %2
 
 ...
bb.0:
     ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
     ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES %a(s32), %a(s32)
     ; CHECK-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES %a(s32), [[C]](s32)
     ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 64
     ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[COPY]], [[C1]]
     ; CHECK-NEXT: [[SUB1:%[0-9]+]]:_(s64) = G_SUB [[C1]], [[COPY]]
     ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
     ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY]](s64), [[C1]]
-    ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32)
     ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY]](s64), [[C2]]
-    ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP1]](s32)
     ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[MV]], [[COPY]](s64)
     ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[MV1]], [[SUB1]](s64)
     ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR]], [[SHL]]
     ; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[MV1]], [[SUB]](s64)
-    ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[TRUNC]](s1), [[OR]], [[LSHR1]]
-    ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[TRUNC1]](s1), [[MV]], [[SELECT]]
+    ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C3]]
+    ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[AND]](s32), [[OR]], [[LSHR1]]
+    ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ICMP1]], [[C3]]
+    ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[AND1]](s32), [[MV]], [[SELECT]]
     ; CHECK-NEXT: %d1:_(s32), %d2:_(s32) = G_UNMERGE_VALUES [[SELECT1]](s64)
     ; CHECK-NEXT: $w0 = COPY %d2(s32)
     %0:_(s64) = COPY $x0
     %a:_(s32) = COPY $w1
     %merge:_(s96) = G_MERGE_VALUES %a, %a, %a
     %lshr:_(s96) = G_LSHR %merge, %0
     %d1:_(s32), %d2:_(s32), %d3:_(s32) = G_UNMERGE_VALUES %lshr
     $w0 = COPY %d2(s32)
bb.0:
     ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES %a(s32), %a(s32)
     ; CHECK-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES %a(s32), %a(s32)
     ; CHECK-NEXT: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES %a(s32), [[C]](s32)
     ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
     ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 128
     ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[COPY]], [[C2]]
     ; CHECK-NEXT: [[SUB1:%[0-9]+]]:_(s64) = G_SUB [[C2]], [[COPY]]
     ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY]](s64), [[C2]]
-    ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32)
     ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY]](s64), [[C1]]
-    ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP1]](s32)
     ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 64
+    ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
     ; CHECK-NEXT: [[SUB2:%[0-9]+]]:_(s64) = G_SUB [[COPY]], [[C3]]
     ; CHECK-NEXT: [[SUB3:%[0-9]+]]:_(s64) = G_SUB [[C3]], [[COPY]]
     ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY]](s64), [[C3]]
-    ; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP2]](s32)
     ; CHECK-NEXT: [[ICMP3:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY]](s64), [[C1]]
-    ; CHECK-NEXT: [[TRUNC3:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP3]](s32)
     ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[MV]], [[COPY]](s64)
     ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[MV1]], [[SUB3]](s64)
     ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR]], [[SHL]]
     ; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[MV1]], [[SUB2]](s64)
-    ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[TRUNC2]](s1), [[OR]], [[LSHR1]]
-    ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[TRUNC3]](s1), [[MV]], [[SELECT]]
+    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP2]], [[C4]]
+    ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[AND]](s32), [[OR]], [[LSHR1]]
+    ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ICMP3]], [[C4]]
+    ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[AND1]](s32), [[MV]], [[SELECT]]
     ; CHECK-NEXT: [[ICMP4:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[SUB1]](s64), [[C3]]
-    ; CHECK-NEXT: [[TRUNC4:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP4]](s32)
     ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[MV2]], [[SUB1]](s64)
-    ; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[TRUNC4]](s1), [[SHL1]], [[C1]]
+    ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ICMP4]], [[C4]]
+    ; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[AND2]](s32), [[SHL1]], [[C1]]
     ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[SELECT1]], [[SELECT2]]
     ; CHECK-NEXT: [[SUB4:%[0-9]+]]:_(s64) = G_SUB [[SUB]], [[C3]]
     ; CHECK-NEXT: [[SUB5:%[0-9]+]]:_(s64) = G_SUB [[C3]], [[SUB]]
     ; CHECK-NEXT: [[ICMP5:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[SUB]](s64), [[C3]]
-    ; CHECK-NEXT: [[TRUNC5:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP5]](s32)
     ; CHECK-NEXT: [[ICMP6:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[SUB]](s64), [[C1]]
-    ; CHECK-NEXT: [[TRUNC6:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP6]](s32)
     ; CHECK-NEXT: [[LSHR2:%[0-9]+]]:_(s64) = G_LSHR [[MV2]], [[SUB]](s64)
     ; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s64) = G_SHL [[C1]], [[SUB5]](s64)
     ; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[LSHR2]], [[SHL2]]
     ; CHECK-NEXT: [[LSHR3:%[0-9]+]]:_(s64) = G_LSHR [[C1]], [[SUB4]](s64)
-    ; CHECK-NEXT: [[SELECT3:%[0-9]+]]:_(s64) = G_SELECT [[TRUNC5]](s1), [[OR2]], [[LSHR3]]
-    ; CHECK-NEXT: [[SELECT4:%[0-9]+]]:_(s64) = G_SELECT [[TRUNC6]](s1), [[MV2]], [[SELECT3]]
-    ; CHECK-NEXT: [[SELECT5:%[0-9]+]]:_(s64) = G_SELECT [[TRUNC]](s1), [[OR1]], [[SELECT4]]
-    ; CHECK-NEXT: [[SELECT6:%[0-9]+]]:_(s64) = G_SELECT [[TRUNC1]](s1), [[MV]], [[SELECT5]]
+    ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[ICMP5]], [[C4]]
+    ; CHECK-NEXT: [[SELECT3:%[0-9]+]]:_(s64) = G_SELECT [[AND3]](s32), [[OR2]], [[LSHR3]]
+    ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[ICMP6]], [[C4]]
+    ; CHECK-NEXT: [[SELECT4:%[0-9]+]]:_(s64) = G_SELECT [[AND4]](s32), [[MV2]], [[SELECT3]]
+    ; CHECK-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C4]]
+    ; CHECK-NEXT: [[SELECT5:%[0-9]+]]:_(s64) = G_SELECT [[AND5]](s32), [[OR1]], [[SELECT4]]
+    ; CHECK-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[ICMP1]], [[C4]]
+    ; CHECK-NEXT: [[SELECT6:%[0-9]+]]:_(s64) = G_SELECT [[AND6]](s32), [[MV]], [[SELECT5]]
     ; CHECK-NEXT: %d1:_(s32), %d2:_(s32) = G_UNMERGE_VALUES [[SELECT6]](s64)
     ; CHECK-NEXT: $w0 = COPY %d2(s32)
     %0:_(s64) = COPY $x0
     %a:_(s32) = COPY $w1
     %merge:_(s160) = G_MERGE_VALUES %a, %a, %a, %a, %a
     %lshr:_(s160) = G_LSHR %merge, %0
     %d1:_(s32), %d2:_(s32), %d3:_(s32), %d4:_(s32), %d5:_(s32) = G_UNMERGE_VALUES %lshr
     $w0 = COPY %d2(s32)
 
 ...

llvm/test/CodeGen/AArch64/GlobalISel/legalize-simple.mir

 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -O0 -march=aarch64 -run-pass=legalizer %s -o - | FileCheck %s
 ---
 name:            test_simple
 body:             |
   ; CHECK-LABEL: name: test_simple
   ; CHECK: bb.0.entry:
   ; CHECK-NEXT:   successors: %bb.1(0x80000000)
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT:   [[COPY:%[0-9]+]]:_(s64) = COPY $x0
-  ; CHECK-NEXT:   [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY]](s64)
-  ; CHECK-NEXT:   [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
+  ; CHECK-NEXT:   [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
   ; CHECK-NEXT:   [[INTTOPTR:%[0-9]+]]:_(p0) = G_INTTOPTR [[COPY]](s64)
   ; CHECK-NEXT:   [[PTRTOINT:%[0-9]+]]:_(s64) = G_PTRTOINT [[INTTOPTR]](p0)
   ; CHECK-NEXT:   $x0 = COPY [[PTRTOINT]](s64)
-  ; CHECK-NEXT:   G_BRCOND [[TRUNC]](s1), %bb.1
+  ; CHECK-NEXT:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+  ; CHECK-NEXT:   [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
+  ; CHECK-NEXT:   [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC1]], [[C]]
+  ; CHECK-NEXT:   G_BRCOND [[AND]](s32), %bb.1
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT: bb.1:
   ; CHECK-NEXT:   [[TRUNC2:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
   ; CHECK-NEXT:   [[TRUNC3:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
-  ; CHECK-NEXT:   [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[TRUNC]](s1), [[TRUNC2]], [[TRUNC3]]
-  ; CHECK-NEXT:   $w0 = COPY [[SELECT]](s32)
+  ; CHECK-NEXT:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
   ; CHECK-NEXT:   [[TRUNC4:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
+  ; CHECK-NEXT:   [[AND1:%[0-9]+]]:_(s32) = G_AND [[TRUNC4]], [[C1]]
+  ; CHECK-NEXT:   [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND1]](s32), [[TRUNC2]], [[TRUNC3]]
+  ; CHECK-NEXT:   $w0 = COPY [[SELECT]](s32)
   ; CHECK-NEXT:   [[TRUNC5:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
-  ; CHECK-NEXT:   [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[TRUNC]](s1), [[TRUNC4]], [[TRUNC5]]
-  ; CHECK-NEXT:   $w0 = COPY [[SELECT1]](s32)
   ; CHECK-NEXT:   [[TRUNC6:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
   ; CHECK-NEXT:   [[TRUNC7:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
-  ; CHECK-NEXT:   [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[TRUNC]](s1), [[TRUNC6]], [[TRUNC7]]
+  ; CHECK-NEXT:   [[AND2:%[0-9]+]]:_(s32) = G_AND [[TRUNC7]], [[C1]]
+  ; CHECK-NEXT:   [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[AND2]](s32), [[TRUNC5]], [[TRUNC6]]
+  ; CHECK-NEXT:   $w0 = COPY [[SELECT1]](s32)
+  ; CHECK-NEXT:   [[TRUNC8:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
+  ; CHECK-NEXT:   [[TRUNC9:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
+  ; CHECK-NEXT:   [[TRUNC10:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
+  ; CHECK-NEXT:   [[AND3:%[0-9]+]]:_(s32) = G_AND [[TRUNC10]], [[C1]]
+  ; CHECK-NEXT:   [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[AND3]](s32), [[TRUNC8]], [[TRUNC9]]
   ; CHECK-NEXT:   $w0 = COPY [[SELECT2]](s32)
-  ; CHECK-NEXT:   [[SELECT3:%[0-9]+]]:_(s32) = G_SELECT [[TRUNC]](s1), [[TRUNC1]], [[TRUNC1]]
-  ; CHECK-NEXT:   [[SELECT4:%[0-9]+]]:_(s64) = G_SELECT [[TRUNC]](s1), [[COPY]], [[COPY]]
+  ; CHECK-NEXT:   [[TRUNC11:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
+  ; CHECK-NEXT:   [[AND4:%[0-9]+]]:_(s32) = G_AND [[TRUNC11]], [[C1]]
+  ; CHECK-NEXT:   [[SELECT3:%[0-9]+]]:_(s32) = G_SELECT [[AND4]](s32), [[TRUNC]], [[TRUNC]]
+  ; CHECK-NEXT:   [[TRUNC12:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
+  ; CHECK-NEXT:   [[AND5:%[0-9]+]]:_(s32) = G_AND [[TRUNC12]], [[C1]]
+  ; CHECK-NEXT:   [[SELECT4:%[0-9]+]]:_(s64) = G_SELECT [[AND5]](s32), [[COPY]], [[COPY]]
   ; CHECK-NEXT:   $x0 = COPY [[SELECT4]](s64)
   ; CHECK-NEXT:   [[BITCAST:%[0-9]+]]:_(<2 x s32>) = G_BITCAST [[COPY]](s64)
   ; CHECK-NEXT:   [[BITCAST1:%[0-9]+]]:_(s64) = G_BITCAST [[BITCAST]](<2 x s32>)
   ; CHECK-NEXT:   $x0 = COPY [[BITCAST1]](s64)
   ; CHECK-NEXT:   [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[SELECT3]](s32)
   ; CHECK-NEXT:   $w0 = COPY [[BITCAST2]](<2 x s16>)
-  ; CHECK-NEXT:   [[BITCAST3:%[0-9]+]]:_(<4 x s8>) = G_BITCAST [[TRUNC1]](s32)
+  ; CHECK-NEXT:   [[BITCAST3:%[0-9]+]]:_(<4 x s8>) = G_BITCAST [[TRUNC]](s32)
   ; CHECK-NEXT:   [[BITCAST4:%[0-9]+]]:_(s32) = G_BITCAST [[BITCAST3]](<4 x s8>)
   ; CHECK-NEXT:   $w0 = COPY [[BITCAST4]](s32)
-  ; CHECK-NEXT:   [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[TRUNC1]](s32)
+  ; CHECK-NEXT:   [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[TRUNC]](s32)
   ; CHECK-NEXT:   [[BITCAST6:%[0-9]+]]:_(s32) = G_BITCAST [[BITCAST5]](<2 x s16>)
   ; CHECK-NEXT:   $w0 = COPY [[BITCAST6]](s32)
   bb.0.entry:
     successors: %bb.1(0x80000000)
 
     %0:_(s64) = COPY $x0
     %1:_(s1) = G_TRUNC %0(s64)
     %2:_(s8) = G_TRUNC %0(s64)

llvm/test/CodeGen/AArch64/GlobalISel/legalize-ssube.mir

 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple aarch64 -verify-machineinstrs -run-pass=legalizer -debugify-and-strip-all-safe %s -o - | FileCheck %s
 
 ---
 name:            narrow_scalar_ssube_s128
 body:             |
   bb.0.entry:
     ; CHECK-LABEL: name: narrow_scalar_ssube_s128
     ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
     ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
     ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
     ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
     ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(s64) = COPY $x4
-    ; CHECK-NEXT: %carry_in:_(s1) = G_TRUNC [[COPY4]](s64)
-    ; CHECK-NEXT: [[USUBE:%[0-9]+]]:_(s64), [[USUBE1:%[0-9]+]]:_(s1) = G_USUBE [[COPY]], [[COPY2]], %carry_in
-    ; CHECK-NEXT: %19:_(s64), %carry_out:_(s1) = G_SSUBE [[COPY1]], [[COPY3]], [[USUBE1]]
-    ; CHECK-NEXT: %carry_out_ext:_(s64) = G_ANYEXT %carry_out(s1)
+    ; CHECK-NEXT: [[USUBE:%[0-9]+]]:_(s64), [[USUBE1:%[0-9]+]]:_(s32) = G_USUBE [[COPY]], [[COPY2]], %24
+    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+    ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY4]](s64)
+    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[C]]
+    ; CHECK-NEXT: [[SSUBE:%[0-9]+]]:_(s64), [[SSUBE1:%[0-9]+]]:_(s32) = G_SSUBE [[COPY1]], [[COPY3]], %22
+    ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[USUBE1]], [[C]]
+    ; CHECK-NEXT: %carry_out_ext:_(s64) = G_ANYEXT [[SSUBE1]](s32)
     ; CHECK-NEXT: $x0 = COPY [[USUBE]](s64)
-    ; CHECK-NEXT: $x1 = COPY %19(s64)
+    ; CHECK-NEXT: $x1 = COPY [[SSUBE]](s64)
     ; CHECK-NEXT: $x2 = COPY %carry_out_ext(s64)
     %0:_(s64) = COPY $x0
     %1:_(s64) = COPY $x1
     %2:_(s64) = COPY $x2
     %3:_(s64) = COPY $x3
     %4:_(s64) = COPY $x4
     %lhs:_(s128) = G_MERGE_VALUES %0, %1
     %rhs:_(s128) = G_MERGE_VALUES %2, %3

 body:             |
   bb.0.entry:
     ; CHECK-LABEL: name: narrow_scalar_ssube_big_nonpow2
     ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
     ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
     ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
     ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
     ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(s64) = COPY $x4
-    ; CHECK-NEXT: %carry_in:_(s1) = G_TRUNC [[COPY4]](s64)
-    ; CHECK-NEXT: [[USUBE:%[0-9]+]]:_(s64), [[USUBE1:%[0-9]+]]:_(s1) = G_USUBE [[COPY]], [[COPY1]], %carry_in
-    ; CHECK-NEXT: [[USUBE2:%[0-9]+]]:_(s64), [[USUBE3:%[0-9]+]]:_(s1) = G_USUBE [[COPY1]], [[COPY2]], [[USUBE1]]
-    ; CHECK-NEXT: %24:_(s64), %carry_out:_(s1) = G_SSUBE [[COPY2]], [[COPY3]], [[USUBE3]]
-    ; CHECK-NEXT: %carry_out_ext:_(s64) = G_ANYEXT %carry_out(s1)
+    ; CHECK-NEXT: [[USUBE:%[0-9]+]]:_(s64), [[USUBE1:%[0-9]+]]:_(s32) = G_USUBE [[COPY]], [[COPY1]], %31
+    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+    ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY4]](s64)
+    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[C]]
+    ; CHECK-NEXT: [[USUBE2:%[0-9]+]]:_(s64), [[USUBE3:%[0-9]+]]:_(s32) = G_USUBE [[COPY1]], [[COPY2]], %29
+    ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[USUBE1]], [[C]]
+    ; CHECK-NEXT: [[SSUBE:%[0-9]+]]:_(s64), [[SSUBE1:%[0-9]+]]:_(s32) = G_SSUBE [[COPY2]], [[COPY3]], %27
+    ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[USUBE3]], [[C]]
+    ; CHECK-NEXT: %carry_out_ext:_(s64) = G_ANYEXT [[SSUBE1]](s32)
     ; CHECK-NEXT: $x0 = COPY [[USUBE]](s64)
     ; CHECK-NEXT: $x1 = COPY [[USUBE2]](s64)
-    ; CHECK-NEXT: $x2 = COPY %24(s64)
+    ; CHECK-NEXT: $x2 = COPY [[SSUBE]](s64)
     ; CHECK-NEXT: $x3 = COPY %carry_out_ext(s64)
     %0:_(s64) = COPY $x0
     %1:_(s64) = COPY $x1
     %2:_(s64) = COPY $x2
     %3:_(s64) = COPY $x3
     %4:_(s64) = COPY $x4
     %lhs:_(s192) = G_MERGE_VALUES %0, %1, %2
     %rhs:_(s192) = G_MERGE_VALUES %1, %2, %3

 ---
 name:            widen_scalar_ssube_s8
 body:             |
   bb.0.entry:
     ; CHECK-LABEL: name: widen_scalar_ssube_s8
     ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
     ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
     ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
-    ; CHECK-NEXT: %carry_in:_(s1) = G_TRUNC [[COPY2]](s64)
     ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
     ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[TRUNC]], 8
     ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
     ; CHECK-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[TRUNC1]], 8
-    ; CHECK-NEXT: [[USUBE:%[0-9]+]]:_(s32), [[USUBE1:%[0-9]+]]:_(s1) = G_USUBE [[SEXT_INREG]], [[SEXT_INREG1]], %carry_in
+    ; CHECK-NEXT: [[USUBE:%[0-9]+]]:_(s32), [[USUBE1:%[0-9]+]]:_(s32) = G_USUBE [[SEXT_INREG]], [[SEXT_INREG1]], %18
+    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+    ; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(s32) = G_TRUNC [[COPY2]](s64)
+    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC2]], [[C]]
     ; CHECK-NEXT: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[USUBE]], 8
     ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[USUBE]](s32), [[SEXT_INREG2]]
     ; CHECK-NEXT: %sub_ext:_(s64) = G_ANYEXT [[USUBE]](s32)
     ; CHECK-NEXT: %carry_out_ext:_(s64) = G_ANYEXT [[ICMP]](s32)
     ; CHECK-NEXT: $x0 = COPY %sub_ext(s64)
     ; CHECK-NEXT: $x1 = COPY %carry_out_ext(s64)
     %0:_(s64) = COPY $x0
     %1:_(s64) = COPY $x1

 ---
 name:            test_scalar_ssube_32
 body:             |
   bb.0.entry:
     ; CHECK-LABEL: name: test_scalar_ssube_32
     ; CHECK: %lhs:_(s32) = COPY $w0
     ; CHECK-NEXT: %rhs:_(s32) = COPY $w1
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w2
-    ; CHECK-NEXT: %carry_in:_(s1) = G_TRUNC [[COPY]](s32)
-    ; CHECK-NEXT: %sub:_(s32), %carry_out:_(s1) = G_SSUBE %lhs, %rhs, %carry_in
-    ; CHECK-NEXT: %carry_out_ext:_(s32) = G_ANYEXT %carry_out(s1)
+    ; CHECK-NEXT: %sub:_(s32), %7:_(s32) = G_SSUBE %lhs, %rhs, %8
+    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
     ; CHECK-NEXT: $w0 = COPY %sub(s32)
-    ; CHECK-NEXT: $w1 = COPY %carry_out_ext(s32)
+    ; CHECK-NEXT: $w1 = COPY %7(s32)
     %lhs:_(s32) = COPY $w0
     %rhs:_(s32) = COPY $w1
     %2:_(s32) = COPY $w2
     %carry_in:_(s1) = G_TRUNC %2
     %sub:_(s32), %carry_out:_(s1) = G_SSUBE %lhs, %rhs, %carry_in
     %carry_out_ext:_(s32) = G_ANYEXT %carry_out
     $w0 = COPY %sub
     $w1 = COPY %carry_out_ext
 
 ...

llvm/test/CodeGen/AArch64/GlobalISel/legalize-ssubo.mir

 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple aarch64 -verify-machineinstrs -run-pass=legalizer -debugify-and-strip-all-safe %s -o - | FileCheck %s
 
 ---
 name:            narrow_scalar_ssubo_s128
 body:             |
   bb.0.entry:
     ; CHECK-LABEL: name: narrow_scalar_ssubo_s128
     ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
     ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
     ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
     ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
-    ; CHECK-NEXT: [[USUBO:%[0-9]+]]:_(s64), [[USUBO1:%[0-9]+]]:_(s1) = G_USUBO [[COPY]], [[COPY2]]
-    ; CHECK-NEXT: %17:_(s64), %carry_out:_(s1) = G_SSUBE [[COPY1]], [[COPY3]], [[USUBO1]]
-    ; CHECK-NEXT: %carry_out_ext:_(s64) = G_ANYEXT %carry_out(s1)
+    ; CHECK-NEXT: [[USUBO:%[0-9]+]]:_(s64), [[USUBO1:%[0-9]+]]:_(s32) = G_USUBO [[COPY]], [[COPY2]]
+    ; CHECK-NEXT: [[SSUBE:%[0-9]+]]:_(s64), [[SSUBE1:%[0-9]+]]:_(s32) = G_SSUBE [[COPY1]], [[COPY3]], %20
+    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[USUBO1]], [[C]]
+    ; CHECK-NEXT: %carry_out_ext:_(s64) = G_ANYEXT [[SSUBE1]](s32)
     ; CHECK-NEXT: $x0 = COPY [[USUBO]](s64)
-    ; CHECK-NEXT: $x1 = COPY %17(s64)
+    ; CHECK-NEXT: $x1 = COPY [[SSUBE]](s64)
     ; CHECK-NEXT: $x2 = COPY %carry_out_ext(s64)
     %0:_(s64) = COPY $x0
     %1:_(s64) = COPY $x1
     %2:_(s64) = COPY $x2
     %3:_(s64) = COPY $x3
     %lhs:_(s128) = G_MERGE_VALUES %0, %1
     %rhs:_(s128) = G_MERGE_VALUES %2, %3
     %sub:_(s128), %carry_out:_(s1) = G_SSUBO %lhs, %rhs
     %sub0:_(s64), %sub1:_(s64) = G_UNMERGE_VALUES %sub
     %carry_out_ext:_(s64) = G_ANYEXT %carry_out
     $x0 = COPY %sub0
     $x1 = COPY %sub1
     $x2 = COPY %carry_out_ext
 
 ...
 ---
 name:            narrow_scalar_ssubo_big_nonpow2
 body:             |
   bb.0.entry:
     ; CHECK-LABEL: name: narrow_scalar_ssubo_big_nonpow2
     ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
     ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
     ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
     ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
-    ; CHECK-NEXT: [[USUBO:%[0-9]+]]:_(s64), [[USUBO1:%[0-9]+]]:_(s1) = G_USUBO [[COPY]], [[COPY1]]
-    ; CHECK-NEXT: [[USUBE:%[0-9]+]]:_(s64), [[USUBE1:%[0-9]+]]:_(s1) = G_USUBE [[COPY1]], [[COPY2]], [[USUBO1]]
-    ; CHECK-NEXT: %22:_(s64), %carry_out:_(s1) = G_SSUBE [[COPY2]], [[COPY3]], [[USUBE1]]
-    ; CHECK-NEXT: %carry_out_ext:_(s64) = G_ANYEXT %carry_out(s1)
+    ; CHECK-NEXT: [[USUBO:%[0-9]+]]:_(s64), [[USUBO1:%[0-9]+]]:_(s32) = G_USUBO [[COPY]], [[COPY1]]
+    ; CHECK-NEXT: [[USUBE:%[0-9]+]]:_(s64), [[USUBE1:%[0-9]+]]:_(s32) = G_USUBE [[COPY1]], [[COPY2]], %27
+    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[USUBO1]], [[C]]
+    ; CHECK-NEXT: [[SSUBE:%[0-9]+]]:_(s64), [[SSUBE1:%[0-9]+]]:_(s32) = G_SSUBE [[COPY2]], [[COPY3]], %25
+    ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[USUBE1]], [[C]]
+    ; CHECK-NEXT: %carry_out_ext:_(s64) = G_ANYEXT [[SSUBE1]](s32)
     ; CHECK-NEXT: $x0 = COPY [[USUBO]](s64)
     ; CHECK-NEXT: $x1 = COPY [[USUBE]](s64)
-    ; CHECK-NEXT: $x2 = COPY %22(s64)
+    ; CHECK-NEXT: $x2 = COPY [[SSUBE]](s64)
     ; CHECK-NEXT: $x3 = COPY %carry_out_ext(s64)
     %0:_(s64) = COPY $x0
     %1:_(s64) = COPY $x1
     %2:_(s64) = COPY $x2
     %3:_(s64) = COPY $x3
     %lhs:_(s192) = G_MERGE_VALUES %0, %1, %2
     %rhs:_(s192) = G_MERGE_VALUES %1, %2, %3
     %sub:_(s192), %carry_out:_(s1) = G_SSUBO %lhs, %rhs

 ...
 ---
 name:            test_scalar_ssubo_32
 body:             |
   bb.0.entry:
     ; CHECK-LABEL: name: test_scalar_ssubo_32
     ; CHECK: %lhs:_(s32) = COPY $w0
     ; CHECK-NEXT: %rhs:_(s32) = COPY $w1
-    ; CHECK-NEXT: %sub:_(s32), %carry_out:_(s1) = G_SSUBO %lhs, %rhs
-    ; CHECK-NEXT: %carry_out_ext:_(s32) = G_ANYEXT %carry_out(s1)
+    ; CHECK-NEXT: %sub:_(s32), %5:_(s32) = G_SSUBO %lhs, %rhs
     ; CHECK-NEXT: $w0 = COPY %sub(s32)
-    ; CHECK-NEXT: $w1 = COPY %carry_out_ext(s32)
+    ; CHECK-NEXT: $w1 = COPY %5(s32)
     %lhs:_(s32) = COPY $w0
     %rhs:_(s32) = COPY $w1
     %sub:_(s32), %carry_out:_(s1) = G_SSUBO %lhs, %rhs
     %carry_out_ext:_(s32) = G_ANYEXT %carry_out
     $w0 = COPY %sub
     $w1 = COPY %carry_out_ext
 
 ...

llvm/test/CodeGen/AArch64/GlobalISel/legalize-ssubsat.mir

 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=aarch64 -run-pass=legalizer -verify-machineinstrs -global-isel-abort=0 %s -o - | FileCheck %s
 
 ...
 ---
 name:            s32
 tracksRegLiveness: true
 body:             |
   bb.0:
     liveins: $w0, $w1
     ; CHECK-LABEL: name: s32
     ; CHECK: liveins: $w0, $w1
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: %x:_(s32) = COPY $w0
     ; CHECK-NEXT: %y:_(s32) = COPY $w1
-    ; CHECK-NEXT: [[SSUBO:%[0-9]+]]:_(s32), [[SSUBO1:%[0-9]+]]:_(s1) = G_SSUBO %x, %y
+    ; CHECK-NEXT: [[SSUBO:%[0-9]+]]:_(s32), [[SSUBO1:%[0-9]+]]:_(s32) = G_SSUBO %x, %y
     ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 31
     ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SSUBO]], [[C]](s64)
     ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648
     ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[ASHR]], [[C1]]
-    ; CHECK-NEXT: %ssubsat:_(s32) = G_SELECT [[SSUBO1]](s1), [[ADD]], [[SSUBO]]
+    ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[SSUBO1]], [[C2]]
+    ; CHECK-NEXT: %ssubsat:_(s32) = G_SELECT [[AND]](s32), [[ADD]], [[SSUBO]]
     ; CHECK-NEXT: $w0 = COPY %ssubsat(s32)
     ; CHECK-NEXT: RET_ReallyLR implicit $w0
     %x:_(s32) = COPY $w0
     %y:_(s32) = COPY $w1
     %ssubsat:_(s32) = G_SSUBSAT %x, %y
     $w0 = COPY %ssubsat(s32)
     RET_ReallyLR implicit $w0
 
 ...
 ---
 name:            s64
 tracksRegLiveness: true
 body:             |
   bb.0:
     liveins: $x0, $x1
     ; CHECK-LABEL: name: s64
     ; CHECK: liveins: $x0, $x1
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: %x:_(s64) = COPY $x0
     ; CHECK-NEXT: %y:_(s64) = COPY $x1
-    ; CHECK-NEXT: [[SSUBO:%[0-9]+]]:_(s64), [[SSUBO1:%[0-9]+]]:_(s1) = G_SSUBO %x, %y
+    ; CHECK-NEXT: [[SSUBO:%[0-9]+]]:_(s64), [[SSUBO1:%[0-9]+]]:_(s32) = G_SSUBO %x, %y
     ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 63
     ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SSUBO]], [[C]](s64)
     ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -9223372036854775808
     ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[ASHR]], [[C1]]
-    ; CHECK-NEXT: %ssubsat:_(s64) = G_SELECT [[SSUBO1]](s1), [[ADD]], [[SSUBO]]
+    ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[SSUBO1]], [[C2]]
+    ; CHECK-NEXT: %ssubsat:_(s64) = G_SELECT [[AND]](s32), [[ADD]], [[SSUBO]]
     ; CHECK-NEXT: $x0 = COPY %ssubsat(s64)
     ; CHECK-NEXT: RET_ReallyLR implicit $x0
     %x:_(s64) = COPY $x0
     %y:_(s64) = COPY $x1
     %ssubsat:_(s64) = G_SSUBSAT %x, %y
     $x0 = COPY %ssubsat(s64)
     RET_ReallyLR implicit $x0
 
bb.0:
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: %copy_1:_(s32) = COPY $w0
     ; CHECK-NEXT: %copy_2:_(s32) = COPY $w1
     ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG %copy_1, 16
     ; CHECK-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG %copy_2, 16
     ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[SEXT_INREG]], [[SEXT_INREG1]]
     ; CHECK-NEXT: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[SUB]], 16
     ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[SUB]](s32), [[SEXT_INREG2]]
-    ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32)
     ; CHECK-NEXT: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[SUB]], 16
     ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 15
     ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG3]], [[C]](s64)
     ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -32768
     ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[ASHR]], [[C1]]
-    ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[TRUNC]](s1), [[ADD]], [[SUB]]
+    ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C2]]
+    ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[ADD]], [[SUB]]
     ; CHECK-NEXT: $w0 = COPY [[SELECT]](s32)
     ; CHECK-NEXT: RET_ReallyLR implicit $w0
     %copy_1:_(s32) = COPY $w0
     %x:_(s16) = G_TRUNC %copy_1(s32)
     %copy_2:_(s32) = COPY $w1
     %y:_(s16) = G_TRUNC %copy_2(s32)
     %ssubsat:_(s16) = G_SSUBSAT %x, %y
     %ext:_(s32) = G_ANYEXT %ssubsat(s16)
bb.0:
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: %copy_1:_(s32) = COPY $w0
     ; CHECK-NEXT: %copy_2:_(s32) = COPY $w1
     ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG %copy_1, 1
     ; CHECK-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG %copy_2, 1
     ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[SEXT_INREG]], [[SEXT_INREG1]]
     ; CHECK-NEXT: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[SUB]], 1
     ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[SUB]](s32), [[SEXT_INREG2]]
-    ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32)
     ; CHECK-NEXT: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[SUB]], 1
     ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
     ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG3]], [[C]](s64)
     ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
     ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[ASHR]], [[C1]]
-    ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[TRUNC]](s1), [[ADD]], [[SUB]]
+    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C1]]
+    ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[ADD]], [[SUB]]
     ; CHECK-NEXT: $w0 = COPY [[SELECT]](s32)
     ; CHECK-NEXT: RET_ReallyLR implicit $w0
     %copy_1:_(s32) = COPY $w0
     %x:_(s1) = G_TRUNC %copy_1(s32)
     %copy_2:_(s32) = COPY $w1
     %y:_(s1) = G_TRUNC %copy_2(s32)
     %ssubsat:_(s1) = G_SSUBSAT %x, %y
     %ext:_(s32) = G_ANYEXT %ssubsat(s1)
bb.0:
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: %copy_1:_(s32) = COPY $w0
     ; CHECK-NEXT: %copy_2:_(s32) = COPY $w1
     ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG %copy_1, 3
     ; CHECK-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG %copy_2, 3
     ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[SEXT_INREG]], [[SEXT_INREG1]]
     ; CHECK-NEXT: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[SUB]], 3
     ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[SUB]](s32), [[SEXT_INREG2]]
-    ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32)
     ; CHECK-NEXT: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[SUB]], 3
     ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
     ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG3]], [[C]](s64)
     ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
     ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[ASHR]], [[C1]]
-    ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[TRUNC]](s1), [[ADD]], [[SUB]]
+    ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C2]]
+    ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[ADD]], [[SUB]]
     ; CHECK-NEXT: $w0 = COPY [[SELECT]](s32)
     ; CHECK-NEXT: RET_ReallyLR implicit $w0
     %copy_1:_(s32) = COPY $w0
     %x:_(s3) = G_TRUNC %copy_1(s32)
     %copy_2:_(s32) = COPY $w1
     %y:_(s3) = G_TRUNC %copy_2(s32)
     %ssubsat:_(s3) = G_SSUBSAT %x, %y
     %ext:_(s32) = G_ANYEXT %ssubsat(s3)
bb.0:
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: %copy_1:_(s64) = COPY $x0
     ; CHECK-NEXT: %copy_2:_(s64) = COPY $x1
     ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG %copy_1, 36
     ; CHECK-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG %copy_2, 36
     ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[SEXT_INREG]], [[SEXT_INREG1]]
     ; CHECK-NEXT: [[SEXT_INREG2:%[0-9]+]]:_(s64) = G_SEXT_INREG [[SUB]], 36
     ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[SUB]](s64), [[SEXT_INREG2]]
-    ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32)
     ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 35
     ; CHECK-NEXT: [[SEXT_INREG3:%[0-9]+]]:_(s64) = G_SEXT_INREG [[SUB]], 36
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY [[C]](s64)
     ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SEXT_INREG3]], [[COPY]](s64)
     ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 34359738368
     ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[ASHR]], [[C1]]
-    ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[TRUNC]](s1), [[ADD]], [[SUB]]
+    ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C2]]
+    ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[AND]](s32), [[ADD]], [[SUB]]
     ; CHECK-NEXT: $x0 = COPY [[SELECT]](s64)
     ; CHECK-NEXT: RET_ReallyLR implicit $x0
     %copy_1:_(s64) = COPY $x0
     %x:_(s36) = G_TRUNC %copy_1(s64)
     %copy_2:_(s64) = COPY $x1
     %y:_(s36) = G_TRUNC %copy_2(s64)
     %ssubsat:_(s36) = G_SSUBSAT %x, %y
     %ext:_(s64) = G_ANYEXT %ssubsat(s36)
bb.0:
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: %copy_1:_(s128) = COPY $q0
     ; CHECK-NEXT: %copy_2:_(s128) = COPY $q1
     ; CHECK-NEXT: [[EXTRACT:%[0-9]+]]:_(s64) = G_EXTRACT %copy_1(s128), 0
     ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
     ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES %copy_1(s128)
     ; CHECK-NEXT: [[EXTRACT1:%[0-9]+]]:_(s64) = G_EXTRACT %copy_2(s128), 0
     ; CHECK-NEXT: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES %copy_2(s128)
-    ; CHECK-NEXT: [[USUBO:%[0-9]+]]:_(s64), [[USUBO1:%[0-9]+]]:_(s1) = G_USUBO [[EXTRACT]], [[EXTRACT1]]
+    ; CHECK-NEXT: [[USUBO:%[0-9]+]]:_(s64), [[USUBO1:%[0-9]+]]:_(s32) = G_USUBO [[EXTRACT]], [[EXTRACT1]]
     ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[UV1]](s64)
     ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[TRUNC]], 24
     ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[UV3]](s64)
     ; CHECK-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[TRUNC1]], 24
-    ; CHECK-NEXT: [[USUBE:%[0-9]+]]:_(s32), [[USUBE1:%[0-9]+]]:_(s1) = G_USUBE [[SEXT_INREG]], [[SEXT_INREG1]], [[USUBO1]]
+    ; CHECK-NEXT: [[USUBE:%[0-9]+]]:_(s32), [[USUBE1:%[0-9]+]]:_(s32) = G_USUBE [[SEXT_INREG]], [[SEXT_INREG1]], %85
+    ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[USUBO1]], [[C1]]
     ; CHECK-NEXT: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[USUBE]], 24
     ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[USUBE]](s32), [[SEXT_INREG2]]
-    ; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32)
     ; CHECK-NEXT: [[UV4:%[0-9]+]]:_(s8), [[UV5:%[0-9]+]]:_(s8), [[UV6:%[0-9]+]]:_(s8), [[UV7:%[0-9]+]]:_(s8), [[UV8:%[0-9]+]]:_(s8), [[UV9:%[0-9]+]]:_(s8), [[UV10:%[0-9]+]]:_(s8), [[UV11:%[0-9]+]]:_(s8) = G_UNMERGE_VALUES [[USUBO]](s64)
     ; CHECK-NEXT: [[UV12:%[0-9]+]]:_(s8), [[UV13:%[0-9]+]]:_(s8), [[UV14:%[0-9]+]]:_(s8), [[UV15:%[0-9]+]]:_(s8) = G_UNMERGE_VALUES [[USUBE]](s32)
     ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s8) = G_IMPLICIT_DEF
     ; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
     ; CHECK-NEXT: [[UV16:%[0-9]+]]:_(s8), [[UV17:%[0-9]+]]:_(s8), [[UV18:%[0-9]+]]:_(s8), [[UV19:%[0-9]+]]:_(s8) = G_UNMERGE_VALUES [[DEF1]](s32)
     ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s32) = G_MERGE_VALUES [[UV4]](s8), [[UV5]](s8), [[UV6]](s8), [[UV7]](s8)
     ; CHECK-NEXT: [[MV1:%[0-9]+]]:_(s32) = G_MERGE_VALUES [[UV8]](s8), [[UV9]](s8), [[UV10]](s8), [[UV11]](s8)
     ; CHECK-NEXT: [[MV2:%[0-9]+]]:_(s32) = G_MERGE_VALUES [[UV12]](s8), [[UV13]](s8), [[UV14]](s8), [[DEF]](s8)
     ; CHECK-NEXT: [[MV3:%[0-9]+]]:_(s32) = G_MERGE_VALUES [[UV16]](s8), [[UV17]](s8), [[UV18]](s8), [[UV16]](s8)
-    ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 40
+    ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 40
     ; CHECK-NEXT: [[MV4:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[MV]](s32), [[MV1]](s32)
     ; CHECK-NEXT: [[MV5:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[MV2]](s32), [[MV3]](s32)
-    ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[MV5]], [[C1]](s64)
-    ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 24
-    ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[MV4]], [[C2]](s64)
+    ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[MV5]], [[C2]](s64)
+    ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 24
+    ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[MV4]], [[C3]](s64)
     ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[SHL]], [[LSHR]]
-    ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[OR]], [[C1]](s64)
-    ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 23
-    ; CHECK-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[ASHR]], [[C3]](s64)
-    ; CHECK-NEXT: [[UADDO:%[0-9]+]]:_(s64), [[UADDO1:%[0-9]+]]:_(s1) = G_UADDO [[ASHR1]], [[C]]
+    ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[OR]], [[C2]](s64)
+    ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 23
+    ; CHECK-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[ASHR]], [[C4]](s64)
+    ; CHECK-NEXT: [[UADDO:%[0-9]+]]:_(s64), [[UADDO1:%[0-9]+]]:_(s32) = G_UADDO [[ASHR1]], [[C]]
     ; CHECK-NEXT: [[MV6:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[MV]](s32), [[MV1]](s32)
-    ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[TRUNC2]](s1), [[UADDO]], [[MV6]]
+    ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C1]]
+    ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[AND1]](s32), [[UADDO]], [[MV6]]
     ; CHECK-NEXT: $x0 = COPY [[SELECT]](s64)
     ; CHECK-NEXT: RET_ReallyLR implicit $x0
     %copy_1:_(s128) = COPY $q0
     %x:_(s88) = G_TRUNC %copy_1(s128)
     %copy_2:_(s128) = COPY $q1
     %y:_(s88) = G_TRUNC %copy_2(s128)
     %ssubsat:_(s88) = G_SSUBSAT %x, %y
     %trunc:_(s64) = G_TRUNC %ssubsat(s88)
     $x0 = COPY %trunc(s64)
     RET_ReallyLR implicit $x0

llvm/test/CodeGen/AArch64/GlobalISel/legalize-sub.mir

 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -march=aarch64 -run-pass=legalizer %s -o - | FileCheck %s
 
 ---
 name:            test_scalar_sub_big
 body:             |
   bb.0.entry:
     ; CHECK-LABEL: name: test_scalar_sub_big
     ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
     ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
     ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
     ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
-    ; CHECK-NEXT: [[USUBO:%[0-9]+]]:_(s64), [[USUBO1:%[0-9]+]]:_(s1) = G_USUBO [[COPY]], [[COPY2]]
-    ; CHECK-NEXT: [[USUBE:%[0-9]+]]:_(s64), [[USUBE1:%[0-9]+]]:_(s1) = G_USUBE [[COPY1]], [[COPY3]], [[USUBO1]]
+    ; CHECK-NEXT: [[USUBO:%[0-9]+]]:_(s64), [[USUBO1:%[0-9]+]]:_(s32) = G_USUBO [[COPY]], [[COPY2]]
+    ; CHECK-NEXT: [[USUBE:%[0-9]+]]:_(s64), [[USUBE1:%[0-9]+]]:_(s32) = G_USUBE [[COPY1]], [[COPY3]], %18
+    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[USUBO1]], [[C]]
     ; CHECK-NEXT: $x0 = COPY [[USUBO]](s64)
     ; CHECK-NEXT: $x1 = COPY [[USUBE]](s64)
     %0:_(s64) = COPY $x0
     %1:_(s64) = COPY $x1
     %2:_(s64) = COPY $x2
     %3:_(s64) = COPY $x3
     %4:_(s128) = G_MERGE_VALUES %0(s64), %1(s64)
     %5:_(s128) = G_MERGE_VALUES %2(s64), %3(s64)
     %6:_(s128) = G_SUB %4, %5
     %7:_(s64), %8:_(s64) = G_UNMERGE_VALUES %6(s128)
     $x0 = COPY %7(s64)
     $x1 = COPY %8(s64)
 
 ...
 ---
 name:            test_scalar_sub_big_nonpow2
 body:             |
   bb.0.entry:
     ; CHECK-LABEL: name: test_scalar_sub_big_nonpow2
     ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
     ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
     ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
     ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
-    ; CHECK-NEXT: [[USUBO:%[0-9]+]]:_(s64), [[USUBO1:%[0-9]+]]:_(s1) = G_USUBO [[COPY]], [[COPY1]]
-    ; CHECK-NEXT: [[USUBE:%[0-9]+]]:_(s64), [[USUBE1:%[0-9]+]]:_(s1) = G_USUBE [[COPY1]], [[COPY2]], [[USUBO1]]
-    ; CHECK-NEXT: [[USUBE2:%[0-9]+]]:_(s64), [[USUBE3:%[0-9]+]]:_(s1) = G_USUBE [[COPY2]], [[COPY3]], [[USUBE1]]
+    ; CHECK-NEXT: [[USUBO:%[0-9]+]]:_(s64), [[USUBO1:%[0-9]+]]:_(s32) = G_USUBO [[COPY]], [[COPY1]]
+    ; CHECK-NEXT: [[USUBE:%[0-9]+]]:_(s64), [[USUBE1:%[0-9]+]]:_(s32) = G_USUBE [[COPY1]], [[COPY2]], %34
+    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[USUBO1]], [[C]]
+    ; CHECK-NEXT: [[USUBE2:%[0-9]+]]:_(s64), [[USUBE3:%[0-9]+]]:_(s32) = G_USUBE [[COPY2]], [[COPY3]], %32
+    ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[USUBE1]], [[C]]
     ; CHECK-NEXT: $x0 = COPY [[USUBO]](s64)
     ; CHECK-NEXT: $x1 = COPY [[USUBE]](s64)
     ; CHECK-NEXT: $x2 = COPY [[USUBE2]](s64)
     %0:_(s64) = COPY $x0
     %1:_(s64) = COPY $x1
     %2:_(s64) = COPY $x2
     %3:_(s64) = COPY $x3
     %4:_(s192) = G_MERGE_VALUES %0(s64), %1(s64), %2(s64)

llvm/test/CodeGen/AArch64/GlobalISel/legalize-uadd-sat.mir

body:             |
   bb.1:
     liveins: $w0, $w1
 
     ; CHECK-LABEL: name: func
     ; CHECK: liveins: $w0, $w1
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
     ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
-    ; CHECK-NEXT: [[UADDO:%[0-9]+]]:_(s32), [[UADDO1:%[0-9]+]]:_(s1) = G_UADDO [[COPY]], [[COPY1]]
+    ; CHECK-NEXT: [[UADDO:%[0-9]+]]:_(s32), [[UADDO1:%[0-9]+]]:_(s32) = G_UADDO [[COPY]], [[COPY1]]
     ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
-    ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[UADDO1]](s1), [[C]], [[UADDO]]
+    ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[UADDO1]], [[C1]]
+    ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[C]], [[UADDO]]
     ; CHECK-NEXT: $w0 = COPY [[SELECT]](s32)
     ; CHECK-NEXT: RET_ReallyLR implicit $w0
     %0:_(s32) = COPY $w0
     %1:_(s32) = COPY $w1
     %2:_(s32) = G_UADDSAT %0, %1
     $w0 = COPY %2(s32)
     RET_ReallyLR implicit $w0
 
body:             |
   bb.1:
     liveins: $x0, $x1
 
     ; CHECK-LABEL: name: func2
     ; CHECK: liveins: $x0, $x1
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
     ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
-    ; CHECK-NEXT: [[UADDO:%[0-9]+]]:_(s64), [[UADDO1:%[0-9]+]]:_(s1) = G_UADDO [[COPY]], [[COPY1]]
+    ; CHECK-NEXT: [[UADDO:%[0-9]+]]:_(s64), [[UADDO1:%[0-9]+]]:_(s32) = G_UADDO [[COPY]], [[COPY1]]
     ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
-    ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[UADDO1]](s1), [[C]], [[UADDO]]
+    ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[UADDO1]], [[C1]]
+    ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[AND]](s32), [[C]], [[UADDO]]
     ; CHECK-NEXT: $x0 = COPY [[SELECT]](s64)
     ; CHECK-NEXT: RET_ReallyLR implicit $x0
     %0:_(s64) = COPY $x0
     %1:_(s64) = COPY $x1
     %2:_(s64) = G_UADDSAT %0, %1
     $x0 = COPY %2(s64)
     RET_ReallyLR implicit $x0
 
bb.1:
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
     ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
     ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
     ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
     ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
     ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[AND]], [[AND1]]
     ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ADD]], [[C]]
     ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[ADD]](s32), [[AND2]]
-    ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32)
     ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
-    ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[TRUNC]](s1), [[C1]], [[ADD]]
+    ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+    ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C2]]
+    ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND3]](s32), [[C1]], [[ADD]]
     ; CHECK-NEXT: $w0 = COPY [[SELECT]](s32)
     ; CHECK-NEXT: RET_ReallyLR implicit $w0
     %2:_(s32) = COPY $w0
     %0:_(s16) = G_TRUNC %2(s32)
     %3:_(s32) = COPY $w1
     %1:_(s16) = G_TRUNC %3(s32)
     %4:_(s16) = G_UADDSAT %0, %1
     %5:_(s32) = G_ANYEXT %4(s16)
bb.1:
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
     ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
     ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
     ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
     ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
     ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[AND]], [[AND1]]
     ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ADD]], [[C]]
     ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[ADD]](s32), [[AND2]]
-    ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32)
     ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
-    ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[TRUNC]](s1), [[C1]], [[ADD]]
+    ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+    ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C2]]
+    ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND3]](s32), [[C1]], [[ADD]]
     ; CHECK-NEXT: $w0 = COPY [[SELECT]](s32)
     ; CHECK-NEXT: RET_ReallyLR implicit $w0
     %2:_(s32) = COPY $w0
     %0:_(s8) = G_TRUNC %2(s32)
     %3:_(s32) = COPY $w1
     %1:_(s8) = G_TRUNC %3(s32)
     %4:_(s8) = G_UADDSAT %0, %1
     %5:_(s32) = G_ANYEXT %4(s8)
bb.1:
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
     ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
     ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 15
     ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
     ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
     ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[AND]], [[AND1]]
     ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ADD]], [[C]]
     ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[ADD]](s32), [[AND2]]
-    ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32)
     ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C]](s32)
-    ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[TRUNC]](s1), [[COPY2]], [[ADD]]
+    ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+    ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C1]]
+    ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND3]](s32), [[COPY2]], [[ADD]]
     ; CHECK-NEXT: $w0 = COPY [[SELECT]](s32)
     ; CHECK-NEXT: RET_ReallyLR implicit $w0
     %2:_(s32) = COPY $w0
     %0:_(s4) = G_TRUNC %2(s32)
     %3:_(s32) = COPY $w1
     %1:_(s4) = G_TRUNC %3(s32)
     %4:_(s4) = G_UADDSAT %0, %1
     %5:_(s32) = G_ANYEXT %4(s4)
     $w0 = COPY %5(s32)
     RET_ReallyLR implicit $w0
 
 ...

llvm/test/CodeGen/AArch64/GlobalISel/legalize-uadde.mir

 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple aarch64 -verify-machineinstrs -run-pass=legalizer -debugify-and-strip-all-safe %s -o - | FileCheck %s
 
 ---
 name:            narrow_scalar_uadde_s128
 body:             |
   bb.0.entry:
     ; CHECK-LABEL: name: narrow_scalar_uadde_s128
     ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
     ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
     ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
     ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
     ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(s64) = COPY $x4
-    ; CHECK-NEXT: %carry_in:_(s1) = G_TRUNC [[COPY4]](s64)
-    ; CHECK-NEXT: [[UADDE:%[0-9]+]]:_(s64), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[COPY]], [[COPY2]], %carry_in
-    ; CHECK-NEXT: %19:_(s64), %carry_out:_(s1) = G_UADDE [[COPY1]], [[COPY3]], [[UADDE1]]
-    ; CHECK-NEXT: %carry_out_ext:_(s64) = G_ANYEXT %carry_out(s1)
+    ; CHECK-NEXT: [[UADDE:%[0-9]+]]:_(s64), [[UADDE1:%[0-9]+]]:_(s32) = G_UADDE [[COPY]], [[COPY2]], %24
+    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+    ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY4]](s64)
+    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[C]]
+    ; CHECK-NEXT: [[UADDE2:%[0-9]+]]:_(s64), [[UADDE3:%[0-9]+]]:_(s32) = G_UADDE [[COPY1]], [[COPY3]], %22
+    ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[UADDE1]], [[C]]
+    ; CHECK-NEXT: %carry_out_ext:_(s64) = G_ANYEXT [[UADDE3]](s32)
     ; CHECK-NEXT: $x0 = COPY [[UADDE]](s64)
-    ; CHECK-NEXT: $x1 = COPY %19(s64)
+    ; CHECK-NEXT: $x1 = COPY [[UADDE2]](s64)
     ; CHECK-NEXT: $x2 = COPY %carry_out_ext(s64)
     %0:_(s64) = COPY $x0
     %1:_(s64) = COPY $x1
     %2:_(s64) = COPY $x2
     %3:_(s64) = COPY $x3
     %4:_(s64) = COPY $x4
     %lhs:_(s128) = G_MERGE_VALUES %0, %1
     %rhs:_(s128) = G_MERGE_VALUES %2, %3

 body:             |
   bb.0.entry:
     ; CHECK-LABEL: name: narrow_scalar_uadde_big_nonpow2
     ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
     ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
     ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
     ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
     ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(s64) = COPY $x4
-    ; CHECK-NEXT: %carry_in:_(s1) = G_TRUNC [[COPY4]](s64)
-    ; CHECK-NEXT: [[UADDE:%[0-9]+]]:_(s64), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[COPY]], [[COPY1]], %carry_in
-    ; CHECK-NEXT: [[UADDE2:%[0-9]+]]:_(s64), [[UADDE3:%[0-9]+]]:_(s1) = G_UADDE [[COPY1]], [[COPY2]], [[UADDE1]]
-    ; CHECK-NEXT: %24:_(s64), %carry_out:_(s1) = G_UADDE [[COPY2]], [[COPY3]], [[UADDE3]]
-    ; CHECK-NEXT: %carry_out_ext:_(s64) = G_ANYEXT %carry_out(s1)
+    ; CHECK-NEXT: [[UADDE:%[0-9]+]]:_(s64), [[UADDE1:%[0-9]+]]:_(s32) = G_UADDE [[COPY]], [[COPY1]], %31
+    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+    ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY4]](s64)
+    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[C]]
+    ; CHECK-NEXT: [[UADDE2:%[0-9]+]]:_(s64), [[UADDE3:%[0-9]+]]:_(s32) = G_UADDE [[COPY1]], [[COPY2]], %29
+    ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[UADDE1]], [[C]]
+    ; CHECK-NEXT: [[UADDE4:%[0-9]+]]:_(s64), [[UADDE5:%[0-9]+]]:_(s32) = G_UADDE [[COPY2]], [[COPY3]], %27
+    ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[UADDE3]], [[C]]
+    ; CHECK-NEXT: %carry_out_ext:_(s64) = G_ANYEXT [[UADDE5]](s32)
     ; CHECK-NEXT: $x0 = COPY [[UADDE]](s64)
     ; CHECK-NEXT: $x1 = COPY [[UADDE2]](s64)
-    ; CHECK-NEXT: $x2 = COPY %24(s64)
+    ; CHECK-NEXT: $x2 = COPY [[UADDE4]](s64)
     ; CHECK-NEXT: $x3 = COPY %carry_out_ext(s64)
     %0:_(s64) = COPY $x0
     %1:_(s64) = COPY $x1
     %2:_(s64) = COPY $x2
     %3:_(s64) = COPY $x3
     %4:_(s64) = COPY $x4
     %lhs:_(s192) = G_MERGE_VALUES %0, %1, %2
     %rhs:_(s192) = G_MERGE_VALUES %1, %2, %3

 ---
 name:            widen_scalar_uadde_s8
 body:             |
   bb.0.entry:
     ; CHECK-LABEL: name: widen_scalar_uadde_s8
     ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
     ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
     ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
-    ; CHECK-NEXT: %carry_in:_(s1) = G_TRUNC [[COPY2]](s64)
     ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
     ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
     ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[C]]
     ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
     ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[TRUNC1]], [[C]]
-    ; CHECK-NEXT: [[UADDE:%[0-9]+]]:_(s32), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[AND]], [[AND1]], %carry_in
-    ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[UADDE]], [[C]]
-    ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[UADDE]](s32), [[AND2]]
+    ; CHECK-NEXT: [[UADDE:%[0-9]+]]:_(s32), [[UADDE1:%[0-9]+]]:_(s32) = G_UADDE [[AND]], [[AND1]], %18
+    ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+    ; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(s32) = G_TRUNC [[COPY2]](s64)
+    ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[TRUNC2]], [[C1]]
+    ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[UADDE]], [[C]]
+    ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[UADDE]](s32), [[AND3]]
     ; CHECK-NEXT: %add_ext:_(s64) = G_ANYEXT [[UADDE]](s32)
     ; CHECK-NEXT: %carry_out_ext:_(s64) = G_ANYEXT [[ICMP]](s32)
     ; CHECK-NEXT: $x0 = COPY %add_ext(s64)
     ; CHECK-NEXT: $x1 = COPY %carry_out_ext(s64)
     %0:_(s64) = COPY $x0
     %1:_(s64) = COPY $x1
     %2:_(s64) = COPY $x2
     %lhs:_(s8) = G_TRUNC %0

 ---
 name:            test_scalar_uadde_32
 body:             |
   bb.0.entry:
     ; CHECK-LABEL: name: test_scalar_uadde_32
     ; CHECK: %lhs:_(s32) = COPY $w0
     ; CHECK-NEXT: %rhs:_(s32) = COPY $w1
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w2
-    ; CHECK-NEXT: %carry_in:_(s1) = G_TRUNC [[COPY]](s32)
-    ; CHECK-NEXT: %add:_(s32), %carry_out:_(s1) = G_UADDE %lhs, %rhs, %carry_in
-    ; CHECK-NEXT: %carry_out_ext:_(s32) = G_ANYEXT %carry_out(s1)
+    ; CHECK-NEXT: %add:_(s32), %7:_(s32) = G_UADDE %lhs, %rhs, %8
+    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
     ; CHECK-NEXT: $w0 = COPY %add(s32)
-    ; CHECK-NEXT: $w1 = COPY %carry_out_ext(s32)
+    ; CHECK-NEXT: $w1 = COPY %7(s32)
     %lhs:_(s32) = COPY $w0
     %rhs:_(s32) = COPY $w1
     %2:_(s32) = COPY $w2
     %carry_in:_(s1) = G_TRUNC %2
     %add:_(s32), %carry_out:_(s1) = G_UADDE %lhs, %rhs, %carry_in
     %carry_out_ext:_(s32) = G_ANYEXT %carry_out
     $w0 = COPY %add
     $w1 = COPY %carry_out_ext
 
 ...

llvm/test/CodeGen/AArch64/GlobalISel/legalize-uaddo.mir

 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple aarch64 -verify-machineinstrs -run-pass=legalizer -debugify-and-strip-all-safe %s -o - | FileCheck %s
 
 ---
 name:            narrow_scalar_uaddo_s128
 body:             |
   bb.0.entry:
     ; CHECK-LABEL: name: narrow_scalar_uaddo_s128
     ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
     ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
     ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
     ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
-    ; CHECK-NEXT: [[UADDO:%[0-9]+]]:_(s64), [[UADDO1:%[0-9]+]]:_(s1) = G_UADDO [[COPY]], [[COPY2]]
-    ; CHECK-NEXT: %17:_(s64), %carry_out:_(s1) = G_UADDE [[COPY1]], [[COPY3]], [[UADDO1]]
-    ; CHECK-NEXT: %carry_out_ext:_(s64) = G_ANYEXT %carry_out(s1)
+    ; CHECK-NEXT: [[UADDO:%[0-9]+]]:_(s64), [[UADDO1:%[0-9]+]]:_(s32) = G_UADDO [[COPY]], [[COPY2]]
+    ; CHECK-NEXT: [[UADDE:%[0-9]+]]:_(s64), [[UADDE1:%[0-9]+]]:_(s32) = G_UADDE [[COPY1]], [[COPY3]], %20
+    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[UADDO1]], [[C]]
+    ; CHECK-NEXT: %carry_out_ext:_(s64) = G_ANYEXT [[UADDE1]](s32)
     ; CHECK-NEXT: $x0 = COPY [[UADDO]](s64)
-    ; CHECK-NEXT: $x1 = COPY %17(s64)
+    ; CHECK-NEXT: $x1 = COPY [[UADDE]](s64)
     ; CHECK-NEXT: $x2 = COPY %carry_out_ext(s64)
     %0:_(s64) = COPY $x0
     %1:_(s64) = COPY $x1
     %2:_(s64) = COPY $x2
     %3:_(s64) = COPY $x3
     %lhs:_(s128) = G_MERGE_VALUES %0, %1
     %rhs:_(s128) = G_MERGE_VALUES %2, %3
     %add:_(s128), %carry_out:_(s1) = G_UADDO %lhs, %rhs
     %add0:_(s64), %add1:_(s64) = G_UNMERGE_VALUES %add
     %carry_out_ext:_(s64) = G_ANYEXT %carry_out
     $x0 = COPY %add0
     $x1 = COPY %add1
     $x2 = COPY %carry_out_ext
 
 ...
 ---
 name:            narrow_scalar_uaddo_big_nonpow2
 body:             |
   bb.0.entry:
     ; CHECK-LABEL: name: narrow_scalar_uaddo_big_nonpow2
     ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
     ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
     ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
     ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
-    ; CHECK-NEXT: [[UADDO:%[0-9]+]]:_(s64), [[UADDO1:%[0-9]+]]:_(s1) = G_UADDO [[COPY]], [[COPY1]]
-    ; CHECK-NEXT: [[UADDE:%[0-9]+]]:_(s64), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[COPY1]], [[COPY2]], [[UADDO1]]
-    ; CHECK-NEXT: %22:_(s64), %carry_out:_(s1) = G_UADDE [[COPY2]], [[COPY3]], [[UADDE1]]
-    ; CHECK-NEXT: %carry_out_ext:_(s64) = G_ANYEXT %carry_out(s1)
+    ; CHECK-NEXT: [[UADDO:%[0-9]+]]:_(s64), [[UADDO1:%[0-9]+]]:_(s32) = G_UADDO [[COPY]], [[COPY1]]
+    ; CHECK-NEXT: [[UADDE:%[0-9]+]]:_(s64), [[UADDE1:%[0-9]+]]:_(s32) = G_UADDE [[COPY1]], [[COPY2]], %27
+    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[UADDO1]], [[C]]
+    ; CHECK-NEXT: [[UADDE2:%[0-9]+]]:_(s64), [[UADDE3:%[0-9]+]]:_(s32) = G_UADDE [[COPY2]], [[COPY3]], %25
+    ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[UADDE1]], [[C]]
+    ; CHECK-NEXT: %carry_out_ext:_(s64) = G_ANYEXT [[UADDE3]](s32)
     ; CHECK-NEXT: $x0 = COPY [[UADDO]](s64)
     ; CHECK-NEXT: $x1 = COPY [[UADDE]](s64)
-    ; CHECK-NEXT: $x2 = COPY %22(s64)
+    ; CHECK-NEXT: $x2 = COPY [[UADDE2]](s64)
     ; CHECK-NEXT: $x3 = COPY %carry_out_ext(s64)
     %0:_(s64) = COPY $x0
     %1:_(s64) = COPY $x1
     %2:_(s64) = COPY $x2
     %3:_(s64) = COPY $x3
     %lhs:_(s192) = G_MERGE_VALUES %0, %1, %2
     %rhs:_(s192) = G_MERGE_VALUES %1, %2, %3
     %add:_(s192), %carry_out:_(s1) = G_UADDO %lhs, %rhs

 ...
 ---
 name:            test_scalar_uaddo_32
 body:             |
   bb.0.entry:
     ; CHECK-LABEL: name: test_scalar_uaddo_32
     ; CHECK: %lhs:_(s32) = COPY $w0
     ; CHECK-NEXT: %rhs:_(s32) = COPY $w1
-    ; CHECK-NEXT: %add:_(s32), %carry_out:_(s1) = G_UADDO %lhs, %rhs
-    ; CHECK-NEXT: %carry_out_ext:_(s32) = G_ANYEXT %carry_out(s1)
+    ; CHECK-NEXT: %add:_(s32), %5:_(s32) = G_UADDO %lhs, %rhs
     ; CHECK-NEXT: $w0 = COPY %add(s32)
-    ; CHECK-NEXT: $w1 = COPY %carry_out_ext(s32)
+    ; CHECK-NEXT: $w1 = COPY %5(s32)
     %lhs:_(s32) = COPY $w0
     %rhs:_(s32) = COPY $w1
     %add:_(s32), %carry_out:_(s1) = G_UADDO %lhs, %rhs
     %carry_out_ext:_(s32) = G_ANYEXT %carry_out
     $w0 = COPY %add
     $w1 = COPY %carry_out_ext
 
 ...

llvm/test/CodeGen/AArch64/GlobalISel/legalize-usub-sat.mir

body:             |
   bb.1:
     liveins: $w0, $w1
 
     ; CHECK-LABEL: name: func
     ; CHECK: liveins: $w0, $w1
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
     ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
-    ; CHECK-NEXT: [[USUBO:%[0-9]+]]:_(s32), [[USUBO1:%[0-9]+]]:_(s1) = G_USUBO [[COPY]], [[COPY1]]
+    ; CHECK-NEXT: [[USUBO:%[0-9]+]]:_(s32), [[USUBO1:%[0-9]+]]:_(s32) = G_USUBO [[COPY]], [[COPY1]]
     ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
-    ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[USUBO1]](s1), [[C]], [[USUBO]]
+    ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[USUBO1]], [[C1]]
+    ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[C]], [[USUBO]]
     ; CHECK-NEXT: $w0 = COPY [[SELECT]](s32)
     ; CHECK-NEXT: RET_ReallyLR implicit $w0
     %0:_(s32) = COPY $w0
     %1:_(s32) = COPY $w1
     %2:_(s32) = G_USUBSAT %0, %1
     $w0 = COPY %2(s32)
     RET_ReallyLR implicit $w0
 
body:             |
   bb.1:
     liveins: $x0, $x1
 
     ; CHECK-LABEL: name: func2
     ; CHECK: liveins: $x0, $x1
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
     ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
-    ; CHECK-NEXT: [[USUBO:%[0-9]+]]:_(s64), [[USUBO1:%[0-9]+]]:_(s1) = G_USUBO [[COPY]], [[COPY1]]
+    ; CHECK-NEXT: [[USUBO:%[0-9]+]]:_(s64), [[USUBO1:%[0-9]+]]:_(s32) = G_USUBO [[COPY]], [[COPY1]]
     ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
-    ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[USUBO1]](s1), [[C]], [[USUBO]]
+    ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[USUBO1]], [[C1]]
+    ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[AND]](s32), [[C]], [[USUBO]]
     ; CHECK-NEXT: $x0 = COPY [[SELECT]](s64)
     ; CHECK-NEXT: RET_ReallyLR implicit $x0
     %0:_(s64) = COPY $x0
     %1:_(s64) = COPY $x1
     %2:_(s64) = G_USUBSAT %0, %1
     $x0 = COPY %2(s64)
     RET_ReallyLR implicit $x0
 
bb.1:
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
     ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
     ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
     ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
     ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
     ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[AND]], [[AND1]]
     ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C]]
     ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[SUB]](s32), [[AND2]]
-    ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32)
     ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
-    ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[TRUNC]](s1), [[C1]], [[SUB]]
+    ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+    ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C2]]
+    ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND3]](s32), [[C1]], [[SUB]]
     ; CHECK-NEXT: $w0 = COPY [[SELECT]](s32)
     ; CHECK-NEXT: RET_ReallyLR implicit $w0
     %2:_(s32) = COPY $w0
     %0:_(s16) = G_TRUNC %2(s32)
     %3:_(s32) = COPY $w1
     %1:_(s16) = G_TRUNC %3(s32)
     %4:_(s16) = G_USUBSAT %0, %1
     %5:_(s32) = G_ANYEXT %4(s16)
bb.1:
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
     ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
     ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
     ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
     ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
     ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[AND]], [[AND1]]
     ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C]]
     ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[SUB]](s32), [[AND2]]
-    ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32)
     ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
-    ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[TRUNC]](s1), [[C1]], [[SUB]]
+    ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+    ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C2]]
+    ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND3]](s32), [[C1]], [[SUB]]
     ; CHECK-NEXT: $w0 = COPY [[SELECT]](s32)
     ; CHECK-NEXT: RET_ReallyLR implicit $w0
     %2:_(s32) = COPY $w0
     %0:_(s8) = G_TRUNC %2(s32)
     %3:_(s32) = COPY $w1
     %1:_(s8) = G_TRUNC %3(s32)
     %4:_(s8) = G_USUBSAT %0, %1
     %5:_(s32) = G_ANYEXT %4(s8)
bb.1:
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
     ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
     ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 15
     ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
     ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
     ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[AND]], [[AND1]]
     ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C]]
     ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[SUB]](s32), [[AND2]]
-    ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32)
     ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
-    ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[TRUNC]](s1), [[C1]], [[SUB]]
+    ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+    ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C2]]
+    ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND3]](s32), [[C1]], [[SUB]]
     ; CHECK-NEXT: $w0 = COPY [[SELECT]](s32)
     ; CHECK-NEXT: RET_ReallyLR implicit $w0
     %2:_(s32) = COPY $w0
     %0:_(s4) = G_TRUNC %2(s32)
     %3:_(s32) = COPY $w1
     %1:_(s4) = G_TRUNC %3(s32)
     %4:_(s4) = G_USUBSAT %0, %1
     %5:_(s32) = G_ANYEXT %4(s4)
     $w0 = COPY %5(s32)
     RET_ReallyLR implicit $w0
 
 ...

llvm/test/CodeGen/AArch64/GlobalISel/legalize-usube.mir

 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple aarch64 -verify-machineinstrs -run-pass=legalizer -debugify-and-strip-all-safe %s -o - | FileCheck %s
 
 ---
 name:            narrow_scalar_usube_s128
 body:             |
   bb.0.entry:
     ; CHECK-LABEL: name: narrow_scalar_usube_s128
     ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
     ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
     ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
     ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
     ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(s64) = COPY $x4
-    ; CHECK-NEXT: %carry_in:_(s1) = G_TRUNC [[COPY4]](s64)
-    ; CHECK-NEXT: [[USUBE:%[0-9]+]]:_(s64), [[USUBE1:%[0-9]+]]:_(s1) = G_USUBE [[COPY]], [[COPY2]], %carry_in
-    ; CHECK-NEXT: %19:_(s64), %carry_out:_(s1) = G_USUBE [[COPY1]], [[COPY3]], [[USUBE1]]
-    ; CHECK-NEXT: %carry_out_ext:_(s64) = G_ANYEXT %carry_out(s1)
+    ; CHECK-NEXT: [[USUBE:%[0-9]+]]:_(s64), [[USUBE1:%[0-9]+]]:_(s32) = G_USUBE [[COPY]], [[COPY2]], %24
+    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+    ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY4]](s64)
+    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[C]]
+    ; CHECK-NEXT: [[USUBE2:%[0-9]+]]:_(s64), [[USUBE3:%[0-9]+]]:_(s32) = G_USUBE [[COPY1]], [[COPY3]], %22
+    ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[USUBE1]], [[C]]
+    ; CHECK-NEXT: %carry_out_ext:_(s64) = G_ANYEXT [[USUBE3]](s32)
     ; CHECK-NEXT: $x0 = COPY [[USUBE]](s64)
-    ; CHECK-NEXT: $x1 = COPY %19(s64)
+    ; CHECK-NEXT: $x1 = COPY [[USUBE2]](s64)
     ; CHECK-NEXT: $x2 = COPY %carry_out_ext(s64)
     %0:_(s64) = COPY $x0
     %1:_(s64) = COPY $x1
     %2:_(s64) = COPY $x2
     %3:_(s64) = COPY $x3
     %4:_(s64) = COPY $x4
     %lhs:_(s128) = G_MERGE_VALUES %0, %1
     %rhs:_(s128) = G_MERGE_VALUES %2, %3

 body:             |
   bb.0.entry:
     ; CHECK-LABEL: name: narrow_scalar_usube_big_nonpow2
     ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
     ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
     ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
     ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
     ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(s64) = COPY $x4
-    ; CHECK-NEXT: %carry_in:_(s1) = G_TRUNC [[COPY4]](s64)
-    ; CHECK-NEXT: [[USUBE:%[0-9]+]]:_(s64), [[USUBE1:%[0-9]+]]:_(s1) = G_USUBE [[COPY]], [[COPY1]], %carry_in
-    ; CHECK-NEXT: [[USUBE2:%[0-9]+]]:_(s64), [[USUBE3:%[0-9]+]]:_(s1) = G_USUBE [[COPY1]], [[COPY2]], [[USUBE1]]
-    ; CHECK-NEXT: %24:_(s64), %carry_out:_(s1) = G_USUBE [[COPY2]], [[COPY3]], [[USUBE3]]
-    ; CHECK-NEXT: %carry_out_ext:_(s64) = G_ANYEXT %carry_out(s1)
+    ; CHECK-NEXT: [[USUBE:%[0-9]+]]:_(s64), [[USUBE1:%[0-9]+]]:_(s32) = G_USUBE [[COPY]], [[COPY1]], %31
+    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+    ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY4]](s64)
+    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[C]]
+    ; CHECK-NEXT: [[USUBE2:%[0-9]+]]:_(s64), [[USUBE3:%[0-9]+]]:_(s32) = G_USUBE [[COPY1]], [[COPY2]], %29
+    ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[USUBE1]], [[C]]
+    ; CHECK-NEXT: [[USUBE4:%[0-9]+]]:_(s64), [[USUBE5:%[0-9]+]]:_(s32) = G_USUBE [[COPY2]], [[COPY3]], %27
+    ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[USUBE3]], [[C]]
+    ; CHECK-NEXT: %carry_out_ext:_(s64) = G_ANYEXT [[USUBE5]](s32)
     ; CHECK-NEXT: $x0 = COPY [[USUBE]](s64)
     ; CHECK-NEXT: $x1 = COPY [[USUBE2]](s64)
-    ; CHECK-NEXT: $x2 = COPY %24(s64)
+    ; CHECK-NEXT: $x2 = COPY [[USUBE4]](s64)
     ; CHECK-NEXT: $x3 = COPY %carry_out_ext(s64)
     %0:_(s64) = COPY $x0
     %1:_(s64) = COPY $x1
     %2:_(s64) = COPY $x2
     %3:_(s64) = COPY $x3
     %4:_(s64) = COPY $x4
     %lhs:_(s192) = G_MERGE_VALUES %0, %1, %2
     %rhs:_(s192) = G_MERGE_VALUES %1, %2, %3

 ---
 name:            widen_scalar_usube_s8
 body:             |
   bb.0.entry:
     ; CHECK-LABEL: name: widen_scalar_usube_s8
     ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
     ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
     ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
-    ; CHECK-NEXT: %carry_in:_(s1) = G_TRUNC [[COPY2]](s64)
     ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
     ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
     ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[C]]
     ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
     ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[TRUNC1]], [[C]]
-    ; CHECK-NEXT: [[USUBE:%[0-9]+]]:_(s32), [[USUBE1:%[0-9]+]]:_(s1) = G_USUBE [[AND]], [[AND1]], %carry_in
-    ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[USUBE]], [[C]]
-    ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[USUBE]](s32), [[AND2]]
+    ; CHECK-NEXT: [[USUBE:%[0-9]+]]:_(s32), [[USUBE1:%[0-9]+]]:_(s32) = G_USUBE [[AND]], [[AND1]], %18
+    ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+    ; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(s32) = G_TRUNC [[COPY2]](s64)
+    ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[TRUNC2]], [[C1]]
+    ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[USUBE]], [[C]]
+    ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[USUBE]](s32), [[AND3]]
     ; CHECK-NEXT: %sub_ext:_(s64) = G_ANYEXT [[USUBE]](s32)
     ; CHECK-NEXT: %carry_out_ext:_(s64) = G_ANYEXT [[ICMP]](s32)
     ; CHECK-NEXT: $x0 = COPY %sub_ext(s64)
     ; CHECK-NEXT: $x1 = COPY %carry_out_ext(s64)
     %0:_(s64) = COPY $x0
     %1:_(s64) = COPY $x1
     %2:_(s64) = COPY $x2
     %lhs:_(s8) = G_TRUNC %0

 ---
 name:            test_scalar_usube_32
 body:             |
   bb.0.entry:
     ; CHECK-LABEL: name: test_scalar_usube_32
     ; CHECK: %lhs:_(s32) = COPY $w0
     ; CHECK-NEXT: %rhs:_(s32) = COPY $w1
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w2
-    ; CHECK-NEXT: %carry_in:_(s1) = G_TRUNC [[COPY]](s32)
-    ; CHECK-NEXT: %sub:_(s32), %carry_out:_(s1) = G_USUBE %lhs, %rhs, %carry_in
-    ; CHECK-NEXT: %carry_out_ext:_(s32) = G_ANYEXT %carry_out(s1)
+    ; CHECK-NEXT: %sub:_(s32), %7:_(s32) = G_USUBE %lhs, %rhs, %8
+    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
     ; CHECK-NEXT: $w0 = COPY %sub(s32)
-    ; CHECK-NEXT: $w1 = COPY %carry_out_ext(s32)
+    ; CHECK-NEXT: $w1 = COPY %7(s32)
     %lhs:_(s32) = COPY $w0
     %rhs:_(s32) = COPY $w1
     %2:_(s32) = COPY $w2
     %carry_in:_(s1) = G_TRUNC %2
     %sub:_(s32), %carry_out:_(s1) = G_USUBE %lhs, %rhs, %carry_in
     %carry_out_ext:_(s32) = G_ANYEXT %carry_out
     $w0 = COPY %sub
     $w1 = COPY %carry_out_ext
 
 ...

llvm/test/CodeGen/AArch64/GlobalISel/legalize-usubo.mir

 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple aarch64 -verify-machineinstrs -run-pass=legalizer -debugify-and-strip-all-safe %s -o - | FileCheck %s
 
 ---
 name:            narrow_scalar_usubo_s128
 body:             |
   bb.0.entry:
     ; CHECK-LABEL: name: narrow_scalar_usubo_s128
     ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
     ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
     ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
     ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
-    ; CHECK-NEXT: [[USUBO:%[0-9]+]]:_(s64), [[USUBO1:%[0-9]+]]:_(s1) = G_USUBO [[COPY]], [[COPY2]]
-    ; CHECK-NEXT: %17:_(s64), %carry_out:_(s1) = G_USUBE [[COPY1]], [[COPY3]], [[USUBO1]]
-    ; CHECK-NEXT: %carry_out_ext:_(s64) = G_ANYEXT %carry_out(s1)
+    ; CHECK-NEXT: [[USUBO:%[0-9]+]]:_(s64), [[USUBO1:%[0-9]+]]:_(s32) = G_USUBO [[COPY]], [[COPY2]]
+    ; CHECK-NEXT: [[USUBE:%[0-9]+]]:_(s64), [[USUBE1:%[0-9]+]]:_(s32) = G_USUBE [[COPY1]], [[COPY3]], %20
+    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[USUBO1]], [[C]]
+    ; CHECK-NEXT: %carry_out_ext:_(s64) = G_ANYEXT [[USUBE1]](s32)
     ; CHECK-NEXT: $x0 = COPY [[USUBO]](s64)
-    ; CHECK-NEXT: $x1 = COPY %17(s64)
+    ; CHECK-NEXT: $x1 = COPY [[USUBE]](s64)
     ; CHECK-NEXT: $x2 = COPY %carry_out_ext(s64)
     %0:_(s64) = COPY $x0
     %1:_(s64) = COPY $x1
     %2:_(s64) = COPY $x2
     %3:_(s64) = COPY $x3
     %lhs:_(s128) = G_MERGE_VALUES %0, %1
     %rhs:_(s128) = G_MERGE_VALUES %2, %3
     %sub:_(s128), %carry_out:_(s1) = G_USUBO %lhs, %rhs
     %sub0:_(s64), %sub1:_(s64) = G_UNMERGE_VALUES %sub
     %carry_out_ext:_(s64) = G_ANYEXT %carry_out
     $x0 = COPY %sub0
     $x1 = COPY %sub1
     $x2 = COPY %carry_out_ext
 
 ...
 ---
 name:            narrow_scalar_usubo_big_nonpow2
 body:             |
   bb.0.entry:
     ; CHECK-LABEL: name: narrow_scalar_usubo_big_nonpow2
     ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
     ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
     ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
     ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
-    ; CHECK-NEXT: [[USUBO:%[0-9]+]]:_(s64), [[USUBO1:%[0-9]+]]:_(s1) = G_USUBO [[COPY]], [[COPY1]]
-    ; CHECK-NEXT: [[USUBE:%[0-9]+]]:_(s64), [[USUBE1:%[0-9]+]]:_(s1) = G_USUBE [[COPY1]], [[COPY2]], [[USUBO1]]
-    ; CHECK-NEXT: %22:_(s64), %carry_out:_(s1) = G_USUBE [[COPY2]], [[COPY3]], [[USUBE1]]
-    ; CHECK-NEXT: %carry_out_ext:_(s64) = G_ANYEXT %carry_out(s1)
+    ; CHECK-NEXT: [[USUBO:%[0-9]+]]:_(s64), [[USUBO1:%[0-9]+]]:_(s32) = G_USUBO [[COPY]], [[COPY1]]
+    ; CHECK-NEXT: [[USUBE:%[0-9]+]]:_(s64), [[USUBE1:%[0-9]+]]:_(s32) = G_USUBE [[COPY1]], [[COPY2]], %27
+    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[USUBO1]], [[C]]
+    ; CHECK-NEXT: [[USUBE2:%[0-9]+]]:_(s64), [[USUBE3:%[0-9]+]]:_(s32) = G_USUBE [[COPY2]], [[COPY3]], %25
+    ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[USUBE1]], [[C]]
+    ; CHECK-NEXT: %carry_out_ext:_(s64) = G_ANYEXT [[USUBE3]](s32)
     ; CHECK-NEXT: $x0 = COPY [[USUBO]](s64)
     ; CHECK-NEXT: $x1 = COPY [[USUBE]](s64)
-    ; CHECK-NEXT: $x2 = COPY %22(s64)
+    ; CHECK-NEXT: $x2 = COPY [[USUBE2]](s64)
     ; CHECK-NEXT: $x3 = COPY %carry_out_ext(s64)
     %0:_(s64) = COPY $x0
     %1:_(s64) = COPY $x1
     %2:_(s64) = COPY $x2
     %3:_(s64) = COPY $x3
     %lhs:_(s192) = G_MERGE_VALUES %0, %1, %2
     %rhs:_(s192) = G_MERGE_VALUES %1, %2, %3
     %sub:_(s192), %carry_out:_(s1) = G_USUBO %lhs, %rhs

 ...
 ---
 name:            test_scalar_usubo_32
 body:             |
   bb.0.entry:
     ; CHECK-LABEL: name: test_scalar_usubo_32
     ; CHECK: %lhs:_(s32) = COPY $w0
     ; CHECK-NEXT: %rhs:_(s32) = COPY $w1
-    ; CHECK-NEXT: %sub:_(s32), %carry_out:_(s1) = G_USUBO %lhs, %rhs
-    ; CHECK-NEXT: %carry_out_ext:_(s32) = G_ANYEXT %carry_out(s1)
+    ; CHECK-NEXT: %sub:_(s32), %5:_(s32) = G_USUBO %lhs, %rhs
     ; CHECK-NEXT: $w0 = COPY %sub(s32)
-    ; CHECK-NEXT: $w1 = COPY %carry_out_ext(s32)
+    ; CHECK-NEXT: $w1 = COPY %5(s32)
     %lhs:_(s32) = COPY $w0
     %rhs:_(s32) = COPY $w1
     %sub:_(s32), %carry_out:_(s1) = G_USUBO %lhs, %rhs
     %carry_out_ext:_(s32) = G_ANYEXT %carry_out
     $w0 = COPY %sub
     $w1 = COPY %carry_out_ext
 
 ...

llvm/test/CodeGen/AArch64/GlobalISel/legalizer-combiner-zext-trunc-crash.mir

body:             |
   ; CHECK: bb.0:
   ; CHECK-NEXT:   successors: %bb.1(0x80000000)
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT:   [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT: bb.1:
   ; CHECK-NEXT:   successors: %bb.2(0x80000000)
   ; CHECK-NEXT: {{  $}}
-  ; CHECK-NEXT:   [[PHI:%[0-9]+]]:_(s16) = G_PHI %32(s16), %bb.2, [[DEF]](s16), %bb.0
+  ; CHECK-NEXT:   [[PHI:%[0-9]+]]:_(s16) = G_PHI %33(s16), %bb.2, [[DEF]](s16), %bb.0
   ; CHECK-NEXT:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
   ; CHECK-NEXT:   [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[PHI]](s16)
   ; CHECK-NEXT:   [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C]]
   ; CHECK-NEXT:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 46
   ; CHECK-NEXT:   [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[AND]](s32), [[C1]]
   ; CHECK-NEXT:   [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
   ; CHECK-NEXT:   [[OR:%[0-9]+]]:_(s32) = G_OR [[ICMP]], [[DEF1]]
   ; CHECK-NEXT:   [[COPY:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32)
   ; CHECK-NEXT:   [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 -33
   ; CHECK-NEXT:   [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C2]]
   ; CHECK-NEXT:   [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 -65
   ; CHECK-NEXT:   [[ADD:%[0-9]+]]:_(s32) = G_ADD [[AND1]], [[C3]]
   ; CHECK-NEXT:   [[AND2:%[0-9]+]]:_(s32) = G_AND [[ADD]], [[C]]
   ; CHECK-NEXT:   [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 26
   ; CHECK-NEXT:   [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[AND2]](s32), [[C4]]
   ; CHECK-NEXT:   [[OR1:%[0-9]+]]:_(s32) = G_OR [[ICMP1]], [[OR]]
-  ; CHECK-NEXT:   [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[OR1]](s32)
-  ; CHECK-NEXT:   G_BRCOND [[TRUNC]](s1), %bb.2
+  ; CHECK-NEXT:   [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+  ; CHECK-NEXT:   [[AND3:%[0-9]+]]:_(s32) = G_AND [[OR1]], [[C5]]
+  ; CHECK-NEXT:   G_BRCOND [[AND3]](s32), %bb.2
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT: bb.2:
   ; CHECK-NEXT:   successors: %bb.1(0x80000000)
   ; CHECK-NEXT: {{  $}}
-  ; CHECK-NEXT:   [[C5:%[0-9]+]]:_(s16) = G_CONSTANT i16 64
+  ; CHECK-NEXT:   [[C6:%[0-9]+]]:_(s16) = G_CONSTANT i16 64
   ; CHECK-NEXT:   G_BR %bb.1
   bb.1:
     %1:_(s8) = G_CONSTANT i8 46
     %3:_(s1) = G_IMPLICIT_DEF
     %5:_(s8) = G_CONSTANT i8 -33
     %7:_(s8) = G_CONSTANT i8 -65
     %9:_(s8) = G_CONSTANT i8 26
     %13:_(s8) = G_IMPLICIT_DEF

llvm/test/CodeGen/AArch64/GlobalISel/localizer-arm64-tti.ll

define i32 @foo() {
   ; CHECK-NEXT:   [[C:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 2
   ; CHECK-NEXT:   [[GV1:%[0-9]+]]:gpr(p0) = G_GLOBAL_VALUE @var2
   ; CHECK-NEXT:   [[C1:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 3
   ; CHECK-NEXT:   [[GV2:%[0-9]+]]:gpr(p0) = G_GLOBAL_VALUE @var3
   ; CHECK-NEXT:   [[C2:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 0
   ; CHECK-NEXT:   [[LOAD:%[0-9]+]]:gpr(s32) = G_LOAD [[GV]](p0) :: (dereferenceable load (s32) from @var1)
   ; CHECK-NEXT:   [[C3:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 1
   ; CHECK-NEXT:   [[ICMP:%[0-9]+]]:gpr(s32) = G_ICMP intpred(ne), [[LOAD]](s32), [[C3]]
-  ; CHECK-NEXT:   [[TRUNC:%[0-9]+]]:gpr(s1) = G_TRUNC [[ICMP]](s32)
-  ; CHECK-NEXT:   G_BRCOND [[TRUNC]](s1), %bb.3
+  ; CHECK-NEXT:   [[AND:%[0-9]+]]:gpr(s32) = G_AND [[ICMP]], [[C3]]
+  ; CHECK-NEXT:   G_BRCOND [[AND]](s32), %bb.3
   ; CHECK-NEXT:   G_BR %bb.2
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT: bb.2.if.then:
   ; CHECK-NEXT:   successors: %bb.3(0x80000000)
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT:   [[GV3:%[0-9]+]]:gpr(p0) = G_GLOBAL_VALUE @var2
   ; CHECK-NEXT:   [[C4:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 2
   ; CHECK-NEXT:   G_STORE [[C4]](s32), [[GV3]](p0) :: (store (s32) into @var2)
define i32 @darwin_tls() {
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT:   [[GV:%[0-9]+]]:gpr(p0) = G_GLOBAL_VALUE @tls_gv
   ; CHECK-NEXT:   [[GV1:%[0-9]+]]:gpr(p0) = G_GLOBAL_VALUE @var2
   ; CHECK-NEXT:   [[C:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 0
   ; CHECK-NEXT:   [[GV2:%[0-9]+]]:gpr(p0) = G_GLOBAL_VALUE @var1
   ; CHECK-NEXT:   [[LOAD:%[0-9]+]]:gpr(s32) = G_LOAD [[GV2]](p0) :: (dereferenceable load (s32) from @var1)
   ; CHECK-NEXT:   [[C1:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 1
   ; CHECK-NEXT:   [[ICMP:%[0-9]+]]:gpr(s32) = G_ICMP intpred(ne), [[LOAD]](s32), [[C1]]
-  ; CHECK-NEXT:   [[TRUNC:%[0-9]+]]:gpr(s1) = G_TRUNC [[ICMP]](s32)
-  ; CHECK-NEXT:   G_BRCOND [[TRUNC]](s1), %bb.3
+  ; CHECK-NEXT:   [[AND:%[0-9]+]]:gpr(s32) = G_AND [[ICMP]], [[C1]]
+  ; CHECK-NEXT:   G_BRCOND [[AND]](s32), %bb.3
   ; CHECK-NEXT:   G_BR %bb.2
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT: bb.2.if.then:
   ; CHECK-NEXT:   successors: %bb.3(0x80000000)
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT:   [[LOAD1:%[0-9]+]]:gpr(s32) = G_LOAD [[GV]](p0) :: (dereferenceable load (s32) from @tls_gv)
   ; CHECK-NEXT:   [[GV3:%[0-9]+]]:gpr(p0) = G_GLOBAL_VALUE @var2
   ; CHECK-NEXT:   G_STORE [[LOAD1]](s32), [[GV3]](p0) :: (store (s32) into @var2)

llvm/test/CodeGen/AArch64/GlobalISel/opt-and-tbnz-tbz.mir

body:             |
   bb.0:
     successors: %bb.0, %bb.1
     liveins: $x0
     %0:gpr(s64) = COPY $x0
     %1:gpr(s64) = G_CONSTANT i64 8589934592 ; Bit number 33 => TBNZX
     %3:gpr(s64) = G_CONSTANT i64 0
     %2:gpr(s64) = G_AND %0, %1
     %5:gpr(s32) = G_ICMP intpred(ne), %2(s64), %3
-    %4:gpr(s1) = G_TRUNC %5(s32)
-    G_BRCOND %4(s1), %bb.1
+    G_BRCOND %5, %bb.1
     G_BR %bb.0
   bb.1:
     RET_ReallyLR
 
 ...
 ---
 name:            tbzx_and
 alignment:       4
body:             |
   bb.0:
     successors: %bb.0, %bb.1
     liveins: $x0
     %0:gpr(s64) = COPY $x0
     %1:gpr(s64) = G_CONSTANT i64 8589934592 ; Bit number 33 => TBNZX
     %3:gpr(s64) = G_CONSTANT i64 0
     %2:gpr(s64) = G_AND %0, %1
     %5:gpr(s32) = G_ICMP intpred(eq), %2(s64), %3
-    %4:gpr(s1) = G_TRUNC %5(s32)
-    G_BRCOND %4(s1), %bb.1
+    G_BRCOND %5, %bb.1
     G_BR %bb.0
   bb.1:
     RET_ReallyLR
 
 ...
 ---
 name:            tbnzw_and
 alignment:       4
body:             |
   bb.0:
     successors: %bb.0, %bb.1
     liveins: $w0
     %0:gpr(s32) = COPY $w0
     %1:gpr(s32) = G_CONSTANT i32 1
     %3:gpr(s32) = G_CONSTANT i32 0
     %2:gpr(s32) = G_AND %0, %1
     %5:gpr(s32) = G_ICMP intpred(ne), %2(s32), %3
-    %4:gpr(s1) = G_TRUNC %5(s32)
-    G_BRCOND %4(s1), %bb.1
+    G_BRCOND %5, %bb.1
     G_BR %bb.0
   bb.1:
     RET_ReallyLR
 
 ...
 ---
 name:            tbzw_and
 alignment:       4
body:             |
   bb.0:
     successors: %bb.0, %bb.1
     liveins: $w0
     %0:gpr(s32) = COPY $w0
     %1:gpr(s32) = G_CONSTANT i32 1
     %3:gpr(s32) = G_CONSTANT i32 0
     %2:gpr(s32) = G_AND %0, %1
     %5:gpr(s32) = G_ICMP intpred(eq), %2(s32), %3
-    %4:gpr(s1) = G_TRUNC %5(s32)
-    G_BRCOND %4(s1), %bb.1
+    G_BRCOND %5, %bb.1
     G_BR %bb.0
   bb.1:
     RET_ReallyLR
 
 ...
 ---
 name:            dont_fold_and_lt
 alignment:       4
body:             |
   bb.0:
     successors: %bb.0, %bb.1
     liveins: $w0
     %0:gpr(s32) = COPY $w0
     %1:gpr(s32) = G_CONSTANT i32 1
     %3:gpr(s32) = G_CONSTANT i32 0
     %2:gpr(s32) = G_AND %0, %1
     %5:gpr(s32) = G_ICMP intpred(slt), %2(s32), %3
-    %4:gpr(s1) = G_TRUNC %5(s32)
-    G_BRCOND %4(s1), %bb.1
+    G_BRCOND %5, %bb.1
     G_BR %bb.0
   bb.1:
     RET_ReallyLR
 
 ...
 ---
 name:            dont_fold_and_gt
 alignment:       4
body:             |
   bb.0:
     successors: %bb.0, %bb.1
     liveins: $w0
     %0:gpr(s32) = COPY $w0
     %1:gpr(s32) = G_CONSTANT i32 1
     %3:gpr(s32) = G_CONSTANT i32 0
     %2:gpr(s32) = G_AND %0, %1
     %5:gpr(s32) = G_ICMP intpred(sgt), %2(s32), %3
-    %4:gpr(s1) = G_TRUNC %5(s32)
-    G_BRCOND %4(s1), %bb.1
+    G_BRCOND %5, %bb.1
     G_BR %bb.0
   bb.1:
     RET_ReallyLR
 
 ...
 ---
 name:            dont_fold_and_not_power_of_2
 alignment:       4
body:             |
   bb.0:
     successors: %bb.0, %bb.1
     liveins: $x0
     %0:gpr(s64) = COPY $x0
     %1:gpr(s64) = G_CONSTANT i64 7
     %3:gpr(s64) = G_CONSTANT i64 0
     %2:gpr(s64) = G_AND %0, %1
     %5:gpr(s32) = G_ICMP intpred(ne), %2(s64), %3
-    %4:gpr(s1) = G_TRUNC %5(s32)
-    G_BRCOND %4(s1), %bb.1
+    G_BRCOND %5, %bb.1
     G_BR %bb.0
   bb.1:
     RET_ReallyLR
 
 ...
 ---
 name:            dont_fold_cmp_not_0
 alignment:       4
body:             |
   bb.0:
     successors: %bb.0, %bb.1
     liveins: $x0
     %0:gpr(s64) = COPY $x0
     %1:gpr(s64) = G_CONSTANT i64 4
     %3:gpr(s64) = G_CONSTANT i64 4
     %2:gpr(s64) = G_AND %0, %1
     %5:gpr(s32) = G_ICMP intpred(ne), %2(s64), %3
-    %4:gpr(s1) = G_TRUNC %5(s32)
-    G_BRCOND %4(s1), %bb.1
+    G_BRCOND %5, %bb.1
     G_BR %bb.0
   bb.1:
     RET_ReallyLR

llvm/test/CodeGen/AArch64/GlobalISel/opt-fold-and-tbz-tbnz.mir

bb.0:
     %fold_cst:gpr(s64) = G_CONSTANT i64 8
 
     ; tbnz (and x, 8), 3 == tbnz x, 3 because the third bit of x & 8 is 1 when
     ; the third bit of x is 1.
     %fold_me:gpr(s64) = G_AND %copy, %fold_cst
 
     %and:gpr(s64) = G_AND %fold_me, %bit
     %cmp:gpr(s32) = G_ICMP intpred(ne), %and(s64), %zero
-    %cmp_trunc:gpr(s1) = G_TRUNC %cmp(s32)
-    G_BRCOND %cmp_trunc(s1), %bb.1
+    G_BRCOND %cmp, %bb.1
     G_BR %bb.0
   bb.1:
     RET_ReallyLR
 ...
 ---
 name:            fold_and_lhs
 alignment:       4
 legalized:       true
bb.0:
     %zero:gpr(s64) = G_CONSTANT i64 0
     %fold_cst:gpr(s64) = G_CONSTANT i64 8
 
     ; Same as above, but with the constant on the other side.
     %fold_me:gpr(s64) = G_AND %fold_cst, %copy
 
     %and:gpr(s64) = G_AND %fold_me, %bit
     %cmp:gpr(s32) = G_ICMP intpred(ne), %and(s64), %zero
-    %cmp_trunc:gpr(s1) = G_TRUNC %cmp(s32)
-    G_BRCOND %cmp_trunc(s1), %bb.1
+    G_BRCOND %cmp, %bb.1
     G_BR %bb.0
   bb.1:
     RET_ReallyLR
 ...
 ---
 name:            dont_fold_and
 alignment:       4
 legalized:       true
bb.0:
 
     ; tbnz (and x, 7), 3 != tbnz x, 3, because the third bit of x & 7 is always
     ; zero.
     %fold_cst:gpr(s64) = G_CONSTANT i64 7
 
     %fold_me:gpr(s64) = G_AND %copy, %fold_cst
     %and:gpr(s64) = G_AND %fold_me, %bit
     %cmp:gpr(s32) = G_ICMP intpred(ne), %and(s64), %zero
-    %cmp_trunc:gpr(s1) = G_TRUNC %cmp(s32)
-    G_BRCOND %cmp_trunc(s1), %bb.1
+    G_BRCOND %cmp, %bb.1
     G_BR %bb.0
   bb.1:
     RET_ReallyLR

llvm/test/CodeGen/AArch64/GlobalISel/opt-fold-compare.mir

bb.0:
     ; CHECK: $w0 = COPY [[CSINCWr]]
     ; CHECK: RET_ReallyLR implicit $w0
     %0:gpr(s32) = COPY $w0
     %1:gpr(s32) = COPY $w1
     %2:gpr(s32) = G_CONSTANT i32 0
     %6:gpr(s32) = G_CONSTANT i32 1
     %3:gpr(s32) = G_SUB %2, %1
     %7:gpr(s32) = G_ICMP intpred(ne), %0(s32), %3
-    %4:gpr(s1) = G_TRUNC %7(s32)
-    %5:gpr(s32) = G_SELECT %4(s1), %6, %2
+    %5:gpr(s32) = G_SELECT %7, %6, %2
     $w0 = COPY %5(s32)
     RET_ReallyLR implicit $w0
 
 ...
 ---
 name:            cmn_s32_lhs
 alignment:       4
 legalized:       true
bb.0:
     ; CHECK: $w0 = COPY [[CSINCWr]]
     ; CHECK: RET_ReallyLR implicit $w0
     %0:gpr(s32) = COPY $w0
     %1:gpr(s32) = COPY $w1
     %2:gpr(s32) = G_CONSTANT i32 0
     %6:gpr(s32) = G_CONSTANT i32 1
     %3:gpr(s32) = G_SUB %2, %0
     %7:gpr(s32) = G_ICMP intpred(ne), %3(s32), %1
-    %4:gpr(s1) = G_TRUNC %7(s32)
-    %5:gpr(s32) = G_SELECT %4(s1), %6, %2
+    %5:gpr(s32) = G_SELECT %7, %6, %2
     $w0 = COPY %5(s32)
     RET_ReallyLR implicit $w0
 
 ...
 ---
 name:            no_cmn_s32_rhs
 alignment:       4
 legalized:       true
bb.0:
     ; CHECK: $w0 = COPY [[CSINCWr]]
     ; CHECK: RET_ReallyLR implicit $w0
     %0:gpr(s32) = COPY $w0
     %1:gpr(s32) = COPY $w1
     %2:gpr(s32) = G_CONSTANT i32 0
     %6:gpr(s32) = G_CONSTANT i32 1
     %3:gpr(s32) = G_SUB %2, %1
     %7:gpr(s32) = G_ICMP intpred(slt), %0(s32), %3
-    %4:gpr(s1) = G_TRUNC %7(s32)
-    %5:gpr(s32) = G_SELECT %4(s1), %6, %2
+    %5:gpr(s32) = G_SELECT %7, %6, %2
     $w0 = COPY %5(s32)
     RET_ReallyLR implicit $w0
 
 ...
 ---
 name:            no_cmn_s32_lhs
 alignment:       4
 legalized:       true
bb.0:
     ; CHECK: $w0 = COPY [[CSINCWr]]
     ; CHECK: RET_ReallyLR implicit $w0
     %0:gpr(s32) = COPY $w0
     %1:gpr(s32) = COPY $w1
     %2:gpr(s32) = G_CONSTANT i32 0
     %6:gpr(s32) = G_CONSTANT i32 1
     %3:gpr(s32) = G_SUB %2, %0
     %7:gpr(s32) = G_ICMP intpred(slt), %3(s32), %1
-    %4:gpr(s1) = G_TRUNC %7(s32)
-    %5:gpr(s32) = G_SELECT %4(s1), %6, %2
+    %5:gpr(s32) = G_SELECT %7, %6, %2
     $w0 = COPY %5(s32)
     RET_ReallyLR implicit $w0
 
 ...
 ---
 name:            cmn_s64_rhs
 alignment:       4
 legalized:       true
bb.0:
     ; CHECK: $x0 = COPY [[CSINCXr]]
     ; CHECK: RET_ReallyLR implicit $x0
     %0:gpr(s64) = COPY $x0
     %1:gpr(s64) = COPY $x1
     %2:gpr(s64) = G_CONSTANT i64 0
     %6:gpr(s64) = G_CONSTANT i64 1
     %3:gpr(s64) = G_SUB %2, %1
     %7:gpr(s32) = G_ICMP intpred(ne), %0(s64), %3
-    %4:gpr(s1) = G_TRUNC %7(s32)
-    %5:gpr(s64) = G_SELECT %4(s1), %6, %2
+    %5:gpr(s64) = G_SELECT %7, %6, %2
     $x0 = COPY %5(s64)
     RET_ReallyLR implicit $x0
 
 ...
 ---
 name:            cmn_s64_lhs
 alignment:       4
 legalized:       true
bb.0:
     ; CHECK: $x0 = COPY [[CSINCXr]]
     ; CHECK: RET_ReallyLR implicit $x0
     %0:gpr(s64) = COPY $x0
     %1:gpr(s64) = COPY $x1
     %2:gpr(s64) = G_CONSTANT i64 0
     %6:gpr(s64) = G_CONSTANT i64 1
     %3:gpr(s64) = G_SUB %2, %0
     %7:gpr(s32) = G_ICMP intpred(ne), %3(s64), %1
-    %4:gpr(s1) = G_TRUNC %7(s32)
-    %5:gpr(s64) = G_SELECT %4(s1), %6, %2
+    %5:gpr(s64) = G_SELECT %7, %6, %2
     $x0 = COPY %5(s64)
     RET_ReallyLR implicit $x0
 
 ...
 ---
 name:            no_cmn_s64_rhs
 alignment:       4
 legalized:       true
bb.0:
     ; CHECK: $x0 = COPY [[CSINCXr]]
     ; CHECK: RET_ReallyLR implicit $x0
     %0:gpr(s64) = COPY $x0
     %1:gpr(s64) = COPY $x1
     %2:gpr(s64) = G_CONSTANT i64 0
     %6:gpr(s64) = G_CONSTANT i64 1
     %3:gpr(s64) = G_SUB %2, %1
     %7:gpr(s32) = G_ICMP intpred(slt), %0(s64), %3
-    %4:gpr(s1) = G_TRUNC %7(s32)
-    %5:gpr(s64) = G_SELECT %4(s1), %6, %2
+    %5:gpr(s64) = G_SELECT %7, %6, %2
     $x0 = COPY %5(s64)
     RET_ReallyLR implicit $x0
 
 ...
 ---
 name:            no_cmn_s64_lhs
 alignment:       4
 legalized:       true
bb.0:
     ; CHECK: $x0 = COPY [[CSINCXr]]
     ; CHECK: RET_ReallyLR implicit $x0
     %0:gpr(s64) = COPY $x0
     %1:gpr(s64) = COPY $x1
     %2:gpr(s64) = G_CONSTANT i64 0
     %6:gpr(s64) = G_CONSTANT i64 1
     %3:gpr(s64) = G_SUB %2, %0
     %7:gpr(s32) = G_ICMP intpred(slt), %3(s64), %1
-    %4:gpr(s1) = G_TRUNC %7(s32)
-    %5:gpr(s64) = G_SELECT %4(s1), %6, %2
+    %5:gpr(s64) = G_SELECT %7, %6, %2
     $x0 = COPY %5(s64)
     RET_ReallyLR implicit $x0
 
 ...
 ---
 name:            tst_s32
 alignment:       4
 legalized:       true
bb.0:
     ; CHECK: RET_ReallyLR implicit $w0
     %0:gpr(s32) = COPY $w0
     %1:gpr(s32) = COPY $w1
     %2:gpr(s32) = G_CONSTANT i32 0
     %6:gpr(s32) = G_CONSTANT i32 1
     %3:gpr(s32) = G_AND %2, %1
     %8:gpr(s32) = G_CONSTANT i32 0
     %7:gpr(s32) = G_ICMP intpred(eq), %3(s32), %8
-    %4:gpr(s1) = G_TRUNC %7(s32)
-    %5:gpr(s32) = G_SELECT %4(s1), %6, %2
+    %5:gpr(s32) = G_SELECT %7, %6, %2
     $w0 = COPY %5(s32)
     RET_ReallyLR implicit $w0
 
 ...
 ---
 name:            tst_s64
 alignment:       4
 legalized:       true
bb.0:
     ; CHECK: RET_ReallyLR implicit $x0
     %0:gpr(s64) = COPY $x0
     %1:gpr(s64) = COPY $x1
     %2:gpr(s64) = G_CONSTANT i64 0
     %6:gpr(s64) = G_CONSTANT i64 1
     %3:gpr(s64) = G_AND %2, %1
     %8:gpr(s64) = G_CONSTANT i64 0
     %7:gpr(s32) = G_ICMP intpred(eq), %3(s64), %8
-    %4:gpr(s1) = G_TRUNC %7(s32)
-    %5:gpr(s64) = G_SELECT %4(s1), %6, %2
+    %5:gpr(s64) = G_SELECT %7, %6, %2
     $x0 = COPY %5(s64)
     RET_ReallyLR implicit $x0
 
 ...
 ---
 name:            no_tst_unsigned_compare
 alignment:       4
 legalized:       true
bb.0:
     ; CHECK: RET_ReallyLR implicit $w0
     %0:gpr(s32) = COPY $w0
     %1:gpr(s32) = COPY $w1
     %2:gpr(s32) = G_CONSTANT i32 0
     %6:gpr(s32) = G_CONSTANT i32 1
     %3:gpr(s32) = G_AND %2, %1
     %8:gpr(s32) = G_CONSTANT i32 0
     %7:gpr(s32) = G_ICMP intpred(ugt), %3(s32), %8
-    %4:gpr(s1) = G_TRUNC %7(s32)
-    %5:gpr(s32) = G_SELECT %4(s1), %6, %2
+    %5:gpr(s32) = G_SELECT %7, %6, %2
     $w0 = COPY %5(s32)
     RET_ReallyLR implicit $w0
 
 ...
 ---
 name:            no_tst_nonzero
 alignment:       4
 legalized:       true
bb.0:
     ; CHECK: RET_ReallyLR implicit $w0
     %0:gpr(s32) = COPY $w0
     %1:gpr(s32) = COPY $w1
     %2:gpr(s32) = G_CONSTANT i32 0
     %6:gpr(s32) = G_CONSTANT i32 1
     %3:gpr(s32) = G_AND %2, %1
     %8:gpr(s32) = G_CONSTANT i32 42
     %7:gpr(s32) = G_ICMP intpred(ugt), %3(s32), %8
-    %4:gpr(s1) = G_TRUNC %7(s32)
-    %5:gpr(s32) = G_SELECT %4(s1), %6, %2
+    %5:gpr(s32) = G_SELECT %7, %6, %2
     $w0 = COPY %5(s32)
     RET_ReallyLR implicit $w0
 
 ...
 ---
 name:            imm_tst
 alignment:       4
 legalized:       true
bb.0:
     ; CHECK: RET_ReallyLR implicit $x0
     %copy:gpr(s64) = COPY $x1
     %zero:gpr(s64) = G_CONSTANT i64 0
     %one:gpr(s64) = G_CONSTANT i64 1
     %cst:gpr(s64) = G_CONSTANT i64 16
     %shift:gpr(s64) = G_SHL %copy(s64), %cst(s64)
     %and:gpr(s64) = G_AND %zero, %shift
     %cmp:gpr(s32) = G_ICMP intpred(eq), %and(s64), %zero
-    %cmp_trunc:gpr(s1) = G_TRUNC %cmp(s32)
-    %select:gpr(s64) = G_SELECT %cmp_trunc(s1), %one, %zero
+    %select:gpr(s64) = G_SELECT %cmp, %one, %zero
     $x0 = COPY %select(s64)
     RET_ReallyLR implicit $x0
 
 ...
 ---
 name:            tst_fold_shift_s32
 alignment:       4
 legalized:       true
bb.0:
     ; CHECK: RET_ReallyLR implicit $w0
     %copy:gpr(s32) = COPY $w1
     %zero:gpr(s32) = G_CONSTANT i32 0
     %one:gpr(s32) = G_CONSTANT i32 1
     %cst:gpr(s32) = G_CONSTANT i32 16
     %shift:gpr(s32) = G_SHL %copy(s32), %cst(s32)
     %and:gpr(s32) = G_AND %zero, %shift
     %cmp:gpr(s32) = G_ICMP intpred(eq), %and(s32), %zero
-    %cmp_trunc:gpr(s1) = G_TRUNC %cmp(s32)
-    %select:gpr(s32) = G_SELECT %cmp_trunc(s1), %one, %zero
+    %select:gpr(s32) = G_SELECT %cmp, %one, %zero
     $w0 = COPY %select(s32)
     RET_ReallyLR implicit $w0
 
 ...
 ---
 name:            cmn_s32_neg_imm
 alignment:       4
 legalized:       true

llvm/test/CodeGen/AArch64/GlobalISel/opt-fold-ext-tbz-tbnz.mir

bb.0:
     successors: %bb.0, %bb.1
     liveins: $x0
     %copy:gpr(s32) = COPY $w0
     %bit:gpr(s64) = G_CONSTANT i64 8
     %zero:gpr(s64) = G_CONSTANT i64 0
     %fold_me:gpr(s64) = G_ZEXT %copy(s32)
     %and:gpr(s64) = G_AND %fold_me, %bit
     %cmp:gpr(s32) = G_ICMP intpred(ne), %and(s64), %zero
-    %cmp_trunc:gpr(s1) = G_TRUNC %cmp(s32)
-    G_BRCOND %cmp_trunc(s1), %bb.1
+    G_BRCOND %cmp, %bb.1
     G_BR %bb.0
   bb.1:
     RET_ReallyLR
 ...
 ---
 name:            fold_anyext
 alignment:       4
 legalized:       true
bb.0:
     successors: %bb.0, %bb.1
     liveins: $x0
     %copy:gpr(s32) = COPY $w0
     %bit:gpr(s64) = G_CONSTANT i64 8
     %zero:gpr(s64) = G_CONSTANT i64 0
     %fold_me:gpr(s64) = G_ANYEXT %copy(s32)
     %and:gpr(s64) = G_AND %fold_me, %bit
     %cmp:gpr(s32) = G_ICMP intpred(ne), %and(s64), %zero
-    %cmp_trunc:gpr(s1) = G_TRUNC %cmp(s32)
-    G_BRCOND %cmp_trunc(s1), %bb.1
+    G_BRCOND %cmp, %bb.1
     G_BR %bb.0
   bb.1:
     RET_ReallyLR
 ...
 ---
 name:            fold_multiple
 alignment:       4
 legalized:       true
bb.0:
     liveins: $h0
     %copy:gpr(s16) = COPY $h0
     %bit:gpr(s64) = G_CONSTANT i64 8
     %zero:gpr(s64) = G_CONSTANT i64 0
     %ext1:gpr(s32) = G_ZEXT %copy(s16)
     %ext2:gpr(s64) = G_ANYEXT %ext1(s32)
     %and:gpr(s64) = G_AND %ext2, %bit
     %cmp:gpr(s32) = G_ICMP intpred(ne), %and(s64), %zero
-    %cmp_trunc:gpr(s1) = G_TRUNC %cmp(s32)
-    G_BRCOND %cmp_trunc(s1), %bb.1
+    G_BRCOND %cmp, %bb.1
     G_BR %bb.0
   bb.1:
     RET_ReallyLR
 ...
 ---
 name:            dont_fold_more_than_one_use
 alignment:       4
 legalized:       true
bb.0:
     successors: %bb.0, %bb.1
     liveins: $x0
     %copy:gpr(s32) = COPY $w0
     %bit:gpr(s64) = G_CONSTANT i64 8
     %zero:gpr(s64) = G_CONSTANT i64 0
     %zext:gpr(s64) = G_ZEXT %copy(s32)
     %and:gpr(s64) = G_AND %zext, %bit
     %cmp:gpr(s32) = G_ICMP intpred(ne), %and(s64), %zero
-    %cmp_trunc:gpr(s1) = G_TRUNC %cmp(s32)
-    G_BRCOND %cmp_trunc(s1), %bb.1
+    G_BRCOND %cmp, %bb.1
     G_BR %bb.0
   bb.1:
     $x0 = COPY %zext:gpr(s64)
     RET_ReallyLR implicit $x0

llvm/test/CodeGen/AArch64/GlobalISel/opt-fold-shift-tbz-tbnz.mir

bb.0:
     %zero:gpr(s64) = G_CONSTANT i64 0
 
     ; tbnz (shl x, 1), 3 == tbnz x, 2
     %fold_cst:gpr(s64) = G_CONSTANT i64 1
     %fold_me:gpr(s64) = G_SHL %copy, %fold_cst
 
     %and:gpr(s64) = G_AND %fold_me, %bit
     %cmp:gpr(s32) = G_ICMP intpred(ne), %and(s64), %zero
-    %cmp_trunc:gpr(s1) = G_TRUNC %cmp(s32)
-    G_BRCOND %cmp_trunc(s1), %bb.1
+    G_BRCOND %cmp, %bb.1
     G_BR %bb.0
   bb.1:
     RET_ReallyLR
 ...
 ---
 name:            dont_fold_shl_1
 alignment:       4
 legalized:       true
bb.0:
     %zero:gpr(s64) = G_CONSTANT i64 0
 
     ; 5 > 3, so we cannot do the transformation as above.
     %fold_cst:gpr(s64) = G_CONSTANT i64 5
     %fold_me:gpr(s64) = G_SHL %copy, %fold_cst
 
     %and:gpr(s64) = G_AND %fold_me, %bit
     %cmp:gpr(s32) = G_ICMP intpred(ne), %and(s64), %zero
-    %cmp_trunc:gpr(s1) = G_TRUNC %cmp(s32)
-    G_BRCOND %cmp_trunc(s1), %bb.1
+    G_BRCOND %cmp, %bb.1
     G_BR %bb.0
   bb.1:
     RET_ReallyLR
 ...
 ---
 name:            dont_fold_shl_2
 alignment:       4
 legalized:       true
bb.0:
     %zero:gpr(s64) = G_CONSTANT i64 0
 
     ; Same case as above, except we wrap around.
     %fold_cst:gpr(s64) = G_CONSTANT i64 -5
     %fold_me:gpr(s64) = G_SHL %copy, %fold_cst
 
     %and:gpr(s64) = G_AND %fold_me, %bit
     %cmp:gpr(s32) = G_ICMP intpred(ne), %and(s64), %zero
-    %cmp_trunc:gpr(s1) = G_TRUNC %cmp(s32)
-    G_BRCOND %cmp_trunc(s1), %bb.1
+    G_BRCOND %cmp, %bb.1
     G_BR %bb.0
   bb.1:
     RET_ReallyLR
 
 ...
 ---
 name:            dont_fold_shl_3
 alignment:       4
bb.0:
     %bit:gpr(s64) = G_CONSTANT i64 8
     %zero:gpr(s64) = G_CONSTANT i64 0
     %fold_cst:gpr(s64) = G_CONSTANT i64 2
 
     ; Don't walk past the G_SHL when it's used more than once.
     %shl:gpr(s64) = G_SHL %copy, %fold_cst
     %and:gpr(s64) = G_AND %shl, %bit
     %cmp:gpr(s32) = G_ICMP intpred(ne), %and(s64), %zero
-    %cmp_trunc:gpr(s1) = G_TRUNC %cmp(s32)
-    G_BRCOND %cmp_trunc(s1), %bb.1
+    G_BRCOND %cmp, %bb.1
     G_BR %bb.0
 
   bb.1:
     %second_use:gpr(s64) = G_OR %shl, %bit
     $x0 = COPY %second_use
     RET_ReallyLR implicit $x0
 
 ...
bb.0:
 
     ; tb(n)z (ashr x, c), b == tbz(x, b + c) when b+c <= the size of the type.
     ; In this case, we should get 1 + 3 = 4 as the bit number.
     %fold_cst:gpr(s64) = G_CONSTANT i64 1
     %fold_me:gpr(s64) = G_ASHR %copy, %fold_cst
 
     %and:gpr(s64) = G_AND %fold_me, %bit
     %cmp:gpr(s32) = G_ICMP intpred(ne), %and(s64), %zero
-    %cmp_trunc:gpr(s1) = G_TRUNC %cmp(s32)
-    G_BRCOND %cmp_trunc(s1), %bb.1
+    G_BRCOND %cmp, %bb.1
     G_BR %bb.0
   bb.1:
     RET_ReallyLR
 
 ...
 ---
 name:            fold_ashr_msb_1
 alignment:       4
bb.0:
     %zero:gpr(s32) = G_CONSTANT i32 0
 
     ; We should get a TBNZW with a 31 as the bit.
     %fold_cst:gpr(s32) = G_CONSTANT i32 1234
     %fold_me:gpr(s32) = G_ASHR %copy, %fold_cst
 
     %and:gpr(s32) = G_AND %fold_me, %bit
     %cmp:gpr(s32) = G_ICMP intpred(ne), %and(s32), %zero
-    %cmp_trunc:gpr(s1) = G_TRUNC %cmp(s32)
-    G_BRCOND %cmp_trunc(s1), %bb.1
+    G_BRCOND %cmp, %bb.1
     G_BR %bb.0
   bb.1:
     RET_ReallyLR
 
 ...
 ---
 name:            fold_ashr_msb_2
 alignment:       4
bb.0:
     %zero:gpr(s64) = G_CONSTANT i64 0
 
     ; We should get a TBNZX with a 63 as the bit.
     %fold_cst:gpr(s64) = G_CONSTANT i64 1234
     %fold_me:gpr(s64) = G_ASHR %copy, %fold_cst
 
     %and:gpr(s64) = G_AND %fold_me, %bit
     %cmp:gpr(s32) = G_ICMP intpred(ne), %and(s64), %zero
-    %cmp_trunc:gpr(s1) = G_TRUNC %cmp(s32)
-    G_BRCOND %cmp_trunc(s1), %bb.1
+    G_BRCOND %cmp, %bb.1
     G_BR %bb.0
   bb.1:
     RET_ReallyLR
 
 ...
 ---
 name:            fold_lshr
 alignment:       4
bb.0:
     %zero:gpr(s32) = G_CONSTANT i32 0
 
     ; We should get 4 as the test bit.
     %fold_cst:gpr(s32) = G_CONSTANT i32 1
     %fold_me:gpr(s32) = G_LSHR %copy, %fold_cst
 
     %and:gpr(s32) = G_AND %fold_me, %bit
     %cmp:gpr(s32) = G_ICMP intpred(ne), %and(s32), %zero
-    %cmp_trunc:gpr(s1) = G_TRUNC %cmp(s32)
-    G_BRCOND %cmp_trunc(s1), %bb.1
+    G_BRCOND %cmp, %bb.1
     G_BR %bb.0
   bb.1:
     RET_ReallyLR
 
 ...
 ---
 name:            fold_lshr_2
 alignment:       4
bb.0:
 
     ; We're testing a s64.
     ; 3 + 29 = 32, which is less than 63, so we can fold.
     %fold_cst:gpr(s64) = G_CONSTANT i64 29
     %fold_me:gpr(s64) = G_LSHR %copy, %fold_cst
 
     %and:gpr(s64) = G_AND %fold_me, %bit
     %cmp:gpr(s32) = G_ICMP intpred(ne), %and(s64), %zero
-    %cmp_trunc:gpr(s1) = G_TRUNC %cmp(s32)
-    G_BRCOND %cmp_trunc(s1), %bb.1
+    G_BRCOND %cmp, %bb.1
     G_BR %bb.0
   bb.1:
     RET_ReallyLR
 
 ...
 ---
 name:            dont_fold_lshr
 alignment:       4
bb.0:
 
     ; We're testing a s32.
     ; 3 + 29 = 32, which is greater than 31, so we don't fold.
     %fold_cst:gpr(s32) = G_CONSTANT i32 29
     %fold_me:gpr(s32) = G_LSHR %copy, %fold_cst
 
     %and:gpr(s32) = G_AND %fold_me, %bit
     %cmp:gpr(s32) = G_ICMP intpred(ne), %and(s32), %zero
-    %cmp_trunc:gpr(s1) = G_TRUNC %cmp(s32)
-    G_BRCOND %cmp_trunc(s1), %bb.1
+    G_BRCOND %cmp, %bb.1
     G_BR %bb.0
   bb.1:
     RET_ReallyLR
 
 ...
 ---
 name:            lshr_negative
 alignment:       4
bb.0:
 
     ; Constant becomes very large and wraps around. Since it's larger than the
     ; bit width, that means the LSHR is poison, so we can still fold.
     %fold_cst:gpr(s32) = G_CONSTANT i32 -1
     %fold_me:gpr(s32) = G_LSHR %copy, %fold_cst
 
     %and:gpr(s32) = G_AND %fold_me, %bit
     %cmp:gpr(s32) = G_ICMP intpred(ne), %and(s32), %zero
-    %cmp_trunc:gpr(s1) = G_TRUNC %cmp(s32)
-    G_BRCOND %cmp_trunc(s1), %bb.1
+    G_BRCOND %cmp, %bb.1
     G_BR %bb.0
   bb.1:
     RET_ReallyLR

llvm/test/CodeGen/AArch64/GlobalISel/opt-fold-trunc-tbz-tbnz.mir

bb.0:
     successors: %bb.0, %bb.1
     liveins: $x0
     %copy:gpr(s64) = COPY $x0
     %bit:gpr(s32) = G_CONSTANT i32 8
     %zero:gpr(s32) = G_CONSTANT i32 0
     %fold_me:gpr(s32) = G_TRUNC %copy(s64)
     %and:gpr(s32) = G_AND %fold_me, %bit
     %cmp:gpr(s32) = G_ICMP intpred(ne), %and(s32), %zero
-    %cmp_trunc:gpr(s1) = G_TRUNC %cmp(s32)
-    G_BRCOND %cmp_trunc(s1), %bb.1
+    G_BRCOND %cmp, %bb.1
     G_BR %bb.0
   bb.1:
     RET_ReallyLR

llvm/test/CodeGen/AArch64/GlobalISel/opt-fold-xor-tbz-tbnz.mir

bb.0:
     %fold_cst:gpr(s64) = G_CONSTANT i64 8
 
     ; This only has the third bit set if %copy does not. So, to walk through
     ; this, we want to use a TBNZW on %copy.
     %fold_me:gpr(s64) = G_XOR %copy, %fold_cst
 
     %and:gpr(s64) = G_AND %fold_me, %bit
     %cmp:gpr(s32) = G_ICMP intpred(eq), %and(s64), %zero
-    %cmp_trunc:gpr(s1) = G_TRUNC %cmp(s32)
-    G_BRCOND %cmp_trunc(s1), %bb.1
+    G_BRCOND %cmp, %bb.1
     G_BR %bb.0
   bb.1:
     RET_ReallyLR
 ...
 ---
 name:            flip_ne
 alignment:       4
 legalized:       true
bb.0:
 
     %copy:gpr(s64) = COPY $x0
     %bit:gpr(s64) = G_CONSTANT i64 8
     %zero:gpr(s64) = G_CONSTANT i64 0
     %fold_cst:gpr(s64) = G_CONSTANT i64 8
     %fold_me:gpr(s64) = G_XOR %copy, %fold_cst
     %and:gpr(s64) = G_AND %fold_me, %bit
     %cmp:gpr(s32) = G_ICMP intpred(ne), %and(s64), %zero
-    %cmp_trunc:gpr(s1) = G_TRUNC %cmp(s32)
-    G_BRCOND %cmp_trunc(s1), %bb.1
+    G_BRCOND %cmp, %bb.1
     G_BR %bb.0
   bb.1:
     RET_ReallyLR
 ...
 ---
 name:            dont_flip_eq
 alignment:       4
 legalized:       true
bb.0:
     %fold_cst:gpr(s64) = G_CONSTANT i64 7
 
     ; This only has the third bit set if %copy does. So, to walk through this,
     ; we should have a TBZW on %copy.
     %fold_me:gpr(s64) = G_XOR %fold_cst, %copy
 
     %and:gpr(s64) = G_AND %fold_me, %bit
     %cmp:gpr(s32) = G_ICMP intpred(eq), %and(s64), %zero
-    %cmp_trunc:gpr(s1) = G_TRUNC %cmp(s32)
-    G_BRCOND %cmp_trunc(s1), %bb.1
+    G_BRCOND %cmp, %bb.1
     G_BR %bb.0
   bb.1:
     RET_ReallyLR
 ...
 ---
 name:            dont_flip_eq_zext
 alignment:       4
 legalized:       true
bb.0:
     successors: %bb.0(0x40000000), %bb.1(0x40000000)
 
     %1:gpr(s32) = G_CONSTANT i32 0
     %3:gpr(s32) = G_CONSTANT i32 -1
     %4:gpr(s32) = G_XOR %1, %3
     %5:gpr(s64) = G_ZEXT %4(s32)
     %15:gpr(s64) = G_CONSTANT i64 0
     %13:gpr(s32) = G_ICMP intpred(slt), %5(s64), %15
-    %7:gpr(s1) = G_TRUNC %13(s32)
-    G_BRCOND %7(s1), %bb.1
+    G_BRCOND %13, %bb.1
     G_BR %bb.0
   bb.1:
     RET_ReallyLR
 ...
 ---
 name:            dont_flip_ne
 alignment:       4
 legalized:       true
bb.0:
 
     %copy:gpr(s64) = COPY $x0
     %bit:gpr(s64) = G_CONSTANT i64 8
     %zero:gpr(s64) = G_CONSTANT i64 0
     %fold_cst:gpr(s64) = G_CONSTANT i64 7
     %fold_me:gpr(s64) = G_XOR %fold_cst, %copy
     %and:gpr(s64) = G_AND %fold_me, %bit
     %cmp:gpr(s32) = G_ICMP intpred(ne), %and(s64), %zero
-    %cmp_trunc:gpr(s1) = G_TRUNC %cmp(s32)
-    G_BRCOND %cmp_trunc(s1), %bb.1
+    G_BRCOND %cmp, %bb.1
     G_BR %bb.0
   bb.1:
     RET_ReallyLR
 ...
 ---
 name:            xor_chain
 alignment:       4
 legalized:       true
bb.0:
     %fold_cst:gpr(s64) = G_CONSTANT i64 8
 
     ; The G_XORs cancel each other out, so we should get a TBZW.
     %xor1:gpr(s64) = G_XOR %copy, %fold_cst
     %xor2:gpr(s64) = G_XOR %xor1, %fold_cst
 
     %and:gpr(s64) = G_AND %xor2, %bit
     %cmp:gpr(s32) = G_ICMP intpred(eq), %and(s64), %zero
-    %cmp_trunc:gpr(s1) = G_TRUNC %cmp(s32)
-    G_BRCOND %cmp_trunc(s1), %bb.1
+    G_BRCOND %cmp, %bb.1
     G_BR %bb.0
   bb.1:
     RET_ReallyLR

llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-adjust-icmp-imm.mir

bb.0:
 
     ; LOWER-LABEL: name: cmp_and_select
     ; LOWER: liveins: $w0, $w1
     ; LOWER-NEXT: {{  $}}
     ; LOWER-NEXT: %reg0:_(s32) = COPY $w0
     ; LOWER-NEXT: %reg1:_(s32) = COPY $w1
     ; LOWER-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
     ; LOWER-NEXT: %cmp:_(s32) = G_ICMP intpred(slt), %reg0(s32), [[C]]
-    ; LOWER-NEXT: %trunc:_(s1) = G_TRUNC %cmp(s32)
-    ; LOWER-NEXT: %select:_(s32) = G_SELECT %trunc(s1), %reg0, %reg1
+    ; LOWER-NEXT: %select:_(s32) = G_SELECT %cmp(s32), %reg0, %reg1
     ; LOWER-NEXT: $w0 = COPY %select(s32)
     ; LOWER-NEXT: RET_ReallyLR implicit $w0
     ; SELECT-LABEL: name: cmp_and_select
     ; SELECT: liveins: $w0, $w1
     ; SELECT-NEXT: {{  $}}
     ; SELECT-NEXT: %reg0:gpr32common = COPY $w0
     ; SELECT-NEXT: %reg1:gpr32 = COPY $w1
     ; SELECT-NEXT: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri %reg0, 0, 0, implicit-def $nzcv
     ; SELECT-NEXT: %select:gpr32 = CSELWr %reg0, %reg1, 11, implicit $nzcv
     ; SELECT-NEXT: $w0 = COPY %select
     ; SELECT-NEXT: RET_ReallyLR implicit $w0
     %reg0:_(s32) = COPY $w0
     %reg1:_(s32) = COPY $w1
     %cst:_(s32) = G_CONSTANT i32 -1
     %cmp:_(s32) = G_ICMP intpred(sle), %reg0(s32), %cst
-    %trunc:_(s1) = G_TRUNC %cmp(s32)
-    %select:_(s32) = G_SELECT %trunc(s1), %reg0, %reg1
+    %select:_(s32) = G_SELECT %cmp, %reg0, %reg1
     $w0 = COPY %select(s32)
     RET_ReallyLR implicit $w0
 
 ...
 ---
 name:             andsxri
 legalized: true
 tracksRegLiveness: true

llvm/test/CodeGen/AArch64/GlobalISel/preselect-process-phis.mir

body:             |
   ; CHECK-NEXT:   [[FCVTHSr:%[0-9]+]]:fpr16 = FCVTHSr [[COPY]]
   ; CHECK-NEXT:   [[SUBREG_TO_REG:%[0-9]+]]:fpr32 = SUBREG_TO_REG 0, [[FCVTHSr]], %subreg.hsub
   ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:gpr32all = COPY [[SUBREG_TO_REG]]
   ; CHECK-NEXT:   STRHHui [[PHI]], [[DEF1]], 0 :: (store (s16) into `half* undef`)
   ; CHECK-NEXT:   B %bb.2
   bb.0:
     successors: %bb.1(0x80000000)
 
-    %0:gpr(s1) = G_IMPLICIT_DEF
+    %0:gpr(s32) = G_IMPLICIT_DEF
     %4:gpr(p0) = G_IMPLICIT_DEF
     %8:fpr(s32) = G_FCONSTANT float 0x7FF8000000000000
 
   bb.1:
     successors: %bb.2(0x80000000)
 
     %6:gpr(s32) = G_IMPLICIT_DEF
-    %7:gpr(s32) = G_SELECT %0(s1), %6, %6
+    %7:gpr(s32) = G_SELECT %0(s32), %6, %6
     %1:gpr(s16) = G_TRUNC %7(s32)
 
   bb.2:
     successors: %bb.2(0x80000000)
 
     %3:gpr(s16) = G_PHI %1(s16), %bb.1, %5(s16), %bb.2
     %5:fpr(s16) = G_FPTRUNC %8(s32)
     G_STORE %3(s16), %4(p0) :: (store (s16) into `half* undef`)
body:             |
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT:   [[PHI:%[0-9]+]]:fpr16 = PHI %7, %bb.2, [[COPY2]], %bb.1
   ; CHECK-NEXT:   [[FCVTHSr:%[0-9]+]]:fpr16 = FCVTHSr [[COPY]]
   ; CHECK-NEXT:   STRHui [[PHI]], [[DEF1]], 0 :: (store (s16) into `half* undef`)
   ; CHECK-NEXT:   B %bb.2
   bb.0:
     successors: %bb.1(0x80000000)
 
-    %0:gpr(s1) = G_IMPLICIT_DEF
+    %0:gpr(s32) = G_IMPLICIT_DEF
     %4:gpr(p0) = G_IMPLICIT_DEF
     %8:fpr(s32) = G_FCONSTANT float 0x7FF8000000000000
 
   bb.1:
     successors: %bb.2(0x80000000)
 
     %6:gpr(s32) = G_IMPLICIT_DEF
-    %7:gpr(s32) = G_SELECT %0(s1), %6, %6
+    %7:gpr(s32) = G_SELECT %0(s32), %6, %6
     %1:gpr(s16) = G_TRUNC %7(s32)
 
   bb.2:
     successors: %bb.2(0x80000000)
 
     %3:fpr(s16) = G_PHI %5(s16), %bb.2, %1(s16), %bb.1
     %5:fpr(s16) = G_FPTRUNC %8(s32)
     G_STORE %3(s16), %4(p0) :: (store (s16) into `half* undef`)
body:             |
   ; CHECK-NEXT:   RET_ReallyLR
 
   ; The copy we insert in bb.4 should appear after all the phi instructions.
 
   bb.1:
     successors: %bb.2, %bb.6
     liveins: $w0, $w1, $x2
     %ptr:gpr(p0) = COPY $x2
-    %cond_1:gpr(s1) = G_IMPLICIT_DEF
+    %cond_1:gpr(s32) = G_IMPLICIT_DEF
     %gpr_1:gpr(s16) = G_IMPLICIT_DEF
-    G_BRCOND %cond_1(s1), %bb.6
+    G_BRCOND %cond_1(s32), %bb.6
     G_BR %bb.2
   bb.2:
     successors: %bb.3, %bb.4
-    %cond_2:gpr(s1) = G_IMPLICIT_DEF
-    G_BRCOND %cond_2(s1), %bb.4
+    %cond_2:gpr(s32) = G_IMPLICIT_DEF
+    G_BRCOND %cond_2(s32), %bb.4
     G_BR %bb.3
   bb.3:
     %gpr_2:gpr(s16) = G_IMPLICIT_DEF
     G_BR %bb.5
   bb.4:
     %fpr:fpr(s16) = G_IMPLICIT_DEF
   bb.5:
     %fp_phi:fpr(s16) = G_PHI %fpr(s16), %bb.4, %gpr_1(s16), %bb.3

llvm/test/CodeGen/AArch64/GlobalISel/regbank-assert-sext.mir

bb.0:
     liveins: $d0, $x1, $w0
 
     ; G_ASSERT_SEXT and G_SELECT should both end up on FPRs.
 
     ; CHECK-LABEL: name: fpr_feeding_select
     ; CHECK: liveins: $d0, $x1, $w0
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: %w0:gpr(s32) = COPY $w0
-    ; CHECK-NEXT: %cond:gpr(s1) = G_TRUNC %w0(s32)
     ; CHECK-NEXT: %fpr:fpr(s64) = COPY $d0
     ; CHECK-NEXT: %fpr_assert_sext:fpr(s64) = G_ASSERT_SEXT %fpr, 32
     ; CHECK-NEXT: %gpr:gpr(s64) = COPY $x1
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr(s64) = COPY %gpr(s64)
-    ; CHECK-NEXT: %select:fpr(s64) = G_SELECT %cond(s1), %fpr_assert_sext, [[COPY]]
+    ; CHECK-NEXT: %select:fpr(s64) = G_SELECT %w0(s32), %fpr_assert_sext, [[COPY]]
     ; CHECK-NEXT: $d0 = COPY %select(s64)
     ; CHECK-NEXT: RET_ReallyLR implicit $d0
     %w0:_(s32) = COPY $w0
-    %cond:_(s1) = G_TRUNC %w0(s32)
     %fpr:_(s64) = COPY $d0
     %fpr_assert_sext:_(s64) = G_ASSERT_SEXT %fpr, 32
     %gpr:_(s64) = COPY $x1
-    %select:_(s64) = G_SELECT %cond(s1), %fpr_assert_sext, %gpr
+    %select:_(s64) = G_SELECT %w0, %fpr_assert_sext, %gpr
     $d0 = COPY %select(s64)
     RET_ReallyLR implicit $d0
 
 ...
 ---
 name:            fpr_feeding_phi
 alignment:       4
 legalized:       true
 tracksRegLiveness: true
 body:             |
   ; CHECK-LABEL: name: fpr_feeding_phi
   ; CHECK: bb.0:
   ; CHECK-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
   ; CHECK-NEXT:   liveins: $s0, $w1
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT:   %copy1:fpr(s32) = COPY $s0
   ; CHECK-NEXT:   %copy2:gpr(s32) = COPY $w1
   ; CHECK-NEXT:   %copy_assert_sext:fpr(s32) = G_ASSERT_SEXT %copy1, 16
   ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gpr(s32) = COPY %copy1(s32)
   ; CHECK-NEXT:   %cmp:gpr(s32) = G_ICMP intpred(eq), [[COPY]](s32), %copy2
-  ; CHECK-NEXT:   %cmp_trunc:gpr(s1) = G_TRUNC %cmp(s32)
-  ; CHECK-NEXT:   G_BRCOND %cmp_trunc(s1), %bb.1
+  ; CHECK-NEXT:   G_BRCOND %cmp(s32), %bb.1
   ; CHECK-NEXT:   G_BR %bb.1
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT: bb.1:
   ; CHECK-NEXT:   successors: %bb.2(0x80000000)
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT:   %bb1_val:gpr(s32) = COPY %copy2(s32)
   ; CHECK-NEXT:   G_BR %bb.2
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT: bb.2:
   ; CHECK-NEXT:   successors: %bb.0(0x80000000)
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT:   %phi:fpr(s32) = G_PHI %copy_assert_sext(s32), %bb.0, %bb1_val(s32), %bb.1
   ; CHECK-NEXT:   G_BR %bb.0
   bb.0:
     successors: %bb.1, %bb.2
     liveins: $s0, $w1
     %copy1:_(s32) = COPY $s0
     %copy2:_(s32) = COPY $w1
 
     ; This should produce a FPR.
     %copy_assert_sext:_(s32) = G_ASSERT_SEXT %copy1(s32), 16
 
     %cmp:_(s32) = G_ICMP intpred(eq), %copy1, %copy2
-    %cmp_trunc:_(s1) = G_TRUNC %cmp
-    G_BRCOND %cmp_trunc, %bb.1
+    G_BRCOND %cmp, %bb.1
     G_BR %bb.1
   bb.1:
     successors: %bb.2
     %bb1_val:_(s32) = COPY %copy2
     G_BR %bb.2
   bb.2:
     successors: %bb.0
     ; This should produce a FPR.
body:             |
   ; CHECK-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
   ; CHECK-NEXT:   liveins: $s0, $s1
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT:   %copy1:fpr(s32) = COPY $s0
   ; CHECK-NEXT:   %copy2:fpr(s32) = COPY $s1
   ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gpr(s32) = COPY %copy1(s32)
   ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:gpr(s32) = COPY %copy2(s32)
   ; CHECK-NEXT:   %cmp:gpr(s32) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY1]]
-  ; CHECK-NEXT:   %cmp_trunc:gpr(s1) = G_TRUNC %cmp(s32)
-  ; CHECK-NEXT:   G_BRCOND %cmp_trunc(s1), %bb.1
+  ; CHECK-NEXT:   G_BRCOND %cmp(s32), %bb.1
   ; CHECK-NEXT:   G_BR %bb.1
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT: bb.1:
   ; CHECK-NEXT:   successors: %bb.2(0x80000000)
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT:   %bb1_val:gpr(s32) = COPY %copy2(s32)
   ; CHECK-NEXT:   G_BR %bb.2
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT: bb.2:
   ; CHECK-NEXT:   successors: %bb.0(0x80000000)
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT:   %phi:fpr(s32) = G_PHI %copy1(s32), %bb.0, %bb1_val(s32), %bb.1
   ; CHECK-NEXT:   %assert_sext:fpr(s32) = G_ASSERT_SEXT %phi, 16
   ; CHECK-NEXT:   G_BR %bb.0
   bb.0:
     successors: %bb.1, %bb.2
     liveins: $s0, $s1
     %copy1:_(s32) = COPY $s0
     %copy2:_(s32) = COPY $s1
     %cmp:_(s32) = G_ICMP intpred(eq), %copy1, %copy2
-    %cmp_trunc:_(s1) = G_TRUNC %cmp
-    G_BRCOND %cmp_trunc, %bb.1
+    G_BRCOND %cmp, %bb.1
     G_BR %bb.1
   bb.1:
     successors: %bb.2
     %bb1_val:_(s32) = COPY %copy2
     G_BR %bb.2
   bb.2:
     successors: %bb.0
     ; The G_PHI and G_ASSERT_SEXT should both end up on FPRs.

llvm/test/CodeGen/AArch64/GlobalISel/regbank-assert-zext.mir

bb.0:
     liveins: $d0, $x1, $w0
 
     ; G_ASSERT_ZEXT and G_SELECT should both end up on FPRs.
 
     ; CHECK-LABEL: name: fpr_feeding_select
     ; CHECK: liveins: $d0, $x1, $w0
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: %w0:gpr(s32) = COPY $w0
-    ; CHECK-NEXT: %cond:gpr(s1) = G_TRUNC %w0(s32)
     ; CHECK-NEXT: %fpr:fpr(s64) = COPY $d0
     ; CHECK-NEXT: %fpr_assert_zext:fpr(s64) = G_ASSERT_ZEXT %fpr, 32
     ; CHECK-NEXT: %gpr:gpr(s64) = COPY $x1
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr(s64) = COPY %gpr(s64)
-    ; CHECK-NEXT: %select:fpr(s64) = G_SELECT %cond(s1), %fpr_assert_zext, [[COPY]]
+    ; CHECK-NEXT: %select:fpr(s64) = G_SELECT %w0(s32), %fpr_assert_zext, [[COPY]]
     ; CHECK-NEXT: $d0 = COPY %select(s64)
     ; CHECK-NEXT: RET_ReallyLR implicit $d0
     %w0:_(s32) = COPY $w0
-    %cond:_(s1) = G_TRUNC %w0(s32)
     %fpr:_(s64) = COPY $d0
     %fpr_assert_zext:_(s64) = G_ASSERT_ZEXT %fpr, 32
     %gpr:_(s64) = COPY $x1
-    %select:_(s64) = G_SELECT %cond(s1), %fpr_assert_zext, %gpr
+    %select:_(s64) = G_SELECT %w0, %fpr_assert_zext, %gpr
     $d0 = COPY %select(s64)
     RET_ReallyLR implicit $d0
 
 ...
 ---
 name:            fpr_feeding_phi
 alignment:       4
 legalized:       true
 tracksRegLiveness: true
 body:             |
   ; CHECK-LABEL: name: fpr_feeding_phi
   ; CHECK: bb.0:
   ; CHECK-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
   ; CHECK-NEXT:   liveins: $s0, $w1
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT:   %copy1:fpr(s32) = COPY $s0
   ; CHECK-NEXT:   %copy2:gpr(s32) = COPY $w1
   ; CHECK-NEXT:   %copy_assert_zext:fpr(s32) = G_ASSERT_ZEXT %copy1, 16
   ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gpr(s32) = COPY %copy1(s32)
   ; CHECK-NEXT:   %cmp:gpr(s32) = G_ICMP intpred(eq), [[COPY]](s32), %copy2
-  ; CHECK-NEXT:   %cmp_trunc:gpr(s1) = G_TRUNC %cmp(s32)
-  ; CHECK-NEXT:   G_BRCOND %cmp_trunc(s1), %bb.1
+  ; CHECK-NEXT:   G_BRCOND %cmp(s32), %bb.1
   ; CHECK-NEXT:   G_BR %bb.1
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT: bb.1:
   ; CHECK-NEXT:   successors: %bb.2(0x80000000)
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT:   %bb1_val:gpr(s32) = COPY %copy2(s32)
   ; CHECK-NEXT:   G_BR %bb.2
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT: bb.2:
   ; CHECK-NEXT:   successors: %bb.0(0x80000000)
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT:   %phi:fpr(s32) = G_PHI %copy_assert_zext(s32), %bb.0, %bb1_val(s32), %bb.1
   ; CHECK-NEXT:   G_BR %bb.0
   bb.0:
     successors: %bb.1, %bb.2
     liveins: $s0, $w1
     %copy1:_(s32) = COPY $s0
     %copy2:_(s32) = COPY $w1
 
     ; This should produce a FPR.
     %copy_assert_zext:_(s32) = G_ASSERT_ZEXT %copy1(s32), 16
 
     %cmp:_(s32) = G_ICMP intpred(eq), %copy1, %copy2
-    %cmp_trunc:_(s1) = G_TRUNC %cmp
-    G_BRCOND %cmp_trunc, %bb.1
+    G_BRCOND %cmp, %bb.1
     G_BR %bb.1
   bb.1:
     successors: %bb.2
     %bb1_val:_(s32) = COPY %copy2
     G_BR %bb.2
   bb.2:
     successors: %bb.0
     ; This should produce a FPR.
body:             |
   ; CHECK-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
   ; CHECK-NEXT:   liveins: $s0, $s1
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT:   %copy1:fpr(s32) = COPY $s0
   ; CHECK-NEXT:   %copy2:fpr(s32) = COPY $s1
   ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gpr(s32) = COPY %copy1(s32)
   ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:gpr(s32) = COPY %copy2(s32)
   ; CHECK-NEXT:   %cmp:gpr(s32) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY1]]
-  ; CHECK-NEXT:   %cmp_trunc:gpr(s1) = G_TRUNC %cmp(s32)
-  ; CHECK-NEXT:   G_BRCOND %cmp_trunc(s1), %bb.1
+  ; CHECK-NEXT:   G_BRCOND %cmp(s32), %bb.1
   ; CHECK-NEXT:   G_BR %bb.1
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT: bb.1:
   ; CHECK-NEXT:   successors: %bb.2(0x80000000)
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT:   %bb1_val:gpr(s32) = COPY %copy2(s32)
   ; CHECK-NEXT:   G_BR %bb.2
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT: bb.2:
   ; CHECK-NEXT:   successors: %bb.0(0x80000000)
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT:   %phi:fpr(s32) = G_PHI %copy1(s32), %bb.0, %bb1_val(s32), %bb.1
   ; CHECK-NEXT:   %assert_zext:fpr(s32) = G_ASSERT_ZEXT %phi, 16
   ; CHECK-NEXT:   G_BR %bb.0
   bb.0:
     successors: %bb.1, %bb.2
     liveins: $s0, $s1
     %copy1:_(s32) = COPY $s0
     %copy2:_(s32) = COPY $s1
     %cmp:_(s32) = G_ICMP intpred(eq), %copy1, %copy2
-    %cmp_trunc:_(s1) = G_TRUNC %cmp
-    G_BRCOND %cmp_trunc, %bb.1
+    G_BRCOND %cmp, %bb.1
     G_BR %bb.1
   bb.1:
     successors: %bb.2
     %bb1_val:_(s32) = COPY %copy2
     G_BR %bb.2
   bb.2:
     successors: %bb.0
     ; The G_PHI and G_ASSERT_ZEXT should both end up on FPRs.

llvm/test/CodeGen/AArch64/GlobalISel/regbank-fp-use-def.mir

 tracksRegLiveness: true
 body:             |
   bb.0:
     liveins: $w0, $w1, $w2
     ; CHECK-LABEL: name: select_defined_by_fp_using_fp
     ; CHECK: liveins: $w0, $w1, $w2
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr(s32) = COPY $w0
-    ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:gpr(s1) = G_TRUNC %2(s32)
     ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr(s32) = COPY $w1
     ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr(s32) = COPY $w2
     ; CHECK-NEXT: [[SITOFP:%[0-9]+]]:fpr(s32) = G_SITOFP [[COPY1]](s32)
     ; CHECK-NEXT: [[COPY3:%[0-9]+]]:fpr(s32) = COPY [[COPY2]](s32)
-    ; CHECK-NEXT: [[SELECT:%[0-9]+]]:fpr(s32) = G_SELECT [[TRUNC]](s1), [[COPY3]], [[SITOFP]]
+    ; CHECK-NEXT: [[SELECT:%[0-9]+]]:fpr(s32) = G_SELECT [[COPY2]](s32), [[COPY3]], [[SITOFP]]
     ; CHECK-NEXT: [[FPTOSI:%[0-9]+]]:gpr(s32) = G_FPTOSI [[SELECT]](s32)
     %0:_(s32) = COPY $w0
-    %1:_(s1) = G_TRUNC %3(s32)
     %2:_(s32) = COPY $w1
     %3:_(s32) = COPY $w2
     %4:_(s32) = G_SITOFP %2
-    %6:_(s32) = G_SELECT %1(s1), %3, %4
+    %6:_(s32) = G_SELECT %3, %3, %4
     %8:_(s32) = G_FPTOSI %6
 
 ...
 ---
 name:            load_used_by_phi_fpr
 legalized:       true
 tracksRegLiveness: true
 body:             |
   ; CHECK-LABEL: name: load_used_by_phi_fpr
   ; CHECK: bb.0:
   ; CHECK-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
   ; CHECK-NEXT:   liveins: $x0, $s0, $s1, $w0, $w1
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT:   %cond_wide:gpr(s32) = COPY $w0
-  ; CHECK-NEXT:   %cond:gpr(s1) = G_TRUNC %cond_wide(s32)
   ; CHECK-NEXT:   %fpr_copy:fpr(s32) = COPY $s0
   ; CHECK-NEXT:   %ptr:gpr(p0) = COPY $x0
-  ; CHECK-NEXT:   G_BRCOND %cond(s1), %bb.1
+  ; CHECK-NEXT:   G_BRCOND %cond_wide(s32), %bb.1
   ; CHECK-NEXT:   G_BR %bb.2
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT: bb.1:
   ; CHECK-NEXT:   successors: %bb.2(0x80000000)
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT:   %load:fpr(s32) = G_LOAD %ptr(p0) :: (load (s32))
   ; CHECK-NEXT:   G_BR %bb.2
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT: bb.2:
   ; CHECK-NEXT:   %phi:fpr(s32) = G_PHI %fpr_copy(s32), %bb.0, %load(s32), %bb.1
   ; CHECK-NEXT:   $s0 = COPY %phi(s32)
   ; CHECK-NEXT:   RET_ReallyLR implicit $s0
   bb.0:
     successors: %bb.1(0x40000000), %bb.2(0x40000000)
     liveins: $x0, $s0, $s1, $w0, $w1
     %cond_wide:_(s32) = COPY $w0
-    %cond:_(s1) = G_TRUNC %cond_wide(s32)
     %fpr_copy:_(s32) = COPY $s0
     %ptr:_(p0) = COPY $x0
-    G_BRCOND %cond(s1), %bb.1
+    G_BRCOND %cond_wide, %bb.1
     G_BR %bb.2
   bb.1:
     successors: %bb.2
     %load:_(s32) = G_LOAD %ptr(p0) :: (load (s32))
     G_BR %bb.2
   bb.2:
     %phi:_(s32) = G_PHI %fpr_copy(s32), %bb.0, %load(s32), %bb.1
     $s0 = COPY %phi(s32)
     RET_ReallyLR implicit $s0
 
 ...
 ---
 name:            load_used_by_phi_gpr
 legalized:       true
 tracksRegLiveness: true
 body:             |
   ; CHECK-LABEL: name: load_used_by_phi_gpr
   ; CHECK: bb.0:
   ; CHECK-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
   ; CHECK-NEXT:   liveins: $x0, $s0, $s1, $w0, $w1
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT:   %cond_wide:gpr(s32) = COPY $w0
-  ; CHECK-NEXT:   %cond:gpr(s1) = G_TRUNC %cond_wide(s32)
   ; CHECK-NEXT:   %gpr_copy:gpr(s32) = COPY $w1
   ; CHECK-NEXT:   %ptr:gpr(p0) = COPY $x0
-  ; CHECK-NEXT:   G_BRCOND %cond(s1), %bb.1
+  ; CHECK-NEXT:   G_BRCOND %cond_wide(s32), %bb.1
   ; CHECK-NEXT:   G_BR %bb.2
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT: bb.1:
   ; CHECK-NEXT:   successors: %bb.2(0x80000000)
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT:   %load:gpr(s32) = G_LOAD %ptr(p0) :: (load (s32))
   ; CHECK-NEXT:   G_BR %bb.2
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT: bb.2:
   ; CHECK-NEXT:   %phi:gpr(s32) = G_PHI %gpr_copy(s32), %bb.0, %load(s32), %bb.1
   ; CHECK-NEXT:   $s0 = COPY %phi(s32)
   ; CHECK-NEXT:   RET_ReallyLR implicit $s0
   bb.0:
     successors: %bb.1(0x40000000), %bb.2(0x40000000)
     liveins: $x0, $s0, $s1, $w0, $w1
     %cond_wide:_(s32) = COPY $w0
-    %cond:_(s1) = G_TRUNC %cond_wide(s32)
     %gpr_copy:_(s32) = COPY $w1
     %ptr:_(p0) = COPY $x0
-    G_BRCOND %cond(s1), %bb.1
+    G_BRCOND %cond_wide, %bb.1
     G_BR %bb.2
   bb.1:
     successors: %bb.2
     %load:_(s32) = G_LOAD %ptr(p0) :: (load (s32))
     G_BR %bb.2
   bb.2:
     %phi:_(s32) = G_PHI %gpr_copy(s32), %bb.0, %load(s32), %bb.1
     $s0 = COPY %phi(s32)
     RET_ReallyLR implicit $s0
 
 ...
 ---
 name:            select_used_by_phi_fpr
 legalized:       true
 tracksRegLiveness: true
 body:             |
   ; CHECK-LABEL: name: select_used_by_phi_fpr
   ; CHECK: bb.0:
   ; CHECK-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
   ; CHECK-NEXT:   liveins: $s0, $s1, $w0, $w1
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT:   %cond_wide:gpr(s32) = COPY $w0
-  ; CHECK-NEXT:   %cond:gpr(s1) = G_TRUNC %cond_wide(s32)
   ; CHECK-NEXT:   %fpr_copy:fpr(s32) = COPY $s0
   ; CHECK-NEXT:   %gpr_copy:gpr(s32) = COPY $w1
-  ; CHECK-NEXT:   G_BRCOND %cond(s1), %bb.1
+  ; CHECK-NEXT:   G_BRCOND %cond_wide(s32), %bb.1
   ; CHECK-NEXT:   G_BR %bb.2
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT: bb.1:
   ; CHECK-NEXT:   successors: %bb.2(0x80000000)
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT:   [[COPY:%[0-9]+]]:fpr(s32) = COPY %gpr_copy(s32)
-  ; CHECK-NEXT:   %select:fpr(s32) = G_SELECT %cond(s1), %fpr_copy, [[COPY]]
+  ; CHECK-NEXT:   %select:fpr(s32) = G_SELECT %cond_wide(s32), %fpr_copy, [[COPY]]
   ; CHECK-NEXT:   G_BR %bb.2
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT: bb.2:
   ; CHECK-NEXT:   %phi:fpr(s32) = G_PHI %fpr_copy(s32), %bb.0, %select(s32), %bb.1
   ; CHECK-NEXT:   $w0 = COPY %phi(s32)
   ; CHECK-NEXT:   RET_ReallyLR implicit $w0
   ; The G_SELECT and G_PHI should end up with the same register bank.
   ;
   bb.0:
     successors: %bb.1(0x40000000), %bb.2(0x40000000)
     liveins: $s0, $s1, $w0, $w1
     %cond_wide:_(s32) = COPY $w0
-    %cond:_(s1) = G_TRUNC %cond_wide(s32)
     %fpr_copy:_(s32) = COPY $s0
     %gpr_copy:_(s32) = COPY $w1
-    G_BRCOND %cond(s1), %bb.1
+    G_BRCOND %cond_wide, %bb.1
     G_BR %bb.2
   bb.1:
     successors: %bb.2
-    %select:_(s32) = G_SELECT %cond(s1), %fpr_copy, %gpr_copy
+    %select:_(s32) = G_SELECT %cond_wide, %fpr_copy, %gpr_copy
     G_BR %bb.2
   bb.2:
     %phi:_(s32) = G_PHI %fpr_copy(s32), %bb.0, %select(s32), %bb.1
     $w0 = COPY %phi(s32)
     RET_ReallyLR implicit $w0
 
 ...
 ---
 name:            select_used_by_phi_gpr
 legalized:       true
 tracksRegLiveness: true
 body:             |
   ; CHECK-LABEL: name: select_used_by_phi_gpr
   ; CHECK: bb.0:
   ; CHECK-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
   ; CHECK-NEXT:   liveins: $s0, $s1, $w0, $w1
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT:   %cond_wide:gpr(s32) = COPY $w0
-  ; CHECK-NEXT:   %cond:gpr(s1) = G_TRUNC %cond_wide(s32)
   ; CHECK-NEXT:   %fpr_copy:fpr(s32) = COPY $s0
   ; CHECK-NEXT:   %gpr_copy:gpr(s32) = COPY $w1
-  ; CHECK-NEXT:   G_BRCOND %cond(s1), %bb.1
+  ; CHECK-NEXT:   G_BRCOND %cond_wide(s32), %bb.1
   ; CHECK-NEXT:   G_BR %bb.2
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT: bb.1:
   ; CHECK-NEXT:   successors: %bb.2(0x80000000)
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gpr(s32) = COPY %fpr_copy(s32)
-  ; CHECK-NEXT:   %select:gpr(s32) = G_SELECT %cond(s1), [[COPY]], %gpr_copy
+  ; CHECK-NEXT:   %select:gpr(s32) = G_SELECT %cond_wide(s32), [[COPY]], %gpr_copy
   ; CHECK-NEXT:   G_BR %bb.2
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT: bb.2:
   ; CHECK-NEXT:   %phi:gpr(s32) = G_PHI %gpr_copy(s32), %bb.0, %select(s32), %bb.1
   ; CHECK-NEXT:   $s0 = COPY %phi(s32)
   ; CHECK-NEXT:   RET_ReallyLR implicit $s0
   ; The G_SELECT and G_PHI should end up with the same register bank.
   ;
   bb.0:
     successors: %bb.1(0x40000000), %bb.2(0x40000000)
     liveins: $s0, $s1, $w0, $w1
     %cond_wide:_(s32) = COPY $w0
-    %cond:_(s1) = G_TRUNC %cond_wide(s32)
     %fpr_copy:_(s32) = COPY $s0
     %gpr_copy:_(s32) = COPY $w1
-    G_BRCOND %cond(s1), %bb.1
+    G_BRCOND %cond_wide, %bb.1
     G_BR %bb.2
   bb.1:
     successors: %bb.2
-    %select:_(s32) = G_SELECT %cond(s1), %fpr_copy, %gpr_copy
+    %select:_(s32) = G_SELECT %cond_wide, %fpr_copy, %gpr_copy
     G_BR %bb.2
   bb.2:
     %phi:_(s32) = G_PHI %gpr_copy(s32), %bb.0, %select(s32), %bb.1
     $s0 = COPY %phi(s32)
     RET_ReallyLR implicit $s0
 
 
 ...
 ---
 name:            unmerge_used_by_phi_fpr
 legalized:       true
 tracksRegLiveness: true
 body:             |
   ; CHECK-LABEL: name: unmerge_used_by_phi_fpr
   ; CHECK: bb.0:
   ; CHECK-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
   ; CHECK-NEXT:   liveins: $x0, $s0, $s1, $w0, $w1
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT:   %cond_wide:gpr(s32) = COPY $w0
-  ; CHECK-NEXT:   %cond:gpr(s1) = G_TRUNC %cond_wide(s32)
   ; CHECK-NEXT:   %fpr_copy:fpr(s32) = COPY $s0
   ; CHECK-NEXT:   %unmerge_src:gpr(s64) = COPY $x0
-  ; CHECK-NEXT:   G_BRCOND %cond(s1), %bb.1
+  ; CHECK-NEXT:   G_BRCOND %cond_wide(s32), %bb.1
   ; CHECK-NEXT:   G_BR %bb.2
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT: bb.1:
   ; CHECK-NEXT:   successors: %bb.2(0x80000000)
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT:   [[COPY:%[0-9]+]]:fpr(s64) = COPY %unmerge_src(s64)
   ; CHECK-NEXT:   %unmerge_1:fpr(s32), %unmerge_2:fpr(s32) = G_UNMERGE_VALUES [[COPY]](s64)
   ; CHECK-NEXT:   G_BR %bb.2
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT: bb.2:
   ; CHECK-NEXT:   %phi:fpr(s32) = G_PHI %fpr_copy(s32), %bb.0, %unmerge_1(s32), %bb.1
   ; CHECK-NEXT:   $s0 = COPY %phi(s32)
   ; CHECK-NEXT:   RET_ReallyLR implicit $s0
   bb.0:
     successors: %bb.1(0x40000000), %bb.2(0x40000000)
     liveins: $x0, $s0, $s1, $w0, $w1
     %cond_wide:_(s32) = COPY $w0
-    %cond:_(s1) = G_TRUNC %cond_wide(s32)
+
     %fpr_copy:_(s32) = COPY $s0
     %unmerge_src:_(s64) = COPY $x0
-    G_BRCOND %cond(s1), %bb.1
+    G_BRCOND %cond_wide, %bb.1
     G_BR %bb.2
   bb.1:
     successors: %bb.2
     %unmerge_1:_(s32), %unmerge_2:_(s32) = G_UNMERGE_VALUES %unmerge_src(s64)
     G_BR %bb.2
   bb.2:
     %phi:_(s32) = G_PHI %fpr_copy(s32), %bb.0, %unmerge_1(s32), %bb.1
     $s0 = COPY %phi(s32)
     RET_ReallyLR implicit $s0
 
 ...
 ---
 name:            unmerge_used_by_phi_gpr
 legalized:       true
 tracksRegLiveness: true
 body:             |
   ; CHECK-LABEL: name: unmerge_used_by_phi_gpr
   ; CHECK: bb.0:
   ; CHECK-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
   ; CHECK-NEXT:   liveins: $x0, $s0, $s1, $w0, $w1
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT:   %cond_wide:gpr(s32) = COPY $w0
-  ; CHECK-NEXT:   %cond:gpr(s1) = G_TRUNC %cond_wide(s32)
   ; CHECK-NEXT:   %gpr_copy:gpr(s32) = COPY $w1
   ; CHECK-NEXT:   %unmerge_src:gpr(s64) = COPY $x0
-  ; CHECK-NEXT:   G_BRCOND %cond(s1), %bb.1
+  ; CHECK-NEXT:   G_BRCOND %cond_wide(s32), %bb.1
   ; CHECK-NEXT:   G_BR %bb.2
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT: bb.1:
   ; CHECK-NEXT:   successors: %bb.2(0x80000000)
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT:   %unmerge_1:gpr(s32), %unmerge_2:gpr(s32) = G_UNMERGE_VALUES %unmerge_src(s64)
   ; CHECK-NEXT:   G_BR %bb.2
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT: bb.2:
   ; CHECK-NEXT:   %phi:gpr(s32) = G_PHI %gpr_copy(s32), %bb.0, %unmerge_1(s32), %bb.1
   ; CHECK-NEXT:   $s0 = COPY %phi(s32)
   ; CHECK-NEXT:   RET_ReallyLR implicit $s0
   bb.0:
     successors: %bb.1(0x40000000), %bb.2(0x40000000)
     liveins: $x0, $s0, $s1, $w0, $w1
     %cond_wide:_(s32) = COPY $w0
-    %cond:_(s1) = G_TRUNC %cond_wide(s32)
     %gpr_copy:_(s32) = COPY $w1
     %unmerge_src:_(s64) = COPY $x0
-    G_BRCOND %cond(s1), %bb.1
+    G_BRCOND %cond_wide, %bb.1
     G_BR %bb.2
   bb.1:
     successors: %bb.2
     %unmerge_1:_(s32), %unmerge_2:_(s32) = G_UNMERGE_VALUES %unmerge_src(s64)
     G_BR %bb.2
   bb.2:
     %phi:_(s32) = G_PHI %gpr_copy(s32), %bb.0, %unmerge_1(s32), %bb.1
     $s0 = COPY %phi(s32)

llvm/test/CodeGen/AArch64/GlobalISel/regbank-select.mir

 body:             |
   bb.0:
     liveins: $s0, $s1, $w0
 
     ; CHECK-LABEL: name: select_f32
     ; CHECK: liveins: $s0, $s1, $w0
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr(s32) = COPY $w0
-    ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:gpr(s1) = G_TRUNC [[COPY]](s32)
     ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr(s32) = COPY $s0
     ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr(s32) = COPY $s1
-    ; CHECK-NEXT: [[SELECT:%[0-9]+]]:fpr(s32) = G_SELECT [[TRUNC]](s1), [[COPY1]], [[COPY2]]
+    ; CHECK-NEXT: [[SELECT:%[0-9]+]]:fpr(s32) = G_SELECT [[COPY]](s32), [[COPY1]], [[COPY2]]
     ; CHECK-NEXT: $s0 = COPY [[SELECT]](s32)
     ; CHECK-NEXT: RET_ReallyLR implicit $s0
     %3:_(s32) = COPY $w0
-    %0:_(s1) = G_TRUNC %3(s32)
     %1:_(s32) = COPY $s0
     %2:_(s32) = COPY $s1
-    %4:_(s32) = G_SELECT %0(s1), %1, %2
+    %4:_(s32) = G_SELECT %3, %1, %2
     $s0 = COPY %4(s32)
     RET_ReallyLR implicit $s0
 
 ...
 ---
 name:            select_f64
 alignment:       4
 legalized:       true
 tracksRegLiveness: true
 machineFunctionInfo: {}
 body:             |
   bb.0:
     liveins: $d0, $d1, $w0
 
     ; CHECK-LABEL: name: select_f64
     ; CHECK: liveins: $d0, $d1, $w0
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr(s32) = COPY $w0
-    ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:gpr(s1) = G_TRUNC [[COPY]](s32)
     ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr(s64) = COPY $d0
     ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr(s64) = COPY $d1
-    ; CHECK-NEXT: [[SELECT:%[0-9]+]]:fpr(s64) = G_SELECT [[TRUNC]](s1), [[COPY1]], [[COPY2]]
+    ; CHECK-NEXT: [[SELECT:%[0-9]+]]:fpr(s64) = G_SELECT [[COPY]](s32), [[COPY1]], [[COPY2]]
     ; CHECK-NEXT: $d0 = COPY [[SELECT]](s64)
     ; CHECK-NEXT: RET_ReallyLR implicit $d0
     %3:_(s32) = COPY $w0
-    %0:_(s1) = G_TRUNC %3(s32)
     %1:_(s64) = COPY $d0
     %2:_(s64) = COPY $d1
-    %4:_(s64) = G_SELECT %0(s1), %1, %2
+    %4:_(s64) = G_SELECT %3, %1, %2
     $d0 = COPY %4(s64)
     RET_ReallyLR implicit $d0
 
 ...
 ---
 name:            two_fpr_inputs_gpr_output
 alignment:       4
 legalized:       true
 tracksRegLiveness: true
 machineFunctionInfo: {}
 body:             |
   bb.0:
     liveins: $d0, $d1, $w0
 
     ; Verify that the G_SELECT only has FPRs.
     ; The only difference between fcsel and csel are the register banks. So,
     ; if we have two FPR inputs and a GPR output, we should do a floating point
     ; select anyway. This will cost one copy for the output, but that's less
     ; than doing two to put the inputs on GPRs.
 
     ; CHECK-LABEL: name: two_fpr_inputs_gpr_output
     ; CHECK: liveins: $d0, $d1, $w0
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr(s32) = COPY $w0
-    ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:gpr(s1) = G_TRUNC [[COPY]](s32)
     ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr(s64) = COPY $d0
     ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr(s64) = COPY $d1
-    ; CHECK-NEXT: [[SELECT:%[0-9]+]]:fpr(s64) = G_SELECT [[TRUNC]](s1), [[COPY1]], [[COPY2]]
+    ; CHECK-NEXT: [[SELECT:%[0-9]+]]:fpr(s64) = G_SELECT [[COPY]](s32), [[COPY1]], [[COPY2]]
     ; CHECK-NEXT: $x0 = COPY [[SELECT]](s64)
     ; CHECK-NEXT: RET_ReallyLR implicit $x0
     %3:_(s32) = COPY $w0
-    %0:_(s1) = G_TRUNC %3(s32)
     %1:_(s64) = COPY $d0
     %2:_(s64) = COPY $d1
-    %4:_(s64) = G_SELECT %0(s1), %1, %2
+    %4:_(s64) = G_SELECT %3, %1, %2
     $x0 = COPY %4(s64)
     RET_ReallyLR implicit $x0
 
 ...
 ---
 name:            one_fpr_input_fpr_output
 alignment:       4
 legalized:       true
 tracksRegLiveness: true
 machineFunctionInfo: {}
 body:             |
   bb.0:
     liveins: $d0, $x1, $w0
 
     ; Same idea as the above test. If the output is an FPR, and one of the
     ; inputs is an FPR, then it's fewer copies to just do a FCSEL.
 
     ; CHECK-LABEL: name: one_fpr_input_fpr_output
     ; CHECK: liveins: $d0, $x1, $w0
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr(s32) = COPY $w0
-    ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:gpr(s1) = G_TRUNC [[COPY]](s32)
     ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr(s64) = COPY $d0
     ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr(s64) = COPY $x1
     ; CHECK-NEXT: [[COPY3:%[0-9]+]]:fpr(s64) = COPY [[COPY2]](s64)
-    ; CHECK-NEXT: [[SELECT:%[0-9]+]]:fpr(s64) = G_SELECT [[TRUNC]](s1), [[COPY1]], [[COPY3]]
+    ; CHECK-NEXT: [[SELECT:%[0-9]+]]:fpr(s64) = G_SELECT [[COPY]](s32), [[COPY1]], [[COPY3]]
     ; CHECK-NEXT: $d0 = COPY [[SELECT]](s64)
     ; CHECK-NEXT: RET_ReallyLR implicit $d0
     %3:_(s32) = COPY $w0
-    %0:_(s1) = G_TRUNC %3(s32)
     %1:_(s64) = COPY $d0
     %2:_(s64) = COPY $x1
-    %4:_(s64) = G_SELECT %0(s1), %1, %2
+    %4:_(s64) = G_SELECT %3, %1, %2
     $d0 = COPY %4(s64)
     RET_ReallyLR implicit $d0
 
 ...
 ---
 name:            one_fpr_input_gpr_output
 alignment:       4
 legalized:       true
 tracksRegLiveness: true
 machineFunctionInfo: {}
 body:             |
   bb.0:
     liveins: $d0, $x1, $w0
 
     ; Now we have more GPR registers on the G_SELECT. It's cheaper here to put
     ; everything on GPR.
 
     ; CHECK-LABEL: name: one_fpr_input_gpr_output
     ; CHECK: liveins: $d0, $x1, $w0
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr(s32) = COPY $w0
-    ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:gpr(s1) = G_TRUNC [[COPY]](s32)
     ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr(s64) = COPY $d0
     ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr(s64) = COPY $x1
     ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr(s64) = COPY [[COPY1]](s64)
-    ; CHECK-NEXT: [[SELECT:%[0-9]+]]:gpr(s64) = G_SELECT [[TRUNC]](s1), [[COPY3]], [[COPY2]]
+    ; CHECK-NEXT: [[SELECT:%[0-9]+]]:gpr(s64) = G_SELECT [[COPY]](s32), [[COPY3]], [[COPY2]]
     ; CHECK-NEXT: $x0 = COPY [[SELECT]](s64)
     ; CHECK-NEXT: RET_ReallyLR implicit $x0
     %3:_(s32) = COPY $w0
-    %0:_(s1) = G_TRUNC %3(s32)
     %1:_(s64) = COPY $d0
     %2:_(s64) = COPY $x1
-    %4:_(s64) = G_SELECT %0(s1), %1, %2
+    %4:_(s64) = G_SELECT %3, %1, %2
     $x0 = COPY %4(s64)
     RET_ReallyLR implicit $x0
 
 ...
 ---
 name:            two_gpr_input_fpr_output
 alignment:       4
 legalized:       true
 tracksRegLiveness: true
 machineFunctionInfo: {}
 body:             |
   bb.0:
     liveins: $x0, $x1, $w0
 
     ; Same as above. The G_SELECT should get all GPRS.
 
     ; CHECK-LABEL: name: two_gpr_input_fpr_output
     ; CHECK: liveins: $x0, $x1, $w0
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr(s32) = COPY $w0
-    ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:gpr(s1) = G_TRUNC [[COPY]](s32)
     ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr(s64) = COPY $x0
     ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr(s64) = COPY $x1
-    ; CHECK-NEXT: [[SELECT:%[0-9]+]]:gpr(s64) = G_SELECT [[TRUNC]](s1), [[COPY1]], [[COPY2]]
+    ; CHECK-NEXT: [[SELECT:%[0-9]+]]:gpr(s64) = G_SELECT [[COPY]](s32), [[COPY1]], [[COPY2]]
     ; CHECK-NEXT: $d0 = COPY [[SELECT]](s64)
     ; CHECK-NEXT: RET_ReallyLR implicit $d0
     %3:_(s32) = COPY $w0
-    %0:_(s1) = G_TRUNC %3(s32)
     %1:_(s64) = COPY $x0
     %2:_(s64) = COPY $x1
-    %4:_(s64) = G_SELECT %0(s1), %1, %2
+    %4:_(s64) = G_SELECT %3, %1, %2
     $d0 = COPY %4(s64)
     RET_ReallyLR implicit $d0

llvm/test/CodeGen/AArch64/GlobalISel/regbankselect-default.mir

 body:             |
   ; CHECK-LABEL: name: test_gphi_ptr
   ; CHECK: bb.0:
   ; CHECK:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
   ; CHECK:   liveins: $w2, $x0, $x1
   ; CHECK:   [[COPY:%[0-9]+]]:gpr(p0) = COPY $x0
   ; CHECK:   [[COPY1:%[0-9]+]]:gpr(p0) = COPY $x1
   ; CHECK:   [[COPY2:%[0-9]+]]:gpr(s32) = COPY $w2
-  ; CHECK:   [[TRUNC:%[0-9]+]]:gpr(s1) = G_TRUNC [[COPY2]](s32)
-  ; CHECK:   G_BRCOND [[TRUNC]](s1), %bb.1
+  ; CHECK:   G_BRCOND [[COPY2]](s32), %bb.1
   ; CHECK:   G_BR %bb.2
   ; CHECK: bb.1:
   ; CHECK:   successors: %bb.2(0x80000000)
   ; CHECK: bb.2:
   ; CHECK:   [[PHI:%[0-9]+]]:gpr(p0) = G_PHI [[COPY]](p0), %bb.0, [[COPY1]](p0), %bb.1
   ; CHECK:   $x0 = COPY [[PHI]](p0)
   ; CHECK:   RET_ReallyLR implicit $x0
   bb.0:
     successors: %bb.1, %bb.2
     liveins: $w2, $x0, $x1
 
     %0(p0) = COPY $x0
     %1(p0) = COPY $x1
     %4(s32) = COPY $w2
-    %2(s1) = G_TRUNC %4(s32)
-    G_BRCOND %2(s1), %bb.1
+    G_BRCOND %4, %bb.1
     G_BR %bb.2
 
   bb.1:
     successors: %bb.2
 
 
   bb.2:
     %3(p0) = G_PHI %0(p0), %bb.0, %1(p0), %bb.1

llvm/test/CodeGen/AArch64/GlobalISel/select-br.mir

 # CHECK:  body:
 # CHECK:   bb.0:
 # CHECK:    TBNZW %1, 0, %bb.1
 # CHECK:    B %bb.0
 body:             |
   bb.0:
     successors: %bb.0, %bb.1
     %1(s32) = COPY $w0
-    %0(s1) = G_TRUNC %1
-    G_BRCOND %0(s1), %bb.1
+    G_BRCOND %1, %bb.1
     G_BR %bb.0
 
   bb.1:
 ...
 
 ---
 # CHECK-LABEL: name: indirect_br
 name:            indirect_br

llvm/test/CodeGen/AArch64/GlobalISel/select-brcond-of-binop.mir

bb.1:
     successors: %bb.2, %bb.3
     liveins: $x0
 
     %0:gpr(p0) = COPY $x0
     %8:gpr(s8) = G_LOAD %0(p0) :: (load (s8))
     %4:gpr(s32) = G_ANYEXT %8(s8)
     %5:gpr(s32) = G_CONSTANT i32 1
     %6:gpr(s32) = G_XOR %4, %5
-    %3:gpr(s1) = G_TRUNC %6(s32)
-    G_BRCOND %3(s1), %bb.3
+    G_BRCOND %6, %bb.3
 
   bb.2:
     RET_ReallyLR
 
   bb.3:
     RET_ReallyLR
 
 ...
bb.1:
     successors: %bb.2, %bb.3
     liveins: $x0
 
     %0:gpr(p0) = COPY $x0
     %8:gpr(s8) = G_LOAD %0(p0) :: (load (s8))
     %4:gpr(s64) = G_ANYEXT %8(s8)
     %5:gpr(s64) = G_CONSTANT i64 1
     %6:gpr(s64) = G_XOR %4, %5
-    %3:gpr(s1) = G_TRUNC %6(s64)
-    G_BRCOND %3(s1), %bb.3
+    %3:gpr(s32) = G_TRUNC %6(s64)
+    G_BRCOND %3(s32), %bb.3
 
   bb.2:
     RET_ReallyLR
 
   bb.3:
     RET_ReallyLR
 
 ...
body:             |
   ; CHECK-NEXT: bb.2:
   ; CHECK-NEXT:   RET_ReallyLR
   bb.1:
     successors: %bb.2, %bb.3
     liveins: $w0
     %lhs:gpr(s32) = COPY $w0
     %rhs:gpr(s32) = G_CONSTANT i32 1
     %op:gpr(s32) = G_AND %lhs, %rhs
-    %trunc:gpr(s1) = G_TRUNC %op(s32)
-    G_BRCOND %trunc(s1), %bb.3
+    G_BRCOND %op, %bb.3
 
   bb.2:
     RET_ReallyLR
 
   bb.3:
     RET_ReallyLR
 
 ...
body:             |
   ; CHECK-NEXT: bb.2:
   ; CHECK-NEXT:   RET_ReallyLR
   bb.1:
     successors: %bb.2, %bb.3
     liveins: $w0, $w1
     %lhs:gpr(s32) = COPY $w0
     %rhs:gpr(s32) = COPY $w1
     %op:gpr(s32) = G_AND %lhs, %rhs
-    %trunc:gpr(s1) = G_TRUNC %op(s32)
-    G_BRCOND %trunc(s1), %bb.3
+    G_BRCOND %op, %bb.3
 
   bb.2:
     RET_ReallyLR
 
   bb.3:
     RET_ReallyLR
 
 ...
body:             |
   ; bit - constant < 0, which isn't valid for tbz/tbnz.
   ;
   bb.1:
     successors: %bb.2, %bb.3
     liveins: $w0
     %lhs:gpr(s32) = COPY $w0
     %rhs:gpr(s32) = G_CONSTANT i32 1
     %op:gpr(s32) = G_SHL %lhs, %rhs
-    %trunc:gpr(s1) = G_TRUNC %op(s32)
-    G_BRCOND %trunc(s1), %bb.3
+    G_BRCOND %op, %bb.3
 
   bb.2:
     RET_ReallyLR
 
   bb.3:
     RET_ReallyLR
 
 ...
body:             |
   ; (tbz (ashr x, c), 0) where 0 + c > # bits in x.
   ;
   bb.1:
     successors: %bb.2, %bb.3
     liveins: $w0
     %lhs:gpr(s32) = COPY $w0
     %rhs:gpr(s32) = G_CONSTANT i32 1
     %op:gpr(s32) = G_ASHR %lhs, %rhs
-    %trunc:gpr(s1) = G_TRUNC %op(s32)
-    G_BRCOND %trunc(s1), %bb.3
+    G_BRCOND %op, %bb.3
 
   bb.2:
     RET_ReallyLR
 
   bb.3:
     RET_ReallyLR
 
 ...
body:             |
   ; CHECK-NEXT: bb.2:
   ; CHECK-NEXT:   RET_ReallyLR
   bb.1:
     successors: %bb.2, %bb.3
     liveins: $x0
     %lhs:gpr(s64) = COPY $x0
     %rhs:gpr(s64) = G_CONSTANT i64 8589934592
     %op:gpr(s64) = G_ASHR %lhs, %rhs
-    %trunc:gpr(s1) = G_TRUNC %op(s64)
-    G_BRCOND %trunc(s1), %bb.3
+    %trunc:gpr(s32) = G_TRUNC %op(s64)
+    G_BRCOND %trunc, %bb.3
   bb.2:
     RET_ReallyLR
   bb.3:
     RET_ReallyLR
 ...

llvm/test/CodeGen/AArch64/GlobalISel/select-cbz.mir

body:             |
   ; CHECK-NEXT: bb.1:
   bb.0:
     liveins: $w0
     successors: %bb.0, %bb.1
 
     %0:gpr(s32) = COPY $w0
     %1:gpr(s32) = G_CONSTANT i32 0
     %2:gpr(s32) = G_ICMP intpred(eq), %0, %1
-    %3:gpr(s1) = G_TRUNC %2(s32)
-    G_BRCOND %3(s1), %bb.1
+    G_BRCOND %2, %bb.1
     G_BR %bb.0
 
   bb.1:
 ...
 
 ---
 name:            cbz_s64
 legalized:       true
body:             |
   ; CHECK-NEXT: bb.1:
   bb.0:
     liveins: $x0
     successors: %bb.0, %bb.1
 
     %0:gpr(s64) = COPY $x0
     %1:gpr(s64) = G_CONSTANT i64 0
     %2:gpr(s32) = G_ICMP intpred(eq), %0, %1
-    %3:gpr(s1) = G_TRUNC %2(s32)
-    G_BRCOND %3(s1), %bb.1
+    G_BRCOND %2, %bb.1
     G_BR %bb.0
 
   bb.1:
 ...
 
 ---
 name:            cbnz_s32
 legalized:       true
body:             |
   ; CHECK-NEXT: bb.1:
   bb.0:
     liveins: $w0
     successors: %bb.0, %bb.1
 
     %0:gpr(s32) = COPY $w0
     %1:gpr(s32) = G_CONSTANT i32 0
     %2:gpr(s32) = G_ICMP intpred(ne), %0, %1
-    %3:gpr(s1) = G_TRUNC %2(s32)
-    G_BRCOND %3(s1), %bb.1
+    G_BRCOND %2, %bb.1
     G_BR %bb.0
 
   bb.1:
 ...
 
 ---
 name:            cbnz_s64
 legalized:       true
body:             |
   ; CHECK-NEXT: bb.1:
   bb.0:
     liveins: $x0
     successors: %bb.0, %bb.1
 
     %0:gpr(s64) = COPY $x0
     %1:gpr(s64) = G_CONSTANT i64 0
     %2:gpr(s32) = G_ICMP intpred(ne), %0, %1
-    %3:gpr(s1) = G_TRUNC %2(s32)
-    G_BRCOND %3(s1), %bb.1
+    G_BRCOND %2, %bb.1
     G_BR %bb.0
 
   bb.1:
 ...
 ---
 name:            test_rhs_inttoptr
 alignment:       4
 legalized:       true
body:             |
   bb.1:
     successors: %bb.2, %bb.3
     liveins: $x0
 
     %0:gpr(p0) = COPY $x0
     %2:gpr(s64) = G_CONSTANT i64 0
     %1:gpr(p0) = G_INTTOPTR %2(s64)
     %4:gpr(s32) = G_ICMP intpred(eq), %0(p0), %1
-    %3:gpr(s1) = G_TRUNC %4(s32)
-    G_BRCOND %3(s1), %bb.3
+    G_BRCOND %4, %bb.3
 
   bb.2:
     %5:gpr(s64) = G_CONSTANT i64 0
     G_STORE %5(s64), %0(p0) :: (store (s64))
 
   bb.3:
     RET_ReallyLR
 
bb.1:
     successors: %bb.2, %bb.3
     liveins: $x0
 
     %0:gpr(p0) = COPY $x0
     %2:gpr(s64) = G_CONSTANT i64 42
     %4:gpr(s64) = G_CONSTANT i64 0
     %1:gpr(s64) = G_LOAD %0(p0) :: (load (s64))
     %5:gpr(s32) = G_ICMP intpred(eq), %1(s64), %2
-    %3:gpr(s1) = G_TRUNC %5(s32)
-    G_BRCOND %3(s1), %bb.3
+    G_BRCOND %5, %bb.3
 
   bb.2:
     %6:gpr(s64) = G_CONSTANT i64 0
     G_STORE %6(s64), %0(p0) :: (store (s64))
 
   bb.3:
     RET_ReallyLR
 
 

llvm/test/CodeGen/AArch64/GlobalISel/select-int-ptr-casts.mir

 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -global-isel-abort=1 -verify-machineinstrs %s -o - | FileCheck %s
 
 --- |
   target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
 
   define void @inttoptr_p0_s64() { ret void }
   define void @ptrtoint_s64_p0() { ret void }
   define void @ptrtoint_s32_p0() { ret void }
   define void @ptrtoint_s16_p0() { ret void }
   define void @ptrtoint_s8_p0() { ret void }
-  define void @ptrtoint_s1_p0() { ret void }
   define void @inttoptr_v2p0_v2s64() { ret void }
   define void @ptrtoint_v2s64_v2p0() { ret void }
 ...
 
 ---
 name:            inttoptr_p0_s64
 legalized:       true
 regBankSelected: true
bb.0:
     ; CHECK-NEXT: $w0 = COPY [[COPY2]]
     %0(p0) = COPY $x0
     %1(s8) = G_PTRTOINT %0
     %2:gpr(s32) = G_ANYEXT %1
     $w0 = COPY %2(s32)
 ...
 
 ---
-name:            ptrtoint_s1_p0
-legalized:       true
-regBankSelected: true
-
-registers:
-  - { id: 0, class: gpr }
-  - { id: 1, class: gpr }
-body:             |
-  bb.0:
-    liveins: $x0
-    ; CHECK-LABEL: name: ptrtoint_s1_p0
-    ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
-    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]].sub_32
-    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr32all = COPY [[COPY1]]
-    ; CHECK-NEXT: $w0 = COPY [[COPY2]]
-    %0(p0) = COPY $x0
-    %1(s1) = G_PTRTOINT %0
-    %2:gpr(s32) = G_ANYEXT %1
-    $w0 = COPY %2(s32)
-...
-
----
 name:            inttoptr_v2p0_v2s64
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 body:             |
   bb.0:
     liveins: $q0, $x0
     ; CHECK-LABEL: name: inttoptr_v2p0_v2s64

llvm/test/CodeGen/AArch64/GlobalISel/select-jump-table-brjt.mir

body:             |
   ; CHECK-NEXT:   [[SUBSXri:%[0-9]+]]:gpr64 = SUBSXri [[SUBREG_TO_REG]], 71, 0, implicit-def $nzcv
   ; CHECK-NEXT:   Bcc 8, %bb.4, implicit $nzcv
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT: bb.1.entry:
   ; CHECK-NEXT:   successors: %bb.3(0x2aaaaaab), %bb.4(0x2aaaaaab), %bb.2(0x2aaaaaab)
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT:   [[COPY2:%[0-9]+]]:gpr32 = COPY $wzr
   ; CHECK-NEXT:   [[MOVaddrJT:%[0-9]+]]:gpr64common = MOVaddrJT target-flags(aarch64-page) %jump-table.0, target-flags(aarch64-pageoff, aarch64-nc) %jump-table.0
-  ; CHECK-NEXT:   early-clobber %18:gpr64, early-clobber %19:gpr64sp = JumpTableDest32 [[MOVaddrJT]], [[SUBREG_TO_REG]], %jump-table.0
-  ; CHECK-NEXT:   BR %18
+  ; CHECK-NEXT:   early-clobber %17:gpr64, early-clobber %18:gpr64sp = JumpTableDest32 [[MOVaddrJT]], [[SUBREG_TO_REG]], %jump-table.0
+  ; CHECK-NEXT:   BR %17
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT: bb.2.sw.bb:
   ; CHECK-NEXT:   successors: %bb.4(0x80000000)
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT:   [[ADDWri:%[0-9]+]]:gpr32sp = nsw ADDWri [[COPY]], 42, 0
   ; CHECK-NEXT:   B %bb.4
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT: bb.3.sw.bb1:
bb.1.entry:
     %8:gpr(s32) = G_CONSTANT i32 3
     %10:gpr(s32) = G_CONSTANT i32 42
     %13:gpr(s32) = G_CONSTANT i32 0
     %1:gpr(s32) = G_CONSTANT i32 4
     %2:gpr(s32) = G_SUB %0, %1
     %3:gpr(s64) = G_ZEXT %2(s32)
     %5:gpr(s64) = G_ZEXT %4(s32)
     %14:gpr(s32) = G_ICMP intpred(ugt), %3(s64), %5
-    %6:gpr(s1) = G_TRUNC %14(s32)
-    G_BRCOND %6(s1), %bb.4
+    G_BRCOND %14, %bb.4
 
   bb.5.entry:
     successors: %bb.3, %bb.4, %bb.2
 
     %17:gpr(s32) = G_CONSTANT i32 0
     %7:gpr(p0) = G_JUMP_TABLE %jump-table.0
     G_BRJT %7(p0), %jump-table.0, %3(s64)
 

llvm/test/CodeGen/AArch64/GlobalISel/select-phi.mir

bb.1.entry:
     ; CHECK-LABEL: name: test_phi
     ; CHECK: [[RES:%.*]]:gpr32 = PHI
 
     %0(s32) = COPY $w0
     %1(s32) = G_CONSTANT i32 0
     %3(s32) = G_CONSTANT i32 1
     %5(s32) = G_CONSTANT i32 2
     %8(s32) = G_ICMP intpred(ugt), %0(s32), %1
-    %2(s1) = G_TRUNC %8(s32)
-    G_BRCOND %2(s1), %bb.2.case1
+    G_BRCOND %8, %bb.2.case1
     G_BR %bb.3.case2
 
   bb.2.case1:
     successors: %bb.4.return(0x80000000)
 
     %4(s32) = G_ADD %0, %3
     G_BR %bb.4.return
 

 body:             |
   bb.0:
     successors: %bb.1, %bb.2
     liveins: $w2, $x0, $x1
     ; CHECK-LABEL: name: test_phi_ptr
 
     %0(p0) = COPY $x0
     %1(p0) = COPY $x1
-    %6:gpr(s32) = COPY $w2
-    %2(s1) = G_TRUNC %6
-    G_BRCOND %2(s1), %bb.1
+    %2:gpr(s32) = COPY $w2
+    G_BRCOND %2, %bb.1
     G_BR %bb.2
 
   bb.1:
     successors: %bb.2
 
 
   bb.2:
     ; CHECK: %{{[0-9]+}}:gpr64 = PHI %{{[0-9]+}}, %bb.0, %{{[0-9]+}}, %bb.1
     %3(p0) = G_PHI %0(p0), %bb.0, %1(p0), %bb.1
     $x0 = COPY %3(p0)
     RET_ReallyLR implicit $x0
 
 ...

llvm/test/CodeGen/AArch64/GlobalISel/select-redundant-zext.mir

body:             |
   ; We should have a ORRWrs here, because isDef32 disallows phis.
 
   bb.0:
     liveins: $w0, $w1, $w2
 
     %copy1:gpr(s32) = COPY $w0
     %copy2:gpr(s32) = COPY $w1
     %cond_wide:gpr(s32) = COPY $w2
-    %cond:gpr(s1) = G_TRUNC %cond_wide(s32)
-    G_BRCOND %cond(s1), %bb.1
+    G_BRCOND %cond_wide, %bb.1
     G_BR %bb.2
 
   bb.1:
 
   bb.2:
     %phi:gpr(s32) = G_PHI %copy1(s32), %bb.0, %copy2(s32), %bb.1
     %5:gpr(s64) = G_ZEXT %phi(s32)
     $x0 = COPY %5(s64)

llvm/test/CodeGen/AArch64/GlobalISel/select-saddo.mir

bb.1.entry:
 
     ; CHECK-LABEL: name: saddo_s32
     ; CHECK: liveins: $w0, $w1, $x2
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
     ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
     ; CHECK-NEXT: [[ADDSWrr:%[0-9]+]]:gpr32 = ADDSWrr [[COPY]], [[COPY1]], implicit-def $nzcv
     ; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 7, implicit $nzcv
-    ; CHECK-NEXT: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[CSINCWr]], 0, 0
-    ; CHECK-NEXT: [[UBFMWri1:%[0-9]+]]:gpr32 = UBFMWri [[UBFMWri]], 0, 7
-    ; CHECK-NEXT: $w0 = COPY [[UBFMWri1]]
-    ; CHECK-NEXT: RET_ReallyLR implicit $w0
+    ; CHECK-NEXT: $w0 = COPY [[ADDSWrr]]
+    ; CHECK-NEXT: $w1 = COPY [[CSINCWr]]
+    ; CHECK-NEXT: RET_ReallyLR implicit $w0, implicit $w1
     %0:gpr(s32) = COPY $w0
     %1:gpr(s32) = COPY $w1
-    %3:gpr(s32), %4:gpr(s1) = G_SADDO %0, %1
-    %5:gpr(s8) = G_ZEXT %4(s1)
-    %6:gpr(s32) = G_ZEXT %5(s8)
-    $w0 = COPY %6(s32)
-    RET_ReallyLR implicit $w0
+    %3:gpr(s32), %4:gpr(s32) = G_SADDO %0, %1
+    $w0 = COPY %3
+    $w1 = COPY %4
+    RET_ReallyLR implicit $w0, implicit $w1
 
 ...
 ---
 name:            saddo_s64
 alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 body:             |
   bb.1.entry:
     liveins: $x0, $x1, $x2
 
     ; CHECK-LABEL: name: saddo_s64
     ; CHECK: liveins: $x0, $x1, $x2
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
     ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
     ; CHECK-NEXT: [[ADDSXrr:%[0-9]+]]:gpr64 = ADDSXrr [[COPY]], [[COPY1]], implicit-def $nzcv
     ; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 7, implicit $nzcv
-    ; CHECK-NEXT: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[CSINCWr]], 0, 0
-    ; CHECK-NEXT: [[UBFMWri1:%[0-9]+]]:gpr32 = UBFMWri [[UBFMWri]], 0, 7
-    ; CHECK-NEXT: $w0 = COPY [[UBFMWri1]]
-    ; CHECK-NEXT: RET_ReallyLR implicit $w0
+    ; CHECK-NEXT: $x0 = COPY [[ADDSXrr]]
+    ; CHECK-NEXT: $w1 = COPY [[CSINCWr]]
+    ; CHECK-NEXT: RET_ReallyLR implicit $x0, implicit $w1
     %0:gpr(s64) = COPY $x0
     %1:gpr(s64) = COPY $x1
-    %3:gpr(s64), %4:gpr(s1) = G_SADDO %0, %1
-    %5:gpr(s8) = G_ZEXT %4(s1)
-    %6:gpr(s32) = G_ZEXT %5(s8)
-    $w0 = COPY %6(s32)
-    RET_ReallyLR implicit $w0
+    %3:gpr(s64), %4:gpr(s32) = G_SADDO %0, %1
+    $x0 = COPY %3
+    $w1 = COPY %4
+    RET_ReallyLR implicit $x0, implicit $w1
 
 ...
 ---
 name:            saddo_s32_imm
 alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 body:             |
   bb.1.entry:
     liveins: $w0, $w1, $x2
     ; Check that we get ADDSWri when we can fold in a constant.
     ;
     ; CHECK-LABEL: name: saddo_s32_imm
     ; CHECK: liveins: $w0, $w1, $x2
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: %copy:gpr32sp = COPY $w0
     ; CHECK-NEXT: %add:gpr32 = ADDSWri %copy, 16, 0, implicit-def $nzcv
     ; CHECK-NEXT: %overflow:gpr32 = CSINCWr $wzr, $wzr, 7, implicit $nzcv
     ; CHECK-NEXT: $w0 = COPY %add
     ; CHECK-NEXT: RET_ReallyLR implicit $w0
     %copy:gpr(s32) = COPY $w0
     %constant:gpr(s32) = G_CONSTANT i32 16
-    %add:gpr(s32), %overflow:gpr(s1) = G_SADDO %copy, %constant
+    %add:gpr(s32), %overflow:gpr(s32) = G_SADDO %copy, %constant
     $w0 = COPY %add(s32)
     RET_ReallyLR implicit $w0
 
 ...
 ---
 name:            saddo_s32_shifted
 alignment:       4
 legalized:       true
bb.1.entry:
     ; CHECK-NEXT: %add:gpr32 = ADDSWrs %copy1, %copy2, 16, implicit-def $nzcv
     ; CHECK-NEXT: %overflow:gpr32 = CSINCWr $wzr, $wzr, 7, implicit $nzcv
     ; CHECK-NEXT: $w0 = COPY %add
     ; CHECK-NEXT: RET_ReallyLR implicit $w0
     %copy1:gpr(s32) = COPY $w0
     %copy2:gpr(s32) = COPY $w1
     %constant:gpr(s32) = G_CONSTANT i32 16
     %shift:gpr(s32) = G_SHL %copy2(s32), %constant(s32)
-    %add:gpr(s32), %overflow:gpr(s1) = G_SADDO %copy1, %shift
+    %add:gpr(s32), %overflow:gpr(s32) = G_SADDO %copy1, %shift
     $w0 = COPY %add(s32)
     RET_ReallyLR implicit $w0
 
 ...
 ---
 name:            saddo_s32_neg_imm
 alignment:       4
 legalized:       true
bb.1.entry:
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: %copy:gpr32sp = COPY $w0
     ; CHECK-NEXT: %add:gpr32 = SUBSWri %copy, 16, 0, implicit-def $nzcv
     ; CHECK-NEXT: %overflow:gpr32 = CSINCWr $wzr, $wzr, 7, implicit $nzcv
     ; CHECK-NEXT: $w0 = COPY %add
     ; CHECK-NEXT: RET_ReallyLR implicit $w0
     %copy:gpr(s32) = COPY $w0
     %constant:gpr(s32) = G_CONSTANT i32 -16
-    %add:gpr(s32), %overflow:gpr(s1) = G_SADDO %copy, %constant
+    %add:gpr(s32), %overflow:gpr(s32) = G_SADDO %copy, %constant
     $w0 = COPY %add(s32)
     RET_ReallyLR implicit $w0
 
 ...
 ---
 name:            saddo_arith_extended
 alignment:       4
 legalized:       true
bb.1.entry:
     ; CHECK-NEXT: %flags:gpr32 = CSINCWr $wzr, $wzr, 7, implicit $nzcv
     ; CHECK-NEXT: $x0 = COPY %add
     ; CHECK-NEXT: RET_ReallyLR implicit $x0
     %reg0:gpr(s64) = COPY $x0
     %reg1:gpr(s32) = COPY $w0
     %ext:gpr(s64) = G_ZEXT %reg1(s32)
     %cst:gpr(s64) = G_CONSTANT i64 2
     %shift:gpr(s64) = G_SHL %ext, %cst(s64)
-    %add:gpr(s64), %flags:gpr(s1) = G_SADDO %reg0, %shift
+    %add:gpr(s64), %flags:gpr(s32) = G_SADDO %reg0, %shift
     $x0 = COPY %add(s64)
     RET_ReallyLR implicit $x0

llvm/test/CodeGen/AArch64/GlobalISel/select-select.mir

bb.0:
     liveins: $s0, $s1, $w0
 
     ; CHECK-LABEL: name: select_f32
     ; CHECK: liveins: $s0, $s1, $w0
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
     ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $s0
     ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr32 = COPY $s1
-    ; CHECK-NEXT: [[COPY3:%[0-9]+]]:fpr32 = COPY [[COPY]]
-    ; CHECK-NEXT: [[COPY4:%[0-9]+]]:gpr32 = COPY [[COPY3]]
-    ; CHECK-NEXT: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri [[COPY4]], 0, implicit-def $nzcv
+    ; CHECK-NEXT: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri [[COPY]], 0, implicit-def $nzcv
     ; CHECK-NEXT: [[FCSELSrrr:%[0-9]+]]:fpr32 = FCSELSrrr [[COPY1]], [[COPY2]], 1, implicit $nzcv
     ; CHECK-NEXT: $s0 = COPY [[FCSELSrrr]]
     ; CHECK-NEXT: RET_ReallyLR implicit $s0
-    %3:gpr(s32) = COPY $w0
-    %0:gpr(s1) = G_TRUNC %3(s32)
+    %0:gpr(s32) = COPY $w0
     %1:fpr(s32) = COPY $s0
     %2:fpr(s32) = COPY $s1
-    %5:fpr(s1) = COPY %0(s1)
-    %4:fpr(s32) = G_SELECT %5(s1), %1, %2
+    %4:fpr(s32) = G_SELECT %0, %1, %2
     $s0 = COPY %4(s32)
     RET_ReallyLR implicit $s0
 
 ...
 ---
 name:            select_f64
 alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 machineFunctionInfo: {}
 body:             |
   bb.0:
     liveins: $d0, $d1, $w0
 
     ; CHECK-LABEL: name: select_f64
     ; CHECK: liveins: $d0, $d1, $w0
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
     ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
     ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY $d1
-    ; CHECK-NEXT: [[COPY3:%[0-9]+]]:fpr32 = COPY [[COPY]]
-    ; CHECK-NEXT: [[COPY4:%[0-9]+]]:gpr32 = COPY [[COPY3]]
-    ; CHECK-NEXT: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri [[COPY4]], 0, implicit-def $nzcv
+    ; CHECK-NEXT: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri [[COPY]], 0, implicit-def $nzcv
     ; CHECK-NEXT: [[FCSELDrrr:%[0-9]+]]:fpr64 = FCSELDrrr [[COPY1]], [[COPY2]], 1, implicit $nzcv
     ; CHECK-NEXT: $d0 = COPY [[FCSELDrrr]]
     ; CHECK-NEXT: RET_ReallyLR implicit $d0
-    %3:gpr(s32) = COPY $w0
-    %0:gpr(s1) = G_TRUNC %3(s32)
+    %0:gpr(s32) = COPY $w0
     %1:fpr(s64) = COPY $d0
     %2:fpr(s64) = COPY $d1
-    %5:fpr(s1) = COPY %0(s1)
-    %4:fpr(s64) = G_SELECT %5(s1), %1, %2
+    %4:fpr(s64) = G_SELECT %0, %1, %2
     $d0 = COPY %4(s64)
     RET_ReallyLR implicit $d0
 ...
 ---
 name:            csel
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
bb.0:
     ; CHECK-NEXT: %f:gpr32 = COPY $w3
     ; CHECK-NEXT: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr %reg0, %reg1, implicit-def $nzcv
     ; CHECK-NEXT: %select:gpr32 = CSELWr %t, %f, 1, implicit $nzcv
     ; CHECK-NEXT: $w0 = COPY %select
     ; CHECK-NEXT: RET_ReallyLR implicit $w0
     %reg0:gpr(s32) = COPY $w0
     %reg1:gpr(s32) = COPY $w1
     %cmp:gpr(s32) = G_ICMP intpred(ne), %reg0(s32), %reg1
-    %cond:gpr(s1) = G_TRUNC %cmp(s32)
     %t:gpr(s32) = COPY $w2
     %f:gpr(s32) = COPY $w3
-    %select:gpr(s32) = G_SELECT %cond(s1), %t, %f
+    %select:gpr(s32) = G_SELECT %cmp, %t, %f
     $w0 = COPY %select(s32)
     RET_ReallyLR implicit $w0
 ...
 ---
 name:            csinc_t_0_f_1
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
bb.0:
     ; CHECK-NEXT: %reg1:gpr32 = COPY $w1
     ; CHECK-NEXT: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr %reg0, %reg1, implicit-def $nzcv
     ; CHECK-NEXT: %select:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv
     ; CHECK-NEXT: $w0 = COPY %select
     ; CHECK-NEXT: RET_ReallyLR implicit $w0
     %reg0:gpr(s32) = COPY $w0
     %reg1:gpr(s32) = COPY $w1
     %cmp:gpr(s32) = G_ICMP intpred(ne), %reg0(s32), %reg1
-    %cond:gpr(s1) = G_TRUNC %cmp(s32)
     %t:gpr(s32) = G_CONSTANT i32 0
     %f:gpr(s32) = G_CONSTANT i32 1
-    %select:gpr(s32) = G_SELECT %cond(s1), %t, %f
+    %select:gpr(s32) = G_SELECT %cmp, %t, %f
     $w0 = COPY %select(s32)
     RET_ReallyLR implicit $w0
 ...
 ---
 name:            csinv_t_0_f_neg_1
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
bb.0:
     ; CHECK-NEXT: %reg1:gpr32 = COPY $w1
     ; CHECK-NEXT: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr %reg0, %reg1, implicit-def $nzcv
     ; CHECK-NEXT: %select:gpr32 = CSINVWr $wzr, $wzr, 1, implicit $nzcv
     ; CHECK-NEXT: $w0 = COPY %select
     ; CHECK-NEXT: RET_ReallyLR implicit $w0
     %reg0:gpr(s32) = COPY $w0
     %reg1:gpr(s32) = COPY $w1
     %cmp:gpr(s32) = G_ICMP intpred(ne), %reg0(s32), %reg1
-    %cond:gpr(s1) = G_TRUNC %cmp(s32)
     %t:gpr(s32) = G_CONSTANT i32 0
     %f:gpr(s32) = G_CONSTANT i32 -1
-    %select:gpr(s32) = G_SELECT %cond(s1), %t, %f
+    %select:gpr(s32) = G_SELECT %cmp, %t, %f
     $w0 = COPY %select(s32)
     RET_ReallyLR implicit $w0
 ...
 ---
 name:            csinc_t_1
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
bb.0:
     ; CHECK-NEXT: %f:gpr32 = COPY $w2
     ; CHECK-NEXT: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr %reg0, %reg1, implicit-def $nzcv
     ; CHECK-NEXT: %select:gpr32 = CSINCWr %f, $wzr, 0, implicit $nzcv
     ; CHECK-NEXT: $w0 = COPY %select
     ; CHECK-NEXT: RET_ReallyLR implicit $w0
     %reg0:gpr(s32) = COPY $w0
     %reg1:gpr(s32) = COPY $w1
     %cmp:gpr(s32) = G_ICMP intpred(ne), %reg0(s32), %reg1
-    %cond:gpr(s1) = G_TRUNC %cmp(s32)
     %t:gpr(s32) = G_CONSTANT i32 1
     %f:gpr(s32) = COPY $w2
-    %select:gpr(s32) = G_SELECT %cond(s1), %t, %f
+    %select:gpr(s32) = G_SELECT %cmp, %t, %f
     $w0 = COPY %select(s32)
     RET_ReallyLR implicit $w0
 ...
 ---
 name:            csinv_t_neg_1
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
bb.0:
     ; CHECK-NEXT: %f:gpr32 = COPY $w2
     ; CHECK-NEXT: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr %reg0, %reg1, implicit-def $nzcv
     ; CHECK-NEXT: %select:gpr32 = CSINVWr %f, $wzr, 0, implicit $nzcv
     ; CHECK-NEXT: $w0 = COPY %select
     ; CHECK-NEXT: RET_ReallyLR implicit $w0
     %reg0:gpr(s32) = COPY $w0
     %reg1:gpr(s32) = COPY $w1
     %cmp:gpr(s32) = G_ICMP intpred(ne), %reg0(s32), %reg1
-    %cond:gpr(s1) = G_TRUNC %cmp(s32)
     %t:gpr(s32) = G_CONSTANT i32 -1
     %f:gpr(s32) = COPY $w2
-    %select:gpr(s32) = G_SELECT %cond(s1), %t, %f
+    %select:gpr(s32) = G_SELECT %cmp, %t, %f
     $w0 = COPY %select(s32)
     RET_ReallyLR implicit $w0
 ...
 ---
 name:            csinc_f_1
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
bb.0:
     ; CHECK-NEXT: %t:gpr32 = COPY $w2
     ; CHECK-NEXT: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr %reg0, %reg1, implicit-def $nzcv
     ; CHECK-NEXT: %select:gpr32 = CSINCWr %t, $wzr, 1, implicit $nzcv
     ; CHECK-NEXT: $w0 = COPY %select
     ; CHECK-NEXT: RET_ReallyLR implicit $w0
     %reg0:gpr(s32) = COPY $w0
     %reg1:gpr(s32) = COPY $w1
     %cmp:gpr(s32) = G_ICMP intpred(ne), %reg0(s32), %reg1
-    %cond:gpr(s1) = G_TRUNC %cmp(s32)
     %t:gpr(s32) = COPY $w2
     %f:gpr(s32) = G_CONSTANT i32 1
-    %select:gpr(s32) = G_SELECT %cond(s1), %t, %f
+    %select:gpr(s32) = G_SELECT %cmp, %t, %f
     $w0 = COPY %select(s32)
     RET_ReallyLR implicit $w0
 ...
 ---
 name:            csinc_f_neg_1
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
bb.0:
     ; CHECK-NEXT: %t:gpr32 = COPY $w2
     ; CHECK-NEXT: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr %reg0, %reg1, implicit-def $nzcv
     ; CHECK-NEXT: %select:gpr32 = CSINVWr %t, $wzr, 1, implicit $nzcv
     ; CHECK-NEXT: $w0 = COPY %select
     ; CHECK-NEXT: RET_ReallyLR implicit $w0
     %reg0:gpr(s32) = COPY $w0
     %reg1:gpr(s32) = COPY $w1
     %cmp:gpr(s32) = G_ICMP intpred(ne), %reg0(s32), %reg1
-    %cond:gpr(s1) = G_TRUNC %cmp(s32)
     %t:gpr(s32) = COPY $w2
     %f:gpr(s32) = G_CONSTANT i32 -1
-    %select:gpr(s32) = G_SELECT %cond(s1), %t, %f
+    %select:gpr(s32) = G_SELECT %cmp, %t, %f
     $w0 = COPY %select(s32)
     RET_ReallyLR implicit $w0
 ...
 ---
 name:            csinc_t_1_no_cmp
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 body:             |
   bb.0:
     liveins: $w0, $w1
     ; G_SELECT cc, 1, f -> CSINC f, zreg, inv_cc
 
     ; CHECK-LABEL: name: csinc_t_1_no_cmp
     ; CHECK: liveins: $w0, $w1
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: %reg0:gpr32 = COPY $w0
     ; CHECK-NEXT: %f:gpr32 = COPY $w1
     ; CHECK-NEXT: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri %reg0, 0, implicit-def $nzcv
     ; CHECK-NEXT: %select:gpr32 = CSINCWr %f, $wzr, 0, implicit $nzcv
     ; CHECK-NEXT: $w0 = COPY %select
     ; CHECK-NEXT: RET_ReallyLR implicit $w0
     %reg0:gpr(s32) = COPY $w0
-    %cond:gpr(s1) = G_TRUNC %reg0(s32)
     %t:gpr(s32) = G_CONSTANT i32 1
     %f:gpr(s32) = COPY $w1
-    %select:gpr(s32) = G_SELECT %cond(s1), %t, %f
+    %select:gpr(s32) = G_SELECT %reg0, %t, %f
     $w0 = COPY %select(s32)
     RET_ReallyLR implicit $w0
 
 ...
 ---
 name:            csinc_f_1_no_cmp
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 body:             |
   bb.0:
     liveins: $w0, $w1
     ; G_SELECT cc, t, 1 -> CSINC t, zreg, cc
 
     ; CHECK-LABEL: name: csinc_f_1_no_cmp
     ; CHECK: liveins: $w0, $w1
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: %reg0:gpr32 = COPY $w0
     ; CHECK-NEXT: %t:gpr32 = COPY $w1
     ; CHECK-NEXT: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri %reg0, 0, implicit-def $nzcv
     ; CHECK-NEXT: %select:gpr32 = CSINCWr %t, $wzr, 1, implicit $nzcv
     ; CHECK-NEXT: $w0 = COPY %select
     ; CHECK-NEXT: RET_ReallyLR implicit $w0
     %reg0:gpr(s32) = COPY $w0
-    %cond:gpr(s1) = G_TRUNC %reg0(s32)
     %t:gpr(s32) = COPY $w1
     %f:gpr(s32) = G_CONSTANT i32 1
-    %select:gpr(s32) = G_SELECT %cond(s1), %t, %f
+    %select:gpr(s32) = G_SELECT %reg0, %t, %f
     $w0 = COPY %select(s32)
     RET_ReallyLR implicit $w0
 
 ...
 ---
 name:            csinc_t_1_no_cmp_s64
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 body:             |
   bb.0:
     liveins: $x0, $x1
     ; G_SELECT cc, 1, f -> CSINC f, zreg, inv_cc
 
     ; CHECK-LABEL: name: csinc_t_1_no_cmp_s64
     ; CHECK: liveins: $x0, $x1
     ; CHECK-NEXT: {{  $}}
-    ; CHECK-NEXT: %reg0:gpr64 = COPY $x0
-    ; CHECK-NEXT: %cond:gpr32 = COPY %reg0.sub_32
+    ; CHECK-NEXT: %reg0:gpr64sp = COPY $x0
+    ; CHECK-NEXT: %cond:gpr32common = COPY %reg0.sub_32
     ; CHECK-NEXT: %f:gpr64 = COPY $x1
     ; CHECK-NEXT: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri %cond, 0, implicit-def $nzcv
     ; CHECK-NEXT: %select:gpr64 = CSINCXr %f, $xzr, 0, implicit $nzcv
     ; CHECK-NEXT: $x0 = COPY %select
     ; CHECK-NEXT: RET_ReallyLR implicit $x0
     %reg0:gpr(s64) = COPY $x0
-    %cond:gpr(s1) = G_TRUNC %reg0(s64)
+    %cond:gpr(s32) = G_TRUNC %reg0(s64)
     %t:gpr(s64) = G_CONSTANT i64 1
     %f:gpr(s64) = COPY $x1
-    %select:gpr(s64) = G_SELECT %cond(s1), %t, %f
+    %select:gpr(s64) = G_SELECT %cond, %t, %f
     $x0 = COPY %select(s64)
     RET_ReallyLR implicit $x0
 
 ...
 ---
 name:            csneg_s32
 legalized:       true
 regBankSelected: true
bb.0:
     ; CHECK-NEXT: %reg0:gpr32 = COPY $w0
     ; CHECK-NEXT: %reg1:gpr32 = COPY $w1
     ; CHECK-NEXT: %t:gpr32 = COPY $w2
     ; CHECK-NEXT: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri %reg0, 0, implicit-def $nzcv
     ; CHECK-NEXT: %select:gpr32 = CSNEGWr %t, %reg1, 1, implicit $nzcv
     ; CHECK-NEXT: $w0 = COPY %select
     ; CHECK-NEXT: RET_ReallyLR implicit $w0
     %reg0:gpr(s32) = COPY $w0
-    %cond:gpr(s1) = G_TRUNC %reg0(s32)
     %reg1:gpr(s32) = COPY $w1
     %t:gpr(s32) = COPY $w2
     %zero:gpr(s32) = G_CONSTANT i32 0
     %sub:gpr(s32) = G_SUB %zero(s32), %reg1
-    %select:gpr(s32) = G_SELECT %cond(s1), %t, %sub
+    %select:gpr(s32) = G_SELECT %reg0, %t, %sub
     $w0 = COPY %select(s32)
     RET_ReallyLR implicit $w0
 
 ...
 ---
 name:            csneg_inverted_cc
 legalized:       true
 regBankSelected: true
bb.0:
     ; CHECK-NEXT: %reg0:gpr32 = COPY $w0
     ; CHECK-NEXT: %reg1:gpr32 = COPY $w1
     ; CHECK-NEXT: %f:gpr32 = COPY $w2
     ; CHECK-NEXT: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri %reg0, 0, implicit-def $nzcv
     ; CHECK-NEXT: %select:gpr32 = CSNEGWr %f, %reg1, 0, implicit $nzcv
     ; CHECK-NEXT: $w0 = COPY %select
     ; CHECK-NEXT: RET_ReallyLR implicit $w0
     %reg0:gpr(s32) = COPY $w0
-    %cond:gpr(s1) = G_TRUNC %reg0(s32)
     %reg1:gpr(s32) = COPY $w1
     %f:gpr(s32) = COPY $w2
     %zero:gpr(s32) = G_CONSTANT i32 0
     %sub:gpr(s32) = G_SUB %zero(s32), %reg1
-    %select:gpr(s32) = G_SELECT %cond(s1), %sub, %f
+    %select:gpr(s32) = G_SELECT %reg0, %sub, %f
     $w0 = COPY %select(s32)
     RET_ReallyLR implicit $w0
 
 ...
 ---
 name:            csneg_s64
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 body:             |
   bb.0:
     liveins: $x0, $x1, $x2
     ; G_SELECT cc, true, (G_SUB 0, x) -> CSNEG true, x, cc
 
     ; CHECK-LABEL: name: csneg_s64
     ; CHECK: liveins: $x0, $x1, $x2
     ; CHECK-NEXT: {{  $}}
-    ; CHECK-NEXT: %reg0:gpr64 = COPY $x0
-    ; CHECK-NEXT: %cond:gpr32 = COPY %reg0.sub_32
+    ; CHECK-NEXT: %reg0:gpr64sp = COPY $x0
+    ; CHECK-NEXT: %cond:gpr32common = COPY %reg0.sub_32
     ; CHECK-NEXT: %reg1:gpr64 = COPY $x1
     ; CHECK-NEXT: %t:gpr64 = COPY $x2
     ; CHECK-NEXT: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri %cond, 0, implicit-def $nzcv
     ; CHECK-NEXT: %select:gpr64 = CSNEGXr %t, %reg1, 1, implicit $nzcv
     ; CHECK-NEXT: $x0 = COPY %select
     ; CHECK-NEXT: RET_ReallyLR implicit $x0
     %reg0:gpr(s64) = COPY $x0
-    %cond:gpr(s1) = G_TRUNC %reg0(s64)
+    %cond:gpr(s32) = G_TRUNC %reg0(s64)
     %reg1:gpr(s64) = COPY $x1
     %t:gpr(s64) = COPY $x2
     %zero:gpr(s64) = G_CONSTANT i64 0
     %sub:gpr(s64) = G_SUB %zero(s64), %reg1
-    %select:gpr(s64) = G_SELECT %cond(s1), %t, %sub
+    %select:gpr(s64) = G_SELECT %cond, %t, %sub
     $x0 = COPY %select(s64)
     RET_ReallyLR implicit $x0
 ...
 ---
 name:            csneg_with_true_cst
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
bb.0:
     ; CHECK-NEXT: %reg0:gpr32 = COPY $w0
     ; CHECK-NEXT: %t:gpr32 = MOVi32imm 1
     ; CHECK-NEXT: %reg2:gpr32 = COPY $w2
     ; CHECK-NEXT: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri %reg0, 0, implicit-def $nzcv
     ; CHECK-NEXT: %select:gpr32 = CSNEGWr %t, %reg2, 1, implicit $nzcv
     ; CHECK-NEXT: $w0 = COPY %select
     ; CHECK-NEXT: RET_ReallyLR implicit $w0
     %reg0:gpr(s32) = COPY $w0
-    %cond:gpr(s1) = G_TRUNC %reg0(s32)
     %reg1:gpr(s32) = COPY $w1
     %t:gpr(s32) = G_CONSTANT i32 1
     %zero:gpr(s32) = G_CONSTANT i32 0
     %reg2:gpr(s32) = COPY $w2
     %sub:gpr(s32) = G_SUB %zero(s32), %reg2
-    %select:gpr(s32) = G_SELECT %cond(s1), %t, %sub
+    %select:gpr(s32) = G_SELECT %reg0, %t, %sub
     $w0 = COPY %select(s32)
     RET_ReallyLR implicit $w0
 ...
 ---
 name:            csinv_s32
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
bb.0:
     ; CHECK-NEXT: %reg1:gpr32 = COPY $w1
     ; CHECK-NEXT: %t:gpr32 = COPY $w2
     ; CHECK-NEXT: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri %reg0, 0, implicit-def $nzcv
     ; CHECK-NEXT: %select:gpr32 = CSINVWr %t, %reg1, 1, implicit $nzcv
     ; CHECK-NEXT: $w0 = COPY %select
     ; CHECK-NEXT: RET_ReallyLR implicit $w0
     %reg0:gpr(s32) = COPY $w0
     %reg1:gpr(s32) = COPY $w1
-    %cond:gpr(s1) = G_TRUNC %reg0(s32)
     %t:gpr(s32) = COPY $w2
     %negative_one:gpr(s32) = G_CONSTANT i32 -1
     %xor:gpr(s32) = G_XOR %reg1(s32), %negative_one
-    %select:gpr(s32) = G_SELECT %cond(s1), %t, %xor
+    %select:gpr(s32) = G_SELECT %reg0, %t, %xor
     $w0 = COPY %select(s32)
     RET_ReallyLR implicit $w0
 
 ...
 ---
 name:            csinv_inverted_cc
 legalized:       true
 regBankSelected: true
bb.0:
     ; CHECK-NEXT: %reg1:gpr32 = COPY $w1
     ; CHECK-NEXT: %f:gpr32 = COPY $w2
     ; CHECK-NEXT: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri %reg0, 0, implicit-def $nzcv
     ; CHECK-NEXT: %select:gpr32 = CSINVWr %f, %reg1, 0, implicit $nzcv
     ; CHECK-NEXT: $w0 = COPY %select
     ; CHECK-NEXT: RET_ReallyLR implicit $w0
     %reg0:gpr(s32) = COPY $w0
     %reg1:gpr(s32) = COPY $w1
-    %cond:gpr(s1) = G_TRUNC %reg0(s32)
     %f:gpr(s32) = COPY $w2
     %negative_one:gpr(s32) = G_CONSTANT i32 -1
     %xor:gpr(s32) = G_XOR %reg1(s32), %negative_one
-    %select:gpr(s32) = G_SELECT %cond(s1), %xor, %f
+    %select:gpr(s32) = G_SELECT %reg0, %xor, %f
     $w0 = COPY %select(s32)
     RET_ReallyLR implicit $w0
 
 ...
 ---
 name:            csinv_s64
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 body:             |
   bb.0:
     liveins: $x0, $x1, $x2
     ; G_SELECT cc, true, (G_XOR x, -1) -> CSINV true, x, cc
 
     ; CHECK-LABEL: name: csinv_s64
     ; CHECK: liveins: $x0, $x1, $x2
     ; CHECK-NEXT: {{  $}}
-    ; CHECK-NEXT: %reg0:gpr64 = COPY $x0
+    ; CHECK-NEXT: %reg0:gpr64sp = COPY $x0
     ; CHECK-NEXT: %reg1:gpr64 = COPY $x1
-    ; CHECK-NEXT: %cond:gpr32 = COPY %reg0.sub_32
+    ; CHECK-NEXT: %cond:gpr32common = COPY %reg0.sub_32
     ; CHECK-NEXT: %t:gpr64 = COPY $x2
     ; CHECK-NEXT: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri %cond, 0, implicit-def $nzcv
     ; CHECK-NEXT: %select:gpr64 = CSINVXr %t, %reg1, 1, implicit $nzcv
     ; CHECK-NEXT: $x0 = COPY %select
     ; CHECK-NEXT: RET_ReallyLR implicit $x0
     %reg0:gpr(s64) = COPY $x0
     %reg1:gpr(s64) = COPY $x1
-    %cond:gpr(s1) = G_TRUNC %reg0(s64)
+    %cond:gpr(s32) = G_TRUNC %reg0(s64)
     %t:gpr(s64) = COPY $x2
     %negative_one:gpr(s64) = G_CONSTANT i64 -1
     %xor:gpr(s64) = G_XOR %reg1(s64), %negative_one
-    %select:gpr(s64) = G_SELECT %cond(s1), %t, %xor
+    %select:gpr(s64) = G_SELECT %cond, %t, %xor
     $x0 = COPY %select(s64)
     RET_ReallyLR implicit $x0
 
 ...
 ---
 name:            xor_not_negative_one
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 body:             |
   bb.0:
     liveins: $x0, $x1, $x2
     ; zext(s32 -1) != s64 -1, so we can't fold it away.
 
     ; CHECK-LABEL: name: xor_not_negative_one
     ; CHECK: liveins: $x0, $x1, $x2
     ; CHECK-NEXT: {{  $}}
-    ; CHECK-NEXT: %reg0:gpr64 = COPY $x0
+    ; CHECK-NEXT: %reg0:gpr64sp = COPY $x0
     ; CHECK-NEXT: %reg1:gpr64 = COPY $x1
-    ; CHECK-NEXT: %cond:gpr32 = COPY %reg0.sub_32
+    ; CHECK-NEXT: %cond:gpr32common = COPY %reg0.sub_32
     ; CHECK-NEXT: %t:gpr64 = COPY $x2
     ; CHECK-NEXT: %negative_one:gpr32 = MOVi32imm -1
     ; CHECK-NEXT: %zext:gpr64 = SUBREG_TO_REG 0, %negative_one, %subreg.sub_32
     ; CHECK-NEXT: %xor:gpr64 = EORXrr %reg1, %zext
     ; CHECK-NEXT: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri %cond, 0, implicit-def $nzcv
     ; CHECK-NEXT: %select:gpr64 = CSELXr %t, %xor, 1, implicit $nzcv
     ; CHECK-NEXT: $x0 = COPY %select
     ; CHECK-NEXT: RET_ReallyLR implicit $x0
     %reg0:gpr(s64) = COPY $x0
     %reg1:gpr(s64) = COPY $x1
-    %cond:gpr(s1) = G_TRUNC %reg0(s64)
+    %cond:gpr(s32) = G_TRUNC %reg0(s64)
     %t:gpr(s64) = COPY $x2
     %negative_one:gpr(s32) = G_CONSTANT i32 -1
     %zext:gpr(s64) = G_ZEXT %negative_one(s32)
     %xor:gpr(s64) = G_XOR %reg1(s64), %zext
-    %select:gpr(s64) = G_SELECT %cond(s1), %t, %xor
+    %select:gpr(s64) = G_SELECT %cond(s32), %t, %xor
     $x0 = COPY %select(s64)
     RET_ReallyLR implicit $x0
 
 ...
 ---
 name:            csinc_s32
 legalized:       true
 regBankSelected: true
bb.0:
     ; CHECK-NEXT: %reg1:gpr32 = COPY $w1
     ; CHECK-NEXT: %t:gpr32 = COPY $w2
     ; CHECK-NEXT: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri %reg0, 0, implicit-def $nzcv
     ; CHECK-NEXT: %select:gpr32 = CSINCWr %t, %reg1, 1, implicit $nzcv
     ; CHECK-NEXT: $w0 = COPY %select
     ; CHECK-NEXT: RET_ReallyLR implicit $w0
     %reg0:gpr(s32) = COPY $w0
     %reg1:gpr(s32) = COPY $w1
-    %cond:gpr(s1) = G_TRUNC %reg0(s32)
     %t:gpr(s32) = COPY $w2
     %one:gpr(s32) = G_CONSTANT i32 1
     %add:gpr(s32) = G_ADD %reg1(s32), %one
-    %select:gpr(s32) = G_SELECT %cond(s1), %t, %add
+    %select:gpr(s32) = G_SELECT %reg0, %t, %add
     $w0 = COPY %select(s32)
     RET_ReallyLR implicit $w0
 
 ...
 ---
 name:            csinc_s32_inverted_cc
 legalized:       true
 regBankSelected: true
bb.0:
     ; CHECK-NEXT: %reg1:gpr32 = COPY $w1
     ; CHECK-NEXT: %f:gpr32 = COPY $w2
     ; CHECK-NEXT: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri %reg0, 0, implicit-def $nzcv
     ; CHECK-NEXT: %select:gpr32 = CSINCWr %f, %reg1, 0, implicit $nzcv
     ; CHECK-NEXT: $w0 = COPY %select
     ; CHECK-NEXT: RET_ReallyLR implicit $w0
     %reg0:gpr(s32) = COPY $w0
     %reg1:gpr(s32) = COPY $w1
-    %cond:gpr(s1) = G_TRUNC %reg0(s32)
     %f:gpr(s32) = COPY $w2
     %one:gpr(s32) = G_CONSTANT i32 1
     %add:gpr(s32) = G_ADD %reg1(s32), %one
-    %select:gpr(s32) = G_SELECT %cond(s1), %add, %f
+    %select:gpr(s32) = G_SELECT %reg0, %add, %f
     $w0 = COPY %select(s32)
     RET_ReallyLR implicit $w0
 
 ...
 ---
 name:            csinc_ptr_add
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 body:             |
   bb.0:
     liveins: $x0, $x1, $x2
     ; G_SELECT cc, %true, (G_PTR_ADD %x, 1) -> CSINC %true, %x, cc
 
     ; CHECK-LABEL: name: csinc_ptr_add
     ; CHECK: liveins: $x0, $x1, $x2
     ; CHECK-NEXT: {{  $}}
-    ; CHECK-NEXT: %reg0:gpr64 = COPY $x0
+    ; CHECK-NEXT: %reg0:gpr64sp = COPY $x0
     ; CHECK-NEXT: %reg1:gpr64 = COPY $x1
-    ; CHECK-NEXT: %cond:gpr32 = COPY %reg0.sub_32
+    ; CHECK-NEXT: %cond:gpr32common = COPY %reg0.sub_32
     ; CHECK-NEXT: %t:gpr64 = COPY $x2
     ; CHECK-NEXT: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri %cond, 0, implicit-def $nzcv
     ; CHECK-NEXT: %select:gpr64 = CSINCXr %t, %reg1, 1, implicit $nzcv
     ; CHECK-NEXT: $x0 = COPY %select
     ; CHECK-NEXT: RET_ReallyLR implicit $x0
     %reg0:gpr(s64) = COPY $x0
     %reg1:gpr(p0) = COPY $x1
-    %cond:gpr(s1) = G_TRUNC %reg0(s64)
+    %cond:gpr(s32) = G_TRUNC %reg0(s64)
     %t:gpr(p0) = COPY $x2
     %one:gpr(s64) = G_CONSTANT i64 1
     %ptr_add:gpr(p0) = G_PTR_ADD %reg1(p0), %one
-    %select:gpr(p0) = G_SELECT %cond(s1), %t, %ptr_add
+    %select:gpr(p0) = G_SELECT %cond(s32), %t, %ptr_add
     $x0 = COPY %select(p0)
     RET_ReallyLR implicit $x0
 
 ...
 ---
 name:            binop_dont_optimize_twice
 legalized:       true
 regBankSelected: true
bb.0:
     ; CHECK-NEXT: %xor:gpr32 = ORNWrr $wzr, %reg1
     ; CHECK-NEXT: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri %reg0, 0, implicit-def $nzcv
     ; CHECK-NEXT: %select:gpr32 = CSNEGWr %xor, %reg2, 1, implicit $nzcv
     ; CHECK-NEXT: $w0 = COPY %select
     ; CHECK-NEXT: RET_ReallyLR implicit $w0
     %reg0:gpr(s32) = COPY $w0
     %reg1:gpr(s32) = COPY $w1
     %reg2:gpr(s32) = COPY $w2
-    %cond:gpr(s1) = G_TRUNC %reg0(s32)
     %f:gpr(s32) = COPY $w2
     %negative_one:gpr(s32) = G_CONSTANT i32 -1
     %xor:gpr(s32) = G_XOR %reg1(s32), %negative_one
     %zero:gpr(s32) = G_CONSTANT i32 0
     %sub:gpr(s32) = G_SUB %zero(s32), %reg2
-    %select:gpr(s32) = G_SELECT %cond(s1), %xor, %sub
+    %select:gpr(s32) = G_SELECT %reg0, %xor, %sub
     $w0 = COPY %select(s32)
     RET_ReallyLR implicit $w0

llvm/test/CodeGen/AArch64/GlobalISel/select-ssubo.mir

bb.1.entry:
 
     ; CHECK-LABEL: name: ssubo_s32
     ; CHECK: liveins: $w0, $w1, $x2
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
     ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
     ; CHECK-NEXT: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr [[COPY]], [[COPY1]], implicit-def $nzcv
     ; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 7, implicit $nzcv
-    ; CHECK-NEXT: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[CSINCWr]], 0, 0
-    ; CHECK-NEXT: [[UBFMWri1:%[0-9]+]]:gpr32 = UBFMWri [[UBFMWri]], 0, 7
-    ; CHECK-NEXT: $w0 = COPY [[UBFMWri1]]
-    ; CHECK-NEXT: RET_ReallyLR implicit $w0
+    ; CHECK-NEXT: $w0 = COPY [[SUBSWrr]]
+    ; CHECK-NEXT: $w1 = COPY [[CSINCWr]]
+    ; CHECK-NEXT: RET_ReallyLR implicit $w0, implicit $w1
     %0:gpr(s32) = COPY $w0
     %1:gpr(s32) = COPY $w1
-    %3:gpr(s32), %4:gpr(s1) = G_SSUBO %0, %1
-    %5:gpr(s8) = G_ZEXT %4(s1)
-    %6:gpr(s32) = G_ZEXT %5(s8)
-    $w0 = COPY %6(s32)
-    RET_ReallyLR implicit $w0
+    %3:gpr(s32), %4:gpr(s32) = G_SSUBO %0, %1
+    $w0 = COPY %3
+    $w1 = COPY %4
+    RET_ReallyLR implicit $w0, implicit $w1
 
 ...
 ---
 name:            ssubo_s64
 alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 body:             |
   bb.1.entry:
     liveins: $x0, $x1, $x2
 
     ; CHECK-LABEL: name: ssubo_s64
     ; CHECK: liveins: $x0, $x1, $x2
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
     ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
     ; CHECK-NEXT: [[SUBSXrr:%[0-9]+]]:gpr64 = SUBSXrr [[COPY]], [[COPY1]], implicit-def $nzcv
     ; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 7, implicit $nzcv
-    ; CHECK-NEXT: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[CSINCWr]], 0, 0
-    ; CHECK-NEXT: [[UBFMWri1:%[0-9]+]]:gpr32 = UBFMWri [[UBFMWri]], 0, 7
-    ; CHECK-NEXT: $w0 = COPY [[UBFMWri1]]
-    ; CHECK-NEXT: RET_ReallyLR implicit $w0
+    ; CHECK-NEXT: $x0 = COPY [[SUBSXrr]]
+    ; CHECK-NEXT: $w1 = COPY [[CSINCWr]]
+    ; CHECK-NEXT: RET_ReallyLR implicit $x0, implicit $w1
     %0:gpr(s64) = COPY $x0
     %1:gpr(s64) = COPY $x1
-    %3:gpr(s64), %4:gpr(s1) = G_SSUBO %0, %1
-    %5:gpr(s8) = G_ZEXT %4(s1)
-    %6:gpr(s32) = G_ZEXT %5(s8)
-    $w0 = COPY %6(s32)
-    RET_ReallyLR implicit $w0
+    %3:gpr(s64), %4:gpr(s32) = G_SSUBO %0, %1
+    $x0 = COPY %3
+    $w1 = COPY %4
+    RET_ReallyLR implicit $x0, implicit $w1
 
 ...
 ---
 name:            ssubo_s32_imm
 alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 body:             |
   bb.1.entry:
     liveins: $w0, $w1, $x2
     ; Check that we get ADDSWri when we can fold in a constant.
     ;
     ; CHECK-LABEL: name: ssubo_s32_imm
     ; CHECK: liveins: $w0, $w1, $x2
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: %copy:gpr32sp = COPY $w0
     ; CHECK-NEXT: %add:gpr32 = SUBSWri %copy, 16, 0, implicit-def $nzcv
     ; CHECK-NEXT: %overflow:gpr32 = CSINCWr $wzr, $wzr, 7, implicit $nzcv
     ; CHECK-NEXT: $w0 = COPY %add
     ; CHECK-NEXT: RET_ReallyLR implicit $w0
     %copy:gpr(s32) = COPY $w0
     %constant:gpr(s32) = G_CONSTANT i32 16
-    %add:gpr(s32), %overflow:gpr(s1) = G_SSUBO %copy, %constant
+    %add:gpr(s32), %overflow:gpr(s32) = G_SSUBO %copy, %constant
     $w0 = COPY %add(s32)
     RET_ReallyLR implicit $w0
 
 ...
 ---
 name:            ssubo_s32_shifted
 alignment:       4
 legalized:       true
bb.1.entry:
     ; CHECK-NEXT: %add:gpr32 = SUBSWrs %copy1, %copy2, 16, implicit-def $nzcv
     ; CHECK-NEXT: %overflow:gpr32 = CSINCWr $wzr, $wzr, 7, implicit $nzcv
     ; CHECK-NEXT: $w0 = COPY %add
     ; CHECK-NEXT: RET_ReallyLR implicit $w0
     %copy1:gpr(s32) = COPY $w0
     %copy2:gpr(s32) = COPY $w1
     %constant:gpr(s32) = G_CONSTANT i32 16
     %shift:gpr(s32) = G_SHL %copy2(s32), %constant(s32)
-    %add:gpr(s32), %overflow:gpr(s1) = G_SSUBO %copy1, %shift
+    %add:gpr(s32), %overflow:gpr(s32) = G_SSUBO %copy1, %shift
     $w0 = COPY %add(s32)
     RET_ReallyLR implicit $w0
 
 ...
 ---
 name:            ssubo_s32_neg_imm
 alignment:       4
 legalized:       true
bb.1.entry:
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: %copy:gpr32sp = COPY $w0
     ; CHECK-NEXT: %add:gpr32 = ADDSWri %copy, 16, 0, implicit-def $nzcv
     ; CHECK-NEXT: %overflow:gpr32 = CSINCWr $wzr, $wzr, 7, implicit $nzcv
     ; CHECK-NEXT: $w0 = COPY %add
     ; CHECK-NEXT: RET_ReallyLR implicit $w0
     %copy:gpr(s32) = COPY $w0
     %constant:gpr(s32) = G_CONSTANT i32 -16
-    %add:gpr(s32), %overflow:gpr(s1) = G_SSUBO %copy, %constant
+    %add:gpr(s32), %overflow:gpr(s32) = G_SSUBO %copy, %constant
     $w0 = COPY %add(s32)
     RET_ReallyLR implicit $w0
 
 ...
 ---
 name:            ssubo_arith_extended
 alignment:       4
 legalized:       true
bb.1.entry:
     ; CHECK-NEXT: %flags:gpr32 = CSINCWr $wzr, $wzr, 7, implicit $nzcv
     ; CHECK-NEXT: $x0 = COPY %add
     ; CHECK-NEXT: RET_ReallyLR implicit $x0
     %reg0:gpr(s64) = COPY $x0
     %reg1:gpr(s32) = COPY $w0
     %ext:gpr(s64) = G_ZEXT %reg1(s32)
     %cst:gpr(s64) = G_CONSTANT i64 2
     %shift:gpr(s64) = G_SHL %ext, %cst(s64)
-    %add:gpr(s64), %flags:gpr(s1) = G_SSUBO %reg0, %shift
+    %add:gpr(s64), %flags:gpr(s32) = G_SSUBO %reg0, %shift
     $x0 = COPY %add(s64)
     RET_ReallyLR implicit $x0

llvm/test/CodeGen/AArch64/GlobalISel/select-static.mir

 # CHECK:    %5:gpr32 = CSINCWr $wzr, $wzr, 0, implicit $nzcv
 
 body:             |
   bb.0:
     liveins: $w0, $x0
 
     %0(s32) = COPY $w0
     %1(s32) = G_ICMP intpred(eq), %0, %0
-    %6(s1) = G_TRUNC %1(s32)
-    %9(s32) = G_ANYEXT %6
-    $w0 = COPY %9(s32)
+    $w0 = COPY %1
 
     %2(s64) = COPY $x0
     %3(s32) = G_ICMP intpred(uge), %2, %2
-    %7(s1) = G_TRUNC %3(s32)
-    %10(s32) = G_ANYEXT %7
-    $w0 = COPY %10(s32)
+    $w0 = COPY %3
 
     %4(p0) = COPY $x0
     %5(s32) = G_ICMP intpred(ne), %4, %4
-    %8(s1) = G_TRUNC %5(s32)
-    %11(s32) = G_ANYEXT %8
-    $w0 = COPY %11(s32)
+    $w0 = COPY %5
 ...
 
 ---
 # CHECK-LABEL: name: fcmp
 name:            fcmp
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
 # CHECK-NEXT:  - { id: 0, class: fpr32, preferred-register: '' }
 # CHECK-NEXT:  - { id: 1, class: gpr32, preferred-register: '' }
 # CHECK-NEXT:  - { id: 2, class: fpr64, preferred-register: '' }
 # CHECK-NEXT:  - { id: 3, class: gpr32, preferred-register: '' }
 # CHECK-NEXT:  - { id: 4, class: gpr32, preferred-register: '' }
 # CHECK-NEXT:  - { id: 5, class: gpr32, preferred-register: '' }
 registers:
   - { id: 0, class: fpr }
   - { id: 1, class: gpr }
   - { id: 2, class: fpr }
   - { id: 3, class: gpr }
-  - { id: 4, class: gpr }
-  - { id: 5, class: gpr }
-  - { id: 6, class: gpr }
-  - { id: 7, class: gpr }
 
 # CHECK:  body:
 # CHECK:    FCMPSrr %0, %0, implicit-def $nzcv
 # CHECK:    [[TST_MI:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 5, implicit $nzcv
 # CHECK:    [[TST_GT:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 13, implicit $nzcv
 # CHECK:    %1:gpr32 = ORRWrr [[TST_MI]], [[TST_GT]]
 
 # CHECK:    FCMPDrr %2, %2, implicit-def $nzcv
 # CHECK:    %3:gpr32 = CSINCWr $wzr, $wzr, 4, implicit $nzcv
 
 body:             |
   bb.0:
     liveins: $w0, $x0
 
     %0(s32) = COPY $s0
     %1(s32) = G_FCMP floatpred(one), %0, %0
-    %4(s1) = G_TRUNC %1(s32)
-    %6(s32) = G_ANYEXT %4
-    $w0 = COPY %6(s32)
+    $w0 = COPY %1
 
     %2(s64) = COPY $d0
     %3(s32) = G_FCMP floatpred(uge), %2, %2
-    %5(s1) = G_TRUNC %3(s32)
-    %7(s32) = G_ANYEXT %5
-    $w0 = COPY %7(s32)
+    $w0 = COPY %3
 
 ...
 
 ---
 # CHECK-LABEL: name: phi
 name:            phi
 legalized:       true
 regBankSelected: true

 # CHECK:      %2:fpr32 = PHI %0, %bb.0, %2, %bb.1
 
 body:             |
   bb.0:
     liveins: $s0, $w0
     successors: %bb.1
     %0(s32) = COPY $s0
     %3:gpr(s32) = COPY $w0
-    %1(s1) = G_TRUNC %3
 
   bb.1:
     successors: %bb.1, %bb.2
     %2(s32) = PHI %0, %bb.0, %2, %bb.1
-    G_BRCOND %1, %bb.1
+    G_BRCOND %3, %bb.1
 
   bb.2:
     $s0 = COPY %2
     RET_ReallyLR implicit $s0
 ...
 
 ---
 # CHECK-LABEL: name: select
registers:
   - { id: 4, class: gpr }
   - { id: 5, class: gpr }
   - { id: 6, class: gpr }
   - { id: 7, class: gpr }
   - { id: 8, class: gpr }
   - { id: 9, class: gpr }
 
 # CHECK:  body:
-# CHECK:      ANDSWri %10, 0, implicit-def $nzcv
+# CHECK:      ANDSWri %0, 0, implicit-def $nzcv
 # CHECK:      %3:gpr32 = CSELWr %1, %2, 1, implicit $nzcv
-# CHECK:      ANDSWri %10, 0, implicit-def $nzcv
+# CHECK:      ANDSWri %0, 0, implicit-def $nzcv
 # CHECK:      %6:gpr64 = CSELXr %4, %5, 1, implicit $nzcv
-# CHECK:      ANDSWri %10, 0, implicit-def $nzcv
+# CHECK:      ANDSWri %0, 0, implicit-def $nzcv
 # CHECK:      %9:gpr64 = CSELXr %7, %8, 1, implicit $nzcv
 body:             |
   bb.0:
     liveins: $w0, $w1, $w2
-    %10:gpr(s32) = COPY $w0
-    %0(s1) = G_TRUNC %10
+    %0:gpr(s32) = COPY $w0
 
     %1(s32) = COPY $w1
     %2(s32) = COPY $w2
     %3(s32) = G_SELECT %0, %1, %2
     $w0 = COPY %3(s32)
 
     %4(s64) = COPY $x0
     %5(s64) = COPY $x1
     %6(s64) = G_SELECT %0, %4, %5
     $x0 = COPY %6(s64)
 
     %7(p0) = COPY $x0
     %8(p0) = COPY $x1
     %9(p0) = G_SELECT %0, %7, %8
     $x0 = COPY %9(p0)
 ...

llvm/test/CodeGen/AArch64/GlobalISel/select-trunc.mir

 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -global-isel-abort=1 -verify-machineinstrs %s -o - | FileCheck %s
 
 --- |
   target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
 
   define void @trunc_s32_s64() { ret void }
   define void @trunc_s8_s64() { ret void }
-  define void @trunc_s1_s32() { ret void }
+  define void @trunc_s8_s32() { ret void }
   define void @trunc_s64_s128() { ret void }
   define void @trunc_s32_s128() { ret void }
 ...
 
 ---
 name:            trunc_s32_s64
 legalized:       true
 regBankSelected: true
bb.0:
     ; CHECK-NEXT: $w0 = COPY [[COPY2]]
     %0(s64) = COPY $x0
     %1(s8) = G_TRUNC %0
     %2:gpr(s32) = G_ANYEXT %1
     $w0 = COPY %2(s32)
 ...
 
 ---
-name:            trunc_s1_s32
+name:            trunc_s8_s32
 legalized:       true
 regBankSelected: true
 
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
 
 body:             |
   bb.0:
     liveins: $w0
 
-    ; CHECK-LABEL: name: trunc_s1_s32
+    ; CHECK-LABEL: name: trunc_s8_s32
     ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
     ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32all = COPY [[COPY]]
     ; CHECK-NEXT: $w0 = COPY [[COPY1]]
     %0(s32) = COPY $w0
-    %1(s1) = G_TRUNC %0
+    %1(s8) = G_TRUNC %0
     %2:gpr(s32) = G_ANYEXT %1
     $w0 = COPY %2(s32)
 ...
 
 ---
 name:            trunc_s64_s128
 legalized:       true
 regBankSelected: true

llvm/test/CodeGen/AArch64/GlobalISel/select-truncstore-atomic.mir

body:             |
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT: bb.2:
   ; CHECK-NEXT:   RET_ReallyLR
   bb.1:
     liveins: $w1, $x0
 
     %0:gpr(p0) = COPY $x0
     %3:gpr(s32) = COPY $w1
-    %2:gpr(s8) = G_TRUNC %3(s32)
-    %4:gpr(s8) = G_ASSERT_ZEXT %2, 1
-    %1:gpr(s1) = G_TRUNC %4(s8)
-    G_BRCOND %1(s1), %bb.3
+    G_BRCOND %3, %bb.3
     G_BR %bb.2
 
   bb.2:
     %8:gpr(s64) = G_CONSTANT i64 4
     G_STORE %8(s64), %0(p0) :: (store release (s32))
 
   bb.3:
     RET_ReallyLR
body:             |
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT: bb.2:
   ; CHECK-NEXT:   RET_ReallyLR
   bb.1:
     liveins: $w1, $x0
 
     %0:gpr(p0) = COPY $x0
     %3:gpr(s32) = COPY $w1
-    %2:gpr(s8) = G_TRUNC %3(s32)
-    %4:gpr(s8) = G_ASSERT_ZEXT %2, 1
-    %1:gpr(s1) = G_TRUNC %4(s8)
-    G_BRCOND %1(s1), %bb.3
+    G_BRCOND %3, %bb.3
     G_BR %bb.2
 
   bb.2:
     %8:gpr(s64) = G_CONSTANT i64 4
     G_STORE %8(s64), %0(p0) :: (store release (s16))
 
   bb.3:
     RET_ReallyLR
body:             |
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT: bb.2:
   ; CHECK-NEXT:   RET_ReallyLR
   bb.1:
     liveins: $w1, $x0
 
     %0:gpr(p0) = COPY $x0
     %3:gpr(s32) = COPY $w1
-    %2:gpr(s8) = G_TRUNC %3(s32)
-    %4:gpr(s8) = G_ASSERT_ZEXT %2, 1
-    %1:gpr(s1) = G_TRUNC %4(s8)
-    G_BRCOND %1(s1), %bb.3
+    G_BRCOND %3, %bb.3
     G_BR %bb.2
 
   bb.2:
     %8:gpr(s64) = G_CONSTANT i64 4
     G_STORE %8(s64), %0(p0) :: (store release (s8))
 
   bb.3:
     RET_ReallyLR
 
 ...

llvm/test/CodeGen/AArch64/GlobalISel/select-uaddo.mir

bb.1.entry:
 
     ; CHECK-LABEL: name: uaddo_s32
     ; CHECK: liveins: $w0, $w1, $x2
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
     ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
     ; CHECK-NEXT: [[ADDSWrr:%[0-9]+]]:gpr32 = ADDSWrr [[COPY]], [[COPY1]], implicit-def $nzcv
     ; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 3, implicit $nzcv
-    ; CHECK-NEXT: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[CSINCWr]], 0, 0
-    ; CHECK-NEXT: [[UBFMWri1:%[0-9]+]]:gpr32 = UBFMWri [[UBFMWri]], 0, 7
-    ; CHECK-NEXT: $w0 = COPY [[UBFMWri1]]
-    ; CHECK-NEXT: RET_ReallyLR implicit $w0
+    ; CHECK-NEXT: $w0 = COPY [[ADDSWrr]]
+    ; CHECK-NEXT: $w1 = COPY [[CSINCWr]]
+    ; CHECK-NEXT: RET_ReallyLR implicit $w0, implicit $w1
     %0:gpr(s32) = COPY $w0
     %1:gpr(s32) = COPY $w1
-    %3:gpr(s32), %4:gpr(s1) = G_UADDO %0, %1
-    %5:gpr(s8) = G_ZEXT %4(s1)
-    %6:gpr(s32) = G_ZEXT %5(s8)
-    $w0 = COPY %6(s32)
-    RET_ReallyLR implicit $w0
+    %3:gpr(s32), %4:gpr(s32) = G_UADDO %0, %1
+    $w0 = COPY %3
+    $w1 = COPY %4
+    RET_ReallyLR implicit $w0, implicit $w1
 
 ...
 ---
 name:            uaddo_s64
 alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 body:             |
   bb.1.entry:
     liveins: $x0, $x1, $x2
 
     ; CHECK-LABEL: name: uaddo_s64
     ; CHECK: liveins: $x0, $x1, $x2
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
     ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
     ; CHECK-NEXT: [[ADDSXrr:%[0-9]+]]:gpr64 = ADDSXrr [[COPY]], [[COPY1]], implicit-def $nzcv
     ; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 3, implicit $nzcv
-    ; CHECK-NEXT: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[CSINCWr]], 0, 0
-    ; CHECK-NEXT: [[UBFMWri1:%[0-9]+]]:gpr32 = UBFMWri [[UBFMWri]], 0, 7
-    ; CHECK-NEXT: $w0 = COPY [[UBFMWri1]]
-    ; CHECK-NEXT: RET_ReallyLR implicit $w0
+    ; CHECK-NEXT: $x0 = COPY [[ADDSXrr]]
+    ; CHECK-NEXT: $w1 = COPY [[CSINCWr]]
+    ; CHECK-NEXT: RET_ReallyLR implicit $x0, implicit $w1
     %0:gpr(s64) = COPY $x0
     %1:gpr(s64) = COPY $x1
-    %3:gpr(s64), %4:gpr(s1) = G_UADDO %0, %1
-    %5:gpr(s8) = G_ZEXT %4(s1)
-    %6:gpr(s32) = G_ZEXT %5(s8)
-    $w0 = COPY %6(s32)
-    RET_ReallyLR implicit $w0
+    %3:gpr(s64), %4:gpr(s32) = G_UADDO %0, %1
+    $x0 = COPY %3
+    $w1 = COPY %4
+    RET_ReallyLR implicit $x0, implicit $w1
 
 ...
 ---
 name:            uaddo_s32_imm
 alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 body:             |
   bb.1.entry:
     liveins: $w0, $w1, $x2
     ; Check that we get ADDSWri when we can fold in a constant.
     ;
     ; CHECK-LABEL: name: uaddo_s32_imm
     ; CHECK: liveins: $w0, $w1, $x2
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: %copy:gpr32sp = COPY $w0
     ; CHECK-NEXT: %add:gpr32 = ADDSWri %copy, 16, 0, implicit-def $nzcv
     ; CHECK-NEXT: %overflow:gpr32 = CSINCWr $wzr, $wzr, 3, implicit $nzcv
     ; CHECK-NEXT: $w0 = COPY %add
     ; CHECK-NEXT: RET_ReallyLR implicit $w0
     %copy:gpr(s32) = COPY $w0
     %constant:gpr(s32) = G_CONSTANT i32 16
-    %add:gpr(s32), %overflow:gpr(s1) = G_UADDO %copy, %constant
+    %add:gpr(s32), %overflow:gpr(s32) = G_UADDO %copy, %constant
     $w0 = COPY %add(s32)
     RET_ReallyLR implicit $w0
 
 ...
 ---
 name:            uaddo_s32_shifted
 alignment:       4
 legalized:       true
bb.1.entry:
     ; CHECK-NEXT: %add:gpr32 = ADDSWrs %copy1, %copy2, 16, implicit-def $nzcv
     ; CHECK-NEXT: %overflow:gpr32 = CSINCWr $wzr, $wzr, 3, implicit $nzcv
     ; CHECK-NEXT: $w0 = COPY %add
     ; CHECK-NEXT: RET_ReallyLR implicit $w0
     %copy1:gpr(s32) = COPY $w0
     %copy2:gpr(s32) = COPY $w1
     %constant:gpr(s32) = G_CONSTANT i32 16
     %shift:gpr(s32) = G_SHL %copy2(s32), %constant(s32)
-    %add:gpr(s32), %overflow:gpr(s1) = G_UADDO %copy1, %shift
+    %add:gpr(s32), %overflow:gpr(s32) = G_UADDO %copy1, %shift
     $w0 = COPY %add(s32)
     RET_ReallyLR implicit $w0
 
 ...
 ---
 name:            uaddo_s32_neg_imm
 alignment:       4
 legalized:       true
bb.1.entry:
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: %copy:gpr32sp = COPY $w0
     ; CHECK-NEXT: %add:gpr32 = SUBSWri %copy, 16, 0, implicit-def $nzcv
     ; CHECK-NEXT: %overflow:gpr32 = CSINCWr $wzr, $wzr, 3, implicit $nzcv
     ; CHECK-NEXT: $w0 = COPY %add
     ; CHECK-NEXT: RET_ReallyLR implicit $w0
     %copy:gpr(s32) = COPY $w0
     %constant:gpr(s32) = G_CONSTANT i32 -16
-    %add:gpr(s32), %overflow:gpr(s1) = G_UADDO %copy, %constant
+    %add:gpr(s32), %overflow:gpr(s32) = G_UADDO %copy, %constant
     $w0 = COPY %add(s32)
     RET_ReallyLR implicit $w0
 
 ...
 ---
 name:            uaddo_arith_extended
 alignment:       4
 legalized:       true
bb.1.entry:
     ; CHECK-NEXT: %flags:gpr32 = CSINCWr $wzr, $wzr, 3, implicit $nzcv
     ; CHECK-NEXT: $x0 = COPY %add
     ; CHECK-NEXT: RET_ReallyLR implicit $x0
     %reg0:gpr(s64) = COPY $x0
     %reg1:gpr(s32) = COPY $w0
     %ext:gpr(s64) = G_ZEXT %reg1(s32)
     %cst:gpr(s64) = G_CONSTANT i64 2
     %shift:gpr(s64) = G_SHL %ext, %cst(s64)
-    %add:gpr(s64), %flags:gpr(s1) = G_UADDO %reg0, %shift
+    %add:gpr(s64), %flags:gpr(s32) = G_UADDO %reg0, %shift
     $x0 = COPY %add(s64)
     RET_ReallyLR implicit $x0

llvm/test/CodeGen/AArch64/GlobalISel/select-usubo.mir

bb.1.entry:
 
     ; CHECK-LABEL: name: usubo_s32
     ; CHECK: liveins: $w0, $w1, $x2
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
     ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
     ; CHECK-NEXT: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr [[COPY]], [[COPY1]], implicit-def $nzcv
     ; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 2, implicit $nzcv
-    ; CHECK-NEXT: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[CSINCWr]], 0, 0
-    ; CHECK-NEXT: [[UBFMWri1:%[0-9]+]]:gpr32 = UBFMWri [[UBFMWri]], 0, 7
-    ; CHECK-NEXT: $w0 = COPY [[UBFMWri1]]
+    ; CHECK-NEXT: $w0 = COPY [[CSINCWr]]
     ; CHECK-NEXT: RET_ReallyLR implicit $w0
     %0:gpr(s32) = COPY $w0
     %1:gpr(s32) = COPY $w1
-    %3:gpr(s32), %4:gpr(s1) = G_USUBO %0, %1
-    %5:gpr(s8) = G_ZEXT %4(s1)
-    %6:gpr(s32) = G_ZEXT %5(s8)
-    $w0 = COPY %6(s32)
+    %3:gpr(s32), %4:gpr(s32) = G_USUBO %0, %1
+    $w0 = COPY %4(s32)
     RET_ReallyLR implicit $w0
 
 ...
 ---
 name:            usubo_s64
 alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 body:             |
   bb.1.entry:
     liveins: $x0, $x1, $x2
 
     ; CHECK-LABEL: name: usubo_s64
     ; CHECK: liveins: $x0, $x1, $x2
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
     ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
     ; CHECK-NEXT: [[SUBSXrr:%[0-9]+]]:gpr64 = SUBSXrr [[COPY]], [[COPY1]], implicit-def $nzcv
     ; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 2, implicit $nzcv
-    ; CHECK-NEXT: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[CSINCWr]], 0, 0
-    ; CHECK-NEXT: [[UBFMWri1:%[0-9]+]]:gpr32 = UBFMWri [[UBFMWri]], 0, 7
-    ; CHECK-NEXT: $w0 = COPY [[UBFMWri1]]
+    ; CHECK-NEXT: $w0 = COPY [[CSINCWr]]
     ; CHECK-NEXT: RET_ReallyLR implicit $w0
     %0:gpr(s64) = COPY $x0
     %1:gpr(s64) = COPY $x1
-    %3:gpr(s64), %4:gpr(s1) = G_USUBO %0, %1
-    %5:gpr(s8) = G_ZEXT %4(s1)
-    %6:gpr(s32) = G_ZEXT %5(s8)
-    $w0 = COPY %6(s32)
+    %3:gpr(s64), %4:gpr(s32) = G_USUBO %0, %1
+    $w0 = COPY %4
     RET_ReallyLR implicit $w0
 
 ...
 ---
 name:            usubo_s32_imm
 alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 body:             |
   bb.1.entry:
     liveins: $w0, $w1, $x2
     ; Check that we get ADDSWri when we can fold in a constant.
     ;
     ; CHECK-LABEL: name: usubo_s32_imm
     ; CHECK: liveins: $w0, $w1, $x2
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: %copy:gpr32sp = COPY $w0
     ; CHECK-NEXT: %add:gpr32 = SUBSWri %copy, 16, 0, implicit-def $nzcv
     ; CHECK-NEXT: %overflow:gpr32 = CSINCWr $wzr, $wzr, 2, implicit $nzcv
     ; CHECK-NEXT: $w0 = COPY %add
-    ; CHECK-NEXT: RET_ReallyLR implicit $w0
+    ; CHECK-NEXT: $w1 = COPY %overflow
+    ; CHECK-NEXT: RET_ReallyLR implicit $w0, implicit $w1
     %copy:gpr(s32) = COPY $w0
     %constant:gpr(s32) = G_CONSTANT i32 16
-    %add:gpr(s32), %overflow:gpr(s1) = G_USUBO %copy, %constant
-    $w0 = COPY %add(s32)
-    RET_ReallyLR implicit $w0
+    %add:gpr(s32), %overflow:gpr(s32) = G_USUBO %copy, %constant
+    $w0 = COPY %add
+    $w1 = COPY %overflow
+    RET_ReallyLR implicit $w0, implicit $w1
 
 ...
 ---
 name:            usubo_s32_shifted
 alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 body:             |
   bb.1.entry:
     liveins: $w0, $w1, $x2
     ; Check that we get ADDSWrs when we can fold in a shift.
     ;
     ; CHECK-LABEL: name: usubo_s32_shifted
     ; CHECK: liveins: $w0, $w1, $x2
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: %copy1:gpr32 = COPY $w0
     ; CHECK-NEXT: %copy2:gpr32 = COPY $w1
     ; CHECK-NEXT: %add:gpr32 = SUBSWrs %copy1, %copy2, 16, implicit-def $nzcv
     ; CHECK-NEXT: %overflow:gpr32 = CSINCWr $wzr, $wzr, 2, implicit $nzcv
     ; CHECK-NEXT: $w0 = COPY %add
-    ; CHECK-NEXT: RET_ReallyLR implicit $w0
+    ; CHECK-NEXT: $w1 = COPY %overflow
+    ; CHECK-NEXT: RET_ReallyLR implicit $w0, implicit $w1
     %copy1:gpr(s32) = COPY $w0
     %copy2:gpr(s32) = COPY $w1
     %constant:gpr(s32) = G_CONSTANT i32 16
     %shift:gpr(s32) = G_SHL %copy2(s32), %constant(s32)
-    %add:gpr(s32), %overflow:gpr(s1) = G_USUBO %copy1, %shift
+    %add:gpr(s32), %overflow:gpr(s32) = G_USUBO %copy1, %shift
     $w0 = COPY %add(s32)
-    RET_ReallyLR implicit $w0
+    $w1 = COPY %overflow(s32)
+    RET_ReallyLR implicit $w0, implicit $w1
 
 ...
 ---
 name:            usubo_s32_neg_imm
 alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 body:             |
   bb.1.entry:
     liveins: $w0, $w1, $x2
     ; Check that we get SUBSWri when we can fold in a negative constant.
     ;
     ; CHECK-LABEL: name: usubo_s32_neg_imm
     ; CHECK: liveins: $w0, $w1, $x2
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: %copy:gpr32sp = COPY $w0
     ; CHECK-NEXT: %add:gpr32 = ADDSWri %copy, 16, 0, implicit-def $nzcv
     ; CHECK-NEXT: %overflow:gpr32 = CSINCWr $wzr, $wzr, 2, implicit $nzcv
     ; CHECK-NEXT: $w0 = COPY %add
-    ; CHECK-NEXT: RET_ReallyLR implicit $w0
+    ; CHECK-NEXT: $w1 = COPY %overflow
+    ; CHECK-NEXT: RET_ReallyLR implicit $w0, implicit $w1
     %copy:gpr(s32) = COPY $w0
     %constant:gpr(s32) = G_CONSTANT i32 -16
-    %add:gpr(s32), %overflow:gpr(s1) = G_USUBO %copy, %constant
+    %add:gpr(s32), %overflow:gpr(s32) = G_USUBO %copy, %constant
     $w0 = COPY %add(s32)
-    RET_ReallyLR implicit $w0
+    $w1 = COPY %overflow(s32)
+    RET_ReallyLR implicit $w0, implicit $w1
 
 ...
 ---
 name:            usubo_arith_extended
 alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 body:             |
   bb.1.entry:
     liveins: $w0, $x0
     ; Check that we get ADDSXrx.
     ; CHECK-LABEL: name: usubo_arith_extended
     ; CHECK: liveins: $w0, $x0
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: %reg0:gpr64sp = COPY $x0
     ; CHECK-NEXT: %reg1:gpr32 = COPY $w0
     ; CHECK-NEXT: %add:gpr64 = SUBSXrx %reg0, %reg1, 18, implicit-def $nzcv
     ; CHECK-NEXT: %flags:gpr32 = CSINCWr $wzr, $wzr, 2, implicit $nzcv
     ; CHECK-NEXT: $x0 = COPY %add
-    ; CHECK-NEXT: RET_ReallyLR implicit $x0
+    ; CHECK-NEXT: $w1 = COPY %flags
+    ; CHECK-NEXT: RET_ReallyLR implicit $x0, implicit $w1
     %reg0:gpr(s64) = COPY $x0
     %reg1:gpr(s32) = COPY $w0
     %ext:gpr(s64) = G_ZEXT %reg1(s32)
     %cst:gpr(s64) = G_CONSTANT i64 2
     %shift:gpr(s64) = G_SHL %ext, %cst(s64)
-    %add:gpr(s64), %flags:gpr(s1) = G_USUBO %reg0, %shift
+    %add:gpr(s64), %flags:gpr(s32) = G_USUBO %reg0, %shift
     $x0 = COPY %add(s64)
-    RET_ReallyLR implicit $x0
+    $w1 = COPY %flags
+    RET_ReallyLR implicit $x0, implicit $w1

llvm/test/CodeGen/AArch64/GlobalISel/select.mir

 # CHECK:    %5:gpr32 = CSINCWr $wzr, $wzr, 0, implicit $nzcv
 
 body:             |
   bb.0:
     liveins: $w0, $x0
 
     %0(s32) = COPY $w0
     %1(s32) = G_ICMP intpred(eq), %0, %0
-    %6(s1) = G_TRUNC %1(s32)
+    %6(s8) = G_TRUNC %1(s32)
     %9(s32) = G_ANYEXT %6
     $w0 = COPY %9(s32)
 
     %2(s64) = COPY $x0
     %3(s32) = G_ICMP intpred(uge), %2, %2
-    %7(s1) = G_TRUNC %3(s32)
+    %7(s8) = G_TRUNC %3(s32)
     %10(s32) = G_ANYEXT %7
     $w0 = COPY %10(s32)
 
     %4(p0) = COPY $x0
     %5(s32) = G_ICMP intpred(ne), %4, %4
-    %8(s1) = G_TRUNC %5(s32)
+    %8(s8) = G_TRUNC %5(s32)
     %11(s32) = G_ANYEXT %8
     $w0 = COPY %11(s32)
 ...
 
 ---
 # CHECK-LABEL: name: fcmp
 name:            fcmp
 legalized:       true

 # CHECK:    %3:gpr32 = CSINCWr $wzr, $wzr, 4, implicit $nzcv
 
 body:             |
   bb.0:
     liveins: $w0, $x0
 
     %0(s32) = COPY $s0
     %1(s32) = G_FCMP floatpred(one), %0, %0
-    %4(s1) = G_TRUNC %1(s32)
+    %4(s8) = G_TRUNC %1(s32)
     %6(s32) = G_ANYEXT %4
     $w0 = COPY %6(s32)
 
     %2(s64) = COPY $d0
     %3(s32) = G_FCMP floatpred(uge), %2, %2
-    %5(s1) = G_TRUNC %3(s32)
+    %5(s8) = G_TRUNC %3(s32)
     %7(s32) = G_ANYEXT %5
     $w0 = COPY %7(s32)
 
 ...
 
 ---
 # CHECK-LABEL: name: phi
 name:            phi

 # CHECK:      %2:fpr32 = PHI %0, %bb.0, %2, %bb.1
 
 body:             |
   bb.0:
     liveins: $s0, $w0
     successors: %bb.1
     %0(s32) = COPY $s0
     %3:gpr(s32) = COPY $w0
-    %1(s1) = G_TRUNC %3
 
   bb.1:
     successors: %bb.1, %bb.2
     %2(s32) = PHI %0, %bb.0, %2, %bb.1
-    G_BRCOND %1, %bb.1
+    G_BRCOND %3, %bb.1
 
   bb.2:
     $s0 = COPY %2
     RET_ReallyLR implicit $s0
 ...
 
 ---
 # CHECK-LABEL: name: select
 name:            select
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 
 # CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr32, preferred-register: '' }
+# CHECK-NEXT:  - { id: 0, class: gpr, preferred-register: '' }
 # CHECK-NEXT:  - { id: 1, class: gpr32, preferred-register: '' }
 # CHECK-NEXT:  - { id: 2, class: gpr32, preferred-register: '' }
 # CHECK-NEXT:  - { id: 3, class: gpr32, preferred-register: '' }
 # CHECK-NEXT:  - { id: 4, class: gpr64, preferred-register: '' }
 # CHECK-NEXT:  - { id: 5, class: gpr64, preferred-register: '' }
 # CHECK-NEXT:  - { id: 6, class: gpr64, preferred-register: '' }
 # CHECK-NEXT:  - { id: 7, class: gpr64, preferred-register: '' }
 # CHECK-NEXT:  - { id: 8, class: gpr64, preferred-register: '' }
 # CHECK-NEXT:  - { id: 9, class: gpr64, preferred-register: '' }
+# CHECK-NEXT:  - { id: 10, class: gpr32, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
   - { id: 3, class: gpr }
   - { id: 4, class: gpr }
   - { id: 5, class: gpr }
   - { id: 6, class: gpr }
   - { id: 7, class: gpr }
   - { id: 8, class: gpr }
   - { id: 9, class: gpr }
 
 # CHECK:  body:
 # CHECK:      ANDSWri %10, 0, implicit-def $nzcv
 # CHECK:      %3:gpr32 = CSELWr %1, %2, 1, implicit $nzcv
 # CHECK:      ANDSWri %10, 0, implicit-def $nzcv
 # CHECK:      %6:gpr64 = CSELXr %4, %5, 1, implicit $nzcv
 # CHECK:      ANDSWri %10, 0, implicit-def $nzcv
 # CHECK:      %9:gpr64 = CSELXr %7, %8, 1, implicit $nzcv
 body:             |
   bb.0:
     liveins: $w0, $w1, $w2
     %10:gpr(s32) = COPY $w0
-    %0(s1) = G_TRUNC %10
 
     %1(s32) = COPY $w1
     %2(s32) = COPY $w2
-    %3(s32) = G_SELECT %0, %1, %2
+    %3(s32) = G_SELECT %10, %1, %2
     $w0 = COPY %3(s32)
 
     %4(s64) = COPY $x0
     %5(s64) = COPY $x1
-    %6(s64) = G_SELECT %0, %4, %5
+    %6(s64) = G_SELECT %10, %4, %5
     $x0 = COPY %6(s64)
 
     %7(p0) = COPY $x0
     %8(p0) = COPY $x1
-    %9(p0) = G_SELECT %0, %7, %8
+    %9(p0) = G_SELECT %10, %7, %8
     $x0 = COPY %9(p0)
 ...

llvm/test/CodeGen/AArch64/GlobalISel/speculative-hardening-brcond.mir

body:             |
   ; CHECK:   Bcc 0, %bb.1, implicit $nzcv
   ; CHECK:   B %bb.0
   ; CHECK: bb.1:
   ; CHECK:   RET_ReallyLR
   bb.0:
     liveins: $w0
     successors: %bb.0, %bb.1
     %reg:gpr(s32) = COPY $w0
-    %cond:gpr(s1) = G_TRUNC %reg
-    G_BRCOND %cond(s1), %bb.1
+    G_BRCOND %reg, %bb.1
     G_BR %bb.0
   bb.1:
     RET_ReallyLR
 ...
 ---
 name:            no_cbz
 legalized:       true
 regBankSelected: true
 body:             |
   ; CHECK-LABEL: name: no_cbz
   ; CHECK: bb.0:
   ; CHECK:   successors: %bb.0(0x40000000), %bb.1(0x40000000)
   ; CHECK:   %reg:gpr32sp = COPY $w0
   ; CHECK:   [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri %reg, 0, 0, implicit-def $nzcv
   ; CHECK:   Bcc 0, %bb.1, implicit $nzcv
   ; CHECK:   B %bb.0
   ; CHECK: bb.1:
   ; CHECK:   RET_ReallyLR
   bb.0:
     liveins: $w0
     successors: %bb.0, %bb.1
     %reg:gpr(s32) = COPY $w0
     %zero:gpr(s32) = G_CONSTANT i32 0
     %cmp:gpr(s32) = G_ICMP intpred(eq), %reg, %zero
-    %cond:gpr(s1) = G_TRUNC %cmp(s32)
-    G_BRCOND %cond(s1), %bb.1
+    G_BRCOND %cmp, %bb.1
     G_BR %bb.0
   bb.1:
     RET_ReallyLR
 ...
 ---
 name:            fp
 legalized:       true
 regBankSelected: true
body:             |
   ; CHECK: bb.1:
   ; CHECK:   RET_ReallyLR
   bb.0:
     liveins: $s0, $s1
     successors: %bb.0, %bb.1
     %reg0:fpr(s32) = COPY $s0
     %reg1:fpr(s32) = COPY $s1
     %cmp:gpr(s32) = G_FCMP floatpred(oeq), %reg0, %reg1
-    %cond:gpr(s1) = G_TRUNC %cmp(s32)
-    G_BRCOND %cond(s1), %bb.1
+    G_BRCOND %cmp, %bb.1
     G_BR %bb.0
   bb.1:
     RET_ReallyLR

llvm/test/CodeGen/AArch64/GlobalISel/subreg-copy.mir

bb.0:
     %1:gpr(p0) = COPY $x0
     %3:gpr(s64) = G_CONSTANT i64 1
     %5:gpr(s64) = G_CONSTANT i64 0
     %0:fpr(s128) = G_LOAD %1:gpr(p0) :: (load (s128))
     %2:fpr(s64) = G_TRUNC %0:fpr(s128)
     %8:gpr(s64) = COPY %2:fpr(s64)
     %4:gpr(s64) = G_AND %8:gpr, %3:gpr
     %7:gpr(s32) = G_ICMP intpred(ne), %4:gpr(s64), %5:gpr
-    %6:gpr(s1) = G_TRUNC %7:gpr(s32)
-    G_BRCOND %6:gpr(s1), %bb.1
+    G_BRCOND %7, %bb.1
 
   bb.1:
     RET_ReallyLR
 ...
 ---
 name:              no_trunc
 alignment:         4
 legalized:         true
bb.0:
     %1:gpr(p0) = COPY $x0
     %3:gpr(s64) = G_CONSTANT i64 8589934592
     %5:gpr(s64) = G_CONSTANT i64 0
     %0:fpr(s128) = G_LOAD %1:gpr(p0) :: (load (s128))
     %2:fpr(s64) = G_TRUNC %0:fpr(s128)
     %8:gpr(s64) = COPY %2:fpr(s64)
     %4:gpr(s64) = G_AND %8:gpr, %3:gpr
     %7:gpr(s32) = G_ICMP intpred(ne), %4:gpr(s64), %5:gpr
-    %6:gpr(s1) = G_TRUNC %7:gpr(s32)
-    G_BRCOND %6:gpr(s1), %bb.1
+    G_BRCOND %7, %bb.1
   bb.1:
     RET_ReallyLR

llvm/test/CodeGen/AArch64/GlobalISel/tbnz-slt.mir

body:             |
   ; CHECK-NEXT: bb.1:
   ; CHECK-NEXT:   RET_ReallyLR
   bb.0:
     successors: %bb.0, %bb.1
     liveins: $x0
     %copy:gpr(s64) = COPY $x0
     %zero:gpr(s64) = G_CONSTANT i64 0
     %cmp:gpr(s32) = G_ICMP intpred(slt), %copy(s64), %zero
-    %cmp_trunc:gpr(s1) = G_TRUNC %cmp(s32)
-    G_BRCOND %cmp_trunc(s1), %bb.1
+    G_BRCOND %cmp, %bb.1
     G_BR %bb.0
   bb.1:
     RET_ReallyLR
 
 ...
 ---
 name:            tbnzw_slt
 alignment:       4
body:             |
   ; CHECK-NEXT: bb.1:
   ; CHECK-NEXT:   RET_ReallyLR
   bb.0:
     successors: %bb.0, %bb.1
     liveins: $x0
     %copy:gpr(s32) = COPY $w0
     %zero:gpr(s32) = G_CONSTANT i32 0
     %cmp:gpr(s32) = G_ICMP intpred(slt), %copy(s32), %zero
-    %cmp_trunc:gpr(s1) = G_TRUNC %cmp(s32)
-    G_BRCOND %cmp_trunc(s1), %bb.1
+    G_BRCOND %cmp, %bb.1
     G_BR %bb.0
   bb.1:
     RET_ReallyLR
 
 ...
 ---
 name:            no_tbnz_not_zero
 alignment:       4
body:             |
   ; CHECK-NEXT: bb.1:
   ; CHECK-NEXT:   RET_ReallyLR
   bb.0:
     successors: %bb.0, %bb.1
     liveins: $x0
     %copy:gpr(s32) = COPY $w0
     %one:gpr(s32) = G_CONSTANT i32 1
     %cmp:gpr(s32) = G_ICMP intpred(slt), %copy(s32), %one
-    %cmp_trunc:gpr(s1) = G_TRUNC %cmp(s32)
-    G_BRCOND %cmp_trunc(s1), %bb.1
+    G_BRCOND %cmp, %bb.1
     G_BR %bb.0
   bb.1:
     RET_ReallyLR
 
 ...
 ---
 name:            dont_fold_and
 alignment:       4
bb.0:
     successors: %bb.0, %bb.1
     liveins: $x0
     %copy:gpr(s64) = COPY $x0
     %bit:gpr(s64) = G_CONSTANT i64 8
     %zero:gpr(s64) = G_CONSTANT i64 0
     %c:gpr(s64) = G_CONSTANT i64 8
     %and:gpr(s64) = G_AND %copy, %bit
     %cmp:gpr(s32) = G_ICMP intpred(slt), %and(s64), %zero
-    %cmp_trunc:gpr(s1) = G_TRUNC %cmp(s32)
-    G_BRCOND %cmp_trunc(s1), %bb.1
+    G_BRCOND %cmp, %bb.1
     G_BR %bb.0
   bb.1:
     RET_ReallyLR
 
 ...
 ---
 name:            dont_commute
 alignment:       4
body:             |
   ; CHECK-NEXT: bb.1:
   ; CHECK-NEXT:   RET_ReallyLR
   bb.0:
     successors: %bb.0, %bb.1
     liveins: $x0
     %copy:gpr(s64) = COPY $x0
     %zero:gpr(s64) = G_CONSTANT i64 0
     %cmp:gpr(s32) = G_ICMP intpred(slt), %zero, %copy(s64)
-    %cmp_trunc:gpr(s1) = G_TRUNC %cmp(s32)
-    G_BRCOND %cmp_trunc(s1), %bb.1
+    G_BRCOND %cmp, %bb.1
     G_BR %bb.0
   bb.1:
     RET_ReallyLR

llvm/test/CodeGen/AArch64/GlobalISel/tbz-sgt.mir

body:             |
   ; CHECK-NEXT: bb.1:
   ; CHECK-NEXT:   RET_ReallyLR
   bb.0:
     successors: %bb.0, %bb.1
     liveins: $x0
     %copy:gpr(s64) = COPY $x0
     %negative_one:gpr(s64) = G_CONSTANT i64 -1
     %cmp:gpr(s32) = G_ICMP intpred(sgt), %copy(s64), %negative_one
-    %cmp_trunc:gpr(s1) = G_TRUNC %cmp(s32)
-    G_BRCOND %cmp_trunc(s1), %bb.1
+    G_BRCOND %cmp, %bb.1
     G_BR %bb.0
   bb.1:
     RET_ReallyLR
 
 ...
 ---
 name:            tbzw_sgt
 alignment:       4
body:             |
   ; CHECK-NEXT: bb.1:
   ; CHECK-NEXT:   RET_ReallyLR
   bb.0:
     successors: %bb.0, %bb.1
     liveins: $x0
     %copy:gpr(s32) = COPY $w0
     %negative_one:gpr(s32) = G_CONSTANT i32 -1
     %cmp:gpr(s32) = G_ICMP intpred(sgt), %copy(s32), %negative_one
-    %cmp_trunc:gpr(s1) = G_TRUNC %cmp(s32)
-    G_BRCOND %cmp_trunc(s1), %bb.1
+    G_BRCOND %cmp, %bb.1
     G_BR %bb.0
   bb.1:
     RET_ReallyLR
 
 ...
 ---
 name:            no_tbz_not_negative_one
 alignment:       4
body:             |
   ; CHECK-NEXT: bb.1:
   ; CHECK-NEXT:   RET_ReallyLR
   bb.0:
     successors: %bb.0, %bb.1
     liveins: $x0
     %copy:gpr(s32) = COPY $w0
     %one:gpr(s32) = G_CONSTANT i32 1
     %cmp:gpr(s32) = G_ICMP intpred(sgt), %copy(s32), %one
-    %cmp_trunc:gpr(s1) = G_TRUNC %cmp(s32)
-    G_BRCOND %cmp_trunc(s1), %bb.1
+    G_BRCOND %cmp, %bb.1
     G_BR %bb.0
   bb.1:
     RET_ReallyLR
 
 ...
 ---
 name:            dont_fold_and
 alignment:       4
bb.0:
     successors: %bb.0, %bb.1
     liveins: $x0
     %copy:gpr(s64) = COPY $x0
     %bit:gpr(s64) = G_CONSTANT i64 8
     %negative_one:gpr(s64) = G_CONSTANT i64 -1
     %c:gpr(s64) = G_CONSTANT i64 8
     %and:gpr(s64) = G_AND %copy, %bit
     %cmp:gpr(s32) = G_ICMP intpred(sgt), %and(s64), %negative_one
-    %cmp_trunc:gpr(s1) = G_TRUNC %cmp(s32)
-    G_BRCOND %cmp_trunc(s1), %bb.1
+    G_BRCOND %cmp, %bb.1
     G_BR %bb.0
   bb.1:
     RET_ReallyLR
 
 ...
 ---
 name:            dont_commute
 alignment:       4
body:             |
   ; CHECK-NEXT: bb.1:
   ; CHECK-NEXT:   RET_ReallyLR
   bb.0:
     successors: %bb.0, %bb.1
     liveins: $x0
     %copy:gpr(s64) = COPY $x0
     %negative_one:gpr(s64) = G_CONSTANT i64 -1
     %cmp:gpr(s32) = G_ICMP intpred(sgt), %negative_one, %copy(s64)
-    %cmp_trunc:gpr(s1) = G_TRUNC %cmp(s32)
-    G_BRCOND %cmp_trunc(s1), %bb.1
+    G_BRCOND %cmp, %bb.1
     G_BR %bb.0
   bb.1:
     RET_ReallyLR

llvm/test/CodeGen/AArch64/GlobalISel/widen-narrow-tbz-tbnz.mir

 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple aarch64-unknown-unknown -run-pass=instruction-select -global-isel-abort=1 -verify-machineinstrs %s -o - | FileCheck %s
 #
 # Test widening and narrowing on test bit operations using subregister copies
 # or SUBREG_TO_REG.
 --- |
  @glob = external dso_local unnamed_addr global i1, align 4
- define void @s1_no_copy() { ret void }
- define void @s16_no_copy() { ret void }
  define void @p0_no_copy() { ret void }
  define void @widen_s32_to_s64() { ret void }
  define void @widen_s16_to_s64() { ret void }
  define void @narrow_s64_to_s32() { ret void }
 
 ...
 ---
-name:            s1_no_copy
-alignment:       4
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-body:             |
-  ; CHECK-LABEL: name: s1_no_copy
-  ; CHECK: bb.0:
-  ; CHECK-NEXT:   successors: %bb.0(0x40000000), %bb.1(0x40000000)
-  ; CHECK-NEXT: {{  $}}
-  ; CHECK-NEXT:   %narrow:gpr32 = IMPLICIT_DEF
-  ; CHECK-NEXT:   TBNZW %narrow, 0, %bb.1
-  ; CHECK-NEXT:   B %bb.0
-  ; CHECK-NEXT: {{  $}}
-  ; CHECK-NEXT: bb.1:
-  ; CHECK-NEXT:   RET_ReallyLR
-  bb.0:
-    successors: %bb.0, %bb.1
-    %narrow:gpr(s1) = G_IMPLICIT_DEF
-
-    ; There should be no copy here, because the s1 can be selected to a GPR32.
-    G_BRCOND %narrow(s1), %bb.1
-    G_BR %bb.0
-  bb.1:
-    RET_ReallyLR
-...
----
-name:            s16_no_copy
-alignment:       4
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-body:             |
-  ; CHECK-LABEL: name: s16_no_copy
-  ; CHECK: bb.0:
-  ; CHECK-NEXT:   successors: %bb.0(0x40000000), %bb.1(0x40000000)
-  ; CHECK-NEXT: {{  $}}
-  ; CHECK-NEXT:   %narrow:gpr32 = IMPLICIT_DEF
-  ; CHECK-NEXT:   TBNZW %narrow, 0, %bb.1
-  ; CHECK-NEXT:   B %bb.0
-  ; CHECK-NEXT: {{  $}}
-  ; CHECK-NEXT: bb.1:
-  ; CHECK-NEXT:   RET_ReallyLR
-  bb.0:
-    successors: %bb.0, %bb.1
-    %narrow:gpr(s16) = G_IMPLICIT_DEF
-    %trunc:gpr(s1) = G_TRUNC %narrow(s16)
-
-    ; Look through the G_TRUNC to get the G_IMPLICIT_DEF. We don't need a
-    ; SUBREG_TO_REG here, because the s16 will end up on a 32-bit register.
-    G_BRCOND %trunc(s1), %bb.1
-    G_BR %bb.0
-  bb.1:
-    RET_ReallyLR
-...
----
 name:            p0_no_copy
 alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 body:             |
   ; CHECK-LABEL: name: p0_no_copy
   ; CHECK: bb.0:
   ; CHECK-NEXT:   successors: %bb.0(0x40000000), %bb.1(0x40000000)
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT:   %glob:gpr64common = MOVaddr target-flags(aarch64-page) @glob, target-flags(aarch64-pageoff, aarch64-nc) @glob
   ; CHECK-NEXT:   %load:gpr32 = LDRBBui %glob, 0 :: (dereferenceable load (s8) from @glob, align 4)
   ; CHECK-NEXT:   TBNZW %load, 0, %bb.1
   ; CHECK-NEXT:   B %bb.0
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT: bb.1:
   ; CHECK-NEXT:   RET_ReallyLR
   bb.0:
     successors: %bb.0, %bb.1
     %glob:gpr(p0) = G_GLOBAL_VALUE @glob
-    %load:gpr(s8) = G_LOAD %glob(p0) :: (dereferenceable load (s8) from @glob, align 4)
-    %trunc:gpr(s1) = G_TRUNC %load(s8)
+    %load:gpr(s32) = G_LOAD %glob(p0) :: (dereferenceable load (s8) from @glob, align 4)
 
     ; Look through G_TRUNC to get the load. The load is into a s8, which will
     ; be selected to a GPR32, so we don't need a copy.
-    G_BRCOND %trunc(s1), %bb.1
+    G_BRCOND %load, %bb.1
     G_BR %bb.0
   bb.1:
     RET_ReallyLR
 ...
 ---
 name:            widen_s32_to_s64
 alignment:       4
 legalized:       true
bb.0:
     %zext:gpr(s64) = G_ZEXT %reg(s32)
     %bit:gpr(s64) = G_CONSTANT i64 8589934592
     %zero:gpr(s64) = G_CONSTANT i64 0
     %and:gpr(s64) = G_AND %zext, %bit
     %cmp:gpr(s32) = G_ICMP intpred(eq), %and(s64), %zero
 
     ; We should widen using a SUBREG_TO_REG here, because we need a TBZX to get
     ; bit 33. The subregister should be sub_32.
-    %trunc:gpr(s1) = G_TRUNC %cmp(s32)
-    G_BRCOND %trunc(s1), %bb.1
+    G_BRCOND %cmp, %bb.1
     G_BR %bb.0
   bb.1:
     RET_ReallyLR
 ...
 ---
 name:            widen_s16_to_s64
 alignment:       4
 legalized:       true
bb.0:
     %bit:gpr(s64) = G_CONSTANT i64 8589934592
     %zero:gpr(s64) = G_CONSTANT i64 0
     %and:gpr(s64) = G_AND %zext, %bit
     %cmp:gpr(s32) = G_ICMP intpred(eq), %and(s64), %zero
 
     ; We should widen using a SUBREG_TO_REG here, because we need a TBZX to get
     ; bit 33. The subregister should be sub_32, because s16 will end up on a
     ; GPR32.
-    %trunc:gpr(s1) = G_TRUNC %cmp(s32)
-    G_BRCOND %trunc(s1), %bb.1
+    G_BRCOND %cmp, %bb.1
     G_BR %bb.0
   bb.1:
     RET_ReallyLR
 ...
 ---
 name:            narrow_s64_to_s32
 alignment:       4
 legalized:       true
body:             |
   ; CHECK-NEXT: bb.1:
   ; CHECK-NEXT:   RET_ReallyLR
   bb.0:
     successors: %bb.0, %bb.1
     liveins: $x0
     %wide:gpr(s64) = COPY $x0
 
     ; We should narrow using a subregister copy here.
-    %trunc:gpr(s1) = G_TRUNC %wide(s64)
-    G_BRCOND %trunc(s1), %bb.1
+    %trunc:gpr(s32) = G_TRUNC %wide(s64)
+    G_BRCOND %trunc, %bb.1
     G_BR %bb.0
   bb.1:
     RET_ReallyLR

llvm/test/CodeGen/AArch64/arm64-xaluo.ll

 ; FAST-NEXT:    cset w9, vs
 ; FAST-NEXT:    and w0, w9, #0x1
 ; FAST-NEXT:    str w8, [x2]
 ; FAST-NEXT:    ret
 ;
 ; GISEL-LABEL: saddo1.i32:
 ; GISEL:       // %bb.0: // %entry
 ; GISEL-NEXT:    adds w8, w0, w1
-; GISEL-NEXT:    cset w9, vs
-; GISEL-NEXT:    ubfx w0, w9, #0, #1
+; GISEL-NEXT:    cset w0, vs
 ; GISEL-NEXT:    str w8, [x2]
 ; GISEL-NEXT:    ret
 entry:
   %t = call {i32, i1} @llvm.sadd.with.overflow.i32(i32 %v1, i32 %v2)
   %val = extractvalue {i32, i1} %t, 0
   %obit = extractvalue {i32, i1} %t, 1
   store i32 %val, i32* %res
   ret i1 %obit

 ; FAST-NEXT:    cset w9, vs
 ; FAST-NEXT:    and w0, w9, #0x1
 ; FAST-NEXT:    str w8, [x1]
 ; FAST-NEXT:    ret
 ;
 ; GISEL-LABEL: saddo2.i32:
 ; GISEL:       // %bb.0: // %entry
 ; GISEL-NEXT:    adds w8, w0, #4
-; GISEL-NEXT:    cset w9, vs
-; GISEL-NEXT:    ubfx w0, w9, #0, #1
+; GISEL-NEXT:    cset w0, vs
 ; GISEL-NEXT:    str w8, [x1]
 ; GISEL-NEXT:    ret
 entry:
   %t = call {i32, i1} @llvm.sadd.with.overflow.i32(i32 %v1, i32 4)
   %val = extractvalue {i32, i1} %t, 0
   %obit = extractvalue {i32, i1} %t, 1
   store i32 %val, i32* %res
   ret i1 %obit

 ; FAST-NEXT:    cset w9, vs
 ; FAST-NEXT:    and w0, w9, #0x1
 ; FAST-NEXT:    str w8, [x1]
 ; FAST-NEXT:    ret
 ;
 ; GISEL-LABEL: saddo3.i32:
 ; GISEL:       // %bb.0: // %entry
 ; GISEL-NEXT:    subs w8, w0, #4
-; GISEL-NEXT:    cset w9, vs
-; GISEL-NEXT:    ubfx w0, w9, #0, #1
+; GISEL-NEXT:    cset w0, vs
 ; GISEL-NEXT:    str w8, [x1]
 ; GISEL-NEXT:    ret
 entry:
   %t = call {i32, i1} @llvm.sadd.with.overflow.i32(i32 %v1, i32 -4)
   %val = extractvalue {i32, i1} %t, 0
   %obit = extractvalue {i32, i1} %t, 1
   store i32 %val, i32* %res
   ret i1 %obit

 ; FAST-NEXT:    and w0, w9, #0x1
 ; FAST-NEXT:    str w8, [x1]
 ; FAST-NEXT:    ret
 ;
 ; GISEL-LABEL: saddo4.i32:
 ; GISEL:       // %bb.0: // %entry
 ; GISEL-NEXT:    mov w8, #16777215
 ; GISEL-NEXT:    adds w8, w0, w8
-; GISEL-NEXT:    cset w9, vs
-; GISEL-NEXT:    ubfx w0, w9, #0, #1
+; GISEL-NEXT:    cset w0, vs
 ; GISEL-NEXT:    str w8, [x1]
 ; GISEL-NEXT:    ret
 entry:
   %t = call {i32, i1} @llvm.sadd.with.overflow.i32(i32 %v1, i32 16777215)
   %val = extractvalue {i32, i1} %t, 0
   %obit = extractvalue {i32, i1} %t, 1
   store i32 %val, i32* %res
   ret i1 %obit

 ; FAST-NEXT:    cset w9, vs
 ; FAST-NEXT:    and w0, w9, #0x1
 ; FAST-NEXT:    str w8, [x2]
 ; FAST-NEXT:    ret
 ;
 ; GISEL-LABEL: saddo5.i32:
 ; GISEL:       // %bb.0: // %entry
 ; GISEL-NEXT:    adds w8, w0, w1, lsl #16
-; GISEL-NEXT:    cset w9, vs
-; GISEL-NEXT:    ubfx w0, w9, #0, #1
+; GISEL-NEXT:    cset w0, vs
 ; GISEL-NEXT:    str w8, [x2]
 ; GISEL-NEXT:    ret
 entry:
   %lsl = shl i32 %v2, 16
   %t = call {i32, i1} @llvm.sadd.with.overflow.i32(i32 %v1, i32 %lsl)
   %val = extractvalue {i32, i1} %t, 0
   %obit = extractvalue {i32, i1} %t, 1
   store i32 %val, i32* %res

 ; FAST-NEXT:    cset w9, vs
 ; FAST-NEXT:    and w0, w9, #0x1
 ; FAST-NEXT:    str x8, [x2]
 ; FAST-NEXT:    ret
 ;
 ; GISEL-LABEL: saddo1.i64:
 ; GISEL:       // %bb.0: // %entry
 ; GISEL-NEXT:    adds x8, x0, x1
-; GISEL-NEXT:    cset w9, vs
-; GISEL-NEXT:    ubfx w0, w9, #0, #1
+; GISEL-NEXT:    cset w0, vs
 ; GISEL-NEXT:    str x8, [x2]
 ; GISEL-NEXT:    ret
 entry:
   %t = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 %v1, i64 %v2)
   %val = extractvalue {i64, i1} %t, 0
   %obit = extractvalue {i64, i1} %t, 1
   store i64 %val, i64* %res
   ret i1 %obit

 ; FAST-NEXT:    cset w9, vs
 ; FAST-NEXT:    and w0, w9, #0x1
 ; FAST-NEXT:    str x8, [x1]
 ; FAST-NEXT:    ret
 ;
 ; GISEL-LABEL: saddo2.i64:
 ; GISEL:       // %bb.0: // %entry
 ; GISEL-NEXT:    adds x8, x0, #4
-; GISEL-NEXT:    cset w9, vs
-; GISEL-NEXT:    ubfx w0, w9, #0, #1
+; GISEL-NEXT:    cset w0, vs
 ; GISEL-NEXT:    str x8, [x1]
 ; GISEL-NEXT:    ret
 entry:
   %t = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 %v1, i64 4)
   %val = extractvalue {i64, i1} %t, 0
   %obit = extractvalue {i64, i1} %t, 1
   store i64 %val, i64* %res
   ret i1 %obit

 ; FAST-NEXT:    cset w9, vs
 ; FAST-NEXT:    and w0, w9, #0x1
 ; FAST-NEXT:    str x8, [x1]
 ; FAST-NEXT:    ret
 ;
 ; GISEL-LABEL: saddo3.i64:
 ; GISEL:       // %bb.0: // %entry
 ; GISEL-NEXT:    subs x8, x0, #4
-; GISEL-NEXT:    cset w9, vs
-; GISEL-NEXT:    ubfx w0, w9, #0, #1
+; GISEL-NEXT:    cset w0, vs
 ; GISEL-NEXT:    str x8, [x1]
 ; GISEL-NEXT:    ret
 entry:
   %t = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 %v1, i64 -4)
   %val = extractvalue {i64, i1} %t, 0
   %obit = extractvalue {i64, i1} %t, 1
   store i64 %val, i64* %res
   ret i1 %obit

 ; FAST-NEXT:    cset w9, hs
 ; FAST-NEXT:    and w0, w9, #0x1
 ; FAST-NEXT:    str w8, [x2]
 ; FAST-NEXT:    ret
 ;
 ; GISEL-LABEL: uaddo.i32:
 ; GISEL:       // %bb.0: // %entry
 ; GISEL-NEXT:    adds w8, w0, w1
-; GISEL-NEXT:    cset w9, hs
-; GISEL-NEXT:    ubfx w0, w9, #0, #1
+; GISEL-NEXT:    cset w0, hs
 ; GISEL-NEXT:    str w8, [x2]
 ; GISEL-NEXT:    ret
 entry:
   %t = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %v1, i32 %v2)
   %val = extractvalue {i32, i1} %t, 0
   %obit = extractvalue {i32, i1} %t, 1
   store i32 %val, i32* %res
   ret i1 %obit

 ; FAST-NEXT:    cset w9, hs
 ; FAST-NEXT:    and w0, w9, #0x1
 ; FAST-NEXT:    str x8, [x2]
 ; FAST-NEXT:    ret
 ;
 ; GISEL-LABEL: uaddo.i64:
 ; GISEL:       // %bb.0: // %entry
 ; GISEL-NEXT:    adds x8, x0, x1
-; GISEL-NEXT:    cset w9, hs
-; GISEL-NEXT:    ubfx w0, w9, #0, #1
+; GISEL-NEXT:    cset w0, hs
 ; GISEL-NEXT:    str x8, [x2]
 ; GISEL-NEXT:    ret
 entry:
   %t = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %v1, i64 %v2)
   %val = extractvalue {i64, i1} %t, 0
   %obit = extractvalue {i64, i1} %t, 1
   store i64 %val, i64* %res
   ret i1 %obit

 ; FAST-NEXT:    cset w9, vs
 ; FAST-NEXT:    and w0, w9, #0x1
 ; FAST-NEXT:    str w8, [x2]
 ; FAST-NEXT:    ret
 ;
 ; GISEL-LABEL: ssubo1.i32:
 ; GISEL:       // %bb.0: // %entry
 ; GISEL-NEXT:    subs w8, w0, w1
-; GISEL-NEXT:    cset w9, vs
-; GISEL-NEXT:    ubfx w0, w9, #0, #1
+; GISEL-NEXT:    cset w0, vs
 ; GISEL-NEXT:    str w8, [x2]
 ; GISEL-NEXT:    ret
 entry:
   %t = call {i32, i1} @llvm.ssub.with.overflow.i32(i32 %v1, i32 %v2)
   %val = extractvalue {i32, i1} %t, 0
   %obit = extractvalue {i32, i1} %t, 1
   store i32 %val, i32* %res
   ret i1 %obit

 ; FAST-NEXT:    cset w9, vs
 ; FAST-NEXT:    and w0, w9, #0x1
 ; FAST-NEXT:    str w8, [x1]
 ; FAST-NEXT:    ret
 ;
 ; GISEL-LABEL: ssubo2.i32:
 ; GISEL:       // %bb.0: // %entry
 ; GISEL-NEXT:    adds w8, w0, #4
-; GISEL-NEXT:    cset w9, vs
-; GISEL-NEXT:    ubfx w0, w9, #0, #1
+; GISEL-NEXT:    cset w0, vs
 ; GISEL-NEXT:    str w8, [x1]
 ; GISEL-NEXT:    ret
 entry:
   %t = call {i32, i1} @llvm.ssub.with.overflow.i32(i32 %v1, i32 -4)
   %val = extractvalue {i32, i1} %t, 0
   %obit = extractvalue {i32, i1} %t, 1
   store i32 %val, i32* %res
   ret i1 %obit

 ; FAST-NEXT:    cset w9, vs
 ; FAST-NEXT:    and w0, w9, #0x1
 ; FAST-NEXT:    str x8, [x2]
 ; FAST-NEXT:    ret
 ;
 ; GISEL-LABEL: ssubo.i64:
 ; GISEL:       // %bb.0: // %entry
 ; GISEL-NEXT:    subs x8, x0, x1
-; GISEL-NEXT:    cset w9, vs
-; GISEL-NEXT:    ubfx w0, w9, #0, #1
+; GISEL-NEXT:    cset w0, vs
 ; GISEL-NEXT:    str x8, [x2]
 ; GISEL-NEXT:    ret
 entry:
   %t = call {i64, i1} @llvm.ssub.with.overflow.i64(i64 %v1, i64 %v2)
   %val = extractvalue {i64, i1} %t, 0
   %obit = extractvalue {i64, i1} %t, 1
   store i64 %val, i64* %res
   ret i1 %obit

 ; FAST-NEXT:    cset w9, lo
 ; FAST-NEXT:    and w0, w9, #0x1
 ; FAST-NEXT:    str w8, [x2]
 ; FAST-NEXT:    ret
 ;
 ; GISEL-LABEL: usubo.i32:
 ; GISEL:       // %bb.0: // %entry
 ; GISEL-NEXT:    subs w8, w0, w1
-; GISEL-NEXT:    cset w9, lo
-; GISEL-NEXT:    ubfx w0, w9, #0, #1
+; GISEL-NEXT:    cset w0, lo
 ; GISEL-NEXT:    str w8, [x2]
 ; GISEL-NEXT:    ret
 entry:
   %t = call {i32, i1} @llvm.usub.with.overflow.i32(i32 %v1, i32 %v2)
   %val = extractvalue {i32, i1} %t, 0
   %obit = extractvalue {i32, i1} %t, 1
   store i32 %val, i32* %res
   ret i1 %obit

 ; FAST-NEXT:    cset w9, lo
 ; FAST-NEXT:    and w0, w9, #0x1
 ; FAST-NEXT:    str x8, [x2]
 ; FAST-NEXT:    ret
 ;
 ; GISEL-LABEL: usubo.i64:
 ; GISEL:       // %bb.0: // %entry
 ; GISEL-NEXT:    subs x8, x0, x1
-; GISEL-NEXT:    cset w9, lo
-; GISEL-NEXT:    ubfx w0, w9, #0, #1
+; GISEL-NEXT:    cset w0, lo
 ; GISEL-NEXT:    str x8, [x2]
 ; GISEL-NEXT:    ret
 entry:
   %t = call {i64, i1} @llvm.usub.with.overflow.i64(i64 %v1, i64 %v2)
   %val = extractvalue {i64, i1} %t, 0
   %obit = extractvalue {i64, i1} %t, 1
   store i64 %val, i64* %res
   ret i1 %obit

 ; FAST-NEXT:    cset w9, vs
 ; FAST-NEXT:    and w0, w9, #0x1
 ; FAST-NEXT:    str x8, [x1]
 ; FAST-NEXT:    ret
 ;
 ; GISEL-LABEL: smulo2.i64:
 ; GISEL:       // %bb.0: // %entry
 ; GISEL-NEXT:    adds x8, x0, x0
-; GISEL-NEXT:    cset w9, vs
-; GISEL-NEXT:    ubfx w0, w9, #0, #1
+; GISEL-NEXT:    cset w0, vs
 ; GISEL-NEXT:    str x8, [x1]
 ; GISEL-NEXT:    ret
 entry:
   %t = call {i64, i1} @llvm.smul.with.overflow.i64(i64 %v1, i64 2)
   %val = extractvalue {i64, i1} %t, 0
   %obit = extractvalue {i64, i1} %t, 1
   store i64 %val, i64* %res
   ret i1 %obit

 ; FAST-NEXT:    cset w9, hs
 ; FAST-NEXT:    and w0, w9, #0x1
 ; FAST-NEXT:    str x8, [x1]
 ; FAST-NEXT:    ret
 ;
 ; GISEL-LABEL: umulo2.i64:
 ; GISEL:       // %bb.0: // %entry
 ; GISEL-NEXT:    adds x8, x0, x0
-; GISEL-NEXT:    cset w9, hs
-; GISEL-NEXT:    ubfx w0, w9, #0, #1
+; GISEL-NEXT:    cset w0, hs
 ; GISEL-NEXT:    str x8, [x1]
 ; GISEL-NEXT:    ret
 entry:
   %t = call {i64, i1} @llvm.umul.with.overflow.i64(i64 %v1, i64 2)
   %val = extractvalue {i64, i1} %t, 0
   %obit = extractvalue {i64, i1} %t, 1
   store i64 %val, i64* %res
   ret i1 %obit

 ; FAST-NEXT:    cmn w0, w1
 ; FAST-NEXT:    cset w0, vc
 ; FAST-NEXT:    ret
 ;
 ; GISEL-LABEL: saddo.not.i32:
 ; GISEL:       // %bb.0: // %entry
 ; GISEL-NEXT:    cmn w0, w1
 ; GISEL-NEXT:    cset w8, vs
-; GISEL-NEXT:    eor w8, w8, #0x1
-; GISEL-NEXT:    and w0, w8, #0x1
+; GISEL-NEXT:    eor w0, w8, #0x1
 ; GISEL-NEXT:    ret
 entry:
   %t = call {i32, i1} @llvm.sadd.with.overflow.i32(i32 %v1, i32 %v2)
   %obit = extractvalue {i32, i1} %t, 1
   %ret = xor i1 %obit, true
   ret i1 %ret
 }
 

 ; FAST-NEXT:    cmn x0, x1
 ; FAST-NEXT:    cset w0, vc
 ; FAST-NEXT:    ret
 ;
 ; GISEL-LABEL: saddo.not.i64:
 ; GISEL:       // %bb.0: // %entry
 ; GISEL-NEXT:    cmn x0, x1
 ; GISEL-NEXT:    cset w8, vs
-; GISEL-NEXT:    eor w8, w8, #0x1
-; GISEL-NEXT:    and w0, w8, #0x1
+; GISEL-NEXT:    eor w0, w8, #0x1
 ; GISEL-NEXT:    ret
 entry:
   %t = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 %v1, i64 %v2)
   %obit = extractvalue {i64, i1} %t, 1
   %ret = xor i1 %obit, true
   ret i1 %ret
 }
 

 ; FAST-NEXT:    cmn w0, w1
 ; FAST-NEXT:    cset w0, lo
 ; FAST-NEXT:    ret
 ;
 ; GISEL-LABEL: uaddo.not.i32:
 ; GISEL:       // %bb.0: // %entry
 ; GISEL-NEXT:    cmn w0, w1
 ; GISEL-NEXT:    cset w8, hs
-; GISEL-NEXT:    eor w8, w8, #0x1
-; GISEL-NEXT:    and w0, w8, #0x1
+; GISEL-NEXT:    eor w0, w8, #0x1
 ; GISEL-NEXT:    ret
 entry:
   %t = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %v1, i32 %v2)
   %obit = extractvalue {i32, i1} %t, 1
   %ret = xor i1 %obit, true
   ret i1 %ret
 }
 

 ; FAST-NEXT:    cmn x0, x1
 ; FAST-NEXT:    cset w0, lo
 ; FAST-NEXT:    ret
 ;
 ; GISEL-LABEL: uaddo.not.i64:
 ; GISEL:       // %bb.0: // %entry
 ; GISEL-NEXT:    cmn x0, x1
 ; GISEL-NEXT:    cset w8, hs
-; GISEL-NEXT:    eor w8, w8, #0x1
-; GISEL-NEXT:    and w0, w8, #0x1
+; GISEL-NEXT:    eor w0, w8, #0x1
 ; GISEL-NEXT:    ret
 entry:
   %t = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %v1, i64 %v2)
   %obit = extractvalue {i64, i1} %t, 1
   %ret = xor i1 %obit, true
   ret i1 %ret
 }
 

 ; FAST-NEXT:    cmp w0, w1
 ; FAST-NEXT:    cset w0, vc
 ; FAST-NEXT:    ret
 ;
 ; GISEL-LABEL: ssubo.not.i32:
 ; GISEL:       // %bb.0: // %entry
 ; GISEL-NEXT:    cmp w0, w1
 ; GISEL-NEXT:    cset w8, vs
-; GISEL-NEXT:    eor w8, w8, #0x1
-; GISEL-NEXT:    and w0, w8, #0x1
+; GISEL-NEXT:    eor w0, w8, #0x1
 ; GISEL-NEXT:    ret
 entry:
   %t = call {i32, i1} @llvm.ssub.with.overflow.i32(i32 %v1, i32 %v2)
   %obit = extractvalue {i32, i1} %t, 1
   %ret = xor i1 %obit, true
   ret i1 %ret
 }
 

 ; FAST-NEXT:    cmp x0, x1
 ; FAST-NEXT:    cset w0, vc
 ; FAST-NEXT:    ret
 ;
 ; GISEL-LABEL: ssub.not.i64:
 ; GISEL:       // %bb.0: // %entry
 ; GISEL-NEXT:    cmp x0, x1
 ; GISEL-NEXT:    cset w8, vs
-; GISEL-NEXT:    eor w8, w8, #0x1
-; GISEL-NEXT:    and w0, w8, #0x1
+; GISEL-NEXT:    eor w0, w8, #0x1
 ; GISEL-NEXT:    ret
 entry:
   %t = call {i64, i1} @llvm.ssub.with.overflow.i64(i64 %v1, i64 %v2)
   %obit = extractvalue {i64, i1} %t, 1
   %ret = xor i1 %obit, true
   ret i1 %ret
 }
 

 ; FAST-NEXT:    cmp w0, w1
 ; FAST-NEXT:    cset w0, hs
 ; FAST-NEXT:    ret
 ;
 ; GISEL-LABEL: usubo.not.i32:
 ; GISEL:       // %bb.0: // %entry
 ; GISEL-NEXT:    cmp w0, w1
 ; GISEL-NEXT:    cset w8, lo
-; GISEL-NEXT:    eor w8, w8, #0x1
-; GISEL-NEXT:    and w0, w8, #0x1
+; GISEL-NEXT:    eor w0, w8, #0x1
 ; GISEL-NEXT:    ret
 entry:
   %t = call {i32, i1} @llvm.usub.with.overflow.i32(i32 %v1, i32 %v2)
   %obit = extractvalue {i32, i1} %t, 1
   %ret = xor i1 %obit, true
   ret i1 %ret
 }
 

 ; FAST-NEXT:    cmp x0, x1
 ; FAST-NEXT:    cset w0, hs
 ; FAST-NEXT:    ret
 ;
 ; GISEL-LABEL: usubo.not.i64:
 ; GISEL:       // %bb.0: // %entry
 ; GISEL-NEXT:    cmp x0, x1
 ; GISEL-NEXT:    cset w8, lo
-; GISEL-NEXT:    eor w8, w8, #0x1
-; GISEL-NEXT:    and w0, w8, #0x1
+; GISEL-NEXT:    eor w0, w8, #0x1
 ; GISEL-NEXT:    ret
 entry:
   %t = call {i64, i1} @llvm.usub.with.overflow.i64(i64 %v1, i64 %v2)
   %obit = extractvalue {i64, i1} %t, 1
   %ret = xor i1 %obit, true
   ret i1 %ret
 }
 

 ; FAST-NEXT:    bic w8, w9, w8
 ; FAST-NEXT:    and w0, w8, #0x1
 ; FAST-NEXT:    ret
 ;
 ; GISEL-LABEL: saddo.br.i32:
 ; GISEL:       // %bb.0: // %entry
 ; GISEL-NEXT:    cmn w0, w1
 ; GISEL-NEXT:    cset w8, vs
-; GISEL-NEXT:    eor w8, w8, #0x1
-; GISEL-NEXT:    and w0, w8, #0x1
+; GISEL-NEXT:    eor w0, w8, #0x1
 ; GISEL-NEXT:    ret
 entry:
   %t = call {i32, i1} @llvm.sadd.with.overflow.i32(i32 %v1, i32 %v2)
   %val = extractvalue {i32, i1} %t, 0
   %obit = extractvalue {i32, i1} %t, 1
   br i1 %obit, label %overflow, label %continue
 
 overflow:

 ; FAST-NEXT:    bic w8, w9, w8
 ; FAST-NEXT:    and w0, w8, #0x1
 ; FAST-NEXT:    ret
 ;
 ; GISEL-LABEL: saddo.br.i64:
 ; GISEL:       // %bb.0: // %entry
 ; GISEL-NEXT:    cmn x0, x1
 ; GISEL-NEXT:    cset w8, vs
-; GISEL-NEXT:    eor w8, w8, #0x1
-; GISEL-NEXT:    and w0, w8, #0x1
+; GISEL-NEXT:    eor w0, w8, #0x1
 ; GISEL-NEXT:    ret
 entry:
   %t = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 %v1, i64 %v2)
   %val = extractvalue {i64, i1} %t, 0
   %obit = extractvalue {i64, i1} %t, 1
   br i1 %obit, label %overflow, label %continue
 
 overflow:

 ; FAST-NEXT:    bic w8, w9, w8
 ; FAST-NEXT:    and w0, w8, #0x1
 ; FAST-NEXT:    ret
 ;
 ; GISEL-LABEL: uaddo.br.i32:
 ; GISEL:       // %bb.0: // %entry
 ; GISEL-NEXT:    cmn w0, w1
 ; GISEL-NEXT:    cset w8, hs
-; GISEL-NEXT:    eor w8, w8, #0x1
-; GISEL-NEXT:    and w0, w8, #0x1
+; GISEL-NEXT:    eor w0, w8, #0x1
 ; GISEL-NEXT:    ret
 entry:
   %t = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %v1, i32 %v2)
   %val = extractvalue {i32, i1} %t, 0
   %obit = extractvalue {i32, i1} %t, 1
   br i1 %obit, label %overflow, label %continue
 
 overflow:

 ; FAST-NEXT:    bic w8, w9, w8
 ; FAST-NEXT:    and w0, w8, #0x1
 ; FAST-NEXT:    ret
 ;
 ; GISEL-LABEL: uaddo.br.i64:
 ; GISEL:       // %bb.0: // %entry
 ; GISEL-NEXT:    cmn x0, x1
 ; GISEL-NEXT:    cset w8, hs
-; GISEL-NEXT:    eor w8, w8, #0x1
-; GISEL-NEXT:    and w0, w8, #0x1
+; GISEL-NEXT:    eor w0, w8, #0x1
 ; GISEL-NEXT:    ret
 entry:
   %t = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %v1, i64 %v2)
   %val = extractvalue {i64, i1} %t, 0
   %obit = extractvalue {i64, i1} %t, 1
   br i1 %obit, label %overflow, label %continue
 
 overflow:

 ; FAST-NEXT:    bic w8, w9, w8
 ; FAST-NEXT:    and w0, w8, #0x1
 ; FAST-NEXT:    ret
 ;
 ; GISEL-LABEL: ssubo.br.i32:
 ; GISEL:       // %bb.0: // %entry
 ; GISEL-NEXT:    cmp w0, w1
 ; GISEL-NEXT:    cset w8, vs
-; GISEL-NEXT:    eor w8, w8, #0x1
-; GISEL-NEXT:    and w0, w8, #0x1
+; GISEL-NEXT:    eor w0, w8, #0x1
 ; GISEL-NEXT:    ret
 entry:
   %t = call {i32, i1} @llvm.ssub.with.overflow.i32(i32 %v1, i32 %v2)
   %val = extractvalue {i32, i1} %t, 0
   %obit = extractvalue {i32, i1} %t, 1
   br i1 %obit, label %overflow, label %continue
 
 overflow:

 ; FAST-NEXT:    bic w8, w9, w8
 ; FAST-NEXT:    and w0, w8, #0x1
 ; FAST-NEXT:    ret
 ;
 ; GISEL-LABEL: ssubo.br.i64:
 ; GISEL:       // %bb.0: // %entry
 ; GISEL-NEXT:    cmp x0, x1
 ; GISEL-NEXT:    cset w8, vs
-; GISEL-NEXT:    eor w8, w8, #0x1
-; GISEL-NEXT:    and w0, w8, #0x1
+; GISEL-NEXT:    eor w0, w8, #0x1
 ; GISEL-NEXT:    ret
 entry:
   %t = call {i64, i1} @llvm.ssub.with.overflow.i64(i64 %v1, i64 %v2)
   %val = extractvalue {i64, i1} %t, 0
   %obit = extractvalue {i64, i1} %t, 1
   br i1 %obit, label %overflow, label %continue
 
 overflow:

 ; FAST-NEXT:    bic w8, w9, w8
 ; FAST-NEXT:    and w0, w8, #0x1
 ; FAST-NEXT:    ret
 ;
 ; GISEL-LABEL: usubo.br.i32:
 ; GISEL:       // %bb.0: // %entry
 ; GISEL-NEXT:    cmp w0, w1
 ; GISEL-NEXT:    cset w8, lo
-; GISEL-NEXT:    eor w8, w8, #0x1
-; GISEL-NEXT:    and w0, w8, #0x1
+; GISEL-NEXT:    eor w0, w8, #0x1
 ; GISEL-NEXT:    ret
 entry:
   %t = call {i32, i1} @llvm.usub.with.overflow.i32(i32 %v1, i32 %v2)
   %val = extractvalue {i32, i1} %t, 0
   %obit = extractvalue {i32, i1} %t, 1
   br i1 %obit, label %overflow, label %continue
 
 overflow:

 ; FAST-NEXT:    bic w8, w9, w8
 ; FAST-NEXT:    and w0, w8, #0x1
 ; FAST-NEXT:    ret
 ;
 ; GISEL-LABEL: usubo.br.i64:
 ; GISEL:       // %bb.0: // %entry
 ; GISEL-NEXT:    cmp x0, x1
 ; GISEL-NEXT:    cset w8, lo
-; GISEL-NEXT:    eor w8, w8, #0x1
-; GISEL-NEXT:    and w0, w8, #0x1
+; GISEL-NEXT:    eor w0, w8, #0x1
 ; GISEL-NEXT:    ret
 entry:
   %t = call {i64, i1} @llvm.usub.with.overflow.i64(i64 %v1, i64 %v2)
   %val = extractvalue {i64, i1} %t, 0
   %obit = extractvalue {i64, i1} %t, 1
   br i1 %obit, label %overflow, label %continue
 
 overflow:

 ; FAST-NEXT:    bic w8, w8, w9
 ; FAST-NEXT:    and w0, w8, #0x1
 ; FAST-NEXT:    ret
 ;
 ; GISEL-LABEL: smulo2.br.i64:
 ; GISEL:       // %bb.0: // %entry
 ; GISEL-NEXT:    cmn x0, x0
 ; GISEL-NEXT:    cset w8, vs
-; GISEL-NEXT:    eor w8, w8, #0x1
-; GISEL-NEXT:    and w0, w8, #0x1
+; GISEL-NEXT:    eor w0, w8, #0x1
 ; GISEL-NEXT:    ret
 entry:
   %t = call {i64, i1} @llvm.smul.with.overflow.i64(i64 %v1, i64 2)
   %val = extractvalue {i64, i1} %t, 0
   %obit = extractvalue {i64, i1} %t, 1
   br i1 %obit, label %overflow, label %continue
 
 overflow:

 ; FAST-NEXT:    bic w8, w8, w9
 ; FAST-NEXT:    and w0, w8, #0x1
 ; FAST-NEXT:    ret
 ;
 ; GISEL-LABEL: umulo2.br.i64:
 ; GISEL:       // %bb.0: // %entry
 ; GISEL-NEXT:    cmn x0, x0
 ; GISEL-NEXT:    cset w8, hs
-; GISEL-NEXT:    eor w8, w8, #0x1
-; GISEL-NEXT:    and w0, w8, #0x1
+; GISEL-NEXT:    eor w0, w8, #0x1
 ; GISEL-NEXT:    ret
 entry:
   %t = call {i64, i1} @llvm.umul.with.overflow.i64(i64 %v1, i64 2)
   %val = extractvalue {i64, i1} %t, 0
   %obit = extractvalue {i64, i1} %t, 1
   br i1 %obit, label %overflow, label %continue
 
 overflow: