test: Don't depend on behavior of switch lower in one test. NFC

[ruiling]

Summary

This is a preliminary change to update the test so that it does not
depend on how switch-case will be lowered. The following change will
lower switch-case more optimally that will make the test no longer
valid.

llvm/test/CodeGen/AMDGPU/ipra-return-address-save-restore.ll

entry:
   br i1 undef, label %common.ret.critedge, label %cond.true
 
 cond.true:                                        ; preds = %entry
   %9 = load float, float* null, align 4
   %phi.cmp = fcmp oeq float %9, 0.000000e+00
   br i1 %phi.cmp, label %common.ret, label %cond.true20
 
 cond.true20:                                      ; preds = %cond.true
-  %trunc1 = trunc i32 %0 to i8
-  switch i8 %trunc, label %common.ret [
-    i8 44, label %sw.bb
-    i8 0, label %if.end.i.i2285
-  ]
+  %v = zext i8 %trunc to i32
+  br label %NodeBlock
+
+NodeBlock:                                        ; preds = %cond.true20
+  %Pivot = icmp slt i32 %v, 44
+  br i1 %Pivot, label %LeafBlock, label %LeafBlock1
+
+LeafBlock1:                                       ; preds = %NodeBlock
+  %SwitchLeaf2 = icmp eq i32 %v, 44
+  br i1 %SwitchLeaf2, label %sw.bb, label %NewDefault
+
+LeafBlock:                                        ; preds = %NodeBlock
+  %SwitchLeaf = icmp eq i32 %v, 0
+  br i1 %SwitchLeaf, label %if.end.i.i2285, label %NewDefault
 
 sw.bb:                                            ; preds = %cond.true20
   %10 = load float, float* null, align 4
   %11 = load float, float* null, align 4
   %12 = tail call float @llvm.amdgcn.fmed3.f32(float %1, float 0.000000e+00, float 0.000000e+00)
   %mul802 = fmul nsz float %1, 0.000000e+00
   %cmp412.old3 = fcmp nsz ogt float %1, 0.000000e+00
   br i1 %cmp412.old, label %if.then413, label %common.ret
 
 if.then413:                                       ; preds = %sw.bb
   %13 = load <4 x i32>, <4 x i32> addrspace(1)* null, align 16
   %14 = extractelement <4 x i32> %node, i64 0
   %cmp4404 = fcmp nsz ole float %1, 0.000000e+00
   %cmp4425 = icmp eq i32 %0, 0
   %or.cond13066 = select i1 %cmp412.old, i1 false, i1 %cmp412.old
   br i1 %or.cond1306, label %if.then443, label %if.else568
 
 if.then443:                                       ; preds = %if.then413
   br i1 true, label %if.end511, label %common.ret
 
 common.ret.critedge:                              ; preds = %entry
   store i32 0, i32* null, align 4
   br label %common.ret
 
-common.ret:                                       ; preds = %if.end.i.i2285, %if.end627.sink.split, %cond.end579, %bsdf_alloc.exit2188, %if.end511, %common.ret.critedge, %if.then443, %sw.bb, %cond.true20, %cond.true
+NewDefault:                                       ; preds = %LeafBlock1, %LeafBlock
+  %phi.store = phi i32 [0, %LeafBlock], [1, %LeafBlock1]
+  store i32 %phi.store, i32* null, align 4
+  br label %common.ret
+
+common.ret:                                       ; preds = %if.end.i.i2285, %if.end627.sink.split, %cond.end579, %bsdf_alloc.exit2188, %if.end511, %common.ret.critedge, %if.then443, %sw.bb, %NewDefault, %cond.true
   ret void
 
 if.end511:                                        ; preds = %if.then443
   br i1 false, label %common.ret, label %if.then519
 
 if.then519:                                       ; preds = %if.end511
   br i1 false, label %bsdf_alloc.exit2188, label %if.then.i2172