[AMDGPU][MC][GFX10] Added helpers for s_waitcnt_depctr operand

[dp]

Summary

Added syntactic sugar for s_waitcnt_depctr:

depctr_hold_cnt(...)
depctr_sa_sdst(...)
depctr_va_vdst(...)
depctr_va_sdst(...)
depctr_va_ssrc(...)
depctr_va_vcc(...)
depctr_vm_vsrc(...)

See https://github.com/llvm/llvm-project/issues/54697

[dp]

Minor improvements and corrections

llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

bool isExpr() const {
     return Kind == Expression;
   }
 
   bool isSoppBrTarget() const {
     return isExpr() || isImm();
   }
 
   bool isSWaitCnt() const;
+  bool isDepCtr() const;
   bool isHwreg() const;
   bool isSendMsg() const;
   bool isSwizzle() const;
   bool isSMRDOffset8() const;
   bool isSMEMOffset() const;
   bool isSMRDLiteralOffset() const;
   bool isDPP8() const;
   bool isDPPCtrl() const;
public:
 
   void cvtDSOffset01(MCInst &Inst, const OperandVector &Operands);
   void cvtDS(MCInst &Inst, const OperandVector &Operands) { cvtDSImpl(Inst, Operands, false); }
   void cvtDSGds(MCInst &Inst, const OperandVector &Operands) { cvtDSImpl(Inst, Operands, true); }
   void cvtExp(MCInst &Inst, const OperandVector &Operands);
 
   bool parseCnt(int64_t &IntVal);
   OperandMatchResultTy parseSWaitCntOps(OperandVector &Operands);
+
+  bool parseDepCtr(int64_t &IntVal, unsigned &Mask);
+  OperandMatchResultTy parseDepCtrOps(OperandVector &Operands);
+
   OperandMatchResultTy parseHwreg(OperandVector &Operands);
 
 private:
   struct OperandInfoTy {
     SMLoc Loc;
     int64_t Id;
     bool IsSymbolic = false;
     bool IsDefined = false;

 }
 
 bool
 AMDGPUOperand::isSWaitCnt() const {
   return isImm();
 }
 
 //===----------------------------------------------------------------------===//
+// DepCtr
+//===----------------------------------------------------------------------===//
+
+bool AMDGPUAsmParser::parseDepCtr(int64_t &DepCtr, unsigned &UsedOprMask) {
+
+  using namespace llvm::AMDGPU::DepCtr;
+
+  SMLoc DepCtrLoc = getLoc();
+  StringRef DepCtrName = getTokenStr();
+
+  if (!skipToken(AsmToken::Identifier, "expected a counter name") ||
+      !skipToken(AsmToken::LParen, "expected a left parenthesis"))
+    return false;
+
+  int64_t ExprVal;
+  SMLoc ExprValLoc = getLoc();
+  if (!parseExpr(ExprVal))
+    return false;
+
+  unsigned PrevOprMask = UsedOprMask;
+  int CntVal = encodeDepCtr(DepCtrName, ExprVal, UsedOprMask, getSTI());
+
+  if (CntVal == OPR_ID_UNKNOWN) {
+    Error(DepCtrLoc, Twine("invalid counter name ", DepCtrName));
+    return false;
+  }
+
+  if (CntVal == OPR_ID_UNSUPPORTED) {
+    Error(DepCtrLoc, "specified counter name is not supported on this GPU");
+    return false;
+  }
+
+  if (CntVal == OPR_ID_DUPLICATE) {
+    Error(DepCtrLoc, Twine("duplicate counter name ", DepCtrName));
+    return false;
+  }
+
+  if (CntVal == OPR_VAL_INVALID) {
+    Error(ExprValLoc, Twine("invalid value for ", DepCtrName));
+    return false;
+  }
+
+  if (!skipToken(AsmToken::RParen, "expected a closing parenthesis"))
+    return false;
+
+  if (trySkipToken(AsmToken::Amp) || trySkipToken(AsmToken::Comma)) {
+    if (isToken(AsmToken::EndOfStatement)) {
+      Error(getLoc(), "expected a counter name");
+      return false;
+    }
+  }
+
+  unsigned CntValMask = PrevOprMask ^ UsedOprMask;
+  DepCtr = (DepCtr & ~CntValMask) | CntVal;
+  return true;
+}
+
+OperandMatchResultTy AMDGPUAsmParser::parseDepCtrOps(OperandVector &Operands) {
+  using namespace llvm::AMDGPU::DepCtr;
+
+  int64_t DepCtr = getDefaultDepCtrEncoding(getSTI());
+  SMLoc Loc = getLoc();
+
+  if (isToken(AsmToken::Identifier) && peekToken().is(AsmToken::LParen)) {
+    unsigned UsedOprMask = 0;
+    while (!isToken(AsmToken::EndOfStatement)) {
+      if (!parseDepCtr(DepCtr, UsedOprMask))
+        return MatchOperand_ParseFail;
+    }
+  } else {
+    if (!parseExpr(DepCtr))
+      return MatchOperand_ParseFail;
+  }
+
+  Operands.push_back(AMDGPUOperand::CreateImm(this, DepCtr, Loc));
+  return MatchOperand_Success;
+}
+
+bool AMDGPUOperand::isDepCtr() const { return isS16Imm(); }
+
+//===----------------------------------------------------------------------===//
 // hwreg
 //===----------------------------------------------------------------------===//
 
 bool
 AMDGPUAsmParser::parseHwregBody(OperandInfoTy &HwReg,
                                 OperandInfoTy &Offset,
                                 OperandInfoTy &Width) {
   using namespace llvm::AMDGPU::Hwreg;

llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h

protected:
   void printKCache(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
                    raw_ostream &O);
   void printSendMsg(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
                     raw_ostream &O);
   void printSwizzle(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
                     raw_ostream &O);
   void printWaitFlag(const MCInst *MI, unsigned OpNo,
                      const MCSubtargetInfo &STI, raw_ostream &O);
+  void printDepCtr(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
+                   raw_ostream &O);
   void printHwreg(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
                   raw_ostream &O);
   void printEndpgm(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
                    raw_ostream &O);
 };
 
 } // End namespace llvm
 
 #endif

llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp

void AMDGPUInstPrinter::printWaitFlag(const MCInst *MI, unsigned OpNo,
 
   if (!IsDefaultLgkmcnt || PrintAll) {
     if (NeedSpace)
       O << ' ';
     O << "lgkmcnt(" << Lgkmcnt << ')';
   }
 }
 
+void AMDGPUInstPrinter::printDepCtr(const MCInst *MI, unsigned OpNo,
+                                    const MCSubtargetInfo &STI,
+                                    raw_ostream &O) {
+  using namespace llvm::AMDGPU::DepCtr;
+
+  uint64_t Imm16 = MI->getOperand(OpNo).getImm() & 0xffff;
+
+  bool HasNonDefaultVal = false;
+  if (isSymbolicDepCtrEncoding(Imm16, HasNonDefaultVal, STI)) {
+    int Id = 0;
+    StringRef Name;
+    unsigned Val;
+    bool IsDefault;
+    bool NeedSpace = false;
+    while (decodeDepCtr(Imm16, Id, Name, Val, IsDefault, STI)) {
+      if (!IsDefault || !HasNonDefaultVal) {
+        if (NeedSpace)
+          O << ' ';
+        O << Name << '(' << Val << ')';
+        NeedSpace = true;
+      }
+    }
+  } else {
+    O << formatHex(Imm16);
+  }
+}
+
 void AMDGPUInstPrinter::printHwreg(const MCInst *MI, unsigned OpNo,
                                    const MCSubtargetInfo &STI, raw_ostream &O) {
   unsigned Id;
   unsigned Offset;
   unsigned Width;
 
   using namespace llvm::AMDGPU::Hwreg;
   unsigned Val = MI->getOperand(OpNo).getImm();

llvm/lib/Target/AMDGPU/SIInstrInfo.td

 }
 
 def SWaitMatchClass : AsmOperandClass {
   let Name = "SWaitCnt";
   let RenderMethod = "addImmOperands";
   let ParserMethod = "parseSWaitCntOps";
 }
 
+def DepCtrMatchClass : AsmOperandClass {
+  let Name = "DepCtr";
+  let RenderMethod = "addImmOperands";
+  let ParserMethod = "parseDepCtrOps";
+}
+
 def VReg32OrOffClass : AsmOperandClass {
   let Name = "VReg32OrOff";
   let ParserMethod = "parseVReg32OrOff";
 }
 
 let OperandType = "OPERAND_IMMEDIATE" in {
 def SendMsgImm : Operand<i32> {
   let PrintMethod = "printSendMsg";
def EndpgmImm : Operand<i16> {
   let PrintMethod = "printEndpgm";
   let ParserMatchClass = EndpgmMatchClass;
 }
 
 def WAIT_FLAG : Operand <i32> {
   let ParserMatchClass = SWaitMatchClass;
   let PrintMethod = "printWaitFlag";
 }
+
+def DepCtrImm : Operand <i32> {
+  let ParserMatchClass = DepCtrMatchClass;
+  let PrintMethod = "printDepCtr";
+}
 } // End OperandType = "OPERAND_IMMEDIATE"
 
 include "SIInstrFormats.td"
 include "VIInstrFormats.td"
 
 def BoolReg : AsmOperandClass {
   let Name = "BoolReg";
   let ParserMethod = "parseBoolReg";

llvm/lib/Target/AMDGPU/SOPInstructions.td

let SubtargetPredicate = isGFX10Plus in {
   def S_CLAUSE :
     SOPP_Pseudo<"s_clause", (ins s16imm:$simm16), "$simm16">;
   def S_WAIT_IDLE :
     SOPP_Pseudo <"s_wait_idle", (ins), ""> {
       let simm16 = 0;
       let fixed_imm = 1;
     }
   def S_WAITCNT_DEPCTR :
-    SOPP_Pseudo <"s_waitcnt_depctr" , (ins s16imm:$simm16), "$simm16">;
+    SOPP_Pseudo <"s_waitcnt_depctr" , (ins DepCtrImm:$simm16), "$simm16">;
 
   let hasSideEffects = 0, Uses = [MODE], Defs = [MODE] in {
     def S_ROUND_MODE :
       SOPP_Pseudo<"s_round_mode", (ins s16imm:$simm16), "$simm16">;
     def S_DENORM_MODE :
       SOPP_Pseudo<"s_denorm_mode", (ins i32imm:$simm16), "$simm16",
       [(SIdenorm_mode (i32 timm:$simm16))]>;
   }

llvm/lib/Target/AMDGPU/Utils/AMDGPUAsmUtils.h

 
 class StringLiteral;
 class MCSubtargetInfo;
 
 namespace AMDGPU {
 
 const int OPR_ID_UNKNOWN = -1;
 const int OPR_ID_UNSUPPORTED = -2;
+const int OPR_ID_DUPLICATE = -3;
+const int OPR_VAL_INVALID = -4;
 
 template <class T> struct CustomOperand {
   StringLiteral Name;
   int Encoding = 0;
   bool (*Cond)(T Context) = nullptr;
 };
 
+struct CustomOperandVal {
+  StringLiteral Name;
+  unsigned Max;
+  unsigned Default;
+  unsigned Shift;
+  unsigned Width;
+  bool (*Cond)(const MCSubtargetInfo &STI) = nullptr;
+  unsigned Mask = (1 << Width) - 1;
+
+  unsigned decode(unsigned Code) const { return (Code >> Shift) & Mask; }
+
+  unsigned encode(unsigned Val) const { return (Val & Mask) << Shift; }
+
+  unsigned getMask() const { return Mask << Shift; }
+
+  bool isValid(unsigned Val) const { return Val <= Max; }
+
+  bool isSupported(const MCSubtargetInfo &STI) const {
+    return !Cond || Cond(STI);
+  }
+};
+
+namespace DepCtr {
+
+extern const CustomOperandVal DepCtrInfo[];
+extern const int DEP_CTR_SIZE;
+
+} // namespace DepCtr
+
 namespace SendMsg { // Symbolic names for the sendmsg(...) syntax.
 
 extern const CustomOperand<const MCSubtargetInfo &> Msg[];
 extern const int MSG_SIZE;
 
 extern const char *const OpSysSymbolic[OP_SYS_LAST_];
 extern const char *const OpGsSymbolic[OP_GS_LAST_];
 

llvm/lib/Target/AMDGPU/Utils/AMDGPUAsmUtils.cpp

 //===-- AMDGPUAsmUtils.cpp - AsmParser/InstPrinter common -----------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 #include "AMDGPUAsmUtils.h"
 #include "AMDGPUBaseInfo.h"
 #include "SIDefines.h"
 
 namespace llvm {
 namespace AMDGPU {
+
+namespace DepCtr {
+
+// NOLINTBEGIN
+const CustomOperandVal DepCtrInfo[] = {
+  // Name               max dflt offset width  constraint
+  {{"depctr_hold_cnt"},  1,   1,    7,    1,   isGFX10_BEncoding},
+  {{"depctr_sa_sdst"},   1,   1,    0,    1},
+  {{"depctr_va_vdst"},  15,  15,   12,    4},
+  {{"depctr_va_sdst"},   7,   7,    9,    3},
+  {{"depctr_va_ssrc"},   1,   1,    8,    1},
+  {{"depctr_va_vcc"},    1,   1,    1,    1},
+  {{"depctr_vm_vsrc"},   7,   7,    2,    3},
+};
+// NOLINTEND
+
+const int DEP_CTR_SIZE =
+    static_cast<int>(sizeof(DepCtrInfo) / sizeof(CustomOperandVal));
+
+} // namespace DepCtr
+
 namespace SendMsg {
 
 // Disable lint checking for this block since it makes the table unreadable.
 // NOLINTBEGIN
 const CustomOperand<const MCSubtargetInfo &> Msg[] = {
   {{""}},
   {{"MSG_INTERRUPT"},           ID_INTERRUPT},
   {{"MSG_GS"},                  ID_GS},

llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h

 
 LLVM_READNONE
 StringRef getHwreg(unsigned Id, const MCSubtargetInfo &STI);
 
 void decodeHwreg(unsigned Val, unsigned &Id, unsigned &Offset, unsigned &Width);
 
 } // namespace Hwreg
 
+namespace DepCtr {
+
+int getDefaultDepCtrEncoding(const MCSubtargetInfo &STI);
+int encodeDepCtr(const StringRef Name, int64_t Val, unsigned &UsedOprMask,
+                 const MCSubtargetInfo &STI);
+bool isSymbolicDepCtrEncoding(unsigned Code, bool &HasNonDefaultVal,
+                              const MCSubtargetInfo &STI);
+bool decodeDepCtr(unsigned Code, int &Id, StringRef &Name, unsigned &Val,
+                  bool &IsDefault, const MCSubtargetInfo &STI);
+
+} // namespace DepCtr
+
 namespace Exp {
 
 bool getTgtName(unsigned Id, StringRef &Name, int &Index);
 
 LLVM_READONLY
 unsigned getTgtId(const StringRef Name);
 
 LLVM_READNONE

llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp

static int getOprIdx(int Id, const CustomOperand<T> OpInfo[], int OpInfoSize,
   if (QuickCheck && isValidOpr<T>(Id, OpInfo, OpInfoSize, Context) &&
       OpInfo[Id].Encoding == Id) {
     return Id;
   }
   return getOprIdx<T>(Test, OpInfo, OpInfoSize, Context);
 }
 
 //===----------------------------------------------------------------------===//
+// Custom Operand Values
+//===----------------------------------------------------------------------===//
+
+static unsigned getDefaultCustomOperandEncoding(const CustomOperandVal *Opr,
+                                                int Size,
+                                                const MCSubtargetInfo &STI) {
+  unsigned Enc = 0;
+  for (int Idx = 0; Idx < Size; ++Idx) {
+    if (Opr[Idx].isSupported(STI))
+      Enc |= Opr[Idx].encode(Opr[Idx].Default);
+  }
+  return Enc;
+}
+
+static bool isSymbolicCustomOperandEncoding(const CustomOperandVal *Opr,
+                                            int Size, unsigned Code,
+                                            bool &HasNonDefaultVal,
+                                            const MCSubtargetInfo &STI) {
+  unsigned UsedOprMask = 0;
+  HasNonDefaultVal = false;
+  for (int Idx = 0; Idx < Size; ++Idx) {
+    if (!Opr[Idx].isSupported(STI))
+      continue;
+    UsedOprMask |= Opr[Idx].getMask();
+    unsigned Val = Opr[Idx].decode(Code);
+    if (!Opr[Idx].isValid(Val))
+      return false;
+    HasNonDefaultVal |= (Val != Opr[Idx].Default);
+  }
+  return (Code & ~UsedOprMask) == 0;
+}
+
+static bool decodeCustomOperand(const CustomOperandVal *Opr, int Size,
+                                unsigned Code, int &Idx, StringRef &Name,
+                                unsigned &Val, bool &IsDefault,
+                                const MCSubtargetInfo &STI) {
+  while (Idx < Size) {
+    const auto &Op = Opr[Idx++];
+    if (Op.isSupported(STI)) {
+      Name = Op.Name;
+      Val = Op.decode(Code);
+      IsDefault = (Val == Op.Default);
+      return true;
+    }
+  }
+
+  return false;
+}
+
+static int encodeCustomOperandVal(const CustomOperandVal &Opr,
+                                  int64_t InputVal) {
+  if (InputVal < 0 || InputVal > Opr.Max)
+    return OPR_VAL_INVALID;
+  return Opr.encode(InputVal);
+}
+
+static int encodeCustomOperand(const CustomOperandVal *Opr, int Size,
+                               const StringRef Name, int64_t InputVal,
+                               unsigned &UsedOprMask,
+                               const MCSubtargetInfo &STI) {
+  int InvalidId = OPR_ID_UNKNOWN;
+  for (int Idx = 0; Idx < Size; ++Idx) {
+    const auto &Op = Opr[Idx];
+    if (Op.Name == Name) {
+      if (!Op.isSupported(STI)) {
+        InvalidId = OPR_ID_UNSUPPORTED;
+        continue;
+      }
+      auto OprMask = Op.getMask();
+      if (OprMask & UsedOprMask)
+        return OPR_ID_DUPLICATE;
+      UsedOprMask |= OprMask;
+      return encodeCustomOperandVal(Op, InputVal);
+    }
+  }
+  return InvalidId;
+}
+
+//===----------------------------------------------------------------------===//
+// DepCtr
+//===----------------------------------------------------------------------===//
+
+namespace DepCtr {
+
+int getDefaultDepCtrEncoding(const MCSubtargetInfo &STI) {
+  static int Default = -1;
+  if (Default == -1)
+    Default = getDefaultCustomOperandEncoding(DepCtrInfo, DEP_CTR_SIZE, STI);
+  return Default;
+}
+
+bool isSymbolicDepCtrEncoding(unsigned Code, bool &HasNonDefaultVal,
+                              const MCSubtargetInfo &STI) {
+  return isSymbolicCustomOperandEncoding(DepCtrInfo, DEP_CTR_SIZE, Code,
+                                         HasNonDefaultVal, STI);
+}
+
+bool decodeDepCtr(unsigned Code, int &Id, StringRef &Name, unsigned &Val,
+                  bool &IsDefault, const MCSubtargetInfo &STI) {
+  return decodeCustomOperand(DepCtrInfo, DEP_CTR_SIZE, Code, Id, Name, Val,
+                             IsDefault, STI);
+}
+
+int encodeDepCtr(const StringRef Name, int64_t Val, unsigned &UsedOprMask,
+                 const MCSubtargetInfo &STI) {
+  return encodeCustomOperand(DepCtrInfo, DEP_CTR_SIZE, Name, Val, UsedOprMask,
+                             STI);
+}
+
+} // namespace DepCtr
+
+//===----------------------------------------------------------------------===//
 // hwreg
 //===----------------------------------------------------------------------===//
 
 namespace Hwreg {
 
 int64_t getHwregId(const StringRef Name, const MCSubtargetInfo &STI) {
   int Idx = getOprIdx<const MCSubtargetInfo &>(Name, Opr, OPR_SIZE, STI);
   return (Idx < 0) ? Idx : Opr[Idx].Encoding;

llvm/test/MC/AMDGPU/gfx1030_err.s

 global_atomic_csub v2, v[0:1], v2, off offset:100 slc
 // GFX10: :[[@LINE-1]]:{{[0-9]+}}: error: instruction must use glc
 
 image_msaa_load v[1:4], v5, s[8:15] dmask:0xf dim:SQ_RSRC_IMG_1D
 // GFX10: :[[@LINE-1]]:{{[0-9]+}}: error: invalid dim; must be MSAA type
 
 image_msaa_load v5, v[1:2], s[8:15] dmask:0x1 dim:SQ_RSRC_IMG_2D d16
 // GFX10: :[[@LINE-1]]:{{[0-9]+}}: error: invalid dim; must be MSAA type
+
+//===----------------------------------------------------------------------===//
+// s_waitcnt_depctr.
+//===----------------------------------------------------------------------===//
+
+s_waitcnt_depctr depctr_hold_cnt(-1)
+// GFX10: :[[@LINE-1]]:{{[0-9]+}}: error: invalid value for depctr_hold_cnt
+
+s_waitcnt_depctr depctr_sa_sdst(-1)
+// GFX10: :[[@LINE-1]]:{{[0-9]+}}: error: invalid value for depctr_sa_sdst
+
+s_waitcnt_depctr depctr_va_vdst(-1)
+// GFX10: :[[@LINE-1]]:{{[0-9]+}}: error: invalid value for depctr_va_vdst
+
+s_waitcnt_depctr depctr_va_sdst(-1)
+// GFX10: :[[@LINE-1]]:{{[0-9]+}}: error: invalid value for depctr_va_sdst
+
+s_waitcnt_depctr depctr_va_ssrc(-1)
+// GFX10: :[[@LINE-1]]:{{[0-9]+}}: error: invalid value for depctr_va_ssrc
+
+s_waitcnt_depctr depctr_va_vcc(-1)
+// GFX10: :[[@LINE-1]]:{{[0-9]+}}: error: invalid value for depctr_va_vcc
+
+s_waitcnt_depctr depctr_vm_vsrc(-1)
+// GFX10: :[[@LINE-1]]:{{[0-9]+}}: error: invalid value for depctr_vm_vsrc
+
+s_waitcnt_depctr depctr_hold_cnt(2)
+// GFX10: :[[@LINE-1]]:{{[0-9]+}}: error: invalid value for depctr_hold_cnt
+
+s_waitcnt_depctr depctr_sa_sdst(2)
+// GFX10: :[[@LINE-1]]:{{[0-9]+}}: error: invalid value for depctr_sa_sdst
+
+s_waitcnt_depctr depctr_va_vdst(16)
+// GFX10: :[[@LINE-1]]:{{[0-9]+}}: error: invalid value for depctr_va_vdst
+
+s_waitcnt_depctr depctr_va_sdst(8)
+// GFX10: :[[@LINE-1]]:{{[0-9]+}}: error: invalid value for depctr_va_sdst
+
+s_waitcnt_depctr depctr_va_ssrc(2)
+// GFX10: :[[@LINE-1]]:{{[0-9]+}}: error: invalid value for depctr_va_ssrc
+
+s_waitcnt_depctr depctr_va_vcc(2)
+// GFX10: :[[@LINE-1]]:{{[0-9]+}}: error: invalid value for depctr_va_vcc
+
+s_waitcnt_depctr depctr_vm_vsrc(8)
+// GFX10: :[[@LINE-1]]:{{[0-9]+}}: error: invalid value for depctr_vm_vsrc
+
+s_waitcnt_depctr depctr_vm_(8)
+// GFX10: :[[@LINE-1]]:{{[0-9]+}}: error: invalid counter name depctr_vm_
+
+s_waitcnt_depctr depctr_hold_cnt(0) depctr_hold_cnt(0)
+// GFX10: :[[@LINE-1]]:{{[0-9]+}}: error: duplicate counter name depctr_hold_cnt
+
+s_waitcnt_depctr depctr_sa_sdst(0) depctr_sa_sdst(0)
+// GFX10: :[[@LINE-1]]:{{[0-9]+}}: error: duplicate counter name depctr_sa_sdst

llvm/test/MC/AMDGPU/gfx1030_new.s

 image_msaa_load v5, v[1:3], s[8:15] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA d16
 // GFX10: encoding: [0x31,0x01,0x00,0xf0,0x01,0x05,0x02,0x80]
 
 image_msaa_load v[1:4], v[5:8], s[8:15] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA_ARRAY
 // GFX10: encoding: [0x39,0x0f,0x00,0xf0,0x05,0x01,0x02,0x00]
 
 image_msaa_load v14, [v204,v11,v14,v19], s[40:47] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY
 // GFX10: encoding: [0x3b,0x01,0x00,0xf0,0xcc,0x0e,0x0a,0x00,0x0b,0x0e,0x13,0x00]
+
+//===----------------------------------------------------------------------===//
+// s_waitcnt_depctr.
+//===----------------------------------------------------------------------===//
+
+s_waitcnt_depctr -32768
+// GFX10: encoding: [0x00,0x80,0xa3,0xbf]
+
+s_waitcnt_depctr 65535
+// GFX10: encoding: [0xff,0xff,0xa3,0xbf]
+
+s_waitcnt_depctr depctr_hold_cnt(0)
+// GFX10: encoding: [0x1f,0xff,0xa3,0xbf]
+
+s_waitcnt_depctr depctr_hold_cnt(1)
+// GFX10: encoding: [0x9f,0xff,0xa3,0xbf]
+
+s_waitcnt_depctr depctr_sa_sdst(0)
+// GFX10: encoding: [0x9e,0xff,0xa3,0xbf]
+
+s_waitcnt_depctr depctr_sa_sdst(1)
+// GFX10: encoding: [0x9f,0xff,0xa3,0xbf]
+
+s_waitcnt_depctr depctr_va_vdst(0)
+// GFX10: encoding: [0x9f,0x0f,0xa3,0xbf]
+
+s_waitcnt_depctr depctr_va_vdst(1)
+// GFX10: encoding: [0x9f,0x1f,0xa3,0xbf]
+
+s_waitcnt_depctr depctr_va_vdst(14)
+// GFX10: encoding: [0x9f,0xef,0xa3,0xbf]
+
+s_waitcnt_depctr depctr_va_vdst(15)
+// GFX10: encoding: [0x9f,0xff,0xa3,0xbf]
+
+s_waitcnt_depctr depctr_va_sdst(0)
+// GFX10: encoding: [0x9f,0xf1,0xa3,0xbf]
+
+s_waitcnt_depctr depctr_va_sdst(1)
+// GFX10: encoding: [0x9f,0xf3,0xa3,0xbf]
+
+s_waitcnt_depctr depctr_va_sdst(6)
+// GFX10: encoding: [0x9f,0xfd,0xa3,0xbf]
+
+s_waitcnt_depctr depctr_va_sdst(7)
+// GFX10: encoding: [0x9f,0xff,0xa3,0xbf]
+
+s_waitcnt_depctr depctr_va_ssrc(0)
+// GFX10: encoding: [0x9f,0xfe,0xa3,0xbf]
+
+s_waitcnt_depctr depctr_va_ssrc(1)
+// GFX10: encoding: [0x9f,0xff,0xa3,0xbf]
+
+s_waitcnt_depctr depctr_va_vcc(0)
+// GFX10: encoding: [0x9d,0xff,0xa3,0xbf]
+
+s_waitcnt_depctr depctr_va_vcc(1)
+// GFX10: encoding: [0x9f,0xff,0xa3,0xbf]
+
+s_waitcnt_depctr depctr_vm_vsrc(0)
+// GFX10: encoding: [0x83,0xff,0xa3,0xbf]
+
+s_waitcnt_depctr depctr_vm_vsrc(1)
+// GFX10: encoding: [0x87,0xff,0xa3,0xbf]
+
+s_waitcnt_depctr depctr_vm_vsrc(6)
+// GFX10: encoding: [0x9b,0xff,0xa3,0xbf]
+
+s_waitcnt_depctr depctr_vm_vsrc(7)
+// GFX10: encoding: [0x9f,0xff,0xa3,0xbf]
+
+s_waitcnt_depctr depctr_hold_cnt(0) depctr_sa_sdst(0) depctr_va_vdst(0) depctr_va_sdst(0) depctr_va_ssrc(0) depctr_va_vcc(0) depctr_vm_vsrc(0)
+// GFX10: encoding: [0x00,0x00,0xa3,0xbf]
+
+s_waitcnt_depctr depctr_hold_cnt(1) depctr_sa_sdst(1) depctr_va_vdst(15) depctr_va_sdst(7) depctr_va_ssrc(1) depctr_va_vcc(1) depctr_vm_vsrc(7)
+// GFX10: encoding: [0x9f,0xff,0xa3,0xbf]
+
+s_waitcnt_depctr depctr_hold_cnt(1) & depctr_sa_sdst(1) & depctr_va_vdst(1) & depctr_va_sdst(1) & depctr_va_ssrc(1) & depctr_va_vcc(1) & depctr_vm_vsrc(1)
+// GFX10: encoding: [0x87,0x13,0xa3,0xbf]
+
+s_waitcnt_depctr depctr_hold_cnt(1), depctr_sa_sdst(1), depctr_va_vdst(14), depctr_va_sdst(6), depctr_va_ssrc(1), depctr_va_vcc(1), depctr_vm_vsrc(6)
+// GFX10: encoding: [0x9b,0xed,0xa3,0xbf]

llvm/test/MC/AMDGPU/sopp-err.s

-// RUN: not llvm-mc -arch=amdgcn %s 2>&1 | FileCheck --check-prefixes=GCN,SICI --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti %s 2>&1 | FileCheck --check-prefixes=GCN,SICI --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=fiji %s 2>&1 | FileCheck --check-prefixes=GCN,VI --implicit-check-not=error: %s
+// RUN: not llvm-mc -arch=amdgcn %s 2>&1 | FileCheck --check-prefixes=GCN,SICI,SICIVI --implicit-check-not=error: %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti %s 2>&1 | FileCheck --check-prefixes=GCN,SICI,SICIVI --implicit-check-not=error: %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=fiji %s 2>&1 | FileCheck --check-prefixes=GCN,VI,SICIVI --implicit-check-not=error: %s
 // RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 %s 2>&1 | FileCheck --check-prefixes=GCN,GFX10 --implicit-check-not=error: %s
 
 //===----------------------------------------------------------------------===//
 // sendmsg
 //===----------------------------------------------------------------------===//
 
 s_sendmsg sendmsg(MSG_INTERRUPTX)
 // GCN: error: expected a message name or an absolute expression

 // GCN: error: expected absolute expression
 
 s_waitcnt x
 // GCN: error: expected absolute expression
 
 s_waitcnt vmcnt(0
 // GCN: error: expected a closing parenthesis
 
+//===----------------------------------------------------------------------===//
+// s_waitcnt_depctr.
+//===----------------------------------------------------------------------===//
+
+s_waitcnt_depctr 65536
+// GFX10: error: invalid operand for instruction
+// SICIVI: error: instruction not supported on this GPU
+
+s_waitcnt_depctr -32769
+// GFX10: error: invalid operand for instruction
+// SICIVI: error: instruction not supported on this GPU
+
+s_waitcnt_depctr depctr_hold_cnt(0)
+// GFX10: error: specified counter name is not supported on this GPU
+// SICIVI: error: instruction not supported on this GPU
+
+s_waitcnt_depctr depctr_sa_sdst(-1)
+// GFX10: error: invalid value for depctr_sa_sdst
+// SICIVI: error: instruction not supported on this GPU
+
+s_waitcnt_depctr depctr_va_vdst(-1)
+// GFX10: error: invalid value for depctr_va_vdst
+// SICIVI: error: instruction not supported on this GPU
+
+s_waitcnt_depctr depctr_va_sdst(-1)
+// GFX10: error: invalid value for depctr_va_sdst
+// SICIVI: error: instruction not supported on this GPU
+
+s_waitcnt_depctr depctr_va_ssrc(-1)
+// GFX10: error: invalid value for depctr_va_ssrc
+// SICIVI: error: instruction not supported on this GPU
+
+s_waitcnt_depctr depctr_va_vcc(-1)
+// GFX10: error: invalid value for depctr_va_vcc
+// SICIVI: error: instruction not supported on this GPU
+
+s_waitcnt_depctr depctr_vm_vsrc(-1)
+// GFX10: error: invalid value for depctr_vm_vsrc
+// SICIVI: error: instruction not supported on this GPU
+
+s_waitcnt_depctr depctr_sa_sdst(2)
+// GFX10: error: invalid value for depctr_sa_sdst
+// SICIVI: error: instruction not supported on this GPU
+
+s_waitcnt_depctr depctr_va_vdst(16)
+// GFX10: error: invalid value for depctr_va_vdst
+// SICIVI: error: instruction not supported on this GPU
+
+s_waitcnt_depctr depctr_va_sdst(8)
+// GFX10: error: invalid value for depctr_va_sdst
+// SICIVI: error: instruction not supported on this GPU
+
+s_waitcnt_depctr depctr_va_ssrc(2)
+// GFX10: error: invalid value for depctr_va_ssrc
+// SICIVI: error: instruction not supported on this GPU
+
+s_waitcnt_depctr depctr_va_vcc(2)
+// GFX10: error: invalid value for depctr_va_vcc
+// SICIVI: error: instruction not supported on this GPU
+
+s_waitcnt_depctr depctr_vm_vsrc(8)
+// GFX10: error: invalid value for depctr_vm_vsrc
+// SICIVI: error: instruction not supported on this GPU
+
+s_waitcnt_depctr depctr_vm_(8)
+// GFX10: error: invalid counter name depctr_vm_
+// SICIVI: error: instruction not supported on this GPU
+
+s_waitcnt_depctr depctr_sa_sdst(0) depctr_sa_sdst(0)
+// GFX10: error: duplicate counter name depctr_sa_sdst
+// SICIVI: error: instruction not supported on this GPU
+
+s_waitcnt_depctr depctr_va_vdst(0) depctr_va_vdst(0)
+// GFX10: error: duplicate counter name depctr_va_vdst
+// SICIVI: error: instruction not supported on this GPU
+
+s_waitcnt_depctr depctr_va_sdst(0) depctr_va_sdst(0)
+// GFX10: error: duplicate counter name depctr_va_sdst
+// SICIVI: error: instruction not supported on this GPU
+
+s_waitcnt_depctr depctr_va_ssrc(0) depctr_va_ssrc(0)
+// GFX10: error: duplicate counter name depctr_va_ssrc
+// SICIVI: error: instruction not supported on this GPU
+
+s_waitcnt_depctr depctr_va_vcc(0) depctr_va_vcc(0)
+// GFX10: error: duplicate counter name depctr_va_vcc
+// SICIVI: error: instruction not supported on this GPU
+
+s_waitcnt_depctr depctr_vm_vsrc(0) depctr_vm_vsrc(0)
+// GFX10: error: duplicate counter name depctr_vm_vsrc
+// SICIVI: error: instruction not supported on this GPU
+
+s_waitcnt_depctr depctr_sa_sdst(0) depctr_va_sdst(0) depctr_sa_sdst(0)
+// GFX10: error: duplicate counter name depctr_sa_sdst
+// SICIVI: error: instruction not supported on this GPU
+
+s_waitcnt_depctr depctr_va_ssrc(0) depctr_va_sdst(0) depctr_va_ssrc(0)
+// GFX10: error: duplicate counter name depctr_va_ssrc
+// SICIVI: error: instruction not supported on this GPU
+
+s_waitcnt_depctr depctr_va_vcc(0) depctr_va_vcc(0) depctr_va_sdst(0)
+// GFX10: error: duplicate counter name depctr_va_vcc
+// SICIVI: error: instruction not supported on this GPU
+
+s_waitcnt_depctr depctr_vm_vsrc(0) depctr_vm_vsrc(0) depctr_va_sdst(0)
+// GFX10: error: duplicate counter name depctr_vm_vsrc
+// SICIVI: error: instruction not supported on this GPU
+
+s_waitcnt_depctr depctr_va_sdst(0) depctr_vm_vsrc 0)
+// GFX10: error: expected a left parenthesis
+// SICIVI: error: instruction not supported on this GPU
+
+s_waitcnt_depctr depctr_va_sdst(0) 0depctr_vm_vsrc(0)
+// GFX10: error: expected a counter name
+// SICIVI: error: instruction not supported on this GPU
+
+s_waitcnt_depctr depctr_va_sdst(0) depctr_vm_vsrc(x)
+// GFX10: error: expected absolute expression
+// SICIVI: error: instruction not supported on this GPU
+
+s_waitcnt_depctr depctr_va_sdst(0) depctr_vm_vsrc(0; & depctr_va_sdst(0)
+// GFX10: error: expected a closing parenthesis
+// SICIVI: error: instruction not supported on this GPU
+
+s_waitcnt_depctr depctr_vm_vsrc 0) depctr_vm_vsrc(0) depctr_va_sdst(0)
+// GFX10: error: expected absolute expression
+// SICIVI: error: instruction not supported on this GPU
+
+s_waitcnt_depctr depctr_vm_vsrc(0) ,
+// GFX10: error: expected a counter name
+// SICIVI: error: instruction not supported on this GPU
+
+s_waitcnt_depctr depctr_vm_vsrc(0) , &
+// GFX10: error: expected a counter name
+// SICIVI: error: instruction not supported on this GPU
+
+s_waitcnt_depctr depctr_vm_vsrc(0) &
+// GFX10: error: expected a counter name
+// SICIVI: error: instruction not supported on this GPU
+
+s_waitcnt_depctr depctr_vm_vsrc(0) & &
+// GFX10: error: expected a counter name
+// SICIVI: error: instruction not supported on this GPU
+
+//===----------------------------------------------------------------------===//
+// s_branch.
+//===----------------------------------------------------------------------===//
+
 s_branch 0x80000000ffff
 // GCN: error: expected a 16-bit signed jump offset
 
 s_branch 0x10000
 // GCN: error: expected a 16-bit signed jump offset
 
 s_branch -32769
 // GCN: error: expected a 16-bit signed jump offset

llvm/test/MC/AMDGPU/sopp-gfx10.s

 s_sendmsg sendmsg(MSG_GET_DOORBELL)
 // GFX10: s_sendmsg sendmsg(MSG_GET_DOORBELL) ; encoding: [0x0a,0x00,0x90,0xbf]
 
 s_sendmsg 11
 // GFX10: s_sendmsg sendmsg(MSG_GET_DDID) ; encoding: [0x0b,0x00,0x90,0xbf]
 
 s_sendmsg sendmsg(MSG_GET_DDID)
 // GFX10: s_sendmsg sendmsg(MSG_GET_DDID) ; encoding: [0x0b,0x00,0x90,0xbf]
+
+//===----------------------------------------------------------------------===//
+// s_waitcnt_depctr
+//===----------------------------------------------------------------------===//
+
+s_waitcnt_depctr 0x0
+// GFX10: encoding: [0x00,0x00,0xa3,0xbf]
+
+s_waitcnt_depctr -32768
+// GFX10: encoding: [0x00,0x80,0xa3,0xbf]
+
+s_waitcnt_depctr -1
+// GFX10: encoding: [0xff,0xff,0xa3,0xbf]
+
+s_waitcnt_depctr 65535
+// GFX10: encoding: [0xff,0xff,0xa3,0xbf]
+
+s_waitcnt_depctr 0xffff
+// GFX10: encoding: [0xff,0xff,0xa3,0xbf]
+
+s_waitcnt_depctr depctr_sa_sdst(0)
+// GFX10: s_waitcnt_depctr depctr_sa_sdst(0) ; encoding: [0x1e,0xff,0xa3,0xbf]
+
+s_waitcnt_depctr depctr_sa_sdst(1)
+// GFX10: s_waitcnt_depctr depctr_sa_sdst(1) depctr_va_vdst(15) depctr_va_sdst(7) depctr_va_ssrc(1) depctr_va_vcc(1) depctr_vm_vsrc(7) ; encoding: [0x1f,0xff,0xa3,0xbf]
+
+s_waitcnt_depctr depctr_va_vdst(0)
+// GFX10: s_waitcnt_depctr depctr_va_vdst(0) ; encoding: [0x1f,0x0f,0xa3,0xbf]
+
+s_waitcnt_depctr depctr_va_vdst(1)
+// GFX10: s_waitcnt_depctr depctr_va_vdst(1) ; encoding: [0x1f,0x1f,0xa3,0xbf]
+
+s_waitcnt_depctr depctr_va_vdst(14)
+// GFX10: s_waitcnt_depctr depctr_va_vdst(14) ; encoding: [0x1f,0xef,0xa3,0xbf]
+
+s_waitcnt_depctr depctr_va_vdst(15)
+// GFX10: s_waitcnt_depctr depctr_sa_sdst(1) depctr_va_vdst(15) depctr_va_sdst(7) depctr_va_ssrc(1) depctr_va_vcc(1) depctr_vm_vsrc(7) ; encoding: [0x1f,0xff,0xa3,0xbf]
+
+s_waitcnt_depctr depctr_va_sdst(0)
+// GFX10: s_waitcnt_depctr depctr_va_sdst(0) ; encoding: [0x1f,0xf1,0xa3,0xbf]
+
+s_waitcnt_depctr depctr_va_sdst(1)
+// GFX10: s_waitcnt_depctr depctr_va_sdst(1) ; encoding: [0x1f,0xf3,0xa3,0xbf]
+
+s_waitcnt_depctr depctr_va_sdst(6)
+// GFX10: s_waitcnt_depctr depctr_va_sdst(6) ; encoding: [0x1f,0xfd,0xa3,0xbf]
+
+s_waitcnt_depctr depctr_va_sdst(7)
+// GFX10: s_waitcnt_depctr depctr_sa_sdst(1) depctr_va_vdst(15) depctr_va_sdst(7) depctr_va_ssrc(1) depctr_va_vcc(1) depctr_vm_vsrc(7) ; encoding: [0x1f,0xff,0xa3,0xbf]
+
+s_waitcnt_depctr depctr_va_ssrc(0)
+// GFX10: s_waitcnt_depctr depctr_va_ssrc(0) ; encoding: [0x1f,0xfe,0xa3,0xbf]
+
+s_waitcnt_depctr depctr_va_ssrc(1)
+// GFX10: s_waitcnt_depctr depctr_sa_sdst(1) depctr_va_vdst(15) depctr_va_sdst(7) depctr_va_ssrc(1) depctr_va_vcc(1) depctr_vm_vsrc(7) ; encoding: [0x1f,0xff,0xa3,0xbf]
+
+s_waitcnt_depctr depctr_va_vcc(0)
+// GFX10: s_waitcnt_depctr depctr_va_vcc(0) ; encoding: [0x1d,0xff,0xa3,0xbf]
+
+s_waitcnt_depctr depctr_va_vcc(1)
+// GFX10: s_waitcnt_depctr depctr_sa_sdst(1) depctr_va_vdst(15) depctr_va_sdst(7) depctr_va_ssrc(1) depctr_va_vcc(1) depctr_vm_vsrc(7) ; encoding: [0x1f,0xff,0xa3,0xbf]
+
+s_waitcnt_depctr depctr_vm_vsrc(0)
+// GFX10: s_waitcnt_depctr depctr_vm_vsrc(0) ; encoding: [0x03,0xff,0xa3,0xbf]
+
+s_waitcnt_depctr depctr_vm_vsrc(1)
+// GFX10: s_waitcnt_depctr depctr_vm_vsrc(1) ; encoding: [0x07,0xff,0xa3,0xbf]
+
+s_waitcnt_depctr depctr_vm_vsrc(6)
+// GFX10: s_waitcnt_depctr depctr_vm_vsrc(6) ; encoding: [0x1b,0xff,0xa3,0xbf]
+
+s_waitcnt_depctr depctr_vm_vsrc(7)
+// GFX10: s_waitcnt_depctr depctr_sa_sdst(1) depctr_va_vdst(15) depctr_va_sdst(7) depctr_va_ssrc(1) depctr_va_vcc(1) depctr_vm_vsrc(7) ; encoding: [0x1f,0xff,0xa3,0xbf]
+
+s_waitcnt_depctr depctr_sa_sdst(0) depctr_va_vdst(0) depctr_va_sdst(0) depctr_va_ssrc(0) depctr_va_vcc(0) depctr_vm_vsrc(0)
+// GFX10: s_waitcnt_depctr depctr_sa_sdst(0) depctr_va_vdst(0) depctr_va_sdst(0) depctr_va_ssrc(0) depctr_va_vcc(0) depctr_vm_vsrc(0) ; encoding: [0x00,0x00,0xa3,0xbf]
+
+s_waitcnt_depctr depctr_sa_sdst(1) depctr_va_vdst(15) depctr_va_sdst(7) depctr_va_ssrc(1) depctr_va_vcc(1) depctr_vm_vsrc(7)
+// GFX10: s_waitcnt_depctr depctr_sa_sdst(1) depctr_va_vdst(15) depctr_va_sdst(7) depctr_va_ssrc(1) depctr_va_vcc(1) depctr_vm_vsrc(7) ; encoding: [0x1f,0xff,0xa3,0xbf]
+
+s_waitcnt_depctr depctr_sa_sdst(1) & depctr_va_vdst(1) & depctr_va_sdst(1) & depctr_va_ssrc(1) & depctr_va_vcc(1) & depctr_vm_vsrc(1)
+// GFX10: s_waitcnt_depctr depctr_va_vdst(1) depctr_va_sdst(1) depctr_vm_vsrc(1) ; encoding: [0x07,0x13,0xa3,0xbf]
+
+s_waitcnt_depctr depctr_sa_sdst(1), depctr_va_vdst(14), depctr_va_sdst(6), depctr_va_ssrc(1), depctr_va_vcc(1), depctr_vm_vsrc(6)
+// GFX10: s_waitcnt_depctr depctr_va_vdst(14) depctr_va_sdst(6) depctr_vm_vsrc(6) ; encoding: [0x1b,0xed,0xa3,0xbf]
+
+s_waitcnt_depctr depctr_va_vdst(14) depctr_va_sdst(6) depctr_vm_vsrc(6)
+// GFX10: s_waitcnt_depctr depctr_va_vdst(14) depctr_va_sdst(6) depctr_vm_vsrc(6) ; encoding: [0x1b,0xed,0xa3,0xbf]

llvm/test/MC/Disassembler/AMDGPU/gfx1030_dasm_new.txt

 # GFX10: scratch_load_short_d16_hi v1, off, off ; encoding: [0x00,0x40,0x94,0xdc,0x00,0x00,0x7f,0x01]
 0x00,0x40,0x94,0xdc,0x00,0x00,0x7f,0x01
 
 # GFX10: scratch_store_byte_d16_hi off, v2, off ; encoding: [0x00,0x40,0x64,0xdc,0x00,0x02,0x7f,0x00]
 0x00,0x40,0x64,0xdc,0x00,0x02,0x7f,0x00
 
 # GFX10: scratch_store_short_d16_hi off, v2, off ; encoding: [0x00,0x40,0x6c,0xdc,0x00,0x02,0x7f,0x00]
 0x00,0x40,0x6c,0xdc,0x00,0x02,0x7f,0x00
+
+#===------------------------------------------------------------------------===#
+# s_waitcnt_depctr.
+#===------------------------------------------------------------------------===#
+
+# GFX10: s_waitcnt_depctr 0x20 ; encoding: [0x20,0x00,0xa3,0xbf]
+0x20,0x00,0xa3,0xbf
+
+# GFX10: s_waitcnt_depctr 0x40 ; encoding: [0x40,0x00,0xa3,0xbf]
+0x40,0x00,0xa3,0xbf
+
+# GFX10: s_waitcnt_depctr 0x60 ; encoding: [0x60,0x00,0xa3,0xbf]
+0x60,0x00,0xa3,0xbf
+
+# GFX10: s_waitcnt_depctr 0xffff ; encoding: [0xff,0xff,0xa3,0xbf]
+0xff,0xff,0xa3,0xbf
+
+# GFX10: s_waitcnt_depctr depctr_hold_cnt(0) ; encoding: [0x1f,0xff,0xa3,0xbf]
+0x1f,0xff,0xa3,0xbf
+
+# GFX10: s_waitcnt_depctr depctr_sa_sdst(0) ; encoding: [0x9e,0xff,0xa3,0xbf]
+0x9e,0xff,0xa3,0xbf
+
+# GFX10: s_waitcnt_depctr depctr_va_vdst(0) ; encoding: [0x9f,0x0f,0xa3,0xbf]
+0x9f,0x0f,0xa3,0xbf
+
+# GFX10: s_waitcnt_depctr depctr_va_vdst(1) ; encoding: [0x9f,0x1f,0xa3,0xbf]
+0x9f,0x1f,0xa3,0xbf
+
+# GFX10: s_waitcnt_depctr depctr_va_vdst(14) ; encoding: [0x9f,0xef,0xa3,0xbf]
+0x9f,0xef,0xa3,0xbf
+
+# GFX10: s_waitcnt_depctr depctr_va_sdst(0) ; encoding: [0x9f,0xf1,0xa3,0xbf]
+0x9f,0xf1,0xa3,0xbf
+
+# GFX10: s_waitcnt_depctr depctr_va_sdst(6) ; encoding: [0x9f,0xfd,0xa3,0xbf]
+0x9f,0xfd,0xa3,0xbf
+
+# GFX10: s_waitcnt_depctr depctr_va_ssrc(0) ; encoding: [0x9f,0xfe,0xa3,0xbf]
+0x9f,0xfe,0xa3,0xbf
+
+# GFX10: s_waitcnt_depctr depctr_va_vcc(0) ; encoding: [0x9d,0xff,0xa3,0xbf]
+0x9d,0xff,0xa3,0xbf
+
+# GFX10: s_waitcnt_depctr depctr_vm_vsrc(0) ; encoding: [0x83,0xff,0xa3,0xbf]
+0x83,0xff,0xa3,0xbf
+
+# GFX10: s_waitcnt_depctr depctr_vm_vsrc(1) ; encoding: [0x87,0xff,0xa3,0xbf]
+0x87,0xff,0xa3,0xbf
+
+# GFX10: s_waitcnt_depctr depctr_vm_vsrc(6) ; encoding: [0x9b,0xff,0xa3,0xbf]
+0x9b,0xff,0xa3,0xbf
+
+# GFX10: s_waitcnt_depctr depctr_hold_cnt(0) depctr_sa_sdst(0) depctr_va_vdst(0) depctr_va_sdst(0) depctr_va_ssrc(0) depctr_va_vcc(0) depctr_vm_vsrc(0) ; encoding: [0x00,0x00,0xa3,0xbf]
+0x00,0x00,0xa3,0xbf
+
+# GFX10: s_waitcnt_depctr depctr_hold_cnt(1) depctr_sa_sdst(1) depctr_va_vdst(15) depctr_va_sdst(7) depctr_va_ssrc(1) depctr_va_vcc(1) depctr_vm_vsrc(7) ; encoding: [0x9f,0xff,0xa3,0xbf]
+0x9f,0xff,0xa3,0xbf
+
+# GFX10: s_waitcnt_depctr depctr_va_vdst(1) depctr_va_sdst(1) depctr_vm_vsrc(1)  ; encoding: [0x87,0x13,0xa3,0xbf]
+0x87,0x13,0xa3,0xbf

llvm/test/MC/Disassembler/AMDGPU/gfx10_dasm_all.txt

 0x34,0x12,0xeb,0xbb
 
 # GFX10: s_waitcnt_vscnt vcc_lo, 0x1234          ; encoding: [0x34,0x12,0xea,0xbb]
 0x34,0x12,0xea,0xbb
 
 # GFX10: s_wait_idle                             ; encoding: [0x00,0x00,0xa2,0xbf]
 0x00,0x00,0xa2,0xbf
 
-# GFX10: s_waitcnt_depctr 0x0                    ; encoding: [0x00,0x00,0xa3,0xbf]
-0x00,0x00,0xa3,0xbf
-
-# GFX10: s_waitcnt_depctr 0xfffe                 ; encoding: [0xfe,0xff,0xa3,0xbf]
-0xfe,0xff,0xa3,0xbf
-
 # GFX10: s_wakeup                                ; encoding: [0x00,0x00,0x83,0xbf]
 0x00,0x00,0x83,0xbf
 
 # GFX10: s_wqm_b32 exec_hi, s1                   ; encoding: [0x01,0x09,0xff,0xbe]
 0x01,0x09,0xff,0xbe
 
 # GFX10: s_wqm_b32 exec_lo, s1                   ; encoding: [0x01,0x09,0xfe,0xbe]
 0x01,0x09,0xfe,0xbe

 # GFX10: v_interp_mov_f32_e64 v5, p10, attr0.x mul:2 ; encoding: [0x05,0x00,0x02,0xd6,0x00,0x00,0x00,0x08]
 0x05 0x00 0x02 0xd6 0x00 0x00 0x00 0x08
 
 # GFX10: v_interp_mov_f32_e64 v5, p10, attr0.x mul:4 ; encoding: [0x05,0x00,0x02,0xd6,0x00,0x00,0x00,0x10]
 0x05 0x00 0x02 0xd6 0x00 0x00 0x00 0x10
 
 # GFX10: v_interp_mov_f32_e64 v5, p10, attr0.x div:2 ; encoding: [0x05,0x00,0x02,0xd6,0x00,0x00,0x00,0x18]
 0x05 0x00 0x02 0xd6 0x00 0x00 0x00 0x18
+
+#===------------------------------------------------------------------------===#
+# s_waitcnt_depctr.
+#===------------------------------------------------------------------------===#
+
+# GFX10: s_waitcnt_depctr 0x20                   ; encoding: [0x20,0x00,0xa3,0xbf]
+0x20,0x00,0xa3,0xbf
+
+# GFX10: s_waitcnt_depctr 0x40                   ; encoding: [0x40,0x00,0xa3,0xbf]
+0x40,0x00,0xa3,0xbf
+
+# GFX10: s_waitcnt_depctr 0x60                   ; encoding: [0x60,0x00,0xa3,0xbf]
+0x60,0x00,0xa3,0xbf
+
+# GFX10: s_waitcnt_depctr 0x80                   ; encoding: [0x80,0x00,0xa3,0xbf]
+0x80,0x00,0xa3,0xbf
+
+# GFX10: s_waitcnt_depctr 0xffff                 ; encoding: [0xff,0xff,0xa3,0xbf]
+0xff,0xff,0xa3,0xbf
+
+# GFX10: s_waitcnt_depctr depctr_sa_sdst(0)      ; encoding: [0x1e,0xff,0xa3,0xbf]
+0x1e,0xff,0xa3,0xbf
+
+# GFX10: s_waitcnt_depctr depctr_va_vdst(0)      ; encoding: [0x1f,0x0f,0xa3,0xbf]
+0x1f,0x0f,0xa3,0xbf
+
+# GFX10: s_waitcnt_depctr depctr_va_vdst(1)      ; encoding: [0x1f,0x1f,0xa3,0xbf]
+0x1f,0x1f,0xa3,0xbf
+
+# GFX10: s_waitcnt_depctr depctr_va_vdst(14)     ; encoding: [0x1f,0xef,0xa3,0xbf]
+0x1f,0xef,0xa3,0xbf
+
+# GFX10: s_waitcnt_depctr depctr_va_sdst(0)      ; encoding: [0x1f,0xf1,0xa3,0xbf]
+0x1f,0xf1,0xa3,0xbf
+
+# GFX10: s_waitcnt_depctr depctr_va_sdst(6)      ; encoding: [0x1f,0xfd,0xa3,0xbf]
+0x1f,0xfd,0xa3,0xbf
+
+# GFX10: s_waitcnt_depctr depctr_va_ssrc(0)      ; encoding: [0x1f,0xfe,0xa3,0xbf]
+0x1f,0xfe,0xa3,0xbf
+
+# GFX10: s_waitcnt_depctr depctr_va_vcc(0)       ; encoding: [0x1d,0xff,0xa3,0xbf]
+0x1d,0xff,0xa3,0xbf
+
+# GFX10: s_waitcnt_depctr depctr_vm_vsrc(0)      ; encoding: [0x03,0xff,0xa3,0xbf]
+0x03,0xff,0xa3,0xbf
+
+# GFX10: s_waitcnt_depctr depctr_vm_vsrc(1)      ; encoding: [0x07,0xff,0xa3,0xbf]
+0x07,0xff,0xa3,0xbf
+
+# GFX10: s_waitcnt_depctr depctr_vm_vsrc(6)      ; encoding: [0x1b,0xff,0xa3,0xbf]
+0x1b,0xff,0xa3,0xbf
+
+# GFX10: s_waitcnt_depctr depctr_sa_sdst(0) depctr_va_vdst(0) depctr_va_sdst(0) depctr_va_ssrc(0) depctr_va_vcc(0) depctr_vm_vsrc(0) ; encoding: [0x00,0x00,0xa3,0xbf]
+0x00,0x00,0xa3,0xbf
+
+# GFX10: s_waitcnt_depctr depctr_va_vdst(1) depctr_va_sdst(1) depctr_vm_vsrc(1) ; encoding: [0x07,0x13,0xa3,0xbf]
+0x07,0x13,0xa3,0xbf
+
+# GFX10: s_waitcnt_depctr depctr_va_vdst(14) depctr_va_sdst(6) depctr_vm_vsrc(6) ; encoding: [0x1b,0xed,0xa3,0xbf]
+0x1b,0xed,0xa3,0xbf