[PowerPC] Mark side effects of Power9 darn instruction

[qiucf]

Summary

This fixes CVE-2019-15847 ( https://gcc.gnu.org/bugzilla/show_bug.cgi?id=91481 ).

For following case:

#include <stdio.h>
#include <stdint.h>

int main()
{
  uint64_t darn[32];
  for(size_t i = 0; i != 32; ++i)
    darn[i] = __builtin_darn();
  for(size_t i = 0; i != 32; ++i)
    printf("%016lX\n", darn[i]);
  return 0;
}

32 outputs are the same, however they should be different.

[lkail]

Could you also add test of opt -passes='default<O3>' to ensure we don't optimize it out for the motivation case?

[qiucf]

Add OPT test

[lkail]

llvm/test/CodeGen/PowerPC/builtins-ppc-p9-darn.ll

52

The test should include the loop in the motivation case, since we might LICM'ed the intrinsic, so we observe the same value of every element in the array.

[lkail]

LGTM with nit.

llvm/test/CodeGen/PowerPC/builtins-ppc-p9-darn.ll

55

I'm not sure this directive is generated via utils/update_llc_test_checks.py. If not, this might diverge from what ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py suggests.

[qiucf]

llvm/test/CodeGen/PowerPC/builtins-ppc-p9-darn.ll

55

update_llc_test_checks.py will ignore the run lines.

[nemanjai]

llvm/lib/Target/PowerPC/PPCInstr64Bit.td

1041

Could you please commit a follow-up patch with a comment explaining why this flag is set. The instruction doesn't really have side effects in that it modifies some machine state, the flag is presumably needed so the instruction doesn't get optimized out.

llvm/test/CodeGen/PowerPC/builtins-ppc-p9-darn.ll

37

As general guidance, it is preferred if you pre-commit a test case like this with the original code generation so that the review (and subsequent commit) shows how the code generation changes as a result of the patch.

llvm/include/llvm/IR/IntrinsicsPowerPC.td

def int_ppc_unpack_longdouble : GCCBuiltin<"__builtin_unpack_longdouble">,
                                             [IntrNoMem]>;
   def int_ppc_pack_longdouble : GCCBuiltin<"__builtin_pack_longdouble">,
                                 Intrinsic<[llvm_ppcf128_ty],
                                           [llvm_double_ty, llvm_double_ty],
                                           [IntrNoMem]>;
 
   // Generate a random number
   def int_ppc_darn : GCCBuiltin<"__builtin_darn">,
-                     Intrinsic<[llvm_i64_ty], [], [IntrNoMem]>;
+                     Intrinsic<[llvm_i64_ty], [],
+                               [IntrNoMerge, IntrHasSideEffects]>;
   def int_ppc_darnraw : GCCBuiltin<"__builtin_darn_raw">,
-                     Intrinsic<[llvm_i64_ty], [], [IntrNoMem]>;
+                     Intrinsic<[llvm_i64_ty], [],
+                               [IntrNoMerge, IntrHasSideEffects]>;
   def int_ppc_darn32 : GCCBuiltin<"__builtin_darn_32">,
-                     Intrinsic<[llvm_i32_ty], [], [IntrNoMem]>;
+                     Intrinsic<[llvm_i32_ty], [],
+                               [IntrNoMerge, IntrHasSideEffects]>;
 
   // Bit permute doubleword
   def int_ppc_bpermd : GCCBuiltin<"__builtin_bpermd">,
                        Intrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty],
                                  [IntrNoMem]>;
 
   // Parallel Bits Deposit/Extract Doubleword Builtins.
   def int_ppc_pdepd

llvm/lib/Target/PowerPC/PPCInstr64Bit.td

let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
   def MADDLD8 : VAForm_1a<51, 
                        (outs g8rc :$RT), (ins g8rc:$RA, g8rc:$RB, g8rc:$RC),
                        "maddld $RT, $RA, $RB, $RC", IIC_IntMulHD,
                        [(set i64:$RT, (add_without_simm16 (mul_without_simm16 i64:$RA, i64:$RB), i64:$RC))]>,
                        isPPC64;
   def SETB8 : XForm_44<31, 128, (outs g8rc:$RT), (ins crrc:$BFA),
                        "setb $RT, $BFA", IIC_IntGeneral>, isPPC64;
 }
-def DARN : XForm_45<31, 755, (outs g8rc:$RT), (ins u2imm:$L),
-                     "darn $RT, $L", IIC_LdStLD>, isPPC64;
 def ADDPCIS : DXForm<19, 2, (outs g8rc:$RT), (ins i32imm:$D),
                      "addpcis $RT, $D", IIC_BrB, []>, isPPC64;
 def MODSD : XForm_8<31, 777, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
                         "modsd $rT, $rA, $rB", IIC_IntDivW,
                         [(set i64:$rT, (srem i64:$rA, i64:$rB))]>;
 def MODUD : XForm_8<31, 265, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
                         "modud $rT, $rA, $rB", IIC_IntDivW,
                         [(set i64:$rT, (urem i64:$rA, i64:$rB))]>;
 }
 
 defm DIVDEU : XOForm_1rcr<31, 393, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
                           "divdeu", "$rT, $rA, $rB", IIC_IntDivD,
                           [(set i64:$rT, (int_ppc_divdeu g8rc:$rA, g8rc:$rB))]>,
                           isPPC64, Requires<[HasExtDiv]>;
 let isCommutable = 1 in
 defm MULLD : XOForm_1rx<31, 233, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
                         "mulld", "$rT, $rA, $rB", IIC_IntMulHD,
                         [(set i64:$rT, (mul i64:$rA, i64:$rB))]>, isPPC64;
 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
 def MULLI8 : DForm_2<7, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm),
                        "mulli $rD, $rA, $imm", IIC_IntMulLI,
                        [(set i64:$rD, (mul i64:$rA, imm64SExt16:$imm))]>;
 }
 
+let hasSideEffects = 1 in {
+def DARN : XForm_45<31, 755, (outs g8rc:$RT), (ins u2imm:$L),
+                    "darn $RT, $L", IIC_LdStLD>, isPPC64;
+}
+
 let hasSideEffects = 0 in {
 defm RLDIMI : MDForm_1r<30, 3, (outs g8rc:$rA),
                         (ins g8rc:$rSi, g8rc:$rS, u6imm:$SH, u6imm:$MBE),
                         "rldimi", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI,
                         []>, isPPC64, RegConstraint<"$rSi = $rA">,
                         NoEncode<"$rSi">;
 
 // Rotate instructions.

llvm/test/CodeGen/PowerPC/builtins-ppc-p9-darn.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -verify-machineinstrs -mtriple powerpc64le -mcpu=pwr9 | FileCheck %s
 ; RUN: llc < %s -verify-machineinstrs -mtriple powerpc64-ibm-aix-xcoff -vec-extabi -mcpu=pwr9 | FileCheck %s
+; RUN: opt < %s -passes="default<O3>" -S -mtriple powerpc64le -mcpu=pwr9 | FileCheck %s --check-prefix=OPT
 
 define i64 @raw() {
 ; CHECK-LABEL: raw:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    darn 3, 2
 ; CHECK-NEXT:    blr
 entry:
   %0 = call i64 @llvm.ppc.darnraw()

 ; CHECK-NEXT:    darn 3, 0
 ; CHECK-NEXT:    extsw 3, 3
 ; CHECK-NEXT:    blr
 entry:
   %0 = call i32 @llvm.ppc.darn32()
   ret i32 %0
 }
 
+define i64 @darn_side_effect() {
+; CHECK-LABEL: darn_side_effect:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    darn 3, 2
+; CHECK-NEXT:    darn 3, 1
+; CHECK-NEXT:    blr
+
+; OPT-LABEL: @darn_side_effect
+; OPT: call i64 @llvm.ppc.darnraw()
+; OPT-NEXT: call i64 @llvm.ppc.darn()
+entry:
+  %0 = call i64 @llvm.ppc.darnraw()
+  %1 = call i64 @llvm.ppc.darn()
+  ret i64 %1
+}
+
+define void @darn_loop(i64* noundef %darn) {
+; OPT-LABEL: @darn_loop
+; OPT-COUNT-32: tail call i64 @llvm.ppc.darn()
+entry:
+  %inc = alloca i32, align 4
+  store i32 0, i32* %inc, align 4
+  br label %cond
+
+cond:
+  %0 = load i32, i32* %inc, align 4
+  %cmp = icmp ne i32 %0, 32
+  br i1 %cmp, label %body, label %end_loop
+
+body:
+  %1 = call i64 @llvm.ppc.darn()
+  %2 = load i32, i32* %inc, align 4
+  %idx = getelementptr inbounds i64, i64* %darn, i32 %2
+  store i64 %1, i64* %idx, align 8
+  br label %incr
+
+incr:
+  %3 = load i32, i32* %inc, align 4
+  %ninc = add nsw i32 %3, 1
+  store i32 %ninc, i32* %inc, align 4
+  br label %cond
+
+end_loop:
+  ret void
+}
+
 declare i64 @llvm.ppc.darn()
 declare i64 @llvm.ppc.darnraw()
 declare i32 @llvm.ppc.darn32()