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Differential D122702

[RISCV] Add CMIX isel pattern for (xor (and (xor rs1, rs3), rs2), rs3)
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Authored by Miss_Grape on Mar 29 2022, 8:22 PM.

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craig.topper
benshi001
Commits
rG4cb85da81124: [RISCV] Add CMIX isel pattern for (xor (and (xor rs1, rs3), rs2), rs3)

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Event Timeline

Miss_Grape created this revision.Mar 29 2022, 8:22 PM
Herald added a project: Restricted Project. · View Herald TranscriptMar 29 2022, 8:22 PM
Herald added subscribers: sunshaoce, VincentWu, luke957 and 29 others. · View Herald Transcript
Miss_Grape requested review of this revision.Mar 29 2022, 8:22 PM
Herald added a project: Restricted Project. · View Herald TranscriptMar 29 2022, 8:22 PM
Herald added subscribers: llvm-commits, • pcwang-thead, eopXD and 2 others. · View Herald Transcript
Miss_Grape retitled this revision from [RISCV] Add CMIX isel pattern for (xor (and （xor rs1, rs3), rs2), rs3) to [RISCV] Add CMIX isel pattern for (xor (and (xor rs1, rs3), rs2), rs3).Mar 29 2022, 8:23 PM
craig.topper added inline comments.Mar 29 2022, 9:45 PM
llvm/test/CodeGen/RISCV/rv32zbt.ll
92

This and should be xor?

Miss_Grape updated this revision to Diff 419055.Mar 29 2022, 11:06 PM

updata test

llvm/test/CodeGen/RISCV/rv32zbt.ll
92

fixed

craig.topper accepted this revision.Mar 30 2022, 12:05 AM

LGTM

This revision is now accepted and ready to land.Mar 30 2022, 12:05 AM
This revision was landed with ongoing or failed builds.Mar 30 2022, 1:51 AM
Closed by commit rG4cb85da81124: [RISCV] Add CMIX isel pattern for (xor (and (xor rs1, rs3), rs2), rs3) (authored by Miss_Grape, committed by benshi001). · Explain Why
This revision was automatically updated to reflect the committed changes.
benshi001 added a commit: rG4cb85da81124: [RISCV] Add CMIX isel pattern for (xor (and (xor rs1, rs3), rs2), rs3).
Harbormaster completed remote builds in B156889: Diff 419055.Mar 30 2022, 2:18 PM

Revision Contents

PathSize
llvm/
lib/
Target/
RISCV/
2 lines
test/
CodeGen/
RISCV/
144 lines
76 lines

Diff 419072

llvm/lib/Target/RISCV/RISCVInstrInfoZb.td

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let Predicates = [HasStdExtZbp, IsRV64] in { let Predicates = [HasStdExtZbp, IsRV64] in {
// We treat rev8 as a separate instruction, so match it directly. // We treat rev8 as a separate instruction, so match it directly.
def : Pat<(i64 (riscv_grev GPR:$rs1, 56)), (REV8_RV64 GPR:$rs1)>; def : Pat<(i64 (riscv_grev GPR:$rs1, 56)), (REV8_RV64 GPR:$rs1)>;
} // Predicates = [HasStdExtZbp, IsRV64] } // Predicates = [HasStdExtZbp, IsRV64]
let Predicates = [HasStdExtZbt] in { let Predicates = [HasStdExtZbt] in {
def : Pat<(or (and (not GPR:$rs2), GPR:$rs3), (and GPR:$rs2, GPR:$rs1)), def : Pat<(or (and (not GPR:$rs2), GPR:$rs3), (and GPR:$rs2, GPR:$rs1)),
(CMIX GPR:$rs1, GPR:$rs2, GPR:$rs3)>; (CMIX GPR:$rs1, GPR:$rs2, GPR:$rs3)>;
def : Pat<(xor (and (xor GPR:$rs1, GPR:$rs3), GPR:$rs2), GPR:$rs3),
(CMIX GPR:$rs1, GPR:$rs2, GPR:$rs3)>;
def : Pat<(select (XLenVT (setne GPR:$rs2, 0)), GPR:$rs1, GPR:$rs3), def : Pat<(select (XLenVT (setne GPR:$rs2, 0)), GPR:$rs1, GPR:$rs3),
(CMOV GPR:$rs1, GPR:$rs2, GPR:$rs3)>; (CMOV GPR:$rs1, GPR:$rs2, GPR:$rs3)>;
def : Pat<(select (XLenVT (seteq GPR:$rs2, 0)), GPR:$rs3, GPR:$rs1), def : Pat<(select (XLenVT (seteq GPR:$rs2, 0)), GPR:$rs3, GPR:$rs1),
(CMOV GPR:$rs1, GPR:$rs2, GPR:$rs3)>; (CMOV GPR:$rs1, GPR:$rs2, GPR:$rs3)>;
def : Pat<(select (XLenVT (setne GPR:$x, simm12_plus1:$y)), GPR:$rs1, GPR:$rs3), def : Pat<(select (XLenVT (setne GPR:$x, simm12_plus1:$y)), GPR:$rs1, GPR:$rs3),
(CMOV GPR:$rs1, (ADDI GPR:$x, (NegImm simm12_plus1:$y)), GPR:$rs3)>; (CMOV GPR:$rs1, (ADDI GPR:$x, (NegImm simm12_plus1:$y)), GPR:$rs3)>;
def : Pat<(select (XLenVT (seteq GPR:$x, simm12_plus1:$y)), GPR:$rs3, GPR:$rs1), def : Pat<(select (XLenVT (seteq GPR:$x, simm12_plus1:$y)), GPR:$rs3, GPR:$rs1),
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llvm/test/CodeGen/RISCV/rv32zbt.ll

Show All 18 Lines
; RV32ZBT-NEXT: ret ; RV32ZBT-NEXT: ret
%and = and i32 %b, %a %and = and i32 %b, %a
%neg = xor i32 %b, -1 %neg = xor i32 %b, -1
%and1 = and i32 %neg, %c %and1 = and i32 %neg, %c
%or = or i32 %and1, %and %or = or i32 %and1, %and
ret i32 %or ret i32 %or
} }
define i32 @cmix_i32_2(i32 %a, i32 %b, i32 %c) nounwind {
; RV32I-LABEL: cmix_i32_2:
; RV32I: # %bb.0:
; RV32I-NEXT: xor a0, a0, a2
; RV32I-NEXT: and a0, a0, a1
; RV32I-NEXT: xor a0, a0, a2
; RV32I-NEXT: ret
;
; RV32ZBT-LABEL: cmix_i32_2:
; RV32ZBT: # %bb.0:
; RV32ZBT-NEXT: cmix a0, a1, a0, a2
; RV32ZBT-NEXT: ret
%xor = xor i32 %a, %c
%and = and i32 %xor, %b
%xor1 = xor i32 %and, %c
ret i32 %xor1
}
define i64 @cmix_i64(i64 %a, i64 %b, i64 %c) nounwind { define i64 @cmix_i64(i64 %a, i64 %b, i64 %c) nounwind {
; RV32I-LABEL: cmix_i64: ; RV32I-LABEL: cmix_i64:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: and a1, a3, a1 ; RV32I-NEXT: and a1, a3, a1
; RV32I-NEXT: and a0, a2, a0 ; RV32I-NEXT: and a0, a2, a0
; RV32I-NEXT: not a2, a2 ; RV32I-NEXT: not a2, a2
; RV32I-NEXT: not a3, a3 ; RV32I-NEXT: not a3, a3
; RV32I-NEXT: and a3, a3, a5 ; RV32I-NEXT: and a3, a3, a5
Show All 9 Lines
; RV32ZBT-NEXT: ret ; RV32ZBT-NEXT: ret
%and = and i64 %b, %a %and = and i64 %b, %a
%neg = xor i64 %b, -1 %neg = xor i64 %b, -1
%and1 = and i64 %neg, %c %and1 = and i64 %neg, %c
%or = or i64 %and1, %and %or = or i64 %and1, %and
ret i64 %or ret i64 %or
} }
define i64 @cmix_i64_2(i64 %a, i64 %b, i64 %c) nounwind {
; RV32I-LABEL: cmix_i64_2:
; RV32I: # %bb.0:
; RV32I-NEXT: xor a0, a0, a4
; RV32I-NEXT: xor a1, a1, a5
; RV32I-NEXT: and a1, a1, a3
; RV32I-NEXT: and a0, a0, a2
; RV32I-NEXT: xor a0, a0, a4
; RV32I-NEXT: xor a1, a1, a5
; RV32I-NEXT: ret
;
; RV32ZBT-LABEL: cmix_i64_2:
; RV32ZBT: # %bb.0:
; RV32ZBT-NEXT: cmix a0, a2, a0, a4
; RV32ZBT-NEXT: cmix a1, a3, a1, a5
; RV32ZBT-NEXT: ret
%xor = xor i64 %a, %c
%and = and i64 %xor, %b
%xor1 = xor i64 %and, %c
ret i64 %xor1
}
define i32 @cmov_i32(i32 %a, i32 %b, i32 %c) nounwind { define i32 @cmov_i32(i32 %a, i32 %b, i32 %c) nounwind {
craig.topperUnsubmitted
Not Done
ReplyInline Actions

This and should be xor?

craig.topper: This `and` should be `xor`?
Miss_GrapeAuthorUnsubmitted
Done
ReplyInline Actions

fixed

Miss_Grape: fixed
; RV32I-LABEL: cmov_i32: ; RV32I-LABEL: cmov_i32:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: beqz a1, .LBB2_2 ; RV32I-NEXT: beqz a1, .LBB4_2
; RV32I-NEXT: # %bb.1: ; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: mv a2, a0 ; RV32I-NEXT: mv a2, a0
; RV32I-NEXT: .LBB2_2: ; RV32I-NEXT: .LBB4_2:
; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32ZBT-LABEL: cmov_i32: ; RV32ZBT-LABEL: cmov_i32:
; RV32ZBT: # %bb.0: ; RV32ZBT: # %bb.0:
; RV32ZBT-NEXT: cmov a0, a1, a0, a2 ; RV32ZBT-NEXT: cmov a0, a1, a0, a2
; RV32ZBT-NEXT: ret ; RV32ZBT-NEXT: ret
%tobool.not = icmp eq i32 %b, 0 %tobool.not = icmp eq i32 %b, 0
%cond = select i1 %tobool.not, i32 %c, i32 %a %cond = select i1 %tobool.not, i32 %c, i32 %a
ret i32 %cond ret i32 %cond
} }
define i32 @cmov_sle_i32(i32 %a, i32 %b, i32 %c, i32 %d) nounwind { define i32 @cmov_sle_i32(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
; RV32I-LABEL: cmov_sle_i32: ; RV32I-LABEL: cmov_sle_i32:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: bge a2, a1, .LBB3_2 ; RV32I-NEXT: bge a2, a1, .LBB5_2
; RV32I-NEXT: # %bb.1: ; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: .LBB3_2: ; RV32I-NEXT: .LBB5_2:
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32ZBT-LABEL: cmov_sle_i32: ; RV32ZBT-LABEL: cmov_sle_i32:
; RV32ZBT: # %bb.0: ; RV32ZBT: # %bb.0:
; RV32ZBT-NEXT: slt a1, a2, a1 ; RV32ZBT-NEXT: slt a1, a2, a1
; RV32ZBT-NEXT: cmov a0, a1, a3, a0 ; RV32ZBT-NEXT: cmov a0, a1, a3, a0
; RV32ZBT-NEXT: ret ; RV32ZBT-NEXT: ret
%tobool = icmp sle i32 %b, %c %tobool = icmp sle i32 %b, %c
%cond = select i1 %tobool, i32 %a, i32 %d %cond = select i1 %tobool, i32 %a, i32 %d
ret i32 %cond ret i32 %cond
} }
define i32 @cmov_sge_i32(i32 %a, i32 %b, i32 %c, i32 %d) nounwind { define i32 @cmov_sge_i32(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
; RV32I-LABEL: cmov_sge_i32: ; RV32I-LABEL: cmov_sge_i32:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: bge a1, a2, .LBB4_2 ; RV32I-NEXT: bge a1, a2, .LBB6_2
; RV32I-NEXT: # %bb.1: ; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: .LBB4_2: ; RV32I-NEXT: .LBB6_2:
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32ZBT-LABEL: cmov_sge_i32: ; RV32ZBT-LABEL: cmov_sge_i32:
; RV32ZBT: # %bb.0: ; RV32ZBT: # %bb.0:
; RV32ZBT-NEXT: slt a1, a1, a2 ; RV32ZBT-NEXT: slt a1, a1, a2
; RV32ZBT-NEXT: cmov a0, a1, a3, a0 ; RV32ZBT-NEXT: cmov a0, a1, a3, a0
; RV32ZBT-NEXT: ret ; RV32ZBT-NEXT: ret
%tobool = icmp sge i32 %b, %c %tobool = icmp sge i32 %b, %c
%cond = select i1 %tobool, i32 %a, i32 %d %cond = select i1 %tobool, i32 %a, i32 %d
ret i32 %cond ret i32 %cond
} }
define i32 @cmov_ule_i32(i32 %a, i32 %b, i32 %c, i32 %d) nounwind { define i32 @cmov_ule_i32(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
; RV32I-LABEL: cmov_ule_i32: ; RV32I-LABEL: cmov_ule_i32:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: bgeu a2, a1, .LBB5_2 ; RV32I-NEXT: bgeu a2, a1, .LBB7_2
; RV32I-NEXT: # %bb.1: ; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: .LBB5_2: ; RV32I-NEXT: .LBB7_2:
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32ZBT-LABEL: cmov_ule_i32: ; RV32ZBT-LABEL: cmov_ule_i32:
; RV32ZBT: # %bb.0: ; RV32ZBT: # %bb.0:
; RV32ZBT-NEXT: sltu a1, a2, a1 ; RV32ZBT-NEXT: sltu a1, a2, a1
; RV32ZBT-NEXT: cmov a0, a1, a3, a0 ; RV32ZBT-NEXT: cmov a0, a1, a3, a0
; RV32ZBT-NEXT: ret ; RV32ZBT-NEXT: ret
%tobool = icmp ule i32 %b, %c %tobool = icmp ule i32 %b, %c
%cond = select i1 %tobool, i32 %a, i32 %d %cond = select i1 %tobool, i32 %a, i32 %d
ret i32 %cond ret i32 %cond
} }
define i32 @cmov_uge_i32(i32 %a, i32 %b, i32 %c, i32 %d) nounwind { define i32 @cmov_uge_i32(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
; RV32I-LABEL: cmov_uge_i32: ; RV32I-LABEL: cmov_uge_i32:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: bgeu a1, a2, .LBB6_2 ; RV32I-NEXT: bgeu a1, a2, .LBB8_2
; RV32I-NEXT: # %bb.1: ; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: .LBB6_2: ; RV32I-NEXT: .LBB8_2:
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32ZBT-LABEL: cmov_uge_i32: ; RV32ZBT-LABEL: cmov_uge_i32:
; RV32ZBT: # %bb.0: ; RV32ZBT: # %bb.0:
; RV32ZBT-NEXT: sltu a1, a1, a2 ; RV32ZBT-NEXT: sltu a1, a1, a2
; RV32ZBT-NEXT: cmov a0, a1, a3, a0 ; RV32ZBT-NEXT: cmov a0, a1, a3, a0
; RV32ZBT-NEXT: ret ; RV32ZBT-NEXT: ret
%tobool = icmp uge i32 %b, %c %tobool = icmp uge i32 %b, %c
%cond = select i1 %tobool, i32 %a, i32 %d %cond = select i1 %tobool, i32 %a, i32 %d
ret i32 %cond ret i32 %cond
} }
define i64 @cmov_i64(i64 %a, i64 %b, i64 %c) nounwind { define i64 @cmov_i64(i64 %a, i64 %b, i64 %c) nounwind {
; RV32I-LABEL: cmov_i64: ; RV32I-LABEL: cmov_i64:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: or a2, a2, a3 ; RV32I-NEXT: or a2, a2, a3
; RV32I-NEXT: beqz a2, .LBB7_2 ; RV32I-NEXT: beqz a2, .LBB9_2
; RV32I-NEXT: # %bb.1: ; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: mv a4, a0 ; RV32I-NEXT: mv a4, a0
; RV32I-NEXT: mv a5, a1 ; RV32I-NEXT: mv a5, a1
; RV32I-NEXT: .LBB7_2: ; RV32I-NEXT: .LBB9_2:
; RV32I-NEXT: mv a0, a4 ; RV32I-NEXT: mv a0, a4
; RV32I-NEXT: mv a1, a5 ; RV32I-NEXT: mv a1, a5
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32ZBT-LABEL: cmov_i64: ; RV32ZBT-LABEL: cmov_i64:
; RV32ZBT: # %bb.0: ; RV32ZBT: # %bb.0:
; RV32ZBT-NEXT: or a2, a2, a3 ; RV32ZBT-NEXT: or a2, a2, a3
; RV32ZBT-NEXT: cmov a0, a2, a0, a4 ; RV32ZBT-NEXT: cmov a0, a2, a0, a4
; RV32ZBT-NEXT: cmov a1, a2, a1, a5 ; RV32ZBT-NEXT: cmov a1, a2, a1, a5
; RV32ZBT-NEXT: ret ; RV32ZBT-NEXT: ret
%tobool.not = icmp eq i64 %b, 0 %tobool.not = icmp eq i64 %b, 0
%cond = select i1 %tobool.not, i64 %c, i64 %a %cond = select i1 %tobool.not, i64 %c, i64 %a
ret i64 %cond ret i64 %cond
} }
define i64 @cmov_sle_i64(i64 %a, i64 %b, i64 %c, i64 %d) nounwind { define i64 @cmov_sle_i64(i64 %a, i64 %b, i64 %c, i64 %d) nounwind {
; RV32I-LABEL: cmov_sle_i64: ; RV32I-LABEL: cmov_sle_i64:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: beq a3, a5, .LBB8_2 ; RV32I-NEXT: beq a3, a5, .LBB10_2
; RV32I-NEXT: # %bb.1: ; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: slt a2, a5, a3 ; RV32I-NEXT: slt a2, a5, a3
; RV32I-NEXT: xori a2, a2, 1 ; RV32I-NEXT: xori a2, a2, 1
; RV32I-NEXT: beqz a2, .LBB8_3 ; RV32I-NEXT: beqz a2, .LBB10_3
; RV32I-NEXT: j .LBB8_4 ; RV32I-NEXT: j .LBB10_4
; RV32I-NEXT: .LBB8_2: ; RV32I-NEXT: .LBB10_2:
; RV32I-NEXT: sltu a2, a4, a2 ; RV32I-NEXT: sltu a2, a4, a2
; RV32I-NEXT: xori a2, a2, 1 ; RV32I-NEXT: xori a2, a2, 1
; RV32I-NEXT: bnez a2, .LBB8_4 ; RV32I-NEXT: bnez a2, .LBB10_4
; RV32I-NEXT: .LBB8_3: ; RV32I-NEXT: .LBB10_3:
; RV32I-NEXT: mv a0, a6 ; RV32I-NEXT: mv a0, a6
; RV32I-NEXT: mv a1, a7 ; RV32I-NEXT: mv a1, a7
; RV32I-NEXT: .LBB8_4: ; RV32I-NEXT: .LBB10_4:
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32ZBT-LABEL: cmov_sle_i64: ; RV32ZBT-LABEL: cmov_sle_i64:
; RV32ZBT: # %bb.0: ; RV32ZBT: # %bb.0:
; RV32ZBT-NEXT: xor t0, a3, a5 ; RV32ZBT-NEXT: xor t0, a3, a5
; RV32ZBT-NEXT: sltu a2, a4, a2 ; RV32ZBT-NEXT: sltu a2, a4, a2
; RV32ZBT-NEXT: xori a2, a2, 1 ; RV32ZBT-NEXT: xori a2, a2, 1
; RV32ZBT-NEXT: slt a3, a5, a3 ; RV32ZBT-NEXT: slt a3, a5, a3
; RV32ZBT-NEXT: xori a3, a3, 1 ; RV32ZBT-NEXT: xori a3, a3, 1
; RV32ZBT-NEXT: cmov a2, t0, a3, a2 ; RV32ZBT-NEXT: cmov a2, t0, a3, a2
; RV32ZBT-NEXT: cmov a0, a2, a0, a6 ; RV32ZBT-NEXT: cmov a0, a2, a0, a6
; RV32ZBT-NEXT: cmov a1, a2, a1, a7 ; RV32ZBT-NEXT: cmov a1, a2, a1, a7
; RV32ZBT-NEXT: ret ; RV32ZBT-NEXT: ret
%tobool = icmp sle i64 %b, %c %tobool = icmp sle i64 %b, %c
%cond = select i1 %tobool, i64 %a, i64 %d %cond = select i1 %tobool, i64 %a, i64 %d
ret i64 %cond ret i64 %cond
} }
define i64 @cmov_sge_i64(i64 %a, i64 %b, i64 %c, i64 %d) nounwind { define i64 @cmov_sge_i64(i64 %a, i64 %b, i64 %c, i64 %d) nounwind {
; RV32I-LABEL: cmov_sge_i64: ; RV32I-LABEL: cmov_sge_i64:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: beq a3, a5, .LBB9_2 ; RV32I-NEXT: beq a3, a5, .LBB11_2
; RV32I-NEXT: # %bb.1: ; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: slt a2, a3, a5 ; RV32I-NEXT: slt a2, a3, a5
; RV32I-NEXT: xori a2, a2, 1 ; RV32I-NEXT: xori a2, a2, 1
; RV32I-NEXT: beqz a2, .LBB9_3 ; RV32I-NEXT: beqz a2, .LBB11_3
; RV32I-NEXT: j .LBB9_4 ; RV32I-NEXT: j .LBB11_4
; RV32I-NEXT: .LBB9_2: ; RV32I-NEXT: .LBB11_2:
; RV32I-NEXT: sltu a2, a2, a4 ; RV32I-NEXT: sltu a2, a2, a4
; RV32I-NEXT: xori a2, a2, 1 ; RV32I-NEXT: xori a2, a2, 1
; RV32I-NEXT: bnez a2, .LBB9_4 ; RV32I-NEXT: bnez a2, .LBB11_4
; RV32I-NEXT: .LBB9_3: ; RV32I-NEXT: .LBB11_3:
; RV32I-NEXT: mv a0, a6 ; RV32I-NEXT: mv a0, a6
; RV32I-NEXT: mv a1, a7 ; RV32I-NEXT: mv a1, a7
; RV32I-NEXT: .LBB9_4: ; RV32I-NEXT: .LBB11_4:
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32ZBT-LABEL: cmov_sge_i64: ; RV32ZBT-LABEL: cmov_sge_i64:
; RV32ZBT: # %bb.0: ; RV32ZBT: # %bb.0:
; RV32ZBT-NEXT: xor t0, a3, a5 ; RV32ZBT-NEXT: xor t0, a3, a5
; RV32ZBT-NEXT: sltu a2, a2, a4 ; RV32ZBT-NEXT: sltu a2, a2, a4
; RV32ZBT-NEXT: xori a2, a2, 1 ; RV32ZBT-NEXT: xori a2, a2, 1
; RV32ZBT-NEXT: slt a3, a3, a5 ; RV32ZBT-NEXT: slt a3, a3, a5
; RV32ZBT-NEXT: xori a3, a3, 1 ; RV32ZBT-NEXT: xori a3, a3, 1
; RV32ZBT-NEXT: cmov a2, t0, a3, a2 ; RV32ZBT-NEXT: cmov a2, t0, a3, a2
; RV32ZBT-NEXT: cmov a0, a2, a0, a6 ; RV32ZBT-NEXT: cmov a0, a2, a0, a6
; RV32ZBT-NEXT: cmov a1, a2, a1, a7 ; RV32ZBT-NEXT: cmov a1, a2, a1, a7
; RV32ZBT-NEXT: ret ; RV32ZBT-NEXT: ret
%tobool = icmp sge i64 %b, %c %tobool = icmp sge i64 %b, %c
%cond = select i1 %tobool, i64 %a, i64 %d %cond = select i1 %tobool, i64 %a, i64 %d
ret i64 %cond ret i64 %cond
} }
define i64 @cmov_ule_i64(i64 %a, i64 %b, i64 %c, i64 %d) nounwind { define i64 @cmov_ule_i64(i64 %a, i64 %b, i64 %c, i64 %d) nounwind {
; RV32I-LABEL: cmov_ule_i64: ; RV32I-LABEL: cmov_ule_i64:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: beq a3, a5, .LBB10_2 ; RV32I-NEXT: beq a3, a5, .LBB12_2
; RV32I-NEXT: # %bb.1: ; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: sltu a2, a5, a3 ; RV32I-NEXT: sltu a2, a5, a3
; RV32I-NEXT: xori a2, a2, 1 ; RV32I-NEXT: xori a2, a2, 1
; RV32I-NEXT: beqz a2, .LBB10_3 ; RV32I-NEXT: beqz a2, .LBB12_3
; RV32I-NEXT: j .LBB10_4 ; RV32I-NEXT: j .LBB12_4
; RV32I-NEXT: .LBB10_2: ; RV32I-NEXT: .LBB12_2:
; RV32I-NEXT: sltu a2, a4, a2 ; RV32I-NEXT: sltu a2, a4, a2
; RV32I-NEXT: xori a2, a2, 1 ; RV32I-NEXT: xori a2, a2, 1
; RV32I-NEXT: bnez a2, .LBB10_4 ; RV32I-NEXT: bnez a2, .LBB12_4
; RV32I-NEXT: .LBB10_3: ; RV32I-NEXT: .LBB12_3:
; RV32I-NEXT: mv a0, a6 ; RV32I-NEXT: mv a0, a6
; RV32I-NEXT: mv a1, a7 ; RV32I-NEXT: mv a1, a7
; RV32I-NEXT: .LBB10_4: ; RV32I-NEXT: .LBB12_4:
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32ZBT-LABEL: cmov_ule_i64: ; RV32ZBT-LABEL: cmov_ule_i64:
; RV32ZBT: # %bb.0: ; RV32ZBT: # %bb.0:
; RV32ZBT-NEXT: xor t0, a3, a5 ; RV32ZBT-NEXT: xor t0, a3, a5
; RV32ZBT-NEXT: sltu a2, a4, a2 ; RV32ZBT-NEXT: sltu a2, a4, a2
; RV32ZBT-NEXT: xori a2, a2, 1 ; RV32ZBT-NEXT: xori a2, a2, 1
; RV32ZBT-NEXT: sltu a3, a5, a3 ; RV32ZBT-NEXT: sltu a3, a5, a3
; RV32ZBT-NEXT: xori a3, a3, 1 ; RV32ZBT-NEXT: xori a3, a3, 1
; RV32ZBT-NEXT: cmov a2, t0, a3, a2 ; RV32ZBT-NEXT: cmov a2, t0, a3, a2
; RV32ZBT-NEXT: cmov a0, a2, a0, a6 ; RV32ZBT-NEXT: cmov a0, a2, a0, a6
; RV32ZBT-NEXT: cmov a1, a2, a1, a7 ; RV32ZBT-NEXT: cmov a1, a2, a1, a7
; RV32ZBT-NEXT: ret ; RV32ZBT-NEXT: ret
%tobool = icmp ule i64 %b, %c %tobool = icmp ule i64 %b, %c
%cond = select i1 %tobool, i64 %a, i64 %d %cond = select i1 %tobool, i64 %a, i64 %d
ret i64 %cond ret i64 %cond
} }
define i64 @cmov_uge_i64(i64 %a, i64 %b, i64 %c, i64 %d) nounwind { define i64 @cmov_uge_i64(i64 %a, i64 %b, i64 %c, i64 %d) nounwind {
; RV32I-LABEL: cmov_uge_i64: ; RV32I-LABEL: cmov_uge_i64:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: beq a3, a5, .LBB11_2 ; RV32I-NEXT: beq a3, a5, .LBB13_2
; RV32I-NEXT: # %bb.1: ; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: sltu a2, a3, a5 ; RV32I-NEXT: sltu a2, a3, a5
; RV32I-NEXT: xori a2, a2, 1 ; RV32I-NEXT: xori a2, a2, 1
; RV32I-NEXT: beqz a2, .LBB11_3 ; RV32I-NEXT: beqz a2, .LBB13_3
; RV32I-NEXT: j .LBB11_4 ; RV32I-NEXT: j .LBB13_4
; RV32I-NEXT: .LBB11_2: ; RV32I-NEXT: .LBB13_2:
; RV32I-NEXT: sltu a2, a2, a4 ; RV32I-NEXT: sltu a2, a2, a4
; RV32I-NEXT: xori a2, a2, 1 ; RV32I-NEXT: xori a2, a2, 1
; RV32I-NEXT: bnez a2, .LBB11_4 ; RV32I-NEXT: bnez a2, .LBB13_4
; RV32I-NEXT: .LBB11_3: ; RV32I-NEXT: .LBB13_3:
; RV32I-NEXT: mv a0, a6 ; RV32I-NEXT: mv a0, a6
; RV32I-NEXT: mv a1, a7 ; RV32I-NEXT: mv a1, a7
; RV32I-NEXT: .LBB11_4: ; RV32I-NEXT: .LBB13_4:
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32ZBT-LABEL: cmov_uge_i64: ; RV32ZBT-LABEL: cmov_uge_i64:
; RV32ZBT: # %bb.0: ; RV32ZBT: # %bb.0:
; RV32ZBT-NEXT: xor t0, a3, a5 ; RV32ZBT-NEXT: xor t0, a3, a5
; RV32ZBT-NEXT: sltu a2, a2, a4 ; RV32ZBT-NEXT: sltu a2, a2, a4
; RV32ZBT-NEXT: xori a2, a2, 1 ; RV32ZBT-NEXT: xori a2, a2, 1
; RV32ZBT-NEXT: sltu a3, a3, a5 ; RV32ZBT-NEXT: sltu a3, a3, a5
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declare i64 @llvm.fshl.i64(i64, i64, i64) declare i64 @llvm.fshl.i64(i64, i64, i64)
define i64 @fshl_i64(i64 %a, i64 %b, i64 %c) nounwind { define i64 @fshl_i64(i64 %a, i64 %b, i64 %c) nounwind {
; RV32I-LABEL: fshl_i64: ; RV32I-LABEL: fshl_i64:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: srli a5, a4, 5 ; RV32I-NEXT: srli a5, a4, 5
; RV32I-NEXT: andi a6, a5, 1 ; RV32I-NEXT: andi a6, a5, 1
; RV32I-NEXT: mv a5, a3 ; RV32I-NEXT: mv a5, a3
; RV32I-NEXT: bnez a6, .LBB13_2 ; RV32I-NEXT: bnez a6, .LBB15_2
; RV32I-NEXT: # %bb.1: ; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: mv a5, a0 ; RV32I-NEXT: mv a5, a0
; RV32I-NEXT: .LBB13_2: ; RV32I-NEXT: .LBB15_2:
; RV32I-NEXT: sll a7, a5, a4 ; RV32I-NEXT: sll a7, a5, a4
; RV32I-NEXT: bnez a6, .LBB13_4 ; RV32I-NEXT: bnez a6, .LBB15_4
; RV32I-NEXT: # %bb.3: ; RV32I-NEXT: # %bb.3:
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: .LBB13_4: ; RV32I-NEXT: .LBB15_4:
; RV32I-NEXT: srli a2, a2, 1 ; RV32I-NEXT: srli a2, a2, 1
; RV32I-NEXT: not a3, a4 ; RV32I-NEXT: not a3, a4
; RV32I-NEXT: srl a2, a2, a3 ; RV32I-NEXT: srl a2, a2, a3
; RV32I-NEXT: or a2, a7, a2 ; RV32I-NEXT: or a2, a7, a2
; RV32I-NEXT: bnez a6, .LBB13_6 ; RV32I-NEXT: bnez a6, .LBB15_6
; RV32I-NEXT: # %bb.5: ; RV32I-NEXT: # %bb.5:
; RV32I-NEXT: mv a0, a1 ; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: .LBB13_6: ; RV32I-NEXT: .LBB15_6:
; RV32I-NEXT: sll a0, a0, a4 ; RV32I-NEXT: sll a0, a0, a4
; RV32I-NEXT: srli a1, a5, 1 ; RV32I-NEXT: srli a1, a5, 1
; RV32I-NEXT: srl a1, a1, a3 ; RV32I-NEXT: srl a1, a1, a3
; RV32I-NEXT: or a1, a0, a1 ; RV32I-NEXT: or a1, a0, a1
; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32ZBT-LABEL: fshl_i64: ; RV32ZBT-LABEL: fshl_i64:
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; extensions introduce instructions that can match more efficiently this pattern. ; extensions introduce instructions that can match more efficiently this pattern.
declare i64 @llvm.fshr.i64(i64, i64, i64) declare i64 @llvm.fshr.i64(i64, i64, i64)
define i64 @fshr_i64(i64 %a, i64 %b, i64 %c) nounwind { define i64 @fshr_i64(i64 %a, i64 %b, i64 %c) nounwind {
; RV32I-LABEL: fshr_i64: ; RV32I-LABEL: fshr_i64:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: andi a5, a4, 32 ; RV32I-NEXT: andi a5, a4, 32
; RV32I-NEXT: beqz a5, .LBB15_2 ; RV32I-NEXT: beqz a5, .LBB17_2
; RV32I-NEXT: # %bb.1: ; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: .LBB15_2: ; RV32I-NEXT: .LBB17_2:
; RV32I-NEXT: srl a2, a2, a4 ; RV32I-NEXT: srl a2, a2, a4
; RV32I-NEXT: beqz a5, .LBB15_4 ; RV32I-NEXT: beqz a5, .LBB17_4
; RV32I-NEXT: # %bb.3: ; RV32I-NEXT: # %bb.3:
; RV32I-NEXT: mv a3, a0 ; RV32I-NEXT: mv a3, a0
; RV32I-NEXT: .LBB15_4: ; RV32I-NEXT: .LBB17_4:
; RV32I-NEXT: slli a7, a3, 1 ; RV32I-NEXT: slli a7, a3, 1
; RV32I-NEXT: not a6, a4 ; RV32I-NEXT: not a6, a4
; RV32I-NEXT: sll a7, a7, a6 ; RV32I-NEXT: sll a7, a7, a6
; RV32I-NEXT: or a2, a7, a2 ; RV32I-NEXT: or a2, a7, a2
; RV32I-NEXT: srl a3, a3, a4 ; RV32I-NEXT: srl a3, a3, a4
; RV32I-NEXT: beqz a5, .LBB15_6 ; RV32I-NEXT: beqz a5, .LBB17_6
; RV32I-NEXT: # %bb.5: ; RV32I-NEXT: # %bb.5:
; RV32I-NEXT: mv a0, a1 ; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: .LBB15_6: ; RV32I-NEXT: .LBB17_6:
; RV32I-NEXT: slli a0, a0, 1 ; RV32I-NEXT: slli a0, a0, 1
; RV32I-NEXT: sll a0, a0, a6 ; RV32I-NEXT: sll a0, a0, a6
; RV32I-NEXT: or a1, a0, a3 ; RV32I-NEXT: or a1, a0, a3
; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32ZBT-LABEL: fshr_i64: ; RV32ZBT-LABEL: fshr_i64:
; RV32ZBT: # %bb.0: ; RV32ZBT: # %bb.0:
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llvm/test/CodeGen/RISCV/rv64zbt.ll

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; RV64ZBT-NEXT: ret ; RV64ZBT-NEXT: ret
%and = and i32 %b, %a %and = and i32 %b, %a
%neg = xor i32 %b, -1 %neg = xor i32 %b, -1
%and1 = and i32 %neg, %c %and1 = and i32 %neg, %c
%or = or i32 %and1, %and %or = or i32 %and1, %and
ret i32 %or ret i32 %or
} }
define signext i32 @cmix_i32_2(i32 signext %a, i32 signext %b, i32 signext %c) nounwind {
; RV64I-LABEL: cmix_i32_2:
; RV64I: # %bb.0:
; RV64I-NEXT: xor a0, a0, a2
; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: xor a0, a0, a2
; RV64I-NEXT: ret
;
; RV64ZBT-LABEL: cmix_i32_2:
; RV64ZBT: # %bb.0:
; RV64ZBT-NEXT: cmix a0, a1, a0, a2
; RV64ZBT-NEXT: ret
%xor = xor i32 %a, %c
%and = and i32 %xor, %b
%xor1 = xor i32 %and, %c
ret i32 %xor1
}
define i64 @cmix_i64(i64 %a, i64 %b, i64 %c) nounwind { define i64 @cmix_i64(i64 %a, i64 %b, i64 %c) nounwind {
; RV64I-LABEL: cmix_i64: ; RV64I-LABEL: cmix_i64:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: and a0, a1, a0 ; RV64I-NEXT: and a0, a1, a0
; RV64I-NEXT: not a1, a1 ; RV64I-NEXT: not a1, a1
; RV64I-NEXT: and a1, a1, a2 ; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64ZBT-LABEL: cmix_i64: ; RV64ZBT-LABEL: cmix_i64:
; RV64ZBT: # %bb.0: ; RV64ZBT: # %bb.0:
; RV64ZBT-NEXT: cmix a0, a1, a0, a2 ; RV64ZBT-NEXT: cmix a0, a1, a0, a2
; RV64ZBT-NEXT: ret ; RV64ZBT-NEXT: ret
%and = and i64 %b, %a %and = and i64 %b, %a
%neg = xor i64 %b, -1 %neg = xor i64 %b, -1
%and1 = and i64 %neg, %c %and1 = and i64 %neg, %c
%or = or i64 %and1, %and %or = or i64 %and1, %and
ret i64 %or ret i64 %or
} }
define i64 @cmix_i64_2(i64 %a, i64 %b, i64 %c) nounwind {
; RV64I-LABEL: cmix_i64_2:
; RV64I: # %bb.0:
; RV64I-NEXT: xor a0, a1, a2
; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: xor a0, a0, a2
; RV64I-NEXT: ret
;
; RV64ZBT-LABEL: cmix_i64_2:
; RV64ZBT: # %bb.0:
; RV64ZBT-NEXT: cmix a0, a1, a1, a2
; RV64ZBT-NEXT: ret
%xor = xor i64 %b, %c
%and = and i64 %xor, %b
%xor1 = xor i64 %and, %c
ret i64 %xor1
}
define signext i32 @cmov_i32(i32 signext %a, i32 signext %b, i32 signext %c) nounwind { define signext i32 @cmov_i32(i32 signext %a, i32 signext %b, i32 signext %c) nounwind {
; RV64I-LABEL: cmov_i32: ; RV64I-LABEL: cmov_i32:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: beqz a1, .LBB2_2 ; RV64I-NEXT: beqz a1, .LBB4_2
; RV64I-NEXT: # %bb.1: ; RV64I-NEXT: # %bb.1:
; RV64I-NEXT: mv a2, a0 ; RV64I-NEXT: mv a2, a0
; RV64I-NEXT: .LBB2_2: ; RV64I-NEXT: .LBB4_2:
; RV64I-NEXT: mv a0, a2 ; RV64I-NEXT: mv a0, a2
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64ZBT-LABEL: cmov_i32: ; RV64ZBT-LABEL: cmov_i32:
; RV64ZBT: # %bb.0: ; RV64ZBT: # %bb.0:
; RV64ZBT-NEXT: cmov a0, a1, a0, a2 ; RV64ZBT-NEXT: cmov a0, a1, a0, a2
; RV64ZBT-NEXT: ret ; RV64ZBT-NEXT: ret
%tobool.not = icmp eq i32 %b, 0 %tobool.not = icmp eq i32 %b, 0
%cond = select i1 %tobool.not, i32 %c, i32 %a %cond = select i1 %tobool.not, i32 %c, i32 %a
ret i32 %cond ret i32 %cond
} }
define signext i32 @cmov_sle_i32(i32 signext %a, i32 signext %b, i32 signext %c, i32 signext %d) nounwind { define signext i32 @cmov_sle_i32(i32 signext %a, i32 signext %b, i32 signext %c, i32 signext %d) nounwind {
; RV64I-LABEL: cmov_sle_i32: ; RV64I-LABEL: cmov_sle_i32:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: bge a2, a1, .LBB3_2 ; RV64I-NEXT: bge a2, a1, .LBB5_2
; RV64I-NEXT: # %bb.1: ; RV64I-NEXT: # %bb.1:
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: .LBB3_2: ; RV64I-NEXT: .LBB5_2:
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64ZBT-LABEL: cmov_sle_i32: ; RV64ZBT-LABEL: cmov_sle_i32:
; RV64ZBT: # %bb.0: ; RV64ZBT: # %bb.0:
; RV64ZBT-NEXT: slt a1, a2, a1 ; RV64ZBT-NEXT: slt a1, a2, a1
; RV64ZBT-NEXT: cmov a0, a1, a3, a0 ; RV64ZBT-NEXT: cmov a0, a1, a3, a0
; RV64ZBT-NEXT: ret ; RV64ZBT-NEXT: ret
%tobool = icmp sle i32 %b, %c %tobool = icmp sle i32 %b, %c
%cond = select i1 %tobool, i32 %a, i32 %d %cond = select i1 %tobool, i32 %a, i32 %d
ret i32 %cond ret i32 %cond
} }
define signext i32 @cmov_sge_i32(i32 signext %a, i32 signext %b, i32 signext %c, i32 signext %d) nounwind { define signext i32 @cmov_sge_i32(i32 signext %a, i32 signext %b, i32 signext %c, i32 signext %d) nounwind {
; RV64I-LABEL: cmov_sge_i32: ; RV64I-LABEL: cmov_sge_i32:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: bge a1, a2, .LBB4_2 ; RV64I-NEXT: bge a1, a2, .LBB6_2
; RV64I-NEXT: # %bb.1: ; RV64I-NEXT: # %bb.1:
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: .LBB4_2: ; RV64I-NEXT: .LBB6_2:
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64ZBT-LABEL: cmov_sge_i32: ; RV64ZBT-LABEL: cmov_sge_i32:
; RV64ZBT: # %bb.0: ; RV64ZBT: # %bb.0:
; RV64ZBT-NEXT: slt a1, a1, a2 ; RV64ZBT-NEXT: slt a1, a1, a2
; RV64ZBT-NEXT: cmov a0, a1, a3, a0 ; RV64ZBT-NEXT: cmov a0, a1, a3, a0
; RV64ZBT-NEXT: ret ; RV64ZBT-NEXT: ret
%tobool = icmp sge i32 %b, %c %tobool = icmp sge i32 %b, %c
%cond = select i1 %tobool, i32 %a, i32 %d %cond = select i1 %tobool, i32 %a, i32 %d
ret i32 %cond ret i32 %cond
} }
define signext i32 @cmov_ule_i32(i32 signext %a, i32 signext %b, i32 signext %c, i32 signext %d) nounwind { define signext i32 @cmov_ule_i32(i32 signext %a, i32 signext %b, i32 signext %c, i32 signext %d) nounwind {
; RV64I-LABEL: cmov_ule_i32: ; RV64I-LABEL: cmov_ule_i32:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: bgeu a2, a1, .LBB5_2 ; RV64I-NEXT: bgeu a2, a1, .LBB7_2
; RV64I-NEXT: # %bb.1: ; RV64I-NEXT: # %bb.1:
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: .LBB5_2: ; RV64I-NEXT: .LBB7_2:
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64ZBT-LABEL: cmov_ule_i32: ; RV64ZBT-LABEL: cmov_ule_i32:
; RV64ZBT: # %bb.0: ; RV64ZBT: # %bb.0:
; RV64ZBT-NEXT: sltu a1, a2, a1 ; RV64ZBT-NEXT: sltu a1, a2, a1
; RV64ZBT-NEXT: cmov a0, a1, a3, a0 ; RV64ZBT-NEXT: cmov a0, a1, a3, a0
; RV64ZBT-NEXT: ret ; RV64ZBT-NEXT: ret
%tobool = icmp ule i32 %b, %c %tobool = icmp ule i32 %b, %c
%cond = select i1 %tobool, i32 %a, i32 %d %cond = select i1 %tobool, i32 %a, i32 %d
ret i32 %cond ret i32 %cond
} }
define signext i32 @cmov_uge_i32(i32 signext %a, i32 signext %b, i32 signext %c, i32 signext %d) nounwind { define signext i32 @cmov_uge_i32(i32 signext %a, i32 signext %b, i32 signext %c, i32 signext %d) nounwind {
; RV64I-LABEL: cmov_uge_i32: ; RV64I-LABEL: cmov_uge_i32:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: bgeu a1, a2, .LBB6_2 ; RV64I-NEXT: bgeu a1, a2, .LBB8_2
; RV64I-NEXT: # %bb.1: ; RV64I-NEXT: # %bb.1:
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: .LBB6_2: ; RV64I-NEXT: .LBB8_2:
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64ZBT-LABEL: cmov_uge_i32: ; RV64ZBT-LABEL: cmov_uge_i32:
; RV64ZBT: # %bb.0: ; RV64ZBT: # %bb.0:
; RV64ZBT-NEXT: sltu a1, a1, a2 ; RV64ZBT-NEXT: sltu a1, a1, a2
; RV64ZBT-NEXT: cmov a0, a1, a3, a0 ; RV64ZBT-NEXT: cmov a0, a1, a3, a0
; RV64ZBT-NEXT: ret ; RV64ZBT-NEXT: ret
%tobool = icmp uge i32 %b, %c %tobool = icmp uge i32 %b, %c
%cond = select i1 %tobool, i32 %a, i32 %d %cond = select i1 %tobool, i32 %a, i32 %d
ret i32 %cond ret i32 %cond
} }
define i64 @cmov_i64(i64 %a, i64 %b, i64 %c) nounwind { define i64 @cmov_i64(i64 %a, i64 %b, i64 %c) nounwind {
; RV64I-LABEL: cmov_i64: ; RV64I-LABEL: cmov_i64:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: beqz a1, .LBB7_2 ; RV64I-NEXT: beqz a1, .LBB9_2
; RV64I-NEXT: # %bb.1: ; RV64I-NEXT: # %bb.1:
; RV64I-NEXT: mv a2, a0 ; RV64I-NEXT: mv a2, a0
; RV64I-NEXT: .LBB7_2: ; RV64I-NEXT: .LBB9_2:
; RV64I-NEXT: mv a0, a2 ; RV64I-NEXT: mv a0, a2
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64ZBT-LABEL: cmov_i64: ; RV64ZBT-LABEL: cmov_i64:
; RV64ZBT: # %bb.0: ; RV64ZBT: # %bb.0:
; RV64ZBT-NEXT: cmov a0, a1, a0, a2 ; RV64ZBT-NEXT: cmov a0, a1, a0, a2
; RV64ZBT-NEXT: ret ; RV64ZBT-NEXT: ret
%tobool.not = icmp eq i64 %b, 0 %tobool.not = icmp eq i64 %b, 0
%cond = select i1 %tobool.not, i64 %c, i64 %a %cond = select i1 %tobool.not, i64 %c, i64 %a
ret i64 %cond ret i64 %cond
} }
define i64 @cmov_sle_i64(i64 %a, i64 %b, i64 %c, i64 %d) nounwind { define i64 @cmov_sle_i64(i64 %a, i64 %b, i64 %c, i64 %d) nounwind {
; RV64I-LABEL: cmov_sle_i64: ; RV64I-LABEL: cmov_sle_i64:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: bge a2, a1, .LBB8_2 ; RV64I-NEXT: bge a2, a1, .LBB10_2
; RV64I-NEXT: # %bb.1: ; RV64I-NEXT: # %bb.1:
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: .LBB8_2: ; RV64I-NEXT: .LBB10_2:
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64ZBT-LABEL: cmov_sle_i64: ; RV64ZBT-LABEL: cmov_sle_i64:
; RV64ZBT: # %bb.0: ; RV64ZBT: # %bb.0:
; RV64ZBT-NEXT: slt a1, a2, a1 ; RV64ZBT-NEXT: slt a1, a2, a1
; RV64ZBT-NEXT: cmov a0, a1, a3, a0 ; RV64ZBT-NEXT: cmov a0, a1, a3, a0
; RV64ZBT-NEXT: ret ; RV64ZBT-NEXT: ret
%tobool = icmp sle i64 %b, %c %tobool = icmp sle i64 %b, %c
%cond = select i1 %tobool, i64 %a, i64 %d %cond = select i1 %tobool, i64 %a, i64 %d
ret i64 %cond ret i64 %cond
} }
define i64 @cmov_sge_i64(i64 %a, i64 %b, i64 %c, i64 %d) nounwind { define i64 @cmov_sge_i64(i64 %a, i64 %b, i64 %c, i64 %d) nounwind {
; RV64I-LABEL: cmov_sge_i64: ; RV64I-LABEL: cmov_sge_i64:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: bge a1, a2, .LBB9_2 ; RV64I-NEXT: bge a1, a2, .LBB11_2
; RV64I-NEXT: # %bb.1: ; RV64I-NEXT: # %bb.1:
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: .LBB9_2: ; RV64I-NEXT: .LBB11_2:
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64ZBT-LABEL: cmov_sge_i64: ; RV64ZBT-LABEL: cmov_sge_i64:
; RV64ZBT: # %bb.0: ; RV64ZBT: # %bb.0:
; RV64ZBT-NEXT: slt a1, a1, a2 ; RV64ZBT-NEXT: slt a1, a1, a2
; RV64ZBT-NEXT: cmov a0, a1, a3, a0 ; RV64ZBT-NEXT: cmov a0, a1, a3, a0
; RV64ZBT-NEXT: ret ; RV64ZBT-NEXT: ret
%tobool = icmp sge i64 %b, %c %tobool = icmp sge i64 %b, %c
%cond = select i1 %tobool, i64 %a, i64 %d %cond = select i1 %tobool, i64 %a, i64 %d
ret i64 %cond ret i64 %cond
} }
define i64 @cmov_ule_i64(i64 %a, i64 %b, i64 %c, i64 %d) nounwind { define i64 @cmov_ule_i64(i64 %a, i64 %b, i64 %c, i64 %d) nounwind {
; RV64I-LABEL: cmov_ule_i64: ; RV64I-LABEL: cmov_ule_i64:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: bgeu a2, a1, .LBB10_2 ; RV64I-NEXT: bgeu a2, a1, .LBB12_2
; RV64I-NEXT: # %bb.1: ; RV64I-NEXT: # %bb.1:
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: .LBB10_2: ; RV64I-NEXT: .LBB12_2:
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64ZBT-LABEL: cmov_ule_i64: ; RV64ZBT-LABEL: cmov_ule_i64:
; RV64ZBT: # %bb.0: ; RV64ZBT: # %bb.0:
; RV64ZBT-NEXT: sltu a1, a2, a1 ; RV64ZBT-NEXT: sltu a1, a2, a1
; RV64ZBT-NEXT: cmov a0, a1, a3, a0 ; RV64ZBT-NEXT: cmov a0, a1, a3, a0
; RV64ZBT-NEXT: ret ; RV64ZBT-NEXT: ret
%tobool = icmp ule i64 %b, %c %tobool = icmp ule i64 %b, %c
%cond = select i1 %tobool, i64 %a, i64 %d %cond = select i1 %tobool, i64 %a, i64 %d
ret i64 %cond ret i64 %cond
} }
define i64 @cmov_uge_i64(i64 %a, i64 %b, i64 %c, i64 %d) nounwind { define i64 @cmov_uge_i64(i64 %a, i64 %b, i64 %c, i64 %d) nounwind {
; RV64I-LABEL: cmov_uge_i64: ; RV64I-LABEL: cmov_uge_i64:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: bgeu a1, a2, .LBB11_2 ; RV64I-NEXT: bgeu a1, a2, .LBB13_2
; RV64I-NEXT: # %bb.1: ; RV64I-NEXT: # %bb.1:
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: .LBB11_2: ; RV64I-NEXT: .LBB13_2:
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64ZBT-LABEL: cmov_uge_i64: ; RV64ZBT-LABEL: cmov_uge_i64:
; RV64ZBT: # %bb.0: ; RV64ZBT: # %bb.0:
; RV64ZBT-NEXT: sltu a1, a1, a2 ; RV64ZBT-NEXT: sltu a1, a1, a2
; RV64ZBT-NEXT: cmov a0, a1, a3, a0 ; RV64ZBT-NEXT: cmov a0, a1, a3, a0
; RV64ZBT-NEXT: ret ; RV64ZBT-NEXT: ret
%tobool = icmp uge i64 %b, %c %tobool = icmp uge i64 %b, %c
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