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Differential D122643

[AArch64] Optimize pattern for converting a half word byte swap in a 64-bit input to a rev16 instruction
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Authored by bipmis on Mar 29 2022, 3:19 AM.

Details

Reviewers
dmgreen
samtebbs
Commits
rGedb452020569: rev16 instruction is being generated for a half word byte swap on a 32-bit…
Summary

rev16 instruction is being generated for a half word byte swap on a 32-bit input as a bswap+rotr. This is not true for a 64-bit input.

This patch implements the rev16 instruction for a AArch64 backend for a half word byte swap on a 64-bit input.

Diff Detail

Unit TestsFailed

TimeTest
60,050 msx64 debian > MLIR.Examples/standalone::test.toy
60,050 msx64 debian > ThreadSanitizer-x86_64.ThreadSanitizer-x86_64::restore_stack.cpp
2,029 msx64 debian > libFuzzer.libFuzzer::fuzzer-finalstats.test
4,030 msx64 debian > libomptarget :: x86_64-pc-linux-gnu-newDriver.mapping::map_back_race.cpp

Event Timeline

bipmis created this revision.Mar 29 2022, 3:19 AM
Herald added a subscriber: kristof.beyls. · View Herald TranscriptMar 29 2022, 3:19 AM
bipmis requested review of this revision.Mar 29 2022, 3:19 AM
samtebbs accepted this revision.Mar 29 2022, 5:24 AM

Nice one. Looks good to me.

This revision is now accepted and ready to land.Mar 29 2022, 5:24 AM
Harbormaster completed remote builds in B156721: Diff 418827.Mar 30 2022, 12:00 AM
bipmis mentioned this in rGafca54f0cfc3: [ARM][AArch64] Optimize pattern for converting a half word byte swap in a 64….Apr 5 2022, 4:35 AM
This revision was landed with ongoing or failed builds.Apr 5 2022, 5:43 AM
Closed by commit rGedb452020569: rev16 instruction is being generated for a half word byte swap on a 32-bit… (authored by bipmis). · Explain Why
This revision was automatically updated to reflect the committed changes.
bipmis added a commit: rGedb452020569: rev16 instruction is being generated for a half word byte swap on a 32-bit….

Revision Contents

PathSize
llvm/
lib/
Target/
AArch64/
4 lines
test/
CodeGen/
AArch64/
23 lines

Diff 418827

llvm/lib/Target/AArch64/AArch64InstrInfo.td

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
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// orders. // orders.
def : Pat<(bswap (rotr GPR32:$Rn, (i64 16))), (REV16Wr GPR32:$Rn)>; def : Pat<(bswap (rotr GPR32:$Rn, (i64 16))), (REV16Wr GPR32:$Rn)>;
def : Pat<(bswap (rotr GPR64:$Rn, (i64 32))), (REV32Xr GPR64:$Rn)>; def : Pat<(bswap (rotr GPR64:$Rn, (i64 32))), (REV32Xr GPR64:$Rn)>;
// Match (srl (bswap x), C) -> revC if the upper bswap bits are known zero. // Match (srl (bswap x), C) -> revC if the upper bswap bits are known zero.
def : Pat<(srl (bswap top16Zero:$Rn), (i64 16)), (REV16Wr GPR32:$Rn)>; def : Pat<(srl (bswap top16Zero:$Rn), (i64 16)), (REV16Wr GPR32:$Rn)>;
def : Pat<(srl (bswap top32Zero:$Rn), (i64 32)), (REV32Xr GPR64:$Rn)>; def : Pat<(srl (bswap top32Zero:$Rn), (i64 32)), (REV32Xr GPR64:$Rn)>;
def : Pat<(or (and (srl GPR64:$Rn, (i64 8)), (i64 0x00ff00ff00ff00ff)),
(and (shl GPR64:$Rn, (i64 8)), (i64 0xff00ff00ff00ff00))),
(REV16Xr GPR64:$Rn)>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Bitfield immediate extraction instruction. // Bitfield immediate extraction instruction.
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
let hasSideEffects = 0 in let hasSideEffects = 0 in
defm EXTR : ExtractImm<"extr">; defm EXTR : ExtractImm<"extr">;
def : InstAlias<"ror $dst, $src, $shift", def : InstAlias<"ror $dst, $src, $shift",
(EXTRWrri GPR32:$dst, GPR32:$src, GPR32:$src, imm0_31:$shift)>; (EXTRWrri GPR32:$dst, GPR32:$src, GPR32:$src, imm0_31:$shift)>;
def : InstAlias<"ror $dst, $src, $shift", def : InstAlias<"ror $dst, $src, $shift",
▲ Show 20 Lines • Show All 6,295 Lines • Show Last 20 Lines

llvm/test/CodeGen/AArch64/arm64-rev.ll

Show First 20 Lines • Show All 674 Lines • ▼ Show 20 Lines; GISEL-NEXT: ret
%and = and i32 %ld, -65536 %and = and i32 %ld, -65536
%bswap = tail call i32 @llvm.bswap.i32(i32 %and) %bswap = tail call i32 @llvm.bswap.i32(i32 %and)
%and16 = zext i32 %bswap to i64 %and16 = zext i32 %bswap to i64
%call17 = tail call i32 bitcast (i32 (...)* @gid_tbl_len to i32 (i64)*)(i64 %and16) %call17 = tail call i32 bitcast (i32 (...)* @gid_tbl_len to i32 (i64)*)(i64 %and16)
store i16 0, i16* %p1, align 4 store i16 0, i16* %p1, align 4
ret void ret void
} }
declare i32 @gid_tbl_len(...) declare i32 @gid_tbl_len(...)
; 64-bit REV16 is *not* a swap then a 16-bit rotation:
; 01234567 ->(bswap) 76543210 ->(rotr) 10765432
; 01234567 ->(rev16) 10325476
; Optimize patterns where rev16 can be generated for a 64-bit input.
define i64 @test_rev16_x_hwbyteswaps(i64 %a) nounwind {
; CHECK-LABEL: test_rev16_x_hwbyteswaps:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: rev16 x0, x0
; CHECK-NEXT: ret
;
; GISEL-LABEL: test_rev16_x_hwbyteswaps:
; GISEL: // %bb.0: // %entry
; GISEL-NEXT: rev16 x0, x0
; GISEL-NEXT: ret
entry:
%0 = lshr i64 %a, 8
%1 = and i64 %0, 71777214294589695
%2 = shl i64 %a, 8
%3 = and i64 %2, -71777214294589696
%4 = or i64 %1, %3
ret i64 %4
}