[X86] Support maskmovdqu,vmaskmovdqu in X32

[skan]

Summary

This is a re-implementation for D103427.

[skan]

Abandon this b/c the author wants to fix it himself in D122540

llvm/lib/Target/X86/X86InstrSSE.td

 
 } // ExeDomain = SSEPackedInt
 
 //===---------------------------------------------------------------------===//
 // SSE2 - Conditional Store
 //===---------------------------------------------------------------------===//
 
 let ExeDomain = SSEPackedInt, SchedRW = [SchedWriteVecMoveLS.XMM.MR] in {
-let Uses = [EDI], Predicates = [HasAVX,Not64BitMode] in
+let Uses = [EDI], Predicates = [HasAVX] in
 def VMASKMOVDQU : VPDI<0xF7, MRMSrcReg, (outs),
            (ins VR128:$src, VR128:$mask),
            "maskmovdqu\t{$mask, $src|$src, $mask}",
            [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)]>,
            VEX, VEX_WIG;
 let Uses = [RDI], Predicates = [HasAVX,In64BitMode] in
 def VMASKMOVDQU64 : VPDI<0xF7, MRMSrcReg, (outs),
            (ins VR128:$src, VR128:$mask),
            "maskmovdqu\t{$mask, $src|$src, $mask}",
            [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)]>,
            VEX, VEX_WIG;
 
-let Uses = [EDI], Predicates = [UseSSE2,Not64BitMode] in
+let Uses = [EDI], Predicates = [UseSSE2] in
 def MASKMOVDQU : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
            "maskmovdqu\t{$mask, $src|$src, $mask}",
            [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)]>;
 let Uses = [RDI], Predicates = [UseSSE2,In64BitMode] in
 def MASKMOVDQU64 : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
            "maskmovdqu\t{$mask, $src|$src, $mask}",
            [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)]>;
 

llvm/lib/Target/X86/X86MCInstLower.cpp

void X86MCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const {
   case X86::LEA32r:
     // LEA should have a segment register, but it must be empty.
     assert(OutMI.getNumOperands() == 1 + X86::AddrNumOperands &&
            "Unexpected # of LEA operands");
     assert(OutMI.getOperand(1 + X86::AddrSegmentReg).getReg() == 0 &&
            "LEA has segment specified!");
     break;
 
+  case X86::MASKMOVDQU:
+  case X86::VMASKMOVDQU: {
+    const X86Subtarget &Subtarget = AsmPrinter.getSubtarget();
+    // A address-size prefix is need in X32
+    if (Subtarget.is64Bit())
+      OutMI.setFlags(X86::IP_HAS_AD_SIZE);
+    break;
+  }
   case X86::MULX32Hrr:
   case X86::MULX32Hrm:
   case X86::MULX64Hrr:
   case X86::MULX64Hrm: {
     // Turn into regular MULX by duplicating the destination.
     unsigned NewOpc;
     switch (OutMI.getOpcode()) {
     default: llvm_unreachable("Invalid opcode");

llvm/test/CodeGen/X86/maskmovdqu.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=i686--    -mattr=+sse2,-avx | FileCheck %s --check-prefix=i686_SSE2
 ; RUN: llc < %s -mtriple=x86_64-- -mattr=+sse2,-avx | FileCheck %s --check-prefix=x86_64_SSE2
+; RUN: llc < %s -mtriple=x86_64--gnux32 -mattr=+sse2,-avx | FileCheck %s --check-prefix=x86_x32_SSE2
 ; RUN: llc < %s -mtriple=i686--    -mattr=+avx | FileCheck %s --check-prefix=i686_AVX
 ; RUN: llc < %s -mtriple=x86_64-- -mattr=+avx | FileCheck %s --check-prefix=x86_64_AVX
+; RUN: llc < %s -mtriple=x86_64--gnux32 -mattr=+avx | FileCheck %s --check-prefix=x86_x32_AVX
 ; rdar://6573467
 
 define void @test(<16 x i8> %a, <16 x i8> %b, i32 %dummy, i8* %c) nounwind {
 ; i686_SSE2-LABEL: test:
 ; i686_SSE2:       # %bb.0: # %entry
 ; i686_SSE2-NEXT:    pushl %edi
 ; i686_SSE2-NEXT:    movl {{[0-9]+}}(%esp), %edi
 ; i686_SSE2-NEXT:    maskmovdqu %xmm1, %xmm0
 ; i686_SSE2-NEXT:    popl %edi
 ; i686_SSE2-NEXT:    retl
 ;
 ; x86_64_SSE2-LABEL: test:
 ; x86_64_SSE2:       # %bb.0: # %entry
 ; x86_64_SSE2-NEXT:    movq %rsi, %rdi
 ; x86_64_SSE2-NEXT:    maskmovdqu %xmm1, %xmm0
 ; x86_64_SSE2-NEXT:    retq
 ;
+; x86_x32_SSE2-LABEL: test:
+; x86_x32_SSE2:       # %bb.0: # %entry
+; x86_x32_SSE2-NEXT:    movq %rsi, %rdi
+; x86_x32_SSE2-NEXT:    # kill: def $edi killed $edi killed $rdi
+; x86_x32_SSE2-NEXT:    addr32 maskmovdqu %xmm1, %xmm0
+; x86_x32_SSE2-NEXT:    retq
+;
 ; i686_AVX-LABEL: test:
 ; i686_AVX:       # %bb.0: # %entry
 ; i686_AVX-NEXT:    pushl %edi
 ; i686_AVX-NEXT:    movl {{[0-9]+}}(%esp), %edi
 ; i686_AVX-NEXT:    vmaskmovdqu %xmm1, %xmm0
 ; i686_AVX-NEXT:    popl %edi
 ; i686_AVX-NEXT:    retl
 ;
 ; x86_64_AVX-LABEL: test:
 ; x86_64_AVX:       # %bb.0: # %entry
 ; x86_64_AVX-NEXT:    movq %rsi, %rdi
 ; x86_64_AVX-NEXT:    vmaskmovdqu %xmm1, %xmm0
 ; x86_64_AVX-NEXT:    retq
+; x86_x32_AVX-LABEL: test:
+; x86_x32_AVX:       # %bb.0: # %entry
+; x86_x32_AVX-NEXT:    movq %rsi, %rdi
+; x86_x32_AVX-NEXT:    # kill: def $edi killed $edi killed $rdi
+; x86_x32_AVX-NEXT:    addr32 vmaskmovdqu %xmm1, %xmm0
+; x86_x32_AVX-NEXT:    retq
 entry:
   tail call void @llvm.x86.sse2.maskmov.dqu( <16 x i8> %a, <16 x i8> %b, i8* %c )
   ret void
 }
 
 declare void @llvm.x86.sse2.maskmov.dqu(<16 x i8>, <16 x i8>, i8*) nounwind

llvm/test/MC/X86/maskmovdqu.s

+// RUN: llvm-mc -triple i386-- --show-encoding %s |\
+// RUN:   FileCheck %s --check-prefixes=CHECK,ENCODING
+
+// RUN: llvm-mc -triple i386-- -filetype=obj %s |\
+// RUN:   llvm-objdump -d - | FileCheck %s
+
+// CHECK-NOT: addr32
+// CHECK: maskmovdqu %xmm1, %xmm0
+// ENCODING:  encoding: [0x66,0x0f,0xf7,0xc1]
+maskmovdqu %xmm1, %xmm0
+
+// CHECK-NOT: addr32
+// CHECK:  vmaskmovdqu %xmm1, %xmm0
+// ENCODING:  encoding: [0xc5,0xf9,0xf7,0xc1]
+vmaskmovdqu %xmm1, %xmm0

llvm/test/MC/X86/maskmovdqu64.s

+// RUN: llvm-mc -triple x86_64-- --show-encoding %s |\
+// RUN:   FileCheck %s --check-prefixes=CHECK,ENCODING
+
+// RUN: llvm-mc -triple x86_64-- -filetype=obj %s |\
+// RUN:   llvm-objdump -d - | FileCheck %s
+
+// CHECK-NOT: addr32
+// CHECK: maskmovdqu %xmm1, %xmm0
+// ENCODING:  encoding: [0x66,0x0f,0xf7,0xc1]
+maskmovdqu %xmm1, %xmm0
+
+// CHECK-NOT: addr32
+// CHECK:  vmaskmovdqu %xmm1, %xmm0
+// ENCODING:  encoding: [0xc5,0xf9,0xf7,0xc1]
+vmaskmovdqu %xmm1, %xmm0
+
+// CHECK:  addr32
+// ENCODING:  encoding: [0x67]
+// CHECK: maskmovdqu %xmm1, %xmm0
+// ENCODING:  encoding: [0x66,0x0f,0xf7,0xc1]
+addr32 maskmovdqu %xmm1, %xmm0
+
+// CHECK:  addr32
+// ENCODING:  encoding: [0x67]
+// CHECK:  vmaskmovdqu %xmm1, %xmm0
+// ENCODING:  encoding: [0xc5,0xf9,0xf7,0xc1]
+addr32 vmaskmovdqu %xmm1, %xmm0