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Differential D122290

[RISCV] Remove check and update test file in D121183
ClosedPublic

Authored by StephenFan on Mar 22 2022, 11:14 PM.

Details

Reviewers
khchen
Commits
rG5800fb41a6b9: [RISCV] Remove check and update test file in D121183

Diff Detail

Event Timeline

StephenFan created this revision.Mar 22 2022, 11:14 PM
Herald added a project: Restricted Project. · View Herald TranscriptMar 22 2022, 11:14 PM
Herald added subscribers: • s, VincentWu, luke957 and 28 others. · View Herald Transcript
StephenFan requested review of this revision.Mar 22 2022, 11:14 PM
Herald added a project: Restricted Project. · View Herald TranscriptMar 22 2022, 11:14 PM
Herald added subscribers: llvm-commits, • pcwang-thead, eopXD, MaskRay. · View Herald Transcript
Harbormaster completed remote builds in B155782: Diff 417506.Mar 22 2022, 11:15 PM
StephenFan mentioned this in D121183: [RISCV] Generate correct ELF EFlags when .ll file has target-abi attribute.Mar 22 2022, 11:18 PM
khchen accepted this revision.Mar 23 2022, 12:35 AM

LGTM, thanks!!!

This revision is now accepted and ready to land.Mar 23 2022, 12:35 AM
This revision was landed with ongoing or failed builds.Mar 23 2022, 9:50 AM
Closed by commit rG5800fb41a6b9: [RISCV] Remove check and update test file in D121183 (authored by StephenFan). · Explain Why
This revision was automatically updated to reflect the committed changes.
StephenFan added a commit: rG5800fb41a6b9: [RISCV] Remove check and update test file in D121183.

Revision Contents

PathSize
llvm/
lib/
Target/
RISCV/
MCTargetDesc/
11 lines
test/
CodeGen/
RISCV/
2 lines
MC/
RISCV/
2 lines

Diff 417671

llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp

Show First 20 Lines • Show All 74 Lines • ▼ Show 20 LinescreateRISCVMCObjectFileInfo(MCContext &Ctx, bool PIC,
return MOFI; return MOFI;
} }
static MCSubtargetInfo *createRISCVMCSubtargetInfo(const Triple &TT, static MCSubtargetInfo *createRISCVMCSubtargetInfo(const Triple &TT,
StringRef CPU, StringRef FS) { StringRef CPU, StringRef FS) {
if (CPU.empty() || CPU == "generic") if (CPU.empty() || CPU == "generic")
CPU = TT.isArch64Bit() ? "generic-rv64" : "generic-rv32"; CPU = TT.isArch64Bit() ? "generic-rv64" : "generic-rv32";
MCSubtargetInfo *STI = return createRISCVMCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS);
createRISCVMCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS);
// Check if Feature string is valid
auto ISAInfo =
RISCVFeatures::parseFeatureBits(TT.isArch64Bit(), STI->getFeatureBits());
if (!ISAInfo)
report_fatal_error(ISAInfo.takeError());
else
return STI;
} }
static MCInstPrinter *createRISCVMCInstPrinter(const Triple &T, static MCInstPrinter *createRISCVMCInstPrinter(const Triple &T,
unsigned SyntaxVariant, unsigned SyntaxVariant,
const MCAsmInfo &MAI, const MCAsmInfo &MAI,
const MCInstrInfo &MII, const MCInstrInfo &MII,
const MCRegisterInfo &MRI) { const MCRegisterInfo &MRI) {
return new RISCVInstPrinter(MAI, MII, MRI); return new RISCVInstPrinter(MAI, MII, MRI);
▲ Show 20 Lines • Show All 93 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/mattr-invalid-combination.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: not --crash llc -mtriple=riscv64 -mattr=+e < %s 2>&1 \ ; RUN: not --crash llc -mtriple=riscv64 -mattr=+e < %s 2>&1 \
; RUN: | FileCheck -check-prefix=RV64E %s ; RUN: | FileCheck -check-prefix=RV64E %s
; RV64E: LLVM ERROR: standard user-level extension 'e' requires 'rv32' ; RV64E: LLVM ERROR: RV32E can't be enabled for an RV64 target

llvm/test/MC/RISCV/mattr-invalid-combination.s

# RUN: not --crash llvm-mc -triple riscv64 -mattr=+e < %s 2>&1 \ # RUN: not --crash llvm-mc -triple riscv64 -mattr=+e < %s 2>&1 \
# RUN: | FileCheck %s -check-prefix=RV64E # RUN: | FileCheck %s -check-prefix=RV64E
# RV64E: LLVM ERROR: standard user-level extension 'e' requires 'rv32' # RV64E: LLVM ERROR: RV32E can't be enabled for an RV64 target