[PowerPC] The BL8_NOTOC_RM instruction needs to produce a notoc relocation.

[stefanp]

Summary

The BL8_NOTOC_RM instruction was incorrectly producing a relocation that reqired
a TOC restore after the call. This patch fixes that issue and the notoc
relocation is now used.

[jsji]

llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp

53

Can we somehow set flag in td eg: set TSFlags in IForm_notoc, then use it for all NOTOC opcode, and check the flag in MC so that we won't miss if we add new variation based on BL8_NOTOC?

[jsji]

LGTM as long as we have followup patch to prevent similar things happen again. Thanks.

llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp

getDirectBrEncoding(const MCInst &MI, unsigned OpNo,
                     const MCSubtargetInfo &STI) const {
   const MCOperand &MO = MI.getOperand(OpNo);
 
   if (MO.isReg() || MO.isImm())
     return getMachineOpValue(MI, MO, Fixups, STI);
   // Add a fixup for the branch target.
   Fixups.push_back(MCFixup::create(0, MO.getExpr(),
                                    ((MI.getOpcode() == PPC::BL8_NOTOC ||
-                                     MI.getOpcode() == PPC::BL8_NOTOC_TLS)
+                                     MI.getOpcode() == PPC::BL8_NOTOC_TLS ||
+                                     MI.getOpcode() == PPC::BL8_NOTOC_RM)
                                         ? (MCFixupKind)PPC::fixup_ppc_br24_notoc
                                         : (MCFixupKind)PPC::fixup_ppc_br24)));
   return 0;
 }
 
 unsigned PPCMCCodeEmitter::getCondBrEncoding(const MCInst &MI, unsigned OpNo,
                                      SmallVectorImpl<MCFixup> &Fixups,
                                      const MCSubtargetInfo &STI) const {

llvm/lib/Target/PowerPC/PPCMCInstLower.cpp

static MCOperand GetSymbolRef(const MachineOperand &MO, const MCSymbol *Symbol,
   const TargetMachine &TM = Printer.TM;
 
   unsigned MIOpcode = MI->getOpcode();
   assert((Subtarget->isUsingPCRelativeCalls() || MIOpcode != PPC::BL8_NOTOC) &&
          "BL8_NOTOC is only valid when using PC Relative Calls.");
   if (Subtarget->isUsingPCRelativeCalls()) {
     if (MIOpcode == PPC::TAILB || MIOpcode == PPC::TAILB8 ||
         MIOpcode == PPC::TCRETURNdi || MIOpcode == PPC::TCRETURNdi8 ||
-        MIOpcode == PPC::BL8_NOTOC) {
+        MIOpcode == PPC::BL8_NOTOC || MIOpcode == PPC::BL8_NOTOC_RM) {
       RefKind = MCSymbolRefExpr::VK_PPC_NOTOC;
     }
     if (MO.getTargetFlags() == PPCII::MO_PCREL_OPT_FLAG)
       RefKind = MCSymbolRefExpr::VK_PPC_PCREL_OPT;
   }
 
   const MCExpr *Expr = MCSymbolRefExpr::create(Symbol, RefKind, Ctx);
   // If -msecure-plt -fPIC, add 32768 to symbol.

llvm/test/CodeGen/PowerPC/ppc64-notoc-rm-relocation.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
+; RUN:   < %s | FileCheck %s --check-prefix LE-P10
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:   -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
+; RUN:   < %s | FileCheck %s --check-prefix BE-P10
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
+; RUN:   < %s | FileCheck %s --check-prefix LE-P9
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:   -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
+; RUN:   < %s | FileCheck %s --check-prefix BE-P9
+
+; Function Attrs: nounwind strictfp
+define dso_local signext i32 @main() #0 {
+; LE-P10-LABEL: main:
+; LE-P10:       # %bb.0: # %_main_entry
+; LE-P10-NEXT:    mflr r0
+; LE-P10-NEXT:    std r0, 16(r1)
+; LE-P10-NEXT:    stdu r1, -32(r1)
+; LE-P10-NEXT:    bl callee@notoc
+; LE-P10-NEXT:    li r3, 0
+; LE-P10-NEXT:    addi r1, r1, 32
+; LE-P10-NEXT:    ld r0, 16(r1)
+; LE-P10-NEXT:    mtlr r0
+; LE-P10-NEXT:    blr
+;
+; BE-P10-LABEL: main:
+; BE-P10:       # %bb.0: # %_main_entry
+; BE-P10-NEXT:    mflr r0
+; BE-P10-NEXT:    std r0, 16(r1)
+; BE-P10-NEXT:    stdu r1, -112(r1)
+; BE-P10-NEXT:    bl callee
+; BE-P10-NEXT:    nop
+; BE-P10-NEXT:    li r3, 0
+; BE-P10-NEXT:    addi r1, r1, 112
+; BE-P10-NEXT:    ld r0, 16(r1)
+; BE-P10-NEXT:    mtlr r0
+; BE-P10-NEXT:    blr
+;
+; LE-P9-LABEL: main:
+; LE-P9:       # %bb.0: # %_main_entry
+; LE-P9-NEXT:    mflr r0
+; LE-P9-NEXT:    std r0, 16(r1)
+; LE-P9-NEXT:    stdu r1, -32(r1)
+; LE-P9-NEXT:    bl callee
+; LE-P9-NEXT:    nop
+; LE-P9-NEXT:    li r3, 0
+; LE-P9-NEXT:    addi r1, r1, 32
+; LE-P9-NEXT:    ld r0, 16(r1)
+; LE-P9-NEXT:    mtlr r0
+; LE-P9-NEXT:    blr
+;
+; BE-P9-LABEL: main:
+; BE-P9:       # %bb.0: # %_main_entry
+; BE-P9-NEXT:    mflr r0
+; BE-P9-NEXT:    std r0, 16(r1)
+; BE-P9-NEXT:    stdu r1, -112(r1)
+; BE-P9-NEXT:    bl callee
+; BE-P9-NEXT:    nop
+; BE-P9-NEXT:    li r3, 0
+; BE-P9-NEXT:    addi r1, r1, 112
+; BE-P9-NEXT:    ld r0, 16(r1)
+; BE-P9-NEXT:    mtlr r0
+; BE-P9-NEXT:    blr
+_main_entry:
+  call void @callee() #1
+  ret i32 0
+}
+
+; Function Attrs: strictfp
+declare void @callee() #1
+
+attributes #0 = { nounwind strictfp }
+attributes #1 = { strictfp }