We still have some problems that need discussion
- Arithmetic instructions with addressing mode dd & dr have decoding conflict. For example: ADD32dd & ADD32dr, SUB16dd & SUB16dr
- pc-relative decoder.
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[WIP][M68k][Disassembler] Adopt the new variable length infrastructure in disassembler AbandonedPublic Authored by 0x59616e on Feb 25 2022, 7:18 PM.
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Event Timeline0x59616e retitled this revision from [WIP][M68k][Disassembler] Adopt the new variable length infra in disassembler to [WIP][M68k][Disassembler] Adopt the new variable length infrastructure in disassembler.Feb 25 2022, 7:18 PM Comment Actions FYI, I've found some bugs in operand decoding. But that doesn't bother the discussion of the problems I listed. Comment Actions OK, after fixing that bug, more decoding conflict show up. I don't know why. It may take some time. Comment Actions FYI, here are the instructions that have decoding conflict: OR16dd / OR16dr I have two ideas:
or
Revision Contents
Diff 411654 llvm/lib/Target/M68k/CMakeLists.txt
llvm/lib/Target/M68k/Disassembler/M68kDisassembler.cpp
llvm/lib/Target/M68k/M68kInstrFormats.td
llvm/test/MC/Disassembler/M68k/bits.txt
llvm/test/MC/Disassembler/M68k/control.txt
llvm/test/MC/Disassembler/M68k/data.txt
llvm/test/MC/Disassembler/M68k/shift-rotate.txt
llvm/test/MC/M68k/Relaxations/branch.s
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