[AMDGPU][MC][GFX10] Added an alias for HW_REG_HW_ID1

[dp]

Summary

Enabled HW_REG_HW_ID as an alias for HW_REG_HW_ID1. This is required for compatibility with existing code.

[dp]

Corrected formatting

[foad]

This is a temporary fix because https://github.com/ROCmSoftwarePlatform/rccl is still using HW_REG_HW_ID, right?

[dp]

In D119939#3329039, @foad wrote:

This is a temporary fix because https://github.com/ROCmSoftwarePlatform/rccl is still using HW_REG_HW_ID, right?

Yes

llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

 AMDGPUAsmParser::parseHwregBody(OperandInfoTy &HwReg,
                                 OperandInfoTy &Offset,
                                 OperandInfoTy &Width) {
   using namespace llvm::AMDGPU::Hwreg;
 
   // The register may be specified by name or using a numeric code
   HwReg.Loc = getLoc();
   if (isToken(AsmToken::Identifier) &&
-      (HwReg.Id = getHwregId(getTokenStr())) >= 0) {
+      (HwReg.Id = getHwregId(getTokenStr(), getSTI())) >= 0) {
     HwReg.IsSymbolic = true;
     lex(); // skip register name
   } else if (!parseExpr(HwReg.Id, "a register name")) {
     return false;
   }
 
   if (trySkipToken(AsmToken::RParen))
     return true;

llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h

 unsigned encodeWaitcnt(const IsaVersion &Version,
                        unsigned Vmcnt, unsigned Expcnt, unsigned Lgkmcnt);
 
 unsigned encodeWaitcnt(const IsaVersion &Version, const Waitcnt &Decoded);
 
 namespace Hwreg {
 
 LLVM_READONLY
-int64_t getHwregId(const StringRef Name);
+int64_t getHwregId(const StringRef Name, const MCSubtargetInfo &STI);
 
 LLVM_READNONE
 bool isValidHwreg(int64_t Id, const MCSubtargetInfo &STI);
 
 LLVM_READNONE
 bool isValidHwreg(int64_t Id);
 
 LLVM_READNONE

llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp

 }
 
 //===----------------------------------------------------------------------===//
 // hwreg
 //===----------------------------------------------------------------------===//
 
 namespace Hwreg {
 
-int64_t getHwregId(const StringRef Name) {
+int64_t getHwregId(const StringRef Name, const MCSubtargetInfo &STI) {
+  if (isGFX10(STI) && Name == "HW_REG_HW_ID")  // An alias
+    return ID_HW_ID1;
   for (int Id = ID_SYMBOLIC_FIRST_; Id < ID_SYMBOLIC_LAST_; ++Id) {
     if (IdSymbolic[Id] && Name == IdSymbolic[Id])
       return Id;
   }
   return ID_UNKNOWN_;
 }
 
 static unsigned getLastSymbolicHwreg(const MCSubtargetInfo &STI) {

llvm/test/MC/AMDGPU/sopk.s

 // SICI: s_setreg_b32 hwreg(HW_REG_TRAPSTS), s2       ; encoding: [0x03,0xf8,0x82,0xb9]
 // VI9:  s_setreg_b32 hwreg(HW_REG_TRAPSTS), s2       ; encoding: [0x03,0xf8,0x02,0xb9]
 // GFX10: s_setreg_b32 hwreg(HW_REG_TRAPSTS), s2 ; encoding: [0x03,0xf8,0x82,0xb9]
 
 // HW register identifier, default offset/width implied
 s_setreg_b32 hwreg(HW_REG_HW_ID), s2
 // SICI: s_setreg_b32 hwreg(HW_REG_HW_ID), s2       ; encoding: [0x04,0xf8,0x82,0xb9]
 // VI9:  s_setreg_b32 hwreg(HW_REG_HW_ID), s2       ; encoding: [0x04,0xf8,0x02,0xb9]
-// NOGFX10: error: specified hardware register is not supported on this GPU
+// GFX10: s_setreg_b32 hwreg(HW_REG_HW_ID1), s2   ; encoding: [0x17,0xf8,0x82,0xb9]
 
 s_setreg_b32 hwreg(HW_REG_HW_ID1), s2
 // NOSICIVI: error: specified hardware register is not supported on this GPU
 // NOGFX9: error: specified hardware register is not supported on this GPU
 // GFX10: s_setreg_b32 hwreg(HW_REG_HW_ID1), s2      ; encoding: [0x17,0xf8,0x82,0xb9]
 
 s_setreg_b32 hwreg(HW_REG_HW_ID2), s2
 // NOSICIVI: error: specified hardware register is not supported on this GPU