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[X86] Update register RCL/RCR by 1 and immediate scheduling for Intel CPUs
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Authored by craig.topper on Feb 7 2022, 11:37 PM.

Details

Summary

Most Intel CPU scheduler files lumped the immediate and 1 instructions
together, but uops.info shows they are quite different.

For the most part the by 1 instructions were pretty accurate to the uops.info
data except the latency was 3 instead of 2 as uops.info indicates.

The by immediate instructions need 7 or 8 uops and have higher latency.

It looks like the 8-bit by immediate instructions may need even more
uops, but I just lumped them with the 16/32/64.

Noticed while checking out PR53648. So mostly I cared about the by 1
instructions.

Diff Detail

Event Timeline

craig.topper created this revision.Feb 7 2022, 11:37 PM
craig.topper requested review of this revision.Feb 7 2022, 11:37 PM
Herald added a project: Restricted Project. · View Herald TranscriptFeb 7 2022, 11:37 PM
RKSimon accepted this revision.Feb 8 2022, 1:53 AM

LGTM

This revision is now accepted and ready to land.Feb 8 2022, 1:53 AM
pengfei accepted this revision.Feb 8 2022, 5:03 AM
pengfei added a subscriber: HaohaiWen.

Thanks for improving on it!

This revision was landed with ongoing or failed builds.Feb 8 2022, 9:34 AM
This revision was automatically updated to reflect the committed changes.