[AMDGPU] SILoadStoreOptimizer: use separate lists for AGPR instructions

[foad]

Summary

Using separate lists for AGPR and non-AGPR instructions seems like a
cleaner solution than putting them all in the same list and then later
refusing to merge instructions of different AGPR-ness.

[rampitec]

LGTM

llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp

struct CombineInfo {
     unsigned EltSize;
     unsigned Offset;
     unsigned Width;
     unsigned Format;
     unsigned BaseOff;
     unsigned DMask;
     InstClassEnum InstClass;
     unsigned CPol = 0;
+    bool IsAGPR;
     bool UseST64;
     int AddrIdx[MaxAddressRegs];
     const MachineOperand *AddrReg[MaxAddressRegs];
     unsigned NumAddresses;
     unsigned Order;
 
     bool hasSameBaseAddress(const MachineInstr &MI) {
       for (unsigned i = 0; i < NumAddresses; i++) {
void SILoadStoreOptimizer::CombineInfo::setMI(MachineBasicBlock::iterator MI,
                                               const SILoadStoreOptimizer &LSO) {
   I = MI;
   unsigned Opc = MI->getOpcode();
   InstClass = getInstClass(Opc, *LSO.TII);
 
   if (InstClass == UNKNOWN)
     return;
 
+  IsAGPR = LSO.TRI->hasAGPRs(LSO.getDataRegClass(*MI));
+
   switch (InstClass) {
   case DS_READ:
    EltSize =
           (Opc == AMDGPU::DS_READ_B64 || Opc == AMDGPU::DS_READ_B64_gfx9) ? 8
                                                                           : 4;
    break;
   case DS_WRITE:
     EltSize =
if (InstClass == UNKNOWN) {
     return false;
   }
   const unsigned InstSubclass = getInstSubclass(Opc, *TII);
 
   DenseSet<Register> RegDefsToMove;
   DenseSet<Register> PhysRegUsesToMove;
   addDefsUsesToList(*CI.I, RegDefsToMove, PhysRegUsesToMove);
 
-  const TargetRegisterClass *DataRC = getDataRegClass(*CI.I);
-  bool IsAGPR = TRI->hasAGPRs(DataRC);
-
   MachineBasicBlock::iterator E = std::next(Paired.I);
   MachineBasicBlock::iterator MBBI = std::next(CI.I);
   MachineBasicBlock::iterator MBBE = CI.I->getParent()->end();
   for (; MBBI != E; ++MBBI) {
 
     if (MBBI == MBBE) {
       // CombineInfo::Order is a hint on the instruction ordering within the
       // basic block. This hint suggests that CI precedes Paired, which is
for (; MBBI != E; ++MBBI) {
     //   DS_WRITE_B32 addr, f(w), idx1
     // where the DS_READ_B32 ends up in InstsToMove and therefore prevents
     // merging of the two writes.
     if (addToListsIfDependent(*MBBI, RegDefsToMove, PhysRegUsesToMove,
                               InstsToMove))
       continue;
 
     if (&*MBBI == &*Paired.I) {
-      if (TRI->hasAGPRs(getDataRegClass(*MBBI)) != IsAGPR)
-        return false;
       // FIXME: nothing is illegal in a ds_write2 opcode with two AGPR data
       //        operands. However we are reporting that ds_write2 shall have
       //        only VGPR data so that machine copy propagation does not
       //        create an illegal instruction with a VGPR and AGPR sources.
       //        Consequenctially if we create such instruction the verifier
       //        will complain.
-      if (IsAGPR && CI.InstClass == DS_WRITE)
+      if (CI.IsAGPR && CI.InstClass == DS_WRITE)
         return false;
 
       // We need to go through the list of instructions that we plan to
       // move and make sure they are all safe to move down past the merged
       // instruction.
       if (canMoveInstsAcrossMemOp(*MBBI, InstsToMove, AA)) {
 
         // Call offsetsCanBeCombined with modify = true so that the offsets are
bool SILoadStoreOptimizer::promoteConstantOffsetToImm(
 
   return false;
 }
 
 void SILoadStoreOptimizer::addInstToMergeableList(const CombineInfo &CI,
                  std::list<std::list<CombineInfo> > &MergeableInsts) const {
   for (std::list<CombineInfo> &AddrList : MergeableInsts) {
     if (AddrList.front().InstClass == CI.InstClass &&
+        AddrList.front().IsAGPR == CI.IsAGPR &&
         AddrList.front().hasSameBaseAddress(*CI.I)) {
       AddrList.emplace_back(CI);
       return;
     }
   }
 
   // Base address not found, so add a new list.
   MergeableInsts.emplace_back(1, CI);