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There is already a helper function isRegIntersect using MCRegAliasIterator.
| llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp | ||
|---|---|---|
| 3643 | I cannot get RC itself. | |
| llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp | ||
|---|---|---|
| 3643 | It's in the MCInstrDesc which you have | |
| llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp | ||
|---|---|---|
| 3643 | It is not: struct MCRegisterDesc {
uint32_t Name; // Printable name for the reg (for debugging)
uint32_t SubRegs; // Sub-register set, described above
uint32_t SuperRegs; // Super-register set, described above
// Offset into MCRI::SubRegIndices of a list of sub-register indices for each
// sub-register in SubRegs.
uint32_t SubRegIndices;
// RegUnits - Points to the list of register units. The low 4 bits holds the
// Scale, the high bits hold an offset into DiffLists. See MCRegUnitIterator.
uint32_t RegUnits;
/// Index into list with lane mask sequences. The sequence contains a lanemask
/// for every register unit.
uint16_t RegUnitLaneMasks;
};I guess because is a register can belong to different classes. | |
| llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp | ||
|---|---|---|
| 3643 | MCRI.getRegClass(Desc.OpInfo[OpIdx].RegClass) | |
| llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp | ||
|---|---|---|
| 3643 | Ugh, InstrDesc, not RegDesc! | |
Can't you get the width directly from the operand register class without making an assumption about the number of register units?