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Differential D117485

AMDGPU: Do not optimize out the kernarg segment for clover
Needs ReviewPublic

Authored by arsenm on Jan 17 2022, 6:47 AM.

Details

Reviewers
jvesely
Group Reviewers
Restricted Project
Summary

As far as I can tell clover is stuck in the middle of migrating from
using kernel arguments placed before the user kernel arguments, to
moving them after. One field is at the end, and the rest are still at
the beginning. The mesa3d OS disables the segment at the beginning,
but doesn't add them to the end area.




Therefore, this is still using implicit arguments placed at the

beginning of the kernarg segment, in addition to the after argument

implicit arg area. We don't track usage of the special intrinsics

loading from the start of the kernarg segment, so stop optimizing

this. Eventually all implicit arguments should be moved to the end of

the buffer.






Fixes using a null dereference for llvm.r600.* intrinsics for kernels

with no arguments.
Diff Detail
Unit TestsFailed
TimeTest
620 msx64 debian > SanitizerCommon-tsan-x86_64-Linux.Linux::decorate_proc_maps.cpp
Revision Contents
PathSize
llvm/
lib/
Target/
AMDGPU/
6 lines
test/
CodeGen/
AMDGPU/
GlobalISel/
48 lines
15 lines
84 lines
10 lines
Diff 400532
llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
Show First 20 Lines • Show All 60 Lines • ▼ Show 20 LinesSIMachineFunctionInfo::SIMachineFunctionInfo(const MachineFunction &MF)

  // FIXME: Should have analysis or something rather than attribute to detect
  // FIXME: Should have analysis or something rather than attribute to detect

  // calls.
  // calls.

  const bool HasCalls = F.hasFnAttribute("amdgpu-calls");
  const bool HasCalls = F.hasFnAttribute("amdgpu-calls");




  const bool IsKernel = CC == CallingConv::AMDGPU_KERNEL ||
  const bool IsKernel = CC == CallingConv::AMDGPU_KERNEL ||

                        CC == CallingConv::SPIR_KERNEL;
                        CC == CallingConv::SPIR_KERNEL;




  if (IsKernel) {
  if (IsKernel) {

    if (!F.arg_empty() || ST.getImplicitArgNumBytes(F) != 0)
    if (!F.arg_empty() || ST.getImplicitArgNumBytes(F) != 0 ||

        // FIXME: Mesa is still using implicit arguments placed before user

        // kernel arguments, and we do not see if we can optimize them

        // out. These should be consolidated into the same implicit arg section

        ST.getExplicitKernelArgOffset(F) != 0)

      KernargSegmentPtr = true;
      KernargSegmentPtr = true;

    WorkGroupIDX = true;
    WorkGroupIDX = true;

    WorkItemIDX = true;
    WorkItemIDX = true;

  } else if (CC == CallingConv::AMDGPU_PS) {
  } else if (CC == CallingConv::AMDGPU_PS) {

    PSInputAddr = AMDGPU::getInitialPSInputAddr(F);
    PSInputAddr = AMDGPU::getInitialPSInputAddr(F);

  }
  }




  if (!isEntryFunction()) {
  if (!isEntryFunction()) {

▲ Show 20 Lines • Show All 554 Lines • Show Last 20 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch.ll
Show First 20 Lines • Show All 50 Lines • ▼ Show 20 Linesbb:

  %i11 = bitcast float addrspace(5)* %i10 to i32 addrspace(5)*
  %i11 = bitcast float addrspace(5)* %i10 to i32 addrspace(5)*

  %i12 = load volatile i32, i32 addrspace(5)* %i11, align 4
  %i12 = load volatile i32, i32 addrspace(5)* %i11, align 4

  ret void
  ret void

}
}




define amdgpu_kernel void @store_load_vindex_kernel() {
define amdgpu_kernel void @store_load_vindex_kernel() {

; GFX9-LABEL: store_load_vindex_kernel:
; GFX9-LABEL: store_load_vindex_kernel:

; GFX9:       ; %bb.0: ; %bb
; GFX9:       ; %bb.0: ; %bb

; GFX9-NEXT:    s_add_u32 flat_scratch_lo, s0, s3
; GFX9-NEXT:    s_add_u32 flat_scratch_lo, s2, s5

; GFX9-NEXT:    v_lshlrev_b32_e32 v1, 2, v0
; GFX9-NEXT:    v_lshlrev_b32_e32 v1, 2, v0

; GFX9-NEXT:    v_mov_b32_e32 v2, 4
; GFX9-NEXT:    v_mov_b32_e32 v2, 4

; GFX9-NEXT:    v_sub_u32_e32 v0, 0, v0
; GFX9-NEXT:    v_sub_u32_e32 v0, 0, v0

; GFX9-NEXT:    s_addc_u32 flat_scratch_hi, s1, 0
; GFX9-NEXT:    s_addc_u32 flat_scratch_hi, s3, 0

; GFX9-NEXT:    v_add_u32_e32 v1, v2, v1
; GFX9-NEXT:    v_add_u32_e32 v1, v2, v1

; GFX9-NEXT:    v_mov_b32_e32 v3, 15
; GFX9-NEXT:    v_mov_b32_e32 v3, 15

; GFX9-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
; GFX9-NEXT:    v_lshlrev_b32_e32 v0, 2, v0

; GFX9-NEXT:    scratch_store_dword v1, v3, off
; GFX9-NEXT:    scratch_store_dword v1, v3, off

; GFX9-NEXT:    s_waitcnt vmcnt(0)
; GFX9-NEXT:    s_waitcnt vmcnt(0)

; GFX9-NEXT:    v_add_u32_e32 v0, v2, v0
; GFX9-NEXT:    v_add_u32_e32 v0, v2, v0

; GFX9-NEXT:    scratch_load_dword v0, v0, off offset:124 glc
; GFX9-NEXT:    scratch_load_dword v0, v0, off offset:124 glc

; GFX9-NEXT:    s_waitcnt vmcnt(0)
; GFX9-NEXT:    s_waitcnt vmcnt(0)

; GFX9-NEXT:    s_endpgm
; GFX9-NEXT:    s_endpgm

;
;

; GFX10-LABEL: store_load_vindex_kernel:
; GFX10-LABEL: store_load_vindex_kernel:

; GFX10:       ; %bb.0: ; %bb
; GFX10:       ; %bb.0: ; %bb

; GFX10-NEXT:    s_add_u32 s0, s0, s3
; GFX10-NEXT:    s_add_u32 s2, s2, s5

; GFX10-NEXT:    s_addc_u32 s1, s1, 0
; GFX10-NEXT:    s_addc_u32 s3, s3, 0

; GFX10-NEXT:    s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s0
; GFX10-NEXT:    s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s2

; GFX10-NEXT:    s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s1
; GFX10-NEXT:    s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s3

; GFX10-NEXT:    v_sub_nc_u32_e32 v1, 0, v0
; GFX10-NEXT:    v_sub_nc_u32_e32 v1, 0, v0

; GFX10-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
; GFX10-NEXT:    v_lshlrev_b32_e32 v0, 2, v0

; GFX10-NEXT:    v_mov_b32_e32 v2, 4
; GFX10-NEXT:    v_mov_b32_e32 v2, 4

; GFX10-NEXT:    v_mov_b32_e32 v3, 15
; GFX10-NEXT:    v_mov_b32_e32 v3, 15

; GFX10-NEXT:    v_lshlrev_b32_e32 v1, 2, v1
; GFX10-NEXT:    v_lshlrev_b32_e32 v1, 2, v1

; GFX10-NEXT:    v_add_nc_u32_e32 v0, v2, v0
; GFX10-NEXT:    v_add_nc_u32_e32 v0, v2, v0

; GFX10-NEXT:    v_add_nc_u32_e32 v1, v2, v1
; GFX10-NEXT:    v_add_nc_u32_e32 v1, v2, v1

; GFX10-NEXT:    scratch_store_dword v0, v3, off
; GFX10-NEXT:    scratch_store_dword v0, v3, off

▲ Show 20 Lines • Show All 140 Lines • ▼ Show 20 Linesbb:

  %i11 = bitcast float addrspace(5)* %i10 to i32 addrspace(5)*
  %i11 = bitcast float addrspace(5)* %i10 to i32 addrspace(5)*

  %i12 = load volatile i32, i32 addrspace(5)* %i11, align 4
  %i12 = load volatile i32, i32 addrspace(5)* %i11, align 4

  ret void
  ret void

}
}




define amdgpu_kernel void @store_load_vindex_small_offset_kernel() {
define amdgpu_kernel void @store_load_vindex_small_offset_kernel() {

; GFX9-LABEL: store_load_vindex_small_offset_kernel:
; GFX9-LABEL: store_load_vindex_small_offset_kernel:

; GFX9:       ; %bb.0: ; %bb
; GFX9:       ; %bb.0: ; %bb

; GFX9-NEXT:    s_add_u32 flat_scratch_lo, s0, s3
; GFX9-NEXT:    s_add_u32 flat_scratch_lo, s2, s5

; GFX9-NEXT:    s_addc_u32 flat_scratch_hi, s1, 0
; GFX9-NEXT:    s_addc_u32 flat_scratch_hi, s3, 0

; GFX9-NEXT:    s_mov_b32 vcc_hi, 0
; GFX9-NEXT:    s_mov_b32 vcc_hi, 0

; GFX9-NEXT:    scratch_load_dword v1, off, vcc_hi offset:4 glc
; GFX9-NEXT:    scratch_load_dword v1, off, vcc_hi offset:4 glc

; GFX9-NEXT:    s_waitcnt vmcnt(0)
; GFX9-NEXT:    s_waitcnt vmcnt(0)

; GFX9-NEXT:    v_lshlrev_b32_e32 v1, 2, v0
; GFX9-NEXT:    v_lshlrev_b32_e32 v1, 2, v0

; GFX9-NEXT:    v_mov_b32_e32 v2, 0x104
; GFX9-NEXT:    v_mov_b32_e32 v2, 0x104

; GFX9-NEXT:    v_sub_u32_e32 v0, 0, v0
; GFX9-NEXT:    v_sub_u32_e32 v0, 0, v0

; GFX9-NEXT:    v_add_u32_e32 v1, v2, v1
; GFX9-NEXT:    v_add_u32_e32 v1, v2, v1

; GFX9-NEXT:    v_mov_b32_e32 v3, 15
; GFX9-NEXT:    v_mov_b32_e32 v3, 15

; GFX9-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
; GFX9-NEXT:    v_lshlrev_b32_e32 v0, 2, v0

; GFX9-NEXT:    scratch_store_dword v1, v3, off
; GFX9-NEXT:    scratch_store_dword v1, v3, off

; GFX9-NEXT:    s_waitcnt vmcnt(0)
; GFX9-NEXT:    s_waitcnt vmcnt(0)

; GFX9-NEXT:    v_add_u32_e32 v0, v2, v0
; GFX9-NEXT:    v_add_u32_e32 v0, v2, v0

; GFX9-NEXT:    scratch_load_dword v0, v0, off offset:124 glc
; GFX9-NEXT:    scratch_load_dword v0, v0, off offset:124 glc

; GFX9-NEXT:    s_waitcnt vmcnt(0)
; GFX9-NEXT:    s_waitcnt vmcnt(0)

; GFX9-NEXT:    s_endpgm
; GFX9-NEXT:    s_endpgm

;
;

; GFX10-LABEL: store_load_vindex_small_offset_kernel:
; GFX10-LABEL: store_load_vindex_small_offset_kernel:

; GFX10:       ; %bb.0: ; %bb
; GFX10:       ; %bb.0: ; %bb

; GFX10-NEXT:    s_add_u32 s0, s0, s3
; GFX10-NEXT:    s_add_u32 s2, s2, s5

; GFX10-NEXT:    s_addc_u32 s1, s1, 0
; GFX10-NEXT:    s_addc_u32 s3, s3, 0

; GFX10-NEXT:    s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s0
; GFX10-NEXT:    s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s2

; GFX10-NEXT:    s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s1
; GFX10-NEXT:    s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s3

; GFX10-NEXT:    v_sub_nc_u32_e32 v1, 0, v0
; GFX10-NEXT:    v_sub_nc_u32_e32 v1, 0, v0

; GFX10-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
; GFX10-NEXT:    v_lshlrev_b32_e32 v0, 2, v0

; GFX10-NEXT:    v_mov_b32_e32 v2, 0x104
; GFX10-NEXT:    v_mov_b32_e32 v2, 0x104

; GFX10-NEXT:    v_mov_b32_e32 v3, 15
; GFX10-NEXT:    v_mov_b32_e32 v3, 15

; GFX10-NEXT:    v_lshlrev_b32_e32 v1, 2, v1
; GFX10-NEXT:    v_lshlrev_b32_e32 v1, 2, v1

; GFX10-NEXT:    v_add_nc_u32_e32 v0, v2, v0
; GFX10-NEXT:    v_add_nc_u32_e32 v0, v2, v0

; GFX10-NEXT:    v_add_nc_u32_e32 v1, v2, v1
; GFX10-NEXT:    v_add_nc_u32_e32 v1, v2, v1

; GFX10-NEXT:    scratch_load_dword v2, off, off offset:4 glc dlc
; GFX10-NEXT:    scratch_load_dword v2, off, off offset:4 glc dlc

▲ Show 20 Lines • Show All 132 Lines • ▼ Show 20 Linesbb:

  %i11 = bitcast float addrspace(5)* %i10 to i32 addrspace(5)*
  %i11 = bitcast float addrspace(5)* %i10 to i32 addrspace(5)*

  %i12 = load volatile i32, i32 addrspace(5)* %i11, align 4
  %i12 = load volatile i32, i32 addrspace(5)* %i11, align 4

  ret void
  ret void

}
}




define amdgpu_kernel void @store_load_vindex_large_offset_kernel() {
define amdgpu_kernel void @store_load_vindex_large_offset_kernel() {

; GFX9-LABEL: store_load_vindex_large_offset_kernel:
; GFX9-LABEL: store_load_vindex_large_offset_kernel:

; GFX9:       ; %bb.0: ; %bb
; GFX9:       ; %bb.0: ; %bb

; GFX9-NEXT:    s_add_u32 flat_scratch_lo, s0, s3
; GFX9-NEXT:    s_add_u32 flat_scratch_lo, s2, s5

; GFX9-NEXT:    s_addc_u32 flat_scratch_hi, s1, 0
; GFX9-NEXT:    s_addc_u32 flat_scratch_hi, s3, 0

; GFX9-NEXT:    s_mov_b32 vcc_hi, 0
; GFX9-NEXT:    s_mov_b32 vcc_hi, 0

; GFX9-NEXT:    scratch_load_dword v1, off, vcc_hi offset:4 glc
; GFX9-NEXT:    scratch_load_dword v1, off, vcc_hi offset:4 glc

; GFX9-NEXT:    s_waitcnt vmcnt(0)
; GFX9-NEXT:    s_waitcnt vmcnt(0)

; GFX9-NEXT:    v_lshlrev_b32_e32 v1, 2, v0
; GFX9-NEXT:    v_lshlrev_b32_e32 v1, 2, v0

; GFX9-NEXT:    v_mov_b32_e32 v2, 0x4004
; GFX9-NEXT:    v_mov_b32_e32 v2, 0x4004

; GFX9-NEXT:    v_sub_u32_e32 v0, 0, v0
; GFX9-NEXT:    v_sub_u32_e32 v0, 0, v0

; GFX9-NEXT:    v_add_u32_e32 v1, v2, v1
; GFX9-NEXT:    v_add_u32_e32 v1, v2, v1

; GFX9-NEXT:    v_mov_b32_e32 v3, 15
; GFX9-NEXT:    v_mov_b32_e32 v3, 15

; GFX9-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
; GFX9-NEXT:    v_lshlrev_b32_e32 v0, 2, v0

; GFX9-NEXT:    scratch_store_dword v1, v3, off
; GFX9-NEXT:    scratch_store_dword v1, v3, off

; GFX9-NEXT:    s_waitcnt vmcnt(0)
; GFX9-NEXT:    s_waitcnt vmcnt(0)

; GFX9-NEXT:    v_add_u32_e32 v0, v2, v0
; GFX9-NEXT:    v_add_u32_e32 v0, v2, v0

; GFX9-NEXT:    scratch_load_dword v0, v0, off offset:124 glc
; GFX9-NEXT:    scratch_load_dword v0, v0, off offset:124 glc

; GFX9-NEXT:    s_waitcnt vmcnt(0)
; GFX9-NEXT:    s_waitcnt vmcnt(0)

; GFX9-NEXT:    s_endpgm
; GFX9-NEXT:    s_endpgm

;
;

; GFX10-LABEL: store_load_vindex_large_offset_kernel:
; GFX10-LABEL: store_load_vindex_large_offset_kernel:

; GFX10:       ; %bb.0: ; %bb
; GFX10:       ; %bb.0: ; %bb

; GFX10-NEXT:    s_add_u32 s0, s0, s3
; GFX10-NEXT:    s_add_u32 s2, s2, s5

; GFX10-NEXT:    s_addc_u32 s1, s1, 0
; GFX10-NEXT:    s_addc_u32 s3, s3, 0

; GFX10-NEXT:    s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s0
; GFX10-NEXT:    s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s2

; GFX10-NEXT:    s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s1
; GFX10-NEXT:    s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s3

; GFX10-NEXT:    v_sub_nc_u32_e32 v1, 0, v0
; GFX10-NEXT:    v_sub_nc_u32_e32 v1, 0, v0

; GFX10-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
; GFX10-NEXT:    v_lshlrev_b32_e32 v0, 2, v0

; GFX10-NEXT:    v_mov_b32_e32 v2, 0x4004
; GFX10-NEXT:    v_mov_b32_e32 v2, 0x4004

; GFX10-NEXT:    v_mov_b32_e32 v3, 15
; GFX10-NEXT:    v_mov_b32_e32 v3, 15

; GFX10-NEXT:    v_lshlrev_b32_e32 v1, 2, v1
; GFX10-NEXT:    v_lshlrev_b32_e32 v1, 2, v1

; GFX10-NEXT:    v_add_nc_u32_e32 v0, v2, v0
; GFX10-NEXT:    v_add_nc_u32_e32 v0, v2, v0

; GFX10-NEXT:    v_add_nc_u32_e32 v1, v2, v1
; GFX10-NEXT:    v_add_nc_u32_e32 v1, v2, v1

; GFX10-NEXT:    scratch_load_dword v2, off, off offset:4 glc dlc
; GFX10-NEXT:    scratch_load_dword v2, off, off offset:4 glc dlc

▲ Show 20 Lines • Show All 74 Lines • ▼ Show 20 Linesbb:

  %i11 = bitcast float addrspace(5)* %i10 to i32 addrspace(5)*
  %i11 = bitcast float addrspace(5)* %i10 to i32 addrspace(5)*

  %i12 = load volatile i32, i32 addrspace(5)* %i11, align 4
  %i12 = load volatile i32, i32 addrspace(5)* %i11, align 4

  ret void
  ret void

}
}




define amdgpu_kernel void @store_load_large_imm_offset_kernel() {
define amdgpu_kernel void @store_load_large_imm_offset_kernel() {

; GFX9-LABEL: store_load_large_imm_offset_kernel:
; GFX9-LABEL: store_load_large_imm_offset_kernel:

; GFX9:       ; %bb.0: ; %bb
; GFX9:       ; %bb.0: ; %bb

; GFX9-NEXT:    s_add_u32 flat_scratch_lo, s0, s3
; GFX9-NEXT:    s_add_u32 flat_scratch_lo, s2, s5

; GFX9-NEXT:    s_addc_u32 flat_scratch_hi, s1, 0
; GFX9-NEXT:    s_addc_u32 flat_scratch_hi, s3, 0

; GFX9-NEXT:    v_mov_b32_e32 v0, 13
; GFX9-NEXT:    v_mov_b32_e32 v0, 13

; GFX9-NEXT:    s_mov_b32 vcc_hi, 0
; GFX9-NEXT:    s_mov_b32 vcc_hi, 0

; GFX9-NEXT:    s_movk_i32 s0, 0x3e80
; GFX9-NEXT:    s_movk_i32 s0, 0x3e80

; GFX9-NEXT:    scratch_store_dword off, v0, vcc_hi offset:4
; GFX9-NEXT:    scratch_store_dword off, v0, vcc_hi offset:4

; GFX9-NEXT:    s_waitcnt vmcnt(0)
; GFX9-NEXT:    s_waitcnt vmcnt(0)

; GFX9-NEXT:    v_mov_b32_e32 v0, 15
; GFX9-NEXT:    v_mov_b32_e32 v0, 15

; GFX9-NEXT:    s_add_i32 s0, s0, 4
; GFX9-NEXT:    s_add_i32 s0, s0, 4

; GFX9-NEXT:    scratch_store_dword off, v0, s0
; GFX9-NEXT:    scratch_store_dword off, v0, s0

; GFX9-NEXT:    s_waitcnt vmcnt(0)
; GFX9-NEXT:    s_waitcnt vmcnt(0)

; GFX9-NEXT:    scratch_load_dword v0, off, s0 glc
; GFX9-NEXT:    scratch_load_dword v0, off, s0 glc

; GFX9-NEXT:    s_waitcnt vmcnt(0)
; GFX9-NEXT:    s_waitcnt vmcnt(0)

; GFX9-NEXT:    s_endpgm
; GFX9-NEXT:    s_endpgm

;
;

; GFX10-LABEL: store_load_large_imm_offset_kernel:
; GFX10-LABEL: store_load_large_imm_offset_kernel:

; GFX10:       ; %bb.0: ; %bb
; GFX10:       ; %bb.0: ; %bb

; GFX10-NEXT:    s_add_u32 s0, s0, s3
; GFX10-NEXT:    s_add_u32 s2, s2, s5

; GFX10-NEXT:    s_addc_u32 s1, s1, 0
; GFX10-NEXT:    s_addc_u32 s3, s3, 0

; GFX10-NEXT:    s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s0
; GFX10-NEXT:    s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s2

; GFX10-NEXT:    s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s1
; GFX10-NEXT:    s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s3

; GFX10-NEXT:    v_mov_b32_e32 v0, 13
; GFX10-NEXT:    v_mov_b32_e32 v0, 13

; GFX10-NEXT:    v_mov_b32_e32 v1, 15
; GFX10-NEXT:    v_mov_b32_e32 v1, 15

; GFX10-NEXT:    s_movk_i32 s0, 0x3e80
; GFX10-NEXT:    s_movk_i32 s0, 0x3e80

; GFX10-NEXT:    s_add_i32 s0, s0, 4
; GFX10-NEXT:    s_add_i32 s0, s0, 4

; GFX10-NEXT:    scratch_store_dword off, v0, off offset:4
; GFX10-NEXT:    scratch_store_dword off, v0, off offset:4

; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0

; GFX10-NEXT:    scratch_store_dword off, v1, s0
; GFX10-NEXT:    scratch_store_dword off, v1, s0

; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0

▲ Show 20 Lines • Show All 238 Lines • Show Last 20 Lines
llvm/test/CodeGen/AMDGPU/amdgpu.work-item-intrinsics.deprecated.ll
Show First 20 Lines • Show All 47 Lines • ▼ Show 20 Lines
; EG: MOV {{\*? *}}[[VAL]], KC0[0].Z
; EG: MOV {{\*? *}}[[VAL]], KC0[0].Z

define amdgpu_kernel void @ngroups_z (i32 addrspace(1)* %out) {
define amdgpu_kernel void @ngroups_z (i32 addrspace(1)* %out) {

entry:
entry:

  %0 = call i32 @llvm.r600.read.ngroups.z() #0
  %0 = call i32 @llvm.r600.read.ngroups.z() #0

  store i32 %0, i32 addrspace(1)* %out
  store i32 %0, i32 addrspace(1)* %out

  ret void
  ret void

}
}




; FUNC-LABEL: {{^}}ngroups_z_no_kernargs:

; SI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x2

; VI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x8

; GCN-NOHSA: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]]

; GCN-NOHSA: buffer_store_dword [[VVAL]]



; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]]

; EG: MOV {{\*? *}}[[VAL]], KC0[0].Z

define amdgpu_kernel void @ngroups_z_no_kernargs() {

entry:

  %ngroups.z = call i32 @llvm.r600.read.ngroups.z() #0

  store volatile i32 %ngroups.z, i32 addrspace(1)* null

  ret void

}



; FUNC-LABEL: {{^}}global_size_x:
; FUNC-LABEL: {{^}}global_size_x:

; SI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x3
; SI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x3

; VI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0xc
; VI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0xc

; GCN-NOHSA: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]]
; GCN-NOHSA: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]]

; GCN-NOHSA: buffer_store_dword [[VVAL]]
; GCN-NOHSA: buffer_store_dword [[VVAL]]




; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]]
; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]]

; EG: MOV {{\*? *}}[[VAL]], KC0[0].W
; EG: MOV {{\*? *}}[[VAL]], KC0[0].W

▲ Show 20 Lines • Show All 95 Lines • Show Last 20 Lines
llvm/test/CodeGen/AMDGPU/flat-scratch.ll
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py

; RUN: llc -march=amdgcn -mcpu=gfx900 -mattr=-promote-alloca -amdgpu-enable-flat-scratch -verify-machineinstrs < %s | FileCheck --check-prefix=GFX9 %s
; RUN: llc -march=amdgcn -mcpu=gfx900 -mattr=-promote-alloca -amdgpu-enable-flat-scratch -verify-machineinstrs < %s | FileCheck --check-prefix=GFX9 %s

; RUN: llc -march=amdgcn -mcpu=gfx1030 -mattr=-promote-alloca -amdgpu-enable-flat-scratch -verify-machineinstrs < %s | FileCheck --check-prefix=GFX10 %s
; RUN: llc -march=amdgcn -mcpu=gfx1030 -mattr=-promote-alloca -amdgpu-enable-flat-scratch -verify-machineinstrs < %s | FileCheck --check-prefix=GFX10 %s

; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx900 -mattr=-promote-alloca -amdgpu-enable-flat-scratch -verify-machineinstrs < %s | FileCheck --check-prefix=GFX9-PAL %s
; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx900 -mattr=-promote-alloca -amdgpu-enable-flat-scratch -verify-machineinstrs < %s | FileCheck --check-prefix=GFX9-PAL %s

; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx1010 -mattr=-promote-alloca -amdgpu-enable-flat-scratch -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX10-PAL,GFX1010-PAL %s
; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx1010 -mattr=-promote-alloca -amdgpu-enable-flat-scratch -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX10-PAL,GFX1010-PAL %s

; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx1030 -mattr=-promote-alloca -amdgpu-enable-flat-scratch -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX10-PAL,GFX1030-PAL %s
; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx1030 -mattr=-promote-alloca -amdgpu-enable-flat-scratch -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX10-PAL,GFX1030-PAL %s




define amdgpu_kernel void @zero_init_kernel() {
define amdgpu_kernel void @zero_init_kernel() {

; GFX9-LABEL: zero_init_kernel:
; GFX9-LABEL: zero_init_kernel:

; GFX9:       ; %bb.0:
; GFX9:       ; %bb.0:

; GFX9-NEXT:    s_add_u32 flat_scratch_lo, s0, s3
; GFX9-NEXT:    s_add_u32 flat_scratch_lo, s2, s5

; GFX9-NEXT:    s_mov_b32 s0, 0
; GFX9-NEXT:    s_mov_b32 s0, 0

; GFX9-NEXT:    s_addc_u32 flat_scratch_hi, s1, 0
; GFX9-NEXT:    s_addc_u32 flat_scratch_hi, s3, 0

; GFX9-NEXT:    s_mov_b32 s1, s0
; GFX9-NEXT:    s_mov_b32 s1, s0

; GFX9-NEXT:    s_mov_b32 s2, s0
; GFX9-NEXT:    s_mov_b32 s2, s0

; GFX9-NEXT:    s_mov_b32 s3, s0
; GFX9-NEXT:    s_mov_b32 s3, s0

; GFX9-NEXT:    v_mov_b32_e32 v0, s0
; GFX9-NEXT:    v_mov_b32_e32 v0, s0

; GFX9-NEXT:    v_mov_b32_e32 v1, s1
; GFX9-NEXT:    v_mov_b32_e32 v1, s1

; GFX9-NEXT:    v_mov_b32_e32 v2, s2
; GFX9-NEXT:    v_mov_b32_e32 v2, s2

; GFX9-NEXT:    v_mov_b32_e32 v3, s3
; GFX9-NEXT:    v_mov_b32_e32 v3, s3

; GFX9-NEXT:    s_mov_b32 vcc_hi, 0
; GFX9-NEXT:    s_mov_b32 vcc_hi, 0

; GFX9-NEXT:    scratch_store_dwordx4 off, v[0:3], vcc_hi offset:64
; GFX9-NEXT:    scratch_store_dwordx4 off, v[0:3], vcc_hi offset:64

; GFX9-NEXT:    s_mov_b32 vcc_hi, 0
; GFX9-NEXT:    s_mov_b32 vcc_hi, 0

; GFX9-NEXT:    scratch_store_dwordx4 off, v[0:3], vcc_hi offset:48
; GFX9-NEXT:    scratch_store_dwordx4 off, v[0:3], vcc_hi offset:48

; GFX9-NEXT:    s_mov_b32 vcc_hi, 0
; GFX9-NEXT:    s_mov_b32 vcc_hi, 0

; GFX9-NEXT:    scratch_store_dwordx4 off, v[0:3], vcc_hi offset:32
; GFX9-NEXT:    scratch_store_dwordx4 off, v[0:3], vcc_hi offset:32

; GFX9-NEXT:    s_mov_b32 vcc_hi, 0
; GFX9-NEXT:    s_mov_b32 vcc_hi, 0

; GFX9-NEXT:    scratch_store_dwordx4 off, v[0:3], vcc_hi offset:16
; GFX9-NEXT:    scratch_store_dwordx4 off, v[0:3], vcc_hi offset:16

; GFX9-NEXT:    s_endpgm
; GFX9-NEXT:    s_endpgm

;
;

; GFX10-LABEL: zero_init_kernel:
; GFX10-LABEL: zero_init_kernel:

; GFX10:       ; %bb.0:
; GFX10:       ; %bb.0:

; GFX10-NEXT:    s_add_u32 s0, s0, s3
; GFX10-NEXT:    s_add_u32 s2, s2, s5

; GFX10-NEXT:    s_addc_u32 s1, s1, 0
; GFX10-NEXT:    s_addc_u32 s3, s3, 0

; GFX10-NEXT:    s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s0
; GFX10-NEXT:    s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s2

; GFX10-NEXT:    s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s1
; GFX10-NEXT:    s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s3

; GFX10-NEXT:    s_mov_b32 s0, 0
; GFX10-NEXT:    s_mov_b32 s0, 0

; GFX10-NEXT:    s_mov_b32 s1, s0
; GFX10-NEXT:    s_mov_b32 s1, s0

; GFX10-NEXT:    s_mov_b32 s2, s0
; GFX10-NEXT:    s_mov_b32 s2, s0

; GFX10-NEXT:    s_mov_b32 s3, s0
; GFX10-NEXT:    s_mov_b32 s3, s0

; GFX10-NEXT:    v_mov_b32_e32 v0, s0
; GFX10-NEXT:    v_mov_b32_e32 v0, s0

; GFX10-NEXT:    v_mov_b32_e32 v1, s1
; GFX10-NEXT:    v_mov_b32_e32 v1, s1

; GFX10-NEXT:    v_mov_b32_e32 v2, s2
; GFX10-NEXT:    v_mov_b32_e32 v2, s2

; GFX10-NEXT:    v_mov_b32_e32 v3, s3
; GFX10-NEXT:    v_mov_b32_e32 v3, s3

▲ Show 20 Lines • Show All 359 Lines • ▼ Show 20 Linesbb:

  %i11 = bitcast float addrspace(5)* %i10 to i32 addrspace(5)*
  %i11 = bitcast float addrspace(5)* %i10 to i32 addrspace(5)*

  %i12 = load volatile i32, i32 addrspace(5)* %i11, align 4
  %i12 = load volatile i32, i32 addrspace(5)* %i11, align 4

  ret void
  ret void

}
}




define amdgpu_kernel void @store_load_vindex_kernel() {
define amdgpu_kernel void @store_load_vindex_kernel() {

; GFX9-LABEL: store_load_vindex_kernel:
; GFX9-LABEL: store_load_vindex_kernel:

; GFX9:       ; %bb.0: ; %bb
; GFX9:       ; %bb.0: ; %bb

; GFX9-NEXT:    s_add_u32 flat_scratch_lo, s0, s3
; GFX9-NEXT:    s_add_u32 flat_scratch_lo, s2, s5

; GFX9-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
; GFX9-NEXT:    v_lshlrev_b32_e32 v0, 2, v0

; GFX9-NEXT:    v_mov_b32_e32 v1, 4
; GFX9-NEXT:    v_mov_b32_e32 v1, 4

; GFX9-NEXT:    s_addc_u32 flat_scratch_hi, s1, 0
; GFX9-NEXT:    s_addc_u32 flat_scratch_hi, s3, 0

; GFX9-NEXT:    v_add_u32_e32 v2, v1, v0
; GFX9-NEXT:    v_add_u32_e32 v2, v1, v0

; GFX9-NEXT:    v_mov_b32_e32 v3, 15
; GFX9-NEXT:    v_mov_b32_e32 v3, 15

; GFX9-NEXT:    scratch_store_dword v2, v3, off
; GFX9-NEXT:    scratch_store_dword v2, v3, off

; GFX9-NEXT:    s_waitcnt vmcnt(0)
; GFX9-NEXT:    s_waitcnt vmcnt(0)

; GFX9-NEXT:    v_sub_u32_e32 v0, v1, v0
; GFX9-NEXT:    v_sub_u32_e32 v0, v1, v0

; GFX9-NEXT:    scratch_load_dword v0, v0, off offset:124 glc
; GFX9-NEXT:    scratch_load_dword v0, v0, off offset:124 glc

; GFX9-NEXT:    s_waitcnt vmcnt(0)
; GFX9-NEXT:    s_waitcnt vmcnt(0)

; GFX9-NEXT:    s_endpgm
; GFX9-NEXT:    s_endpgm

;
;

; GFX10-LABEL: store_load_vindex_kernel:
; GFX10-LABEL: store_load_vindex_kernel:

; GFX10:       ; %bb.0: ; %bb
; GFX10:       ; %bb.0: ; %bb

; GFX10-NEXT:    s_add_u32 s0, s0, s3
; GFX10-NEXT:    s_add_u32 s2, s2, s5

; GFX10-NEXT:    s_addc_u32 s1, s1, 0
; GFX10-NEXT:    s_addc_u32 s3, s3, 0

; GFX10-NEXT:    s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s0
; GFX10-NEXT:    s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s2

; GFX10-NEXT:    s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s1
; GFX10-NEXT:    s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s3

; GFX10-NEXT:    v_mov_b32_e32 v1, 4
; GFX10-NEXT:    v_mov_b32_e32 v1, 4

; GFX10-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
; GFX10-NEXT:    v_lshlrev_b32_e32 v0, 2, v0

; GFX10-NEXT:    v_mov_b32_e32 v3, 15
; GFX10-NEXT:    v_mov_b32_e32 v3, 15

; GFX10-NEXT:    v_add_nc_u32_e32 v2, v1, v0
; GFX10-NEXT:    v_add_nc_u32_e32 v2, v1, v0

; GFX10-NEXT:    v_sub_nc_u32_e32 v0, v1, v0
; GFX10-NEXT:    v_sub_nc_u32_e32 v0, v1, v0

; GFX10-NEXT:    scratch_store_dword v2, v3, off
; GFX10-NEXT:    scratch_store_dword v2, v3, off

; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0

; GFX10-NEXT:    scratch_load_dword v0, v0, off offset:124 glc dlc
; GFX10-NEXT:    scratch_load_dword v0, v0, off offset:124 glc dlc

▲ Show 20 Lines • Show All 164 Lines • ▼ Show 20 Lines; GFX10-PAL-NEXT:    s_setpc_b64 s[30:31]

  %gep = getelementptr inbounds float, float addrspace(5)* %arg, i32 1
  %gep = getelementptr inbounds float, float addrspace(5)* %arg, i32 1

  store float 1.000000e+01, float addrspace(5)* %gep, align 4
  store float 1.000000e+01, float addrspace(5)* %gep, align 4

  ret void
  ret void

}
}




define amdgpu_kernel void @zero_init_small_offset_kernel() {
define amdgpu_kernel void @zero_init_small_offset_kernel() {

; GFX9-LABEL: zero_init_small_offset_kernel:
; GFX9-LABEL: zero_init_small_offset_kernel:

; GFX9:       ; %bb.0:
; GFX9:       ; %bb.0:

; GFX9-NEXT:    s_add_u32 flat_scratch_lo, s0, s3
; GFX9-NEXT:    s_add_u32 flat_scratch_lo, s2, s5

; GFX9-NEXT:    s_addc_u32 flat_scratch_hi, s1, 0
; GFX9-NEXT:    s_addc_u32 flat_scratch_hi, s3, 0

; GFX9-NEXT:    s_mov_b32 vcc_hi, 0
; GFX9-NEXT:    s_mov_b32 vcc_hi, 0

; GFX9-NEXT:    scratch_load_dword v0, off, vcc_hi offset:4 glc
; GFX9-NEXT:    scratch_load_dword v0, off, vcc_hi offset:4 glc

; GFX9-NEXT:    s_waitcnt vmcnt(0)
; GFX9-NEXT:    s_waitcnt vmcnt(0)

; GFX9-NEXT:    s_mov_b32 s0, 0
; GFX9-NEXT:    s_mov_b32 s0, 0

; GFX9-NEXT:    s_mov_b32 s1, s0
; GFX9-NEXT:    s_mov_b32 s1, s0

; GFX9-NEXT:    s_mov_b32 s2, s0
; GFX9-NEXT:    s_mov_b32 s2, s0

; GFX9-NEXT:    s_mov_b32 s3, s0
; GFX9-NEXT:    s_mov_b32 s3, s0

; GFX9-NEXT:    v_mov_b32_e32 v0, s0
; GFX9-NEXT:    v_mov_b32_e32 v0, s0

; GFX9-NEXT:    v_mov_b32_e32 v1, s1
; GFX9-NEXT:    v_mov_b32_e32 v1, s1

; GFX9-NEXT:    v_mov_b32_e32 v2, s2
; GFX9-NEXT:    v_mov_b32_e32 v2, s2

; GFX9-NEXT:    v_mov_b32_e32 v3, s3
; GFX9-NEXT:    v_mov_b32_e32 v3, s3

; GFX9-NEXT:    s_mov_b32 vcc_hi, 0
; GFX9-NEXT:    s_mov_b32 vcc_hi, 0

; GFX9-NEXT:    scratch_store_dwordx4 off, v[0:3], vcc_hi offset:272
; GFX9-NEXT:    scratch_store_dwordx4 off, v[0:3], vcc_hi offset:272

; GFX9-NEXT:    s_mov_b32 vcc_hi, 0
; GFX9-NEXT:    s_mov_b32 vcc_hi, 0

; GFX9-NEXT:    scratch_store_dwordx4 off, v[0:3], vcc_hi offset:288
; GFX9-NEXT:    scratch_store_dwordx4 off, v[0:3], vcc_hi offset:288

; GFX9-NEXT:    s_mov_b32 vcc_hi, 0
; GFX9-NEXT:    s_mov_b32 vcc_hi, 0

; GFX9-NEXT:    scratch_store_dwordx4 off, v[0:3], vcc_hi offset:304
; GFX9-NEXT:    scratch_store_dwordx4 off, v[0:3], vcc_hi offset:304

; GFX9-NEXT:    s_mov_b32 vcc_hi, 0
; GFX9-NEXT:    s_mov_b32 vcc_hi, 0

; GFX9-NEXT:    scratch_store_dwordx4 off, v[0:3], vcc_hi offset:320
; GFX9-NEXT:    scratch_store_dwordx4 off, v[0:3], vcc_hi offset:320

; GFX9-NEXT:    s_endpgm
; GFX9-NEXT:    s_endpgm

;
;

; GFX10-LABEL: zero_init_small_offset_kernel:
; GFX10-LABEL: zero_init_small_offset_kernel:

; GFX10:       ; %bb.0:
; GFX10:       ; %bb.0:

; GFX10-NEXT:    s_add_u32 s0, s0, s3
; GFX10-NEXT:    s_add_u32 s2, s2, s5

; GFX10-NEXT:    s_addc_u32 s1, s1, 0
; GFX10-NEXT:    s_addc_u32 s3, s3, 0

; GFX10-NEXT:    s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s0
; GFX10-NEXT:    s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s2

; GFX10-NEXT:    s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s1
; GFX10-NEXT:    s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s3

; GFX10-NEXT:    scratch_load_dword v0, off, off offset:4 glc dlc
; GFX10-NEXT:    scratch_load_dword v0, off, off offset:4 glc dlc

; GFX10-NEXT:    s_waitcnt vmcnt(0)
; GFX10-NEXT:    s_waitcnt vmcnt(0)

; GFX10-NEXT:    s_mov_b32 s0, 0
; GFX10-NEXT:    s_mov_b32 s0, 0

; GFX10-NEXT:    s_mov_b32 s1, s0
; GFX10-NEXT:    s_mov_b32 s1, s0

; GFX10-NEXT:    s_mov_b32 s2, s0
; GFX10-NEXT:    s_mov_b32 s2, s0

; GFX10-NEXT:    s_mov_b32 s3, s0
; GFX10-NEXT:    s_mov_b32 s3, s0

; GFX10-NEXT:    v_mov_b32_e32 v0, s0
; GFX10-NEXT:    v_mov_b32_e32 v0, s0

; GFX10-NEXT:    v_mov_b32_e32 v1, s1
; GFX10-NEXT:    v_mov_b32_e32 v1, s1

▲ Show 20 Lines • Show All 462 Lines • ▼ Show 20 Linesbb:

  %i11 = bitcast float addrspace(5)* %i10 to i32 addrspace(5)*
  %i11 = bitcast float addrspace(5)* %i10 to i32 addrspace(5)*

  %i12 = load volatile i32, i32 addrspace(5)* %i11, align 4
  %i12 = load volatile i32, i32 addrspace(5)* %i11, align 4

  ret void
  ret void

}
}




define amdgpu_kernel void @store_load_vindex_small_offset_kernel() {
define amdgpu_kernel void @store_load_vindex_small_offset_kernel() {

; GFX9-LABEL: store_load_vindex_small_offset_kernel:
; GFX9-LABEL: store_load_vindex_small_offset_kernel:

; GFX9:       ; %bb.0: ; %bb
; GFX9:       ; %bb.0: ; %bb

; GFX9-NEXT:    s_add_u32 flat_scratch_lo, s0, s3
; GFX9-NEXT:    s_add_u32 flat_scratch_lo, s2, s5

; GFX9-NEXT:    s_addc_u32 flat_scratch_hi, s1, 0
; GFX9-NEXT:    s_addc_u32 flat_scratch_hi, s3, 0

; GFX9-NEXT:    s_mov_b32 vcc_hi, 0
; GFX9-NEXT:    s_mov_b32 vcc_hi, 0

; GFX9-NEXT:    scratch_load_dword v1, off, vcc_hi offset:4 glc
; GFX9-NEXT:    scratch_load_dword v1, off, vcc_hi offset:4 glc

; GFX9-NEXT:    s_waitcnt vmcnt(0)
; GFX9-NEXT:    s_waitcnt vmcnt(0)

; GFX9-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
; GFX9-NEXT:    v_lshlrev_b32_e32 v0, 2, v0

; GFX9-NEXT:    v_mov_b32_e32 v1, 0x104
; GFX9-NEXT:    v_mov_b32_e32 v1, 0x104

; GFX9-NEXT:    v_add_u32_e32 v2, v1, v0
; GFX9-NEXT:    v_add_u32_e32 v2, v1, v0

; GFX9-NEXT:    v_mov_b32_e32 v3, 15
; GFX9-NEXT:    v_mov_b32_e32 v3, 15

; GFX9-NEXT:    scratch_store_dword v2, v3, off
; GFX9-NEXT:    scratch_store_dword v2, v3, off

; GFX9-NEXT:    s_waitcnt vmcnt(0)
; GFX9-NEXT:    s_waitcnt vmcnt(0)

; GFX9-NEXT:    v_sub_u32_e32 v0, v1, v0
; GFX9-NEXT:    v_sub_u32_e32 v0, v1, v0

; GFX9-NEXT:    scratch_load_dword v0, v0, off offset:124 glc
; GFX9-NEXT:    scratch_load_dword v0, v0, off offset:124 glc

; GFX9-NEXT:    s_waitcnt vmcnt(0)
; GFX9-NEXT:    s_waitcnt vmcnt(0)

; GFX9-NEXT:    s_endpgm
; GFX9-NEXT:    s_endpgm

;
;

; GFX10-LABEL: store_load_vindex_small_offset_kernel:
; GFX10-LABEL: store_load_vindex_small_offset_kernel:

; GFX10:       ; %bb.0: ; %bb
; GFX10:       ; %bb.0: ; %bb

; GFX10-NEXT:    s_add_u32 s0, s0, s3
; GFX10-NEXT:    s_add_u32 s2, s2, s5

; GFX10-NEXT:    s_addc_u32 s1, s1, 0
; GFX10-NEXT:    s_addc_u32 s3, s3, 0

; GFX10-NEXT:    s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s0
; GFX10-NEXT:    s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s2

; GFX10-NEXT:    s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s1
; GFX10-NEXT:    s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s3

; GFX10-NEXT:    v_mov_b32_e32 v1, 0x104
; GFX10-NEXT:    v_mov_b32_e32 v1, 0x104

; GFX10-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
; GFX10-NEXT:    v_lshlrev_b32_e32 v0, 2, v0

; GFX10-NEXT:    v_mov_b32_e32 v3, 15
; GFX10-NEXT:    v_mov_b32_e32 v3, 15

; GFX10-NEXT:    v_add_nc_u32_e32 v2, v1, v0
; GFX10-NEXT:    v_add_nc_u32_e32 v2, v1, v0

; GFX10-NEXT:    v_sub_nc_u32_e32 v0, v1, v0
; GFX10-NEXT:    v_sub_nc_u32_e32 v0, v1, v0

; GFX10-NEXT:    scratch_load_dword v1, off, off offset:4 glc dlc
; GFX10-NEXT:    scratch_load_dword v1, off, off offset:4 glc dlc

; GFX10-NEXT:    s_waitcnt vmcnt(0)
; GFX10-NEXT:    s_waitcnt vmcnt(0)

; GFX10-NEXT:    scratch_store_dword v2, v3, off
; GFX10-NEXT:    scratch_store_dword v2, v3, off

▲ Show 20 Lines • Show All 175 Lines • ▼ Show 20 Linesbb:

  %i11 = bitcast float addrspace(5)* %i10 to i32 addrspace(5)*
  %i11 = bitcast float addrspace(5)* %i10 to i32 addrspace(5)*

  %i12 = load volatile i32, i32 addrspace(5)* %i11, align 4
  %i12 = load volatile i32, i32 addrspace(5)* %i11, align 4

  ret void
  ret void

}
}




define amdgpu_kernel void @zero_init_large_offset_kernel() {
define amdgpu_kernel void @zero_init_large_offset_kernel() {

; GFX9-LABEL: zero_init_large_offset_kernel:
; GFX9-LABEL: zero_init_large_offset_kernel:

; GFX9:       ; %bb.0:
; GFX9:       ; %bb.0:

; GFX9-NEXT:    s_add_u32 flat_scratch_lo, s0, s3
; GFX9-NEXT:    s_add_u32 flat_scratch_lo, s2, s5

; GFX9-NEXT:    s_addc_u32 flat_scratch_hi, s1, 0
; GFX9-NEXT:    s_addc_u32 flat_scratch_hi, s3, 0

; GFX9-NEXT:    s_mov_b32 vcc_hi, 0
; GFX9-NEXT:    s_mov_b32 vcc_hi, 0

; GFX9-NEXT:    scratch_load_dword v0, off, vcc_hi offset:16 glc
; GFX9-NEXT:    scratch_load_dword v0, off, vcc_hi offset:16 glc

; GFX9-NEXT:    s_waitcnt vmcnt(0)
; GFX9-NEXT:    s_waitcnt vmcnt(0)

; GFX9-NEXT:    s_mov_b32 s0, 0
; GFX9-NEXT:    s_mov_b32 s0, 0

; GFX9-NEXT:    s_mov_b32 s1, s0
; GFX9-NEXT:    s_mov_b32 s1, s0

; GFX9-NEXT:    s_mov_b32 s2, s0
; GFX9-NEXT:    s_mov_b32 s2, s0

; GFX9-NEXT:    s_mov_b32 s3, s0
; GFX9-NEXT:    s_mov_b32 s3, s0

; GFX9-NEXT:    v_mov_b32_e32 v0, s0
; GFX9-NEXT:    v_mov_b32_e32 v0, s0

; GFX9-NEXT:    v_mov_b32_e32 v1, s1
; GFX9-NEXT:    v_mov_b32_e32 v1, s1

; GFX9-NEXT:    v_mov_b32_e32 v2, s2
; GFX9-NEXT:    v_mov_b32_e32 v2, s2

; GFX9-NEXT:    v_mov_b32_e32 v3, s3
; GFX9-NEXT:    v_mov_b32_e32 v3, s3

; GFX9-NEXT:    s_movk_i32 vcc_hi, 0x4010
; GFX9-NEXT:    s_movk_i32 vcc_hi, 0x4010

; GFX9-NEXT:    scratch_store_dwordx4 off, v[0:3], vcc_hi
; GFX9-NEXT:    scratch_store_dwordx4 off, v[0:3], vcc_hi

; GFX9-NEXT:    s_movk_i32 vcc_hi, 0x4010
; GFX9-NEXT:    s_movk_i32 vcc_hi, 0x4010

; GFX9-NEXT:    scratch_store_dwordx4 off, v[0:3], vcc_hi offset:16
; GFX9-NEXT:    scratch_store_dwordx4 off, v[0:3], vcc_hi offset:16

; GFX9-NEXT:    s_movk_i32 vcc_hi, 0x4010
; GFX9-NEXT:    s_movk_i32 vcc_hi, 0x4010

; GFX9-NEXT:    scratch_store_dwordx4 off, v[0:3], vcc_hi offset:32
; GFX9-NEXT:    scratch_store_dwordx4 off, v[0:3], vcc_hi offset:32

; GFX9-NEXT:    s_movk_i32 vcc_hi, 0x4010
; GFX9-NEXT:    s_movk_i32 vcc_hi, 0x4010

; GFX9-NEXT:    scratch_store_dwordx4 off, v[0:3], vcc_hi offset:48
; GFX9-NEXT:    scratch_store_dwordx4 off, v[0:3], vcc_hi offset:48

; GFX9-NEXT:    s_endpgm
; GFX9-NEXT:    s_endpgm

;
;

; GFX10-LABEL: zero_init_large_offset_kernel:
; GFX10-LABEL: zero_init_large_offset_kernel:

; GFX10:       ; %bb.0:
; GFX10:       ; %bb.0:

; GFX10-NEXT:    s_add_u32 s0, s0, s3
; GFX10-NEXT:    s_add_u32 s2, s2, s5

; GFX10-NEXT:    s_addc_u32 s1, s1, 0
; GFX10-NEXT:    s_addc_u32 s3, s3, 0

; GFX10-NEXT:    s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s0
; GFX10-NEXT:    s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s2

; GFX10-NEXT:    s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s1
; GFX10-NEXT:    s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s3

; GFX10-NEXT:    scratch_load_dword v0, off, off offset:16 glc dlc
; GFX10-NEXT:    scratch_load_dword v0, off, off offset:16 glc dlc

; GFX10-NEXT:    s_waitcnt vmcnt(0)
; GFX10-NEXT:    s_waitcnt vmcnt(0)

; GFX10-NEXT:    s_mov_b32 s0, 0
; GFX10-NEXT:    s_mov_b32 s0, 0

; GFX10-NEXT:    s_movk_i32 vcc_lo, 0x4010
; GFX10-NEXT:    s_movk_i32 vcc_lo, 0x4010

; GFX10-NEXT:    s_mov_b32 s1, s0
; GFX10-NEXT:    s_mov_b32 s1, s0

; GFX10-NEXT:    s_mov_b32 s2, s0
; GFX10-NEXT:    s_mov_b32 s2, s0

; GFX10-NEXT:    s_mov_b32 s3, s0
; GFX10-NEXT:    s_mov_b32 s3, s0

; GFX10-NEXT:    v_mov_b32_e32 v0, s0
; GFX10-NEXT:    v_mov_b32_e32 v0, s0

▲ Show 20 Lines • Show All 514 Lines • ▼ Show 20 Linesbb:

  %i11 = bitcast float addrspace(5)* %i10 to i32 addrspace(5)*
  %i11 = bitcast float addrspace(5)* %i10 to i32 addrspace(5)*

  %i12 = load volatile i32, i32 addrspace(5)* %i11, align 4
  %i12 = load volatile i32, i32 addrspace(5)* %i11, align 4

  ret void
  ret void

}
}




define amdgpu_kernel void @store_load_vindex_large_offset_kernel() {
define amdgpu_kernel void @store_load_vindex_large_offset_kernel() {

; GFX9-LABEL: store_load_vindex_large_offset_kernel:
; GFX9-LABEL: store_load_vindex_large_offset_kernel:

; GFX9:       ; %bb.0: ; %bb
; GFX9:       ; %bb.0: ; %bb

; GFX9-NEXT:    s_add_u32 flat_scratch_lo, s0, s3
; GFX9-NEXT:    s_add_u32 flat_scratch_lo, s2, s5

; GFX9-NEXT:    s_addc_u32 flat_scratch_hi, s1, 0
; GFX9-NEXT:    s_addc_u32 flat_scratch_hi, s3, 0

; GFX9-NEXT:    s_mov_b32 vcc_hi, 0
; GFX9-NEXT:    s_mov_b32 vcc_hi, 0

; GFX9-NEXT:    scratch_load_dword v1, off, vcc_hi offset:4 glc
; GFX9-NEXT:    scratch_load_dword v1, off, vcc_hi offset:4 glc

; GFX9-NEXT:    s_waitcnt vmcnt(0)
; GFX9-NEXT:    s_waitcnt vmcnt(0)

; GFX9-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
; GFX9-NEXT:    v_lshlrev_b32_e32 v0, 2, v0

; GFX9-NEXT:    v_mov_b32_e32 v1, 0x4004
; GFX9-NEXT:    v_mov_b32_e32 v1, 0x4004

; GFX9-NEXT:    v_add_u32_e32 v2, v1, v0
; GFX9-NEXT:    v_add_u32_e32 v2, v1, v0

; GFX9-NEXT:    v_mov_b32_e32 v3, 15
; GFX9-NEXT:    v_mov_b32_e32 v3, 15

; GFX9-NEXT:    scratch_store_dword v2, v3, off
; GFX9-NEXT:    scratch_store_dword v2, v3, off

; GFX9-NEXT:    s_waitcnt vmcnt(0)
; GFX9-NEXT:    s_waitcnt vmcnt(0)

; GFX9-NEXT:    v_sub_u32_e32 v0, v1, v0
; GFX9-NEXT:    v_sub_u32_e32 v0, v1, v0

; GFX9-NEXT:    scratch_load_dword v0, v0, off offset:124 glc
; GFX9-NEXT:    scratch_load_dword v0, v0, off offset:124 glc

; GFX9-NEXT:    s_waitcnt vmcnt(0)
; GFX9-NEXT:    s_waitcnt vmcnt(0)

; GFX9-NEXT:    s_endpgm
; GFX9-NEXT:    s_endpgm

;
;

; GFX10-LABEL: store_load_vindex_large_offset_kernel:
; GFX10-LABEL: store_load_vindex_large_offset_kernel:

; GFX10:       ; %bb.0: ; %bb
; GFX10:       ; %bb.0: ; %bb

; GFX10-NEXT:    s_add_u32 s0, s0, s3
; GFX10-NEXT:    s_add_u32 s2, s2, s5

; GFX10-NEXT:    s_addc_u32 s1, s1, 0
; GFX10-NEXT:    s_addc_u32 s3, s3, 0

; GFX10-NEXT:    s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s0
; GFX10-NEXT:    s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s2

; GFX10-NEXT:    s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s1
; GFX10-NEXT:    s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s3

; GFX10-NEXT:    v_mov_b32_e32 v1, 0x4004
; GFX10-NEXT:    v_mov_b32_e32 v1, 0x4004

; GFX10-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
; GFX10-NEXT:    v_lshlrev_b32_e32 v0, 2, v0

; GFX10-NEXT:    v_mov_b32_e32 v3, 15
; GFX10-NEXT:    v_mov_b32_e32 v3, 15

; GFX10-NEXT:    v_add_nc_u32_e32 v2, v1, v0
; GFX10-NEXT:    v_add_nc_u32_e32 v2, v1, v0

; GFX10-NEXT:    v_sub_nc_u32_e32 v0, v1, v0
; GFX10-NEXT:    v_sub_nc_u32_e32 v0, v1, v0

; GFX10-NEXT:    scratch_load_dword v1, off, off offset:4 glc dlc
; GFX10-NEXT:    scratch_load_dword v1, off, off offset:4 glc dlc

; GFX10-NEXT:    s_waitcnt vmcnt(0)
; GFX10-NEXT:    s_waitcnt vmcnt(0)

; GFX10-NEXT:    scratch_store_dword v2, v3, off
; GFX10-NEXT:    scratch_store_dword v2, v3, off

▲ Show 20 Lines • Show All 175 Lines • ▼ Show 20 Linesbb:

  %i11 = bitcast float addrspace(5)* %i10 to i32 addrspace(5)*
  %i11 = bitcast float addrspace(5)* %i10 to i32 addrspace(5)*

  %i12 = load volatile i32, i32 addrspace(5)* %i11, align 4
  %i12 = load volatile i32, i32 addrspace(5)* %i11, align 4

  ret void
  ret void

}
}




define amdgpu_kernel void @store_load_large_imm_offset_kernel() {
define amdgpu_kernel void @store_load_large_imm_offset_kernel() {

; GFX9-LABEL: store_load_large_imm_offset_kernel:
; GFX9-LABEL: store_load_large_imm_offset_kernel:

; GFX9:       ; %bb.0: ; %bb
; GFX9:       ; %bb.0: ; %bb

; GFX9-NEXT:    s_add_u32 flat_scratch_lo, s0, s3
; GFX9-NEXT:    s_add_u32 flat_scratch_lo, s2, s5

; GFX9-NEXT:    s_addc_u32 flat_scratch_hi, s1, 0
; GFX9-NEXT:    s_addc_u32 flat_scratch_hi, s3, 0

; GFX9-NEXT:    v_mov_b32_e32 v0, 13
; GFX9-NEXT:    v_mov_b32_e32 v0, 13

; GFX9-NEXT:    s_mov_b32 vcc_hi, 0
; GFX9-NEXT:    s_mov_b32 vcc_hi, 0

; GFX9-NEXT:    s_movk_i32 s0, 0x3000
; GFX9-NEXT:    s_movk_i32 s0, 0x3000

; GFX9-NEXT:    scratch_store_dword off, v0, vcc_hi offset:4
; GFX9-NEXT:    scratch_store_dword off, v0, vcc_hi offset:4

; GFX9-NEXT:    s_waitcnt vmcnt(0)
; GFX9-NEXT:    s_waitcnt vmcnt(0)

; GFX9-NEXT:    s_add_i32 s0, s0, 4
; GFX9-NEXT:    s_add_i32 s0, s0, 4

; GFX9-NEXT:    v_mov_b32_e32 v0, 15
; GFX9-NEXT:    v_mov_b32_e32 v0, 15

; GFX9-NEXT:    scratch_store_dword off, v0, s0 offset:3712
; GFX9-NEXT:    scratch_store_dword off, v0, s0 offset:3712

; GFX9-NEXT:    s_waitcnt vmcnt(0)
; GFX9-NEXT:    s_waitcnt vmcnt(0)

; GFX9-NEXT:    scratch_load_dword v0, off, s0 offset:3712 glc
; GFX9-NEXT:    scratch_load_dword v0, off, s0 offset:3712 glc

; GFX9-NEXT:    s_waitcnt vmcnt(0)
; GFX9-NEXT:    s_waitcnt vmcnt(0)

; GFX9-NEXT:    s_endpgm
; GFX9-NEXT:    s_endpgm

;
;

; GFX10-LABEL: store_load_large_imm_offset_kernel:
; GFX10-LABEL: store_load_large_imm_offset_kernel:

; GFX10:       ; %bb.0: ; %bb
; GFX10:       ; %bb.0: ; %bb

; GFX10-NEXT:    s_add_u32 s0, s0, s3
; GFX10-NEXT:    s_add_u32 s2, s2, s5

; GFX10-NEXT:    s_addc_u32 s1, s1, 0
; GFX10-NEXT:    s_addc_u32 s3, s3, 0

; GFX10-NEXT:    s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s0
; GFX10-NEXT:    s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s2

; GFX10-NEXT:    s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s1
; GFX10-NEXT:    s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s3

; GFX10-NEXT:    v_mov_b32_e32 v0, 13
; GFX10-NEXT:    v_mov_b32_e32 v0, 13

; GFX10-NEXT:    v_mov_b32_e32 v1, 15
; GFX10-NEXT:    v_mov_b32_e32 v1, 15

; GFX10-NEXT:    s_movk_i32 s0, 0x3800
; GFX10-NEXT:    s_movk_i32 s0, 0x3800

; GFX10-NEXT:    s_add_i32 s0, s0, 4
; GFX10-NEXT:    s_add_i32 s0, s0, 4

; GFX10-NEXT:    scratch_store_dword off, v0, off offset:4
; GFX10-NEXT:    scratch_store_dword off, v0, off offset:4

; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0

; GFX10-NEXT:    scratch_store_dword off, v1, s0 offset:1664
; GFX10-NEXT:    scratch_store_dword off, v1, s0 offset:1664

; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0

▲ Show 20 Lines • Show All 717 Lines • Show Last 20 Lines
llvm/test/CodeGen/AMDGPU/spill-sgpr-stack-no-sgpr.ll
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py

; RUN: llc -march=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX10 %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX10 %s




; Spill an SGPR to scratch without having spare SGPRs available to save exec
; Spill an SGPR to scratch without having spare SGPRs available to save exec




define amdgpu_kernel void @test() #1 {
define amdgpu_kernel void @test() #1 {

; GFX10-LABEL: test:
; GFX10-LABEL: test:

; GFX10:       ; %bb.0:
; GFX10:       ; %bb.0:

; GFX10-NEXT:    s_mov_b32 s8, SCRATCH_RSRC_DWORD0
; GFX10-NEXT:    s_mov_b64 s[10:11], s[2:3]

; GFX10-NEXT:    s_mov_b32 s9, SCRATCH_RSRC_DWORD1
; GFX10-NEXT:    s_mov_b64 s[8:9], s[0:1]

; GFX10-NEXT:    s_mov_b32 s10, -1
; GFX10-NEXT:    s_add_u32 s8, s8, s5

; GFX10-NEXT:    s_mov_b32 s11, 0x31e16000

; GFX10-NEXT:    s_add_u32 s8, s8, s1

; GFX10-NEXT:    s_addc_u32 s9, s9, 0
; GFX10-NEXT:    s_addc_u32 s9, s9, 0

; GFX10-NEXT:    ;;#ASMSTART
; GFX10-NEXT:    ;;#ASMSTART

; GFX10-NEXT:    ; def s[0:7]
; GFX10-NEXT:    ; def s[0:7]

; GFX10-NEXT:    ;;#ASMEND
; GFX10-NEXT:    ;;#ASMEND

; GFX10-NEXT:    ;;#ASMSTART
; GFX10-NEXT:    ;;#ASMSTART

; GFX10-NEXT:    ; def s[8:12]
; GFX10-NEXT:    ; def s[8:12]

; GFX10-NEXT:    ;;#ASMEND
; GFX10-NEXT:    ;;#ASMEND

; GFX10-NEXT:    s_not_b64 exec, exec
; GFX10-NEXT:    s_not_b64 exec, exec

▲ Show 20 Lines • Show All 49 Lines • Show Last 20 Lines