[RISCV] Add patterns for vector narrowing integer right shift instructions

[eopXD]

Update code.

[jacquesguan]

llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td

611

Because only the low lg2(2*SEW) bits of the shift-amount value are used, I think we could also add zero extend here.

[eopXD]

Address @jacquesguan 's comment.

llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td

611

Good idea, thanks!

[jacquesguan]

llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td

609

Because here we always have truncate from SEW*2 to SEW, could we directly use trunc here and move these classes and patterns to RISCVInstrInfoVSDPatterns.td? In this way, maybe no need to use (riscv_vmset_vl (XLenVT -1)) for mask and (XLenVT -1) for vl.

[eopXD]

llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td

609

I have tried to use trunc and found out we can't do this. The reason is that the RISCV backend only support one stage of truncate. So the compiler will first legalize it to RISCVISD::TRUNCATE_VECTOR_VL and split it into step(s) (e.g. if doing i64 -> i16, it will turnt into 2 instruction)

Here are the llc debug message to show you the "legalization" from trunc to RISCVISD::TRUNCATE_VECTOR_VL:

Type-legalized selection DAG: %bb.0 'vnsrl_wv_nxv1i32:'
SelectionDAG has 11 nodes:
  t0: ch = EntryToken
        t2: nxv1i64,ch = CopyFromReg t0, Register:nxv1i64 %0
          t4: nxv1i32,ch = CopyFromReg t0, Register:nxv1i32 %1
        t6: nxv1i64 = sign_extend t4
      t7: nxv1i64 = srl t2, t6
    t8: nxv1i32 = truncate t7
  t11: ch,glue = CopyToReg t0, Register:nxv1i32 $v8, t8
  t12: ch = RISCVISD::RET_FLAG t11, Register:nxv1i32 $v8, t11:1



Legalizing vector op: t6: nxv1i64 = sign_extend t4
Trying custom legalization

Legalizing vector op: t7: nxv1i64 = srl t2, t6
Legal node: nothing to do

Legalizing vector op: t8: nxv1i32 = truncate t7
Trying custom legalization
Creating constant: t13: i32 = TargetConstant<-1>
Creating new node: t14: nxv1i1 = RISCVISD::VMSET_VL TargetConstant:i32<-1>
Creating new node: t15: nxv1i32 = RISCVISD::TRUNCATE_VECTOR_VL t7, t14, TargetConstant:i32<-1>
Vector-legalized selection DAG: %bb.0 'vnsrl_wv_nxv1i32:'
SelectionDAG has 13 nodes:
  t0: ch = EntryToken
        t2: nxv1i64,ch = CopyFromReg t0, Register:nxv1i64 %0
          t4: nxv1i32,ch = CopyFromReg t0, Register:nxv1i32 %1
        t6: nxv1i64 = sign_extend t4
      t7: nxv1i64 = srl t2, t6
      t14: nxv1i1 = RISCVISD::VMSET_VL TargetConstant:i32<-1>
    t15: nxv1i32 = RISCVISD::TRUNCATE_VECTOR_VL t7, t14, TargetConstant:i32<-1>
  t11: ch,glue = CopyToReg t0, Register:nxv1i32 $v8, t15
  t12: ch = RISCVISD::RET_FLAG t11, Register:nxv1i32 $v8, t11:1

[craig.topper]

llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td

612

(XlenVT -1) -> VLMax

613

(XlenVT -1) -> VLMax

627

Same here

[eopXD]

Address @craig.topper 's comment.

[eopXD]

Update code: rewrite to VLMax

[eopXD]

Rebase.

[craig.topper]

LGTM

llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td

def: Pat<(vti_m1.Vector (vop (vti_m1.Vector VR:$merge), (vti.Vector vti.RegClass:$rs1), VR:$rs2,
         (!cast<Instruction>(instruction_name#"_VS_"#vti.LMul.MX#"_MASK")
             (vti_m1.Vector VR:$merge),
             (vti.Vector vti.RegClass:$rs1),
             (vti_m1.Vector VR:$rs2),
             (vti.Mask V0), GPR:$vl, vti.Log2SEW)>;
   }
 }
 
+multiclass VPatBinarySDNodeExt_V_WV<SDNode op, PatFrags extop, string instruction_name> {
+  foreach vti = AllWidenableIntVectors in {
+    def : Pat<
+      (vti.Vti.Vector 
+        (riscv_trunc_vector_vl
+          (op (vti.Wti.Vector vti.Wti.RegClass:$rs2),
+              (vti.Wti.Vector (extop (vti.Vti.Vector vti.Vti.RegClass:$rs1)))),
+          (riscv_vmset_vl VLMax),
+          VLMax)),
+      (!cast<Instruction>(instruction_name#"_WV_"#vti.Vti.LMul.MX)
+        vti.Wti.RegClass:$rs2, vti.Vti.RegClass:$rs1,
+        vti.Vti.AVL, vti.Vti.Log2SEW)>;
+  }
+}
+
+multiclass VPatBinarySDNodeExt_V_WX<SDNode op, PatFrags extop, string instruction_name> {
+  foreach vti = AllWidenableIntVectors in {
+    def : Pat<
+      (vti.Vti.Vector 
+        (riscv_trunc_vector_vl
+          (op (vti.Wti.Vector vti.Wti.RegClass:$rs2),
+              (vti.Wti.Vector (extop (vti.Vti.Vector (SplatPat GPR:$rs1))))),
+          (riscv_vmset_vl VLMax),
+          VLMax)),
+      (!cast<Instruction>(instruction_name#"_WX_"#vti.Vti.LMul.MX)
+        vti.Wti.RegClass:$rs2, GPR:$rs1,
+        vti.Vti.AVL, vti.Vti.Log2SEW)>;
+  }
+}
+
+
+multiclass VPatBinarySDNode_V_WV<SDNode op, string instruction_name> {
+  defm : VPatBinarySDNodeExt_V_WV<op, sext_oneuse, instruction_name>;
+  defm : VPatBinarySDNodeExt_V_WV<op, zext_oneuse, instruction_name>;
+}
+
+multiclass VPatBinarySDNode_V_WX<SDNode op, string instruction_name> {
+  defm : VPatBinarySDNodeExt_V_WX<op, sext_oneuse, instruction_name>;
+  defm : VPatBinarySDNodeExt_V_WX<op, zext_oneuse, instruction_name>;
+}
+
 //===----------------------------------------------------------------------===//
 // Patterns.
 //===----------------------------------------------------------------------===//
 
 let Predicates = [HasVInstructions] in {
 
 // 7.4. Vector Unit-Stride Instructions
 foreach vti = AllVectors in {
def : Pat<(riscv_shl_vl (vti.Vector vti.RegClass:$rs1),
                           (riscv_vmv_v_x_vl 1, (XLenVT srcvalue)),
                           (vti.Mask true_mask),
                           VLOpFrag),
             (!cast<Instruction>("PseudoVADD_VV_"# vti.LMul.MX)
                  vti.RegClass:$rs1, vti.RegClass:$rs1, GPR:$vl, vti.Log2SEW)>;
 }
 
 // 12.7. Vector Narrowing Integer Right Shift Instructions
+defm : VPatBinarySDNode_V_WV<srl, "PseudoVNSRL">;
+defm : VPatBinarySDNode_V_WX<srl, "PseudoVNSRL">;
+defm : VPatBinarySDNode_V_WV<sra, "PseudoVNSRA">;
+defm : VPatBinarySDNode_V_WX<sra, "PseudoVNSRA">;
+
 foreach vtiTowti = AllWidenableIntVectors in {
   defvar vti = vtiTowti.Vti;
   defvar wti = vtiTowti.Wti;
   def : Pat<(vti.Vector (riscv_trunc_vector_vl (wti.Vector wti.RegClass:$rs1),
                                                (vti.Mask true_mask),
                                                VLOpFrag)),
             (!cast<Instruction>("PseudoVNSRL_WI_"#vti.LMul.MX)
                 wti.RegClass:$rs1, 0, GPR:$vl, vti.Log2SEW)>;

llvm/test/CodeGen/RISCV/rvv/vnsra-sdnode.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -target-abi=ilp32 \
+; RUN:     -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -target-abi=lp64 \
+; RUN:     -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK
+
+define <vscale x 1 x i32> @vnsra_wv_nxv1i32_sext(<vscale x 1 x i64> %va, <vscale x 1 x i32> %vb) {
+; CHECK-LABEL: vnsra_wv_nxv1i32_sext:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, mu
+; CHECK-NEXT:    vnsra.wv v8, v8, v9
+; CHECK-NEXT:    ret
+  %vc = sext <vscale x 1 x i32> %vb to <vscale x 1 x i64>
+  %x = ashr <vscale x 1 x i64> %va, %vc
+  %y = trunc <vscale x 1 x i64> %x to <vscale x 1 x i32>
+  ret <vscale x 1 x i32> %y
+}
+
+define <vscale x 1 x i32> @vnsra_wx_i32_nxv1i32_sext(<vscale x 1 x i64> %va, i32 %b) {
+; CHECK-LABEL: vnsra_wx_i32_nxv1i32_sext:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32, mf2, ta, mu
+; CHECK-NEXT:    vnsra.wx v8, v8, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 1 x i32> undef, i32 %b, i32 0
+  %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
+  %vb = sext <vscale x 1 x i32> %splat to <vscale x 1 x i64>
+  %x = ashr <vscale x 1 x i64> %va, %vb
+  %y = trunc <vscale x 1 x i64> %x to <vscale x 1 x i32>
+  ret <vscale x 1 x i32> %y
+}
+
+define <vscale x 2 x i32> @vnsra_wv_nxv2i32_sext(<vscale x 2 x i64> %va, <vscale x 2 x i32> %vb) {
+; CHECK-LABEL: vnsra_wv_nxv2i32_sext:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, mu
+; CHECK-NEXT:    vnsra.wv v11, v8, v10
+; CHECK-NEXT:    vmv.v.v v8, v11
+; CHECK-NEXT:    ret
+  %vc = sext <vscale x 2 x i32> %vb to <vscale x 2 x i64>
+  %x = ashr <vscale x 2 x i64> %va, %vc
+  %y = trunc <vscale x 2 x i64> %x to <vscale x 2 x i32>
+  ret <vscale x 2 x i32> %y
+}
+
+define <vscale x 2 x i32> @vnsra_wx_i32_nxv2i32_sext(<vscale x 2 x i64> %va, i32 %b) {
+; CHECK-LABEL: vnsra_wx_i32_nxv2i32_sext:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32, m1, ta, mu
+; CHECK-NEXT:    vnsra.wx v10, v8, a0
+; CHECK-NEXT:    vmv.v.v v8, v10
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 2 x i32> undef, i32 %b, i32 0
+  %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
+  %vb = sext <vscale x 2 x i32> %splat to <vscale x 2 x i64>
+  %x = ashr <vscale x 2 x i64> %va, %vb
+  %y = trunc <vscale x 2 x i64> %x to <vscale x 2 x i32>
+  ret <vscale x 2 x i32> %y
+}
+
+define <vscale x 4 x i32> @vnsra_wv_nxv4i32_sext(<vscale x 4 x i64> %va, <vscale x 4 x i32> %vb) {
+; CHECK-LABEL: vnsra_wv_nxv4i32_sext:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, mu
+; CHECK-NEXT:    vnsra.wv v14, v8, v12
+; CHECK-NEXT:    vmv.v.v v8, v14
+; CHECK-NEXT:    ret
+  %vc = sext <vscale x 4 x i32> %vb to <vscale x 4 x i64>
+  %x = ashr <vscale x 4 x i64> %va, %vc
+  %y = trunc <vscale x 4 x i64> %x to <vscale x 4 x i32>
+  ret <vscale x 4 x i32> %y
+}
+
+define <vscale x 4 x i32> @vnsra_wx_i32_nxv4i32_sext(<vscale x 4 x i64> %va, i32 %b) {
+; CHECK-LABEL: vnsra_wx_i32_nxv4i32_sext:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32, m2, ta, mu
+; CHECK-NEXT:    vnsra.wx v12, v8, a0
+; CHECK-NEXT:    vmv.v.v v8, v12
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 4 x i32> undef, i32 %b, i32 0
+  %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
+  %vb = sext <vscale x 4 x i32> %splat to <vscale x 4 x i64>
+  %x = ashr <vscale x 4 x i64> %va, %vb
+  %y = trunc <vscale x 4 x i64> %x to <vscale x 4 x i32>
+  ret <vscale x 4 x i32> %y
+}
+
+define <vscale x 8 x i32> @vnsra_wv_nxv8i32_sext(<vscale x 8 x i64> %va, <vscale x 8 x i32> %vb) {
+; CHECK-LABEL: vnsra_wv_nxv8i32_sext:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vnsra.wv v20, v8, v16
+; CHECK-NEXT:    vmv.v.v v8, v20
+; CHECK-NEXT:    ret
+  %vc = sext <vscale x 8 x i32> %vb to <vscale x 8 x i64>
+  %x = ashr <vscale x 8 x i64> %va, %vc
+  %y = trunc <vscale x 8 x i64> %x to <vscale x 8 x i32>
+  ret <vscale x 8 x i32> %y
+}
+
+define <vscale x 8 x i32> @vnsra_wx_i32_nxv8i32_sext(<vscale x 8 x i64> %va, i32 %b) {
+; CHECK-LABEL: vnsra_wx_i32_nxv8i32_sext:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vnsra.wx v16, v8, a0
+; CHECK-NEXT:    vmv.v.v v8, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> undef, i32 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+  %vb = sext <vscale x 8 x i32> %splat to <vscale x 8 x i64>
+  %x = ashr <vscale x 8 x i64> %va, %vb
+  %y = trunc <vscale x 8 x i64> %x to <vscale x 8 x i32>
+  ret <vscale x 8 x i32> %y
+}
+
+define <vscale x 1 x i32> @vnsra_wv_nxv1i32_zext(<vscale x 1 x i64> %va, <vscale x 1 x i32> %vb) {
+; CHECK-LABEL: vnsra_wv_nxv1i32_zext:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, mu
+; CHECK-NEXT:    vnsra.wv v8, v8, v9
+; CHECK-NEXT:    ret
+  %vc = zext <vscale x 1 x i32> %vb to <vscale x 1 x i64>
+  %x = ashr <vscale x 1 x i64> %va, %vc
+  %y = trunc <vscale x 1 x i64> %x to <vscale x 1 x i32>
+  ret <vscale x 1 x i32> %y
+}
+
+define <vscale x 1 x i32> @vnsra_wx_i32_nxv1i32_zext(<vscale x 1 x i64> %va, i32 %b) {
+; CHECK-LABEL: vnsra_wx_i32_nxv1i32_zext:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32, mf2, ta, mu
+; CHECK-NEXT:    vnsra.wx v8, v8, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 1 x i32> undef, i32 %b, i32 0
+  %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
+  %vb = zext <vscale x 1 x i32> %splat to <vscale x 1 x i64>
+  %x = ashr <vscale x 1 x i64> %va, %vb
+  %y = trunc <vscale x 1 x i64> %x to <vscale x 1 x i32>
+  ret <vscale x 1 x i32> %y
+}
+
+define <vscale x 2 x i32> @vnsra_wv_nxv2i32_zext(<vscale x 2 x i64> %va, <vscale x 2 x i32> %vb) {
+; CHECK-LABEL: vnsra_wv_nxv2i32_zext:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, mu
+; CHECK-NEXT:    vnsra.wv v11, v8, v10
+; CHECK-NEXT:    vmv.v.v v8, v11
+; CHECK-NEXT:    ret
+  %vc = zext <vscale x 2 x i32> %vb to <vscale x 2 x i64>
+  %x = ashr <vscale x 2 x i64> %va, %vc
+  %y = trunc <vscale x 2 x i64> %x to <vscale x 2 x i32>
+  ret <vscale x 2 x i32> %y
+}
+
+define <vscale x 2 x i32> @vnsra_wx_i32_nxv2i32_zext(<vscale x 2 x i64> %va, i32 %b) {
+; CHECK-LABEL: vnsra_wx_i32_nxv2i32_zext:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32, m1, ta, mu
+; CHECK-NEXT:    vnsra.wx v10, v8, a0
+; CHECK-NEXT:    vmv.v.v v8, v10
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 2 x i32> undef, i32 %b, i32 0
+  %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
+  %vb = zext <vscale x 2 x i32> %splat to <vscale x 2 x i64>
+  %x = ashr <vscale x 2 x i64> %va, %vb
+  %y = trunc <vscale x 2 x i64> %x to <vscale x 2 x i32>
+  ret <vscale x 2 x i32> %y
+}
+
+define <vscale x 4 x i32> @vnsra_wv_nxv4i32_zext(<vscale x 4 x i64> %va, <vscale x 4 x i32> %vb) {
+; CHECK-LABEL: vnsra_wv_nxv4i32_zext:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, mu
+; CHECK-NEXT:    vnsra.wv v14, v8, v12
+; CHECK-NEXT:    vmv.v.v v8, v14
+; CHECK-NEXT:    ret
+  %vc = zext <vscale x 4 x i32> %vb to <vscale x 4 x i64>
+  %x = ashr <vscale x 4 x i64> %va, %vc
+  %y = trunc <vscale x 4 x i64> %x to <vscale x 4 x i32>
+  ret <vscale x 4 x i32> %y
+}
+
+define <vscale x 4 x i32> @vnsra_wx_i32_nxv4i32_zext(<vscale x 4 x i64> %va, i32 %b) {
+; CHECK-LABEL: vnsra_wx_i32_nxv4i32_zext:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32, m2, ta, mu
+; CHECK-NEXT:    vnsra.wx v12, v8, a0
+; CHECK-NEXT:    vmv.v.v v8, v12
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 4 x i32> undef, i32 %b, i32 0
+  %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
+  %vb = zext <vscale x 4 x i32> %splat to <vscale x 4 x i64>
+  %x = ashr <vscale x 4 x i64> %va, %vb
+  %y = trunc <vscale x 4 x i64> %x to <vscale x 4 x i32>
+  ret <vscale x 4 x i32> %y
+}
+
+define <vscale x 8 x i32> @vnsra_wv_nxv8i32_zext(<vscale x 8 x i64> %va, <vscale x 8 x i32> %vb) {
+; CHECK-LABEL: vnsra_wv_nxv8i32_zext:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vnsra.wv v20, v8, v16
+; CHECK-NEXT:    vmv.v.v v8, v20
+; CHECK-NEXT:    ret
+  %vc = zext <vscale x 8 x i32> %vb to <vscale x 8 x i64>
+  %x = ashr <vscale x 8 x i64> %va, %vc
+  %y = trunc <vscale x 8 x i64> %x to <vscale x 8 x i32>
+  ret <vscale x 8 x i32> %y
+}
+
+define <vscale x 8 x i32> @vnsra_wx_i32_nxv8i32_zext(<vscale x 8 x i64> %va, i32 %b) {
+; CHECK-LABEL: vnsra_wx_i32_nxv8i32_zext:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vnsra.wx v16, v8, a0
+; CHECK-NEXT:    vmv.v.v v8, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> undef, i32 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+  %vb = zext <vscale x 8 x i32> %splat to <vscale x 8 x i64>
+  %x = ashr <vscale x 8 x i64> %va, %vb
+  %y = trunc <vscale x 8 x i64> %x to <vscale x 8 x i32>
+  ret <vscale x 8 x i32> %y
+}

llvm/test/CodeGen/RISCV/rvv/vnsrl-sdnode.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -target-abi=ilp32 \
+; RUN:     -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -target-abi=lp64 \
+; RUN:     -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK
+
+define <vscale x 1 x i32> @vnsrl_wv_nxv1i32_sext(<vscale x 1 x i64> %va, <vscale x 1 x i32> %vb) {
+; CHECK-LABEL: vnsrl_wv_nxv1i32_sext:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, mu
+; CHECK-NEXT:    vnsrl.wv v8, v8, v9
+; CHECK-NEXT:    ret
+  %vc = sext <vscale x 1 x i32> %vb to <vscale x 1 x i64>
+  %x = lshr <vscale x 1 x i64> %va, %vc
+  %y = trunc <vscale x 1 x i64> %x to <vscale x 1 x i32>
+  ret <vscale x 1 x i32> %y
+}
+
+define <vscale x 1 x i32> @vnsrl_wx_i32_nxv1i32_sext(<vscale x 1 x i64> %va, i32 %b) {
+; CHECK-LABEL: vnsrl_wx_i32_nxv1i32_sext:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32, mf2, ta, mu
+; CHECK-NEXT:    vnsrl.wx v8, v8, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 1 x i32> undef, i32 %b, i32 0
+  %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
+  %vb = sext <vscale x 1 x i32> %splat to <vscale x 1 x i64>
+  %x = lshr <vscale x 1 x i64> %va, %vb
+  %y = trunc <vscale x 1 x i64> %x to <vscale x 1 x i32>
+  ret <vscale x 1 x i32> %y
+}
+
+define <vscale x 2 x i32> @vnsrl_wv_nxv2i32_sext(<vscale x 2 x i64> %va, <vscale x 2 x i32> %vb) {
+; CHECK-LABEL: vnsrl_wv_nxv2i32_sext:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, mu
+; CHECK-NEXT:    vnsrl.wv v11, v8, v10
+; CHECK-NEXT:    vmv.v.v v8, v11
+; CHECK-NEXT:    ret
+  %vc = sext <vscale x 2 x i32> %vb to <vscale x 2 x i64>
+  %x = lshr <vscale x 2 x i64> %va, %vc
+  %y = trunc <vscale x 2 x i64> %x to <vscale x 2 x i32>
+  ret <vscale x 2 x i32> %y
+}
+
+define <vscale x 2 x i32> @vnsrl_wx_i32_nxv2i32_sext(<vscale x 2 x i64> %va, i32 %b) {
+; CHECK-LABEL: vnsrl_wx_i32_nxv2i32_sext:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32, m1, ta, mu
+; CHECK-NEXT:    vnsrl.wx v10, v8, a0
+; CHECK-NEXT:    vmv.v.v v8, v10
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 2 x i32> undef, i32 %b, i32 0
+  %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
+  %vb = sext <vscale x 2 x i32> %splat to <vscale x 2 x i64>
+  %x = lshr <vscale x 2 x i64> %va, %vb
+  %y = trunc <vscale x 2 x i64> %x to <vscale x 2 x i32>
+  ret <vscale x 2 x i32> %y
+}
+
+define <vscale x 4 x i32> @vnsrl_wv_nxv4i32_sext(<vscale x 4 x i64> %va, <vscale x 4 x i32> %vb) {
+; CHECK-LABEL: vnsrl_wv_nxv4i32_sext:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, mu
+; CHECK-NEXT:    vnsrl.wv v14, v8, v12
+; CHECK-NEXT:    vmv.v.v v8, v14
+; CHECK-NEXT:    ret
+  %vc = sext <vscale x 4 x i32> %vb to <vscale x 4 x i64>
+  %x = lshr <vscale x 4 x i64> %va, %vc
+  %y = trunc <vscale x 4 x i64> %x to <vscale x 4 x i32>
+  ret <vscale x 4 x i32> %y
+}
+
+define <vscale x 4 x i32> @vnsrl_wx_i32_nxv4i32_sext(<vscale x 4 x i64> %va, i32 %b) {
+; CHECK-LABEL: vnsrl_wx_i32_nxv4i32_sext:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32, m2, ta, mu
+; CHECK-NEXT:    vnsrl.wx v12, v8, a0
+; CHECK-NEXT:    vmv.v.v v8, v12
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 4 x i32> undef, i32 %b, i32 0
+  %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
+  %vb = sext <vscale x 4 x i32> %splat to <vscale x 4 x i64>
+  %x = lshr <vscale x 4 x i64> %va, %vb
+  %y = trunc <vscale x 4 x i64> %x to <vscale x 4 x i32>
+  ret <vscale x 4 x i32> %y
+}
+
+define <vscale x 8 x i32> @vnsrl_wv_nxv8i32_sext(<vscale x 8 x i64> %va, <vscale x 8 x i32> %vb) {
+; CHECK-LABEL: vnsrl_wv_nxv8i32_sext:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vnsrl.wv v20, v8, v16
+; CHECK-NEXT:    vmv.v.v v8, v20
+; CHECK-NEXT:    ret
+  %vc = sext <vscale x 8 x i32> %vb to <vscale x 8 x i64>
+  %x = lshr <vscale x 8 x i64> %va, %vc
+  %y = trunc <vscale x 8 x i64> %x to <vscale x 8 x i32>
+  ret <vscale x 8 x i32> %y
+}
+
+define <vscale x 8 x i32> @vnsrl_wx_i32_nxv8i32_sext(<vscale x 8 x i64> %va, i32 %b) {
+; CHECK-LABEL: vnsrl_wx_i32_nxv8i32_sext:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vnsrl.wx v16, v8, a0
+; CHECK-NEXT:    vmv.v.v v8, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> undef, i32 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+  %vb = sext <vscale x 8 x i32> %splat to <vscale x 8 x i64>
+  %x = lshr <vscale x 8 x i64> %va, %vb
+  %y = trunc <vscale x 8 x i64> %x to <vscale x 8 x i32>
+  ret <vscale x 8 x i32> %y
+}
+
+define <vscale x 1 x i32> @vnsrl_wv_nxv1i32_zext(<vscale x 1 x i64> %va, <vscale x 1 x i32> %vb) {
+; CHECK-LABEL: vnsrl_wv_nxv1i32_zext:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, mu
+; CHECK-NEXT:    vnsrl.wv v8, v8, v9
+; CHECK-NEXT:    ret
+  %vc = zext <vscale x 1 x i32> %vb to <vscale x 1 x i64>
+  %x = lshr <vscale x 1 x i64> %va, %vc
+  %y = trunc <vscale x 1 x i64> %x to <vscale x 1 x i32>
+  ret <vscale x 1 x i32> %y
+}
+
+define <vscale x 1 x i32> @vnsrl_wx_i32_nxv1i32_zext(<vscale x 1 x i64> %va, i32 %b) {
+; CHECK-LABEL: vnsrl_wx_i32_nxv1i32_zext:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32, mf2, ta, mu
+; CHECK-NEXT:    vnsrl.wx v8, v8, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 1 x i32> undef, i32 %b, i32 0
+  %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
+  %vb = zext <vscale x 1 x i32> %splat to <vscale x 1 x i64>
+  %x = lshr <vscale x 1 x i64> %va, %vb
+  %y = trunc <vscale x 1 x i64> %x to <vscale x 1 x i32>
+  ret <vscale x 1 x i32> %y
+}
+
+define <vscale x 2 x i32> @vnsrl_wv_nxv2i32_zext(<vscale x 2 x i64> %va, <vscale x 2 x i32> %vb) {
+; CHECK-LABEL: vnsrl_wv_nxv2i32_zext:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, mu
+; CHECK-NEXT:    vnsrl.wv v11, v8, v10
+; CHECK-NEXT:    vmv.v.v v8, v11
+; CHECK-NEXT:    ret
+  %vc = zext <vscale x 2 x i32> %vb to <vscale x 2 x i64>
+  %x = lshr <vscale x 2 x i64> %va, %vc
+  %y = trunc <vscale x 2 x i64> %x to <vscale x 2 x i32>
+  ret <vscale x 2 x i32> %y
+}
+
+define <vscale x 2 x i32> @vnsrl_wx_i32_nxv2i32_zext(<vscale x 2 x i64> %va, i32 %b) {
+; CHECK-LABEL: vnsrl_wx_i32_nxv2i32_zext:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32, m1, ta, mu
+; CHECK-NEXT:    vnsrl.wx v10, v8, a0
+; CHECK-NEXT:    vmv.v.v v8, v10
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 2 x i32> undef, i32 %b, i32 0
+  %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
+  %vb = zext <vscale x 2 x i32> %splat to <vscale x 2 x i64>
+  %x = lshr <vscale x 2 x i64> %va, %vb
+  %y = trunc <vscale x 2 x i64> %x to <vscale x 2 x i32>
+  ret <vscale x 2 x i32> %y
+}
+
+define <vscale x 4 x i32> @vnsrl_wv_nxv4i32_zext(<vscale x 4 x i64> %va, <vscale x 4 x i32> %vb) {
+; CHECK-LABEL: vnsrl_wv_nxv4i32_zext:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, mu
+; CHECK-NEXT:    vnsrl.wv v14, v8, v12
+; CHECK-NEXT:    vmv.v.v v8, v14
+; CHECK-NEXT:    ret
+  %vc = zext <vscale x 4 x i32> %vb to <vscale x 4 x i64>
+  %x = lshr <vscale x 4 x i64> %va, %vc
+  %y = trunc <vscale x 4 x i64> %x to <vscale x 4 x i32>
+  ret <vscale x 4 x i32> %y
+}
+
+define <vscale x 4 x i32> @vnsrl_wx_i32_nxv4i32_zext(<vscale x 4 x i64> %va, i32 %b) {
+; CHECK-LABEL: vnsrl_wx_i32_nxv4i32_zext:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32, m2, ta, mu
+; CHECK-NEXT:    vnsrl.wx v12, v8, a0
+; CHECK-NEXT:    vmv.v.v v8, v12
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 4 x i32> undef, i32 %b, i32 0
+  %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
+  %vb = zext <vscale x 4 x i32> %splat to <vscale x 4 x i64>
+  %x = lshr <vscale x 4 x i64> %va, %vb
+  %y = trunc <vscale x 4 x i64> %x to <vscale x 4 x i32>
+  ret <vscale x 4 x i32> %y
+}
+
+define <vscale x 8 x i32> @vnsrl_wv_nxv8i32_zext(<vscale x 8 x i64> %va, <vscale x 8 x i32> %vb) {
+; CHECK-LABEL: vnsrl_wv_nxv8i32_zext:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vnsrl.wv v20, v8, v16
+; CHECK-NEXT:    vmv.v.v v8, v20
+; CHECK-NEXT:    ret
+  %vc = zext <vscale x 8 x i32> %vb to <vscale x 8 x i64>
+  %x = lshr <vscale x 8 x i64> %va, %vc
+  %y = trunc <vscale x 8 x i64> %x to <vscale x 8 x i32>
+  ret <vscale x 8 x i32> %y
+}
+
+define <vscale x 8 x i32> @vnsrl_wx_i32_nxv8i32_zext(<vscale x 8 x i64> %va, i32 %b) {
+; CHECK-LABEL: vnsrl_wx_i32_nxv8i32_zext:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vnsrl.wx v16, v8, a0
+; CHECK-NEXT:    vmv.v.v v8, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> undef, i32 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+  %vb = zext <vscale x 8 x i32> %splat to <vscale x 8 x i64>
+  %x = lshr <vscale x 8 x i64> %va, %vb
+  %y = trunc <vscale x 8 x i64> %x to <vscale x 8 x i32>
+  ret <vscale x 8 x i32> %y
+}